Indication device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MAGNOLIA WHITE CORP
- Filing Date
- 2022-03-01
- Publication Date
- 2026-08-04
Smart Images
Figure 0007900032000001 
Figure 0007900032000002 
Figure 0007900032000003
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.
Background Art
[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light-emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Patent Document 3
Patent Document 4
Patent Document 5
Patent Document 6
Summary of the Invention
Problems to be Solved by the Invention
[0004] An object of the present invention is to provide a display device and a method for manufacturing the display device capable of suppressing a decrease in reliability.
Means for Solving the Problems
[0005] According to one embodiment, the display device is A partition wall comprising a substrate, a first lower electrode and a second lower electrode disposed above the substrate, a rib having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, a lower part disposed on the rib between the first and second openings, and an upper part disposed above the lower part and protruding from the side surface of the lower part, a first organic layer disposed on the first lower electrode in the first opening and including a first light-emitting layer, and a second organic layer disposed on the second lower electrode in the second opening and made of a different material from the first light-emitting layer The device comprises a second organic layer including a light-emitting layer, a first upper electrode disposed on the first organic layer and in contact with the lower part of the partition wall, a second upper electrode disposed on the second organic layer and in contact with the lower part of the partition wall, a first sealing layer disposed above the first upper electrode and in contact with the lower part of the partition wall, and a second sealing layer disposed above the second upper electrode, in contact with the lower part of the partition wall and spaced apart from the first sealing layer, wherein the thickness of the first sealing layer directly above the first lower electrode is 0.5 times or more and less than 2 times the thickness of the lower part of the partition wall.
[0006] According to one embodiment, the method for manufacturing a display device is: A processing substrate is prepared, having a lower electrode, a rib having an opening that overlaps with the lower electrode, and a partition wall having a lower part positioned on the rib and an upper part positioned on the lower part and protruding from the side of the lower part. A thin film including an organic layer, an upper electrode, and a cap layer is formed on the processing substrate. A sealing layer is formed covering the thin film and the partition wall. A resist is formed covering a part of the sealing layer. Dry etching is performed using the resist as a mask to remove the sealing layer exposed from the resist. The thin film exposed from the resist and the sealing layer is removed. The process of forming the sealing layer includes forming a first inorganic insulating layer in contact with the thin film and the partition wall. Anisotropic dry etching of the first inorganic insulating layer is performed to reduce the film thickness of the first inorganic insulating layer located directly above the lower electrode and directly above the upper part of the partition wall. A second inorganic insulating layer is formed on the first inorganic insulating layer. [Brief explanation of the drawing]
[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. [Figure 3] Figure 3 is a schematic cross-sectional view of the DSP display device along the line III-III in Figure 2. [Figure 4] Figure 4 shows an example of the configuration of the display element 20. [Figure 5] Figure 5 is a flowchart illustrating an example of a manufacturing method for a display device DSP. [Figure 6] Figure 6 is a diagram illustrating an example of the process for forming the sealing layer SE10. [Figure 7] Figure 7 is a diagram illustrating another example of the process for forming the sealing layer SE10. [Figure 8] Figure 8 is a diagram illustrating step ST1. [Figure 9] Figure 9 is a diagram illustrating step ST21. [Figure 10] Figure 10 is a diagram illustrating step ST22. [Figure 11] Figure 11 is a diagram illustrating step ST22. [Figure 12] Figure 12 is a cross-sectional view of the sealing layer SE10 formed by the process described with reference to Figure 7. [Figure 13] Figure 13 is another cross-sectional view of the sealing layer SE10 formed through the process described with reference to Figure 7. [Figure 14] Figure 14 is a diagram illustrating step ST23. [Figure 15] Figure 15 is a diagram illustrating step ST23. [Figure 16] Figure 16 is a diagram illustrating step ST24. [Figure 17] Figure 17 is a diagram illustrating step ST25. [Figure 18]FIG. 18 is a diagram for explaining step ST26.
Embodiment for Carrying out the Invention
[0008] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those who can easily conceive appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above with respect to the previously shown figures may be assigned the same reference numerals, and detailed descriptions that are duplicates may be omitted as appropriate.
[0009] In the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Looking at various elements parallel to the third direction Z is referred to as a plan view.
[0010] The display device according to this embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, etc.
[0011] FIG. 1 is a diagram showing a configuration example of the display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.
[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.
[0013] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a blue sub-pixel SP2, and a green sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.
[0014] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.
[0015] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and drain electrodes is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.
[0016] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.
[0017] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the blue wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the green wavelength range.
[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the first direction X.
[0019] When subpixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which subpixels SP1 and SP3 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP2 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.
[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.
[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP3 is larger than aperture AP1, and aperture AP2 is larger than aperture AP3.
[0022] The partition wall 6 overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP3 in the second direction Y, and between two adjacent openings AP2 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP2 in the first direction X, and between adjacent openings AP2 and AP3 in the first direction X.
[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole is formed in a grid shape that surrounds the openings AP1, AP2, and AP3. The partition wall 6 can also be said to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.
[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3.
[0025] In the example in Figure 2, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. The periphery of each of the lower electrodes LE1, LE2, and LE3 overlaps with the rib 5. The outline of the upper electrode UE1 is almost identical to the outline of the organic layer OR1, and the periphery of both the upper electrode UE1 and the organic layer OR1 overlaps with the partition wall 6. The outline of the upper electrode UE2 is almost identical to the outline of the organic layer OR2, and the periphery of both the upper electrode UE2 and the organic layer OR2 overlaps with the partition wall 6. The outline of the upper electrode UE3 is almost identical to the outline of the organic layer OR3, and the periphery of both the upper electrode UE3 and the organic layer OR3 overlaps with the partition wall 6.
[0026] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of the display element 20.
[0027] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.
[0028] Figure 3 is a schematic cross-sectional view of the DSP display device along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.
[0029] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. In other words, the ends of the lower electrodes LE1, LE2, and LE3 are positioned between the insulating layer 12 and the rib 5. Between the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the insulating layer 12 is covered by the rib 5.
[0030] The partition wall 6 includes a lower part (stem) 61 positioned on the rib 5 and an upper part (cap) 62 positioned on the lower part 61. The lower part 61 of the partition wall 6 shown on the left side of the figure is located between opening AP1 and opening AP2. The lower part 61 of the partition wall 6 shown on the right side of the figure is located between opening AP2 and opening AP3. The upper part 62 has a greater width than the lower part 61. As a result, in Figure 3, both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the partition wall 6 can also be described as overhanging. The part of the upper part 62 that protrudes beyond the lower part 61 is sometimes simply referred to as the protruding part.
[0031] The organic layer OR1 shown in Figure 2 includes a first portion OR1a and a second portion OR1b that are spaced apart from each other, as shown in Figure 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a portion of the rib 5. The second portion OR1b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE1 shown in Figure 2 includes a first portion UE1a and a second portion UE1b that are spaced apart from each other, as shown in Figure 3. The first portion UE1a faces the lower electrode LE1 and is positioned above the first portion OR1a. In addition, the first portion UE1a is in contact with the side surface of the lower part 61. The second portion UE1b is located above the partition wall 6 and is positioned above the second portion OR1b. The first part OR1a and the first part UE1a are located below the upper part 62.
[0032] The organic layer OR2 shown in Figure 2 includes a first portion OR2a and a second portion OR2b that are spaced apart from each other, as shown in Figure 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a portion of the rib 5. The second portion OR2b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE2 shown in Figure 2 includes a first portion UE2a and a second portion UE2b that are spaced apart from each other, as shown in Figure 3. The first portion UE2a faces the lower electrode LE2 and is positioned above the first portion OR2a. In addition, the first portion UE2a is in contact with the side surface of the lower part 61. The second portion UE2b is located above the partition wall 6 and is positioned above the second portion OR2b. The first part OR2a and the first part UE2a are located below the upper part 62.
[0033] The organic layer OR3 shown in Figure 2 includes a first portion OR3a and a second portion OR3b that are spaced apart from each other, as shown in Figure 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a portion of the rib 5. The second portion OR3b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE3 shown in Figure 2 includes a first portion UE3a and a second portion UE3b that are spaced apart from each other, as shown in Figure 3. The first portion UE3a faces the lower electrode LE3 and is positioned above the first portion OR3a. In addition, the first portion UE3a is in contact with the side surface of the lower part 61. The second portion UE3b is located above the partition wall 6 and is positioned above the second portion OR3b. The first part OR3a and the first part UE3a are located below the upper part 62.
[0034] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.
[0035] The cap layer CP1 includes a first portion CP1a and a second portion CP1b that are spaced apart from each other. The first portion CP1a is located at the opening AP1, below the upper portion 62, and positioned above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and positioned above the second portion UE1b.
[0036] The cap layer CP2 includes a first portion CP2a and a second portion CP2b that are spaced apart from each other. The first portion CP2a is located in the opening AP2, below the upper portion 62, and positioned above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and positioned above the second portion UE2b.
[0037] The cap layer CP3 includes a first portion CP3a and a second portion CP3b that are spaced apart from each other. The first portion CP3a is located in the opening AP3, below the upper portion 62, and positioned above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and positioned above the second portion UE3b.
[0038] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE1, SE2, and SE3, respectively. The sealing layer SE1 is in contact with the first portion CP1a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP1b, and continuously covers each component of the sub-pixel SP1. In the illustrated example, the sealing layer SE1 has a closed void V1 below the upper portion 62 of the partition wall 6 (below the protruding portion 621). The void V1 is spaced apart from the partition wall 6. This void V1 is surrounded by the portion of the sealing layer SE1 that is in contact with the side surface of the lower portion 61 of the partition wall 6, the portion that is in contact with the bottom surface of the upper portion 62 of the partition wall 6, and the portion that is in contact with the first portion CP1a. The void V1 is formed along the entire circumference of the partition wall 6 surrounding the opening AP1, but may be partially absent. The void V1 is closed throughout. The sealing layer SE2 is in contact with the first portion CP2a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP2b, and continuously covers each component of the sub-pixel SP2. The sealing layer SE2 has a closed void V2 below the upper 62 of the partition wall 6 (below the protrusion 622). The void V2 is located on the opposite side of the partition wall 6 from the void V1. The void V2 is formed along the entire circumference of the partition wall 6 surrounding the opening AP2, but may be partially absent. The void V2 is closed throughout. The sealing layer SE3 is in contact with the first portion CP3a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP3b, and continuously covers each component of the sub-pixel SP3. The sealing layer SE3 has a closed void V3 below the upper 62 of the partition wall 6 (below the protruding portion 623). The void V3 is located on the opposite side of the partition wall 6 from the void V2. The void V3 is formed along the entire circumference of the partition wall 6 surrounding the opening AP3, but may be partially absent. The void V3 is closed throughout.
[0039] The sealing layers SE1, SE2, and SE3 are covered by a protective layer 13.
[0040] In the example shown in Figure 3, on the partition wall 6 between sub-pixels SP1 and SP2, the second portion OR1b of organic layer OR1 is separated from the second portion OR2b of organic layer OR2, the second portion UE1b of upper electrode UE1 is separated from the second portion UE2b of upper electrode UE2, the second portion CP1b of cap layer CP1 is separated from the second portion CP2b of cap layer CP2, and the sealing layer SE1 is separated from the sealing layer SE2. The protective layer 13 is positioned between the second portions OR1b and OR2b, between the second portions UE1b and UE2b, between the second portions CP1b and CP2b, and between the sealing layer SE1 and the sealing layer SE2.
[0041] Furthermore, on the partition wall 6 between sub-pixels SP2 and SP3, the second portion OR2b of the organic layer OR2 is separated from the second portion OR3b of the organic layer OR3, the second portion UE2b of the upper electrode UE2 is separated from the second portion UE3b of the upper electrode UE3, the second portion CP2b of the cap layer CP2 is separated from the second portion CP3b of the cap layer CP3, and the sealing layer SE2 is separated from the sealing layer SE3. The protective layer 13 is positioned between the second portions OR2b and OR3b, between the second portions UE2b and UE3b, between the second portions CP2b and CP3b, and between the sealing layers SE2 and SE3.
[0042] The insulating layer 12 is an organic insulating layer. The ribs 5 and the sealing layers SE1, SE2, and SE3 are inorganic insulating layers.
[0043] The ribs 5 and the sealing layers SE1, SE2, and SE3 are formed from, for example, the same inorganic insulating material. Rib 5 is formed, for example, from silicon nitride (SiNx). Alternatively, rib 5 may be formed as a single layer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Furthermore, rib 5 may be formed as a laminate of at least two combinations of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The sealing layers SE1, SE2, and SE3 are formed from, for example, silicon nitride (SiNx).
[0044] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the first portions UE1a, UE2a, and UE3a of each upper electrode. Both the lower part 61 and the upper part 62 of the partition wall 6 may be conductive.
[0045] The thickness T5 of rib 5 is sufficiently small compared to the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness T5 of rib 5 is between 200 nm and 400 nm.
[0046] Directly above the lower electrode LE1 overlapping the aperture AP1, the sealing layer SE1 has a thickness T1. Directly above the lower electrode LE2 overlapping the aperture AP2, the sealing layer SE2 has a thickness T2. Directly above the lower electrode LE3 overlapping the aperture AP3, the sealing layer SE3 has a thickness T3. Thicknesses T1, T2, and T3 are approximately equivalent, between 0.5 μm and less than 2 μm. The thickness T61 of the lower part 61 of the bulkhead 6 (thickness from the upper surface of the rib 5 to the lower surface of the upper part 62) is greater than the thickness T5 of the rib 5. Also, the thicknesses T1 to T3 are 0.5 times or more and less than 2 times the thickness T61.
[0047] The lower electrodes LE1, LE2, and LE3 may be formed from a transparent conductive material such as ITO, or they may have a laminated structure of a metallic material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed from a transparent conductive material such as ITO.
[0048] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.
[0049] The organic layers OR1, OR2, and OR3 contain multiple functional layers. Furthermore, the first portion OR1a and the second portion OR1b of organic layer OR1 contain an emissive layer EM1 formed from the same material. The first portion OR2a and the second portion OR2b of organic layer OR2 contain an emissive layer EM2 formed from the same material. The emissive layer EM2 is formed from a different material than the emissive layer EM1. The first portion OR3a and the second portion OR3b of organic layer OR3 contain an emissive layer EM3 formed from the same material. The emissive layer EM3 is formed from a different material than the emissive layers EM1 and EM2. The materials forming the emissive layer EM1, the emissive layer EM2, and the emissive layer EM3 are materials that emit light in different wavelength ranges.
[0050] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed of inorganic materials and thin films formed of organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.
[0051] The protective layer 13 is formed by a multilayer structure of transparent thin films, and for example, the thin films include thin films formed of inorganic materials and thin films formed of organic materials.
[0052] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of each upper electrode that are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.
[0053] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 of the first portion OR1a of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 of the first portion OR2a of the organic layer OR2 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 of the first portion OR3a of the organic layer OR3 emits light in the green wavelength range.
[0054] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.
[0055] In the examples shown in Figures 1 to 3, the opening AP1 corresponds to the first opening, the opening AP2 corresponds to the second opening, the lower electrode LE1 corresponds to the first lower electrode, the organic layer OR1 corresponds to the first organic layer, the light-emitting layer EM1 corresponds to the first light-emitting layer, the upper electrode UE1 corresponds to the first upper electrode, the cap layer CP1 corresponds to the first cap layer, the sealing layer SE1 corresponds to the first sealing layer, the lower electrode LE2 corresponds to the second lower electrode, the organic layer OR2 corresponds to the second organic layer, the light-emitting layer EM2 corresponds to the second light-emitting layer, the upper electrode UE2 corresponds to the second upper electrode, the cap layer CP2 corresponds to the second cap layer, and the sealing layer SE2 corresponds to the second sealing layer.
[0056] Figure 4 shows an example of the configuration of the display element 20. The lower electrode LE shown in Figure 4 corresponds to the lower electrodes LE1, LE2, and LE3 in Figure 3, respectively. The organic layer OR shown in Figure 4 corresponds to the organic layers OR1, OR2, and OR3 in Figure 3, respectively. The upper electrode UE shown in Figure 4 corresponds to the upper electrodes UE1, UE2, and UE3 in Figure 3, respectively.
[0057] The organic layer OR comprises a carrier adjustment layer CA1, an emissive layer EM, and a carrier adjustment layer CA2. Carrier adjustment layer CA1 is located between the lower electrode LE and the emissive layer EM, and carrier adjustment layer CA2 is located between the emissive layer EM and the upper electrode UE. Carrier adjustment layers CA1 and CA2 contain multiple functional layers. The following explanation will use the case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode as an example.
[0058] The carrier adjustment layer CA1 includes functional layers such as a hole injection layer F11, a hole transport layer F12, and an electron blocking layer F13. The hole injection layer F11 is placed on the lower electrode LE, the hole transport layer F12 is placed on top of the hole injection layer F11, the electron blocking layer F13 is placed on top of the hole transport layer F12, and the light emission layer EM is placed on top of the electron blocking layer F13.
[0059] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, and an electron injection layer F23. The hole blocking layer F21 is located on top of the light-emitting layer EM, the electron transport layer F22 is located on top of the hole blocking layer F21, the electron injection layer F23 is located on top of the electron transport layer F22, and the upper electrode UE is located on top of the electron injection layer F23.
[0060] Furthermore, the carrier adjustment layers CA1 and CA2 may include other functional layers, such as a carrier generation layer, as needed, in addition to the functional layers described above, or at least one of the functional layers may be omitted.
[0061] Next, we will describe an example of a manufacturing method for a display device DSP.
[0062] Figure 5 is a flowchart illustrating an example of a manufacturing method for a display device DSP. The manufacturing method described herein broadly includes the steps of preparing a processing substrate SUB to serve as the base for sub-pixels SPα, SPβ, and SPγ (step ST1), forming sub-pixel SPα (step ST2), forming sub-pixel SPβ (step ST3), and forming sub-pixel SPγ (step ST4). Note that sub-pixels SPα, SPβ, and SPγ here refer to any of the sub-pixels SP1, SP2, and SP3 described above.
[0063] In step ST1, first, a processing substrate SUB is prepared on the substrate 10, with the lower electrodes LEα, LEβ, LEγ, ribs 5, and partition walls 6 formed on top of it. As shown in Figure 3, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the lower electrodes LEα, LEβ, LEγ.
[0064] In step ST2, first, a first thin film 31 including an emissive layer EMα is formed on the processing substrate SUB (step ST21). Then, a sealing layer SE10 is formed to cover the first thin film 31 and the partition wall 6 (step ST22). Then, a first resist 41 patterned in a predetermined shape is formed on the sealing layer SE10 (step ST23). Then, a part of the sealing layer SE10 is removed by etching using the first resist 41 as a mask (step ST24). Then, a part of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST25). Then, the first resist 41 is removed (step ST26). This forms a sub-pixel SPα. The sub-pixel SPα comprises a display element 21 having the first thin film 31 of a predetermined shape. The display element 21 is sealed with the sealing layer SE10.
[0065] In step ST3, first, a second thin film 32 including an emissive layer EMβ is formed on the processing substrate SUB (step ST31). Then, a sealing layer SE20 is formed to cover the second thin film 32 and the partition wall 6 (step ST32). Then, a second resist 42 patterned in a predetermined shape is formed on the sealing layer SE20 (step ST33). Then, a part of the sealing layer SE20 is removed by etching using the second resist 42 as a mask (step ST34). Then, a part of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST35). Then, the second resist 42 is removed (step ST36). This forms a sub-pixel SPβ. The sub-pixel SPβ comprises a display element 22 having a second thin film 32 of a predetermined shape. The display element 22 is sealed with the sealing layer SE20.
[0066] In step ST4, first, a third thin film 33 including an emissive layer EMγ is formed on the processing substrate SUB (step ST41). Then, a sealing layer SE30 is formed to cover the third thin film 33 and the partition wall 6 (step ST42). Then, a third resist 43 patterned in a predetermined shape is formed on the sealing layer SE30 (step ST43). Then, a part of the sealing layer SE30 is removed by etching using the third resist 43 as a mask (step ST44). Then, a part of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST45). Then, the third resist 43 is removed (step ST46). This forms a sub-pixel SPγ. The sub-pixel SPγ comprises a display element 23 having a third thin film 33 of a predetermined shape. The display element 23 is sealed with the sealing layer SE30.
[0067] The light-emitting layers EMα, EMβ, and EMγ are formed from materials that emit light in different wavelength ranges.
[0068] Detailed illustrations of the second thin film 32, light-emitting layer EMβ, display element 22, sealing layer SE20, third thin film 33, light-emitting layer EMγ, display element 23, and sealing layer SE30 are omitted.
[0069] Here, we will explain in more detail the process of forming the sealing layer SE10 in step ST22.
[0070] Figure 6 is a diagram illustrating an example of the process for forming the sealing layer SE10. First, a first inorganic insulating layer IL1 is formed in contact with the first thin film 31 and the partition wall 6 (step ST221). Then, anisotropic dry etching is performed on the first inorganic insulating layer IL1 to reduce its thickness (step ST222). At this point, the thickness of the first inorganic insulating layer IL1 is greater than 0 μm. In other words, no through holes are formed in the first inorganic insulating layer IL1. Then, a second inorganic insulating layer IL2 is formed on top of the first inorganic insulating layer IL1 (step ST223).
[0071] This forms the sealing layer SE10. In other words, in the example shown in Figure 6, the sealing layer SE10 is formed as a laminate of the first inorganic insulating layer IL1 and the second inorganic insulating layer IL2.
[0072] Figure 7 is a diagram illustrating another example of the process for forming the sealing layer SE10. First, a first inorganic insulating layer IL1 is formed in contact with the first thin film 31 and the partition wall 6 (step ST221). Then, anisotropic dry etching is performed on the first inorganic insulating layer IL1 to reduce its thickness (step ST222). At this point, the thickness of the first inorganic insulating layer IL1 is greater than 0 μm. Next, a second inorganic insulating layer IL2 is formed on top of the first inorganic insulating layer IL1 (step ST223). Then, anisotropic dry etching is performed on the second inorganic insulating layer IL2 to reduce its thickness (step ST224). At this point, the thickness of the second inorganic insulating layer IL2 is greater than 0 μm. In other words, no through holes are formed in the second inorganic insulating layer IL2. Next, a third inorganic insulating layer IL3 is formed on top of the second inorganic insulating layer IL2 (step ST225).
[0073] This forms the sealing layer SE10. In other words, in the example shown in Figure 7, the sealing layer SE10 is formed as a laminate of the first inorganic insulating layer IL1, the second inorganic insulating layer IL2, and the third inorganic insulating layer IL3.
[0074] In the example shown in Figure 7, after forming the third inorganic insulating layer IL3, the process of performing anisotropic dry etching and forming an inorganic insulating layer may be repeated. In this case, the sealing layer SE10 is formed as a laminate of four or more inorganic insulating layers.
[0075] Figures 6 and 7 illustrate the process of forming the sealing layer SE10 in step ST22, but the process shown in Figure 6 or Figure 7 can also be applied to the process of forming the sealing layer SE20 in step ST32 and the process of forming the sealing layer SE30 in step ST42.
[0076] Steps ST1 and ST2 will be explained below with reference to Figures 8 through 18.
[0077] First, in step ST1, a processing substrate SUB is prepared as shown in Figure 8. The process of preparing the processing substrate SUB includes the steps of forming a circuit layer 11 on a substrate 10, forming an insulating layer 12 on the circuit layer 11, forming the lower electrode LEα of the sub-pixel SPα, the lower electrode LEβ of the sub-pixel SPβ, and the lower electrode LEγ of the sub-pixel SPγ on the insulating layer 12, forming ribs 5 having openings APα, APβ, and APγ that overlap with the lower electrodes LEα, LEβ, and LEγ respectively, and forming a partition wall 6 including a lower part 61 placed on the ribs 5 and an upper part 62 placed on the lower part 61 and protruding from the side surface of the lower part 61. Note that in Figures 9 to 18, the substrate 10 and circuit layer 11 below the insulating layer 12 are not shown.
[0078] Next, in step ST21, as shown in Figure 9, a first thin film 31 is formed over sub-pixels SPα, SPβ, and SPγ. The step of forming the first thin film 31 includes the steps of forming an organic layer OR10 containing an emissive layer EMα on the processing substrate SUB, forming an upper electrode UE10 on the organic layer OR10, and forming a cap layer CP10 on the upper electrode UE10. In other words, in the illustrated example, the first thin film 31 includes the organic layer OR10, the upper electrode UE10, and the cap layer CP10.
[0079] The organic layer OR10 includes organic layers OR11, OR12, OR13, OR14, and OR15. All of the organic layers OR11, OR12, OR13, OR14, and OR15 contain the luminescent layer EMα. Organic layer OR11 is formed to cover the lower electrode LEα. Organic layer OR12 is spaced apart from organic layer OR11 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEα and LEβ. Organic layer OR13 is spaced apart from organic layer OR12 and is formed to cover the lower electrode LEβ. Organic layer OR14 is spaced apart from organic layer OR13 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEβ and LEγ. Organic layer OR15 is spaced apart from organic layer OR14 and is formed to cover the lower electrode LEγ.
[0080] The upper electrode UE10 includes upper electrodes UE11, UE12, UE13, UE14, and UE15. The upper electrode UE11 is located on the organic layer OR11 and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ. The upper electrode UE12 is spaced apart from the upper electrode UE11 and is located on the organic layer OR12 between the lower electrodes LEα and LEβ. The upper electrode UE13 is spaced apart from the upper electrode UE12 and is located on the organic layer OR13. In the illustrated example, the upper electrode UE13 is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ, and between the lower electrodes LEβ and LEγ, but it may be in contact with either one of the lower parts 61. The upper electrode UE14 is spaced apart from the upper electrode UE13 and is located on the organic layer OR14 between the lower electrodes LEβ and LEγ. The upper electrode UE15 is spaced apart from the upper electrode UE14, located on the organic layer OR15, and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEβ and LEγ.
[0081] The cap layer CP10 includes cap layers CP11, CP12, CP13, CP14, and CP15. The cap layer CP11 is located above the upper electrode UE11. The cap layer CP12 is spaced apart from the cap layer CP11 and is located above the upper electrode UE12. The cap layer CP13 is spaced apart from the cap layer CP12 and is located above the upper electrode UE13. The cap layer CP14 is spaced apart from the cap layer CP13 and is located above the upper electrode UE14. The cap layer CP15 is spaced apart from the cap layer CP14 and is located above the upper electrode UE15.
[0082] Subsequently, in step ST22, as shown in Figure 10, a sealing layer SE10 is formed over sub-pixels SPα, SPβ, and SPγ. The sealing layer SE10 is formed to cover the cap layers CP11, CP12, CP13, CP14, CP15, and the partition wall 6. The sealing layer SE10 covering the partition wall 6 is in contact with the lower part of the upper part 62 and with the side surface of the lower part 61. For example, the thickness T10 of the sealing layer SE10 directly above the lower electrode LEα is, for example, 1 μm.
[0083] The sealing layer SE10 has a void Vα facing the sub-pixel SPα of the partition wall 6, a void Vβ facing the sub-pixel SPβ of the partition wall 6, and a void Vγ facing the sub-pixel SPγ of the partition wall 6.
[0084] Here, the process for forming the sealing layer SE10 will be explained with reference to Figure 11. Figure 11 shows a cross-section of the processing substrate including the sub-pixels SPα and SPβ.
[0085] First, in step ST221, a first inorganic insulating layer IL1 is formed as shown in the upper part of Figure 11. The first inorganic insulating layer IL1 is formed, for example, from silicon nitride. The first inorganic insulating layer IL1 is formed, for example, through a CVD (Chemical-Vapor Deposition) process.
[0086] Focusing on the first inorganic insulating layer IL1 located at the sub-pixel SPα, the first inorganic insulating layer IL1 is in contact with the cap layers CP11 and CP12, the side surface of the lower part 61 of the partition wall 6, and the bottom surface of the upper part 62 of the partition wall 6. Furthermore, the first inorganic insulating layer IL1 has closed voids Vα and Vβ below the upper part 62. Directly above the lower electrode LEα, the thickness T11 of the first inorganic insulating layer IL1 is, for example, 3 μm.
[0087] Subsequently, in step ST222, as shown in the middle of Figure 11, anisotropic dry etching is performed on the entire first inorganic insulating layer IL1 without the use of a resist. In anisotropic dry etching, side etching is less likely to occur compared to isotropic dry etching. As a result, the film thickness of the first inorganic insulating layer IL1 located directly above the lower electrodes LEα and LEβ is reduced, as is the film thickness of the first inorganic insulating layer IL1 located directly above the upper part 62 of the partition wall 6. Furthermore, the first inorganic insulating layer IL1 on the leading edges of the voids Vα and Vβ is removed, opening up the voids Vα and Vβ. After anisotropic dry etching, the thickness T12 of the first inorganic insulating layer IL1 directly above the lower electrode LEα is, for example, 0.3 μm.
[0088] Furthermore, the first inorganic insulating layer IL1 located below the upper part 62 of the partition wall 6 is hardly removed. In other words, after anisotropic dry etching, the first inorganic insulating layer IL1 covers the side surface of the lower part 61 of the partition wall 6 and the bottom surface of the upper part 62 of the partition wall 6.
[0089] Subsequently, in step ST223, as shown in the lower part of Figure 11, a second inorganic insulating layer IL2 is formed on the first inorganic insulating layer IL1. The second inorganic insulating layer IL2 is formed, for example, from silicon nitride. The second inorganic insulating layer IL2 is formed, for example, by a CVD process. When the first inorganic insulating layer IL1 and the second inorganic insulating layer IL2 are formed from the same material, the interface between them is hardly noticeable. In other words, the sealing layer SE10 shown in Figure 10 is a laminate of the first inorganic insulating layer IL1 and the second inorganic insulating layer IL2, but can be considered as a single layer. Therefore, unwanted light reflection and scattering within the sealing layer SE10 are suppressed.
[0090] Furthermore, in the illustrated example, the sealing layer SE10 has closed voids Vα and Vβ below the upper part 62. However, comparing the upper cross-sectional view in Figure 11 with the lower cross-sectional view in Figure 11, the cross-sectional area of void Vα immediately after the formation of the second inorganic insulating layer IL2 is smaller than the cross-sectional area of void Vα immediately after the formation of the first inorganic insulating layer IL1. Also, void Vα immediately after the formation of the first inorganic insulating layer IL1 extends widely to the outside of the partition wall 6 and extends diagonally upward from the lower part 61 of the partition wall 6, whereas void Vα immediately after the formation of the second inorganic insulating layer IL2 does not extend much to the outside of the partition wall 6, and the inclination of void Vα tends to decrease. In addition, the film thickness of the sealing layer SE10 increases along the extension line passing through the tip of void Vα, suppressing the occurrence of cracks originating from void Vα.
[0091] Similarly, the cross-sectional area of the void Vβ immediately after the formation of the second inorganic insulating layer IL2 is smaller than the cross-sectional area of the void Vβ immediately after the formation of the first inorganic insulating layer IL1.
[0092] Figure 12 is a cross-sectional view of the sealing layer SE10 formed by the process described with reference to Figure 7. In other words, the sealing layer SE10 is a laminate of a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer. Note that the reference numerals IL1 for the first inorganic insulating layer, IL2 for the second inorganic insulating layer, and IL3 for the third inorganic insulating layer are not shown in the figure. The third inorganic insulating layer is formed, for example, from silicon nitride. The third inorganic insulating layer is formed, for example, by a CVD process. When the second and third inorganic insulating layers are formed from the same material, the interface between them is hardly noticeable.
[0093] Furthermore, in the illustrated example, the sealing layer SE10 has closed voids Vα and Vβ below the upper part 62. However, comparing the lower cross-sectional view in Figure 11 with the cross-sectional view in Figure 12, the cross-sectional area of void Vα immediately after the formation of the third inorganic insulating layer is smaller than the cross-sectional area of void Vα immediately after the formation of the second inorganic insulating layer. Also, void Vα immediately after the formation of the third inorganic insulating layer does not extend much outside the partition wall 6, and the inclination of void Vα tends to become even smaller.
[0094] Figure 13 is another cross-sectional view of the sealing layer SE10 formed through the process described with reference to Figure 7. The sealing layer SE10 is a laminate of the first inorganic insulating layer, the second inorganic insulating layer, and the third inorganic insulating layer, which is the same as the example shown in Figure 12.
[0095] The sealing layer SE10 fills the area below the upper part 62 without creating any voids below it. Because the sealing layer SE10 does not have voids, cracks originating from voids can be prevented.
[0096] The above is a description of step ST22 for forming the sealing layer SE10.
[0097] Next, in step ST23, as shown in Figure 14, the resist 40 is first applied to the entire surface of the sealing layer SE10. At this time, since all of the voids Vα, Vβ, and Vγ are closed, the resist 40 is prevented from flowing into these voids Vα, Vβ, and Vγ. Also, as explained with reference to Figure 13, if the sealing layer SE10 does not have voids, the resist 40 will not flow into unwanted areas.
[0098] Next, this resist 40 is patterned. The resist 40 is, for example, a photosensitive resin, and is a positive type that becomes soluble in the developer solution when exposed to light. Therefore, a mask is prepared that has an opening corresponding to the area where the resist 40 should be removed, and the resist 40 is exposed using this mask. After that, the resist 40 is developed using the developer solution, and the remaining resist is cured. The cured resist corresponds to the first resist 41.
[0099] As shown in Figure 15, the first resist 41 formed by patterning covers the sub-pixel SPα. That is, the first resist 41 is positioned directly above the lower electrode LEα, the organic layer OR11, the upper electrode UE11, and the cap layer CP11. The first resist 41 also extends upward from the sub-pixel SPα to the partition wall 6. Between the sub-pixel SPα and the sub-pixel SPβ, the first resist 41 is positioned on the sub-pixel SPα side (left side of the figure) and exposes the sealing layer SE10 on the sub-pixel SPβ side (right side of the figure). In the illustrated example, the first resist 41 exposes the sealing layer SE10 at sub-pixels SPβ and SPγ.
[0100] Subsequently, in step ST24, as shown in Figure 16, dry etching is performed using the first resist 41 as a mask to remove the encapsulation layer SE10 exposed from the first resist 41. In the illustrated example, the portion of the encapsulation layer SE10 that covers the subpixel SPα (the portion that covers the cap layer CP11) and the portion on the subpixel SPα side (left side of the figure) directly above the partition wall 6 (the portion of the cap layer CP12 that covers the subpixel SPα side) remain. On the other hand, the portion of the encapsulation layer SE10 on the subpixel SPβ side (right side of the figure) directly above the partition wall 6 (the portion that covers the subpixel SPβ side of the cap layer CP12), the portion that covers the subpixel SPβ (the portion that covers the cap layer CP13), the portion that covers the partition wall 6 between subpixel SPβ and subpixel SPγ (the portion that covers the cap layer CP14), and the portion that covers subpixel SPγ (the portion that covers the cap layer CP15) are removed. As a result, a portion of the cap layer CP12, cap layer CP13, cap layer CP14, and cap layer CP15 are exposed from the sealing layer SE10.
[0101] Subsequently, in step ST25, as shown in Figure 17, etching is performed using the first resist 41 as a mask to remove the first thin film 31 exposed from the first resist 41 and the sealing layer SE10. The step of removing the first thin film 31 includes removing a portion of the cap layer CP10, removing a portion of the upper electrode UE10, and removing a portion of the organic layer OR10.
[0102] First, etching is performed using the first resist 41 as a mask to remove the first resist 41 and a portion of the cap layer CP10 exposed from the sealing layer SE10. In the illustrated example, a portion of the cap layer CP12, all of the cap layer CP13, all of the cap layer CP14, and all of the cap layer CP15 are removed. Then, etching is performed using the first resist 41 as a mask to remove the first resist 41, the sealing layer SE10, and a portion of the upper electrode UE10 exposed from the cap layer CP10. In the illustrated example, a portion of the upper electrode UE12, all of the upper electrode UE13, all of the upper electrode UE14, and all of the upper electrode UE15 are removed. Then, etching is performed using the first resist 41 as a mask to remove the first resist 41, the sealing layer SE10, the cap layer CP10, and a portion of the organic layer OR10 exposed from the upper electrode UE10. In the illustrated example, a portion of the organic layer OR12, all of the organic layer OR13, all of the organic layer OR14, and all of the organic layer OR15 are removed.
[0103] As a result, the lower electrode LEβ is exposed in the sub-pixel SPβ, and the lower electrode LEγ is exposed in the sub-pixel SPγ.
[0104] Regarding the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, directly above the upper part 62, the organic layer OR12, upper electrode UE12, cap layer CP12, and sealing layer SE10 remain on the sub-pixel SPα side, while on the sub-pixel SPβ side, the organic layer OR12, upper electrode UE12, cap layer CP12, and sealing layer SE10 are removed. As a result, the sub-pixel SPβ side of the partition wall 6 is exposed. Furthermore, the partition wall 6 between sub-pixels SPβ and SPγ is also exposed.
[0105] Subsequently, in step ST26, the first resist 41 is removed as shown in Figure 18. This exposes the sealing layer SE10 of the sub-pixel SPα. Through these steps ST21 to ST26, the display element 21 is formed in the sub-pixel SPα. The display element 21 consists of a lower electrode LEα, an organic layer OR11 including an emissive layer EMα, an upper electrode UE11, and a cap layer CP11. The display element 21 is also covered by the sealing layer SE10.
[0106] A laminate is formed on the partition wall 6 between the sub-pixels SPα and SPβ, consisting of an organic layer OR12 containing a light-emitting layer EMα, an upper electrode UE12, and a cap layer CP12. This laminate is covered with a sealing layer SE10. In addition, the portion of the partition wall 6 on the side of the sub-pixels SPα is covered with the sealing layer SE10.
[0107] In the example described above, the sub-pixel SPα is one of the sub-pixels SP1, SP2, or SP3 shown in Figure 2. For example, if sub-pixel SPα corresponds to sub-pixel SP1, then the lower electrode LEα corresponds to the first lower electrode LE1, the organic layer OR11 corresponds to the first part OR1a of the first organic layer OR1, the organic layer OR12 corresponds to the second part OR1b of the first organic layer OR1, the light-emitting layer EMα corresponds to the first light-emitting layer EM1, the upper electrode UE11 corresponds to the first part UE1a of the first upper electrode UE1, the upper electrode UE12 corresponds to the second part UE1b of the first upper electrode UE1, the cap layer CP11 corresponds to the first part CP1a of the first cap layer CP1, the cap layer CP12 corresponds to the second part CP1b of the first cap layer CP1, and the sealing layer SE10 corresponds to the sealing layer SE1.
[0108] Here, we will explain the case where the resist 40 flows into the area below the upper part 62 of the partition wall 6 during the patterning process of the resist 40. As described above, if the resist 40 is a positive type, the resist 40 located below the upper part 62 is not exposed because it is in the shadow of the upper part 62, and remains after development. As a result, the sealing layer SE10 that overlaps the remaining resist 40 may not be sufficiently removed in the subsequent dry etching process and may remain. In addition, during the dry etching process, products may appear due to carbon and other substances contained in the remaining resist 40.
[0109] For example, in the above example, if resist 40 remains in the partition wall 6 between sub-pixels SPβ and SPγ, or if the product adheres to the partition wall 6, the sealing layer SE10 may remain on the side surface of the lower part 61, potentially leading to poor electrical connection between the upper electrodes of sub-pixels SPβ and SPγ and the lower part 61. Furthermore, cracks may occur in the sealing layer during the formation of sub-pixels SPβ or SPγ, potentially leading to poor sealing.
[0110] According to this embodiment, the inflow of resist 40 into the lower part 62 of the partition wall 6 is suppressed. Therefore, in the dry etching process of the sealing layer SE10, the sealing layer SE10 of subpixels not covered by the first resist 41 or the sealing layer SE10 covering the partition wall 6 is reliably removed. Moreover, the appearance of unwanted products is suppressed. Therefore, in the subsequent subpixel formation process, the upper electrode and the lower part 61 of the partition wall 6 are reliably electrically connected. Furthermore, in the subsequent subpixel formation process, the display element is reliably sealed with the sealing layer, and the formation of unwanted holes (moisture intrusion paths) is suppressed. Thus, a decrease in reliability can be suppressed.
[0111] According to various studies conducted by the inventors, it was confirmed that by setting the thickness of the sealing layer SE10 formed through multiple CVD processes to 0.5 μm or more (or 0.5 times the thickness T61 or more), closed voids are formed in the sealing layer SE10, or the formation of voids is suppressed.
[0112] Furthermore, when the sealing layer SE10 is formed through multiple CVD processes, even if voids are formed, the cross-sectional area of these voids can be reduced compared to voids in a sealing layer formed through a single CVD process. This suppresses the occurrence of cracks originating from these voids.
[0113] Furthermore, by setting the thickness of the sealing layer overlapping the lower electrode to less than 2 μm (or less than twice the thickness T61 of the lower part 61), a decrease in the transmittance of light emitted from the display element can be suppressed.
[0114] Furthermore, after multiple CVD processes, the interface between the stacked inorganic insulating layers is almost imperceptible in the encapsulation layer SE10. This makes it possible to suppress unwanted reflections and scattering within the encapsulation layer SE10.
[0115] As described above, according to this embodiment, it is possible to provide a display device and a method for manufacturing a display device that can suppress a decrease in reliability and improve manufacturing yield.
[0116] All display devices and methods for manufacturing display devices that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices and methods for manufacturing display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.
[0117] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.
[0118] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]
[0119] DSP…display device 10...Substrate 12...Insulating layer 5...Rib 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3, SPα, SPβ, SPγ... Sub-pixels 20, 21, 22, 23… Display elements (organic EL elements) LE, LE1, LE2, LE3, LEα, LEβ, LEγ... Lower electrode (anode) UE, UE1, UE2, UE3, UE10... Upper electrode (cathode) OR,OR1,OR2,OR3,OR10…Organic layer CP, CP1, CP2, CP3, CP10… Cap layers SE, SE1, SE2, SE3, SE10…Sealing layer
Claims
1. circuit board and A first lower electrode and a second lower electrode are positioned above the substrate, A rib having a first opening that overlaps with the first lower electrode and a second opening that overlaps with the second lower electrode, A partition wall having a lower portion positioned on the rib between the first opening and the second opening, and an upper portion positioned on the lower portion and protruding from the side surface of the lower portion, Displaced on the first lower electrode in the first aperture, the first organic layer includes a first light-emitting layer, A second organic layer is provided in the second opening, which is positioned on the second lower electrode and includes a second light-emitting layer made of a different material from the first light-emitting layer. A first upper electrode is placed on the first organic layer and is in contact with the lower part of the partition wall, A second upper electrode is placed on the second organic layer and is in contact with the lower part of the partition wall, A first sealing layer is positioned above the first upper electrode and in contact with the lower part of the partition wall, The device comprises a second sealing layer positioned above the second upper electrode, in contact with the lower part of the partition wall, and spaced apart from the first sealing layer, A display device in which, directly above the first lower electrode, the thickness of the first sealing layer is 0.5 times or more and less than 2 times the thickness of the lower part of the partition wall.
2. The display device according to claim 1, wherein the thickness of the first sealing layer is 0.5 μm or more and less than 2 μm.
3. The display device according to claim 1, wherein the first sealing layer and the second sealing layer are formed of an inorganic insulating material.
4. The display device according to claim 1, wherein the first sealing layer and the second sealing layer are formed of silicon nitride.
5. The display device according to claim 1, wherein each of the first sealing layer and the second sealing layer has a closed void below the upper part of the partition wall.
6. The display device according to claim 1, wherein each of the first sealing layer and the second sealing layer is filled below the upper part of the partition wall without forming any voids.
7. moreover, A first cap layer is placed on the first upper electrode and covered with the first sealing layer, The display device according to claim 1, comprising: a second cap layer disposed on the second upper electrode and covered with the second sealing layer.
8. Each of the first organic layer, the first upper electrode, and the first cap layer has a first portion located below the upper part of the partition wall and a second portion located above the upper part and spaced apart from the first portion. The display device according to claim 7, wherein the first sealing layer is in contact with the first and second portions of the first cap layer.
9. Each of the second organic layer, the second upper electrode, and the second cap layer has a first portion located below the upper part of the partition wall and a second portion located above the upper part and spaced apart from the first portion. The display device according to claim 8, wherein the second sealing layer is in contact with the first and second portions of the second cap layer.
10. The second portion of the first organic layer is spaced apart from the second portion of the second organic layer, The second portion of the first upper electrode is spaced apart from the second portion of the second upper electrode, The display device according to claim 9, wherein the second portion of the first cap layer is spaced apart from the second portion of the second cap layer.