Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device including a 3C-SiC single crystal layer having excellent crystallinity, in which production of a twin crystal is suppressed.SOLUTION: A semiconductor device includes a single crystal SiC substrate 11 of 4H or 6H having a first principal surface, and a single crystal 3C-SiC layer 12 provided on the first principal surface. The first principal surface 11a is inclined at a prescribed angle in a prescribed direction from a (0001) plane or a (000-1) plane, to form a step, and a height of the step is equal to one unit cell length of a crystal structure of the SiC substrate.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a single-crystal semiconductor layer formed by epitaxial crystal growth on a semiconductor substrate and a method for manufacturing the same.

Background Art

[0002] SiC single crystals can take various polytypes (crystal polymorphs). The 3C (cubic)-SiC single crystal is used as a channel material for transistors, a substrate for epitaxial growth of gallium nitride single crystals, a hydrolysis catalyst, and the like. These 3C (cubic)-SiC single crystals are manufactured by epitaxial growth on Si substrates or 4H (hexagonal)-SiC substrates by methods such as thermal CVD (chemical vapor deposition).

[0003] The 3C-SiC single crystal layer epitaxially grown on an Si substrate or a 4H-SiC substrate often has problems with crystal quality. When growing on an Si substrate, due to the difference in lattice constants between Si and 3C-SiC, dislocations are likely to occur in the 3C-SiC single crystal layer. When growing on a 4H-SiC substrate, in the growth on a substrate whose main plane is (0001) or (000-1), two types of crystals (hereinafter, these two crystals are also referred to as X and Y) in which 3C-SiC is rotated 60 degrees with respect to each other in the plane grow. What grows with X and Y adjacent to each other is called a twin. The interface where X and Y are adjacent is known to be a crystal defect. In order to obtain a crystal without twins, there is a method of using the difference in the growth rates of the X and Y crystals and growing for a long time so that one of them covers the entire surface, and forming a crystal without twins in the outermost layer (see, for example, Non-Patent Document 1). When this method is used, the growth layer becomes thick. Usually, at least about 1 μm is required even if it is thin. Therefore, the cost is high. In addition, twins and defects remain in the growth film at the initial stage of growth, so the characteristics deteriorate significantly when used as a channel of a transistor.

[0004] It is known that a 3C-SiC single crystal layer can be grown on a 4H-SiC substrate with the (0001) plane and (000-1) plane tilted at a specific angle in a specific direction (see, for example, Patent Documents 1 and 2, and Non-Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-178762 [Patent Document 2] Japanese Patent Application Publication No. 11-162850 [Non-patent literature]

[0006] [Non-Patent Document 1] K. Nishino et al., Jpn. J. Appl. Phys (1997) vol. 36, 5202 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] Patent Document 2 discloses that a 3C-SiC single crystal layer with good crystalline properties can be epitaxially grown by using a 4H-SiC substrate and heating the (0001) plane and (000-1) plane, which are tilted at a specific angle in a specific direction, to a temperature of 800°C to 1300°C, thereby cleaning the crystal growth surface to a √3 × √3 surface rearrangement structure. However, it does not describe how to suppress the formation of twins.

[0008] The object of the present invention is to provide a semiconductor device having a 3C-SiC single crystal layer with good crystallinity in which twin formation is suppressed, and a method for manufacturing the same. [Means for solving the problem]

[0009] According to one aspect of the present invention, a semiconductor device is provided comprising a 4H or 6H single-crystal SiC substrate having a first main surface, and a single-crystal 3C-SiC layer provided on the first main surface, wherein the first main surface has steps formed on it by being inclined at a predetermined angle in a predetermined direction from the (0001) plane or the (000-1) plane, and the height of the steps is the length of one unit cell of the crystal structure of the SiC substrate.

[0010] According to the above embodiment, a step with a height equal to one unit cell length of the crystal structure of the SiC substrate is formed on a first main surface that is inclined at a predetermined angle in a predetermined direction from the (0001) plane or (000-1) plane of a 4H or 6H single crystal SiC substrate. As a result, the orientation directions of the Si-C atomic pairs on the two terraces flanking the step edge are aligned, and the orientation directions of the Si-C atomic pairs of the epitaxially grown 3C-SiC layer thereon are also aligned. This suppresses the formation of twins in the 3C-SiC layer and makes it possible to provide a semiconductor device having a high-quality single-crystal 3C-SiC layer.

[0011] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the steps of: preparing a 4H or 6H single-crystal SiC substrate having a first main surface inclined at a predetermined angle in a predetermined direction from a (0001) plane or a (000-1) plane; etching the first main surface of the SiC substrate in a gas atmosphere containing hydrogen to set the step height on the first main surface to the length of one unit cell of the crystal structure of the SiC substrate; and epitaxially growing a single-crystal 3C-SiC layer on the first main surface after the etching process.

[0012] According to the above-described other aspect, using a 4H or 6H single-crystal SiC substrate having a first main surface inclined at a predetermined angle in a predetermined direction from the (0001) plane or the (000-1) plane, the first main surface is etched in a gas atmosphere containing hydrogen to form a step having a height of one unit cell length, and the orientation directions of the Si-C atom pairs of the two terraces sandwiching the step end are aligned. By epitaxially growing a 3C-SiC layer thereon, the orientation direction of the Si-C atom pairs of the 3C-SiC layer is formed to be aligned with the orientation direction of the Si-C atom pairs of the SiC substrate. Thereby, a high-quality single-crystal 3C-SiC layer in which the generation of twins in the 3C-SiC layer is suppressed can be formed.

Brief Description of the Drawings

[0013] [Figure 1] It is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment of the present invention. [Figure 2] It is an explanatory diagram of epitaxial growth of a 3C-SiC layer on the main surface of a 4H-SiC substrate. [Figure 3] It is a flowchart of a manufacturing method of a semiconductor device according to the first embodiment of the present invention. [Figure 4] It is an AFM cross-sectional profile of the main surface (off-plane) of a 4H-SiC substrate after hydrogen etching treatment. [Figure 5] It is a diagram showing an X-ray diffraction φ scan in the 113 reflection of a 3C-SiC layer. [Figure 6] It is a cross-sectional TEM photograph of Example 2. [Figure 7] It is a diagram showing the temperature changes of the hole mobility and sheet carrier concentration of the 3C-SiC layers of Example 1 and Comparative Example 1. [Figure 8] It is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment of the present invention. [Figure 9] It is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described based on the drawings. For elements common among a plurality of drawings, the same reference numerals are given, and repeated detailed descriptions thereof are omitted.

[0015] [First Embodiment] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device 10 includes a 4H or 6H single-crystal SiC substrate (4H-SiC or 6H-SiC substrate) 11 and a single-crystal 3C-SiC layer 12 on its main surface 11a. The notations 3C-, 4H-, and 6H- of 3C-SiC, 4H-SiC, and 6H-SiC are based on the Ransdell notation method, and the leading numbers indicate the number of one unit cell in the (0001) direction of three types of atoms (Si-C atom pairs) in the hexagonal close-packed structure, namely, "A", "B", and "C". The "C" and "H" in 3C- and 4H- represent cubic and hexagonal, respectively. 3C-SiC is composed of one unit cell in the (0001) direction in the order of A, B, C, 4H-SiC is composed of A, B, C, B in this order, and 6H-SiC is composed of A, B, C, A, C, B. The main surface (off-surface) 11a of the SiC substrate 11 is an off-surface inclined at a predetermined angle in a predetermined orientation from the (000-1) plane. The predetermined orientation (i.e., the tilt orientation) is within a range of ±10 degrees from the <01-10> direction, preferably within a range of ±7 degrees, more preferably within a range of ±5 degrees, and most preferably within a range of ±3 degrees. The predetermined angle (i.e., the tilt angle) is within a range of 0.05 degrees or more and 0.24 degrees or less from the (000-1) plane, preferably within a range of 0.06 degrees or more and 0.20 degrees or less, more preferably within a range of 0.08 degrees or more and 0.19 degrees or less, and most preferably within a range of 0.11 degrees or more and 0.17 degrees or less. The <01-10> direction represents six equivalent directions, namely, [10-10], [1-100], [0-110], [-1010], [-1100], and [01-10] directions. The 3C-SiC layer 12 is joined to the main surface (off-surface) 11a of the SiC substrate 11 such that the substantially (111) plane is joined.

[0016] A step is formed on the main surface (off-surface) 11a of the SiC substrate 11 at the boundary of the 3C-SiC layer 12. The height of the step is the length of one unit cell in the crystal structure of the SiC substrate. That is, if the SiC substrate 11 is a 4H-SiC single crystal substrate, the length of one unit cell is 1.0 nm, and if the SiC substrate 11 is a 6H-SiC single crystal substrate, the length of one unit cell is 1.5 nm.

[0017] The inclination angle of the main surface (off-surface) 11a of the SiC substrate 11 can be determined by finding the distance between adjacent steps, i.e., the terrace spacing and the step height. These can be determined by observing a transmission electron microscope (TEM) image of the cross-section of the semiconductor device 10, or, if the device is still in the manufacturing process, by observing the main surface (off-surface) 11a of the SiC substrate 11 with an AFM.

[0018] Figure 2 is an explanatory diagram of the epitaxial growth of a 3C-SiC layer on the main surface of a 4H-SiC substrate. Figure 2 is a schematic cross-sectional view from the [11-20] direction. The shaded lines in Figure 2 indicate the crystal axis, and the thick arrows indicate the direction of its arrangement. Referring to Figure 2(a), in the semiconductor device 10 of this embodiment, a step 11s is formed on the main surface (off-surface) 11a of the 4H-SiC substrate 11. The height of the step 11s (indicated by double arrows) is the length of one unit cell, and the arrangement direction of Si-C atomic pairs is aligned between the terrace 11t1 and terrace 11t2 that sandwich the step 11s. The arrangement direction of Si-C atomic pairs in the 3C-SiC layer 12 formed by epitaxial growth on the main surface 11a is aligned with the arrangement direction of Si-C atomic pairs in the SiC substrate 11. As a result, the 3C-SiC layer 12 has the same orientation of Si-C atom pairs on both sides of step 11s, suppressing twin formation and forming a single domain. Similarly, when the SiC substrate 11 is a 6H-SiC single crystal substrate, the 3C-SiC layer 12 grows epitaxially, suppressing twin formation and forming a single domain.

[0019] On the other hand, as shown in Figure 2(b), in a semiconductor device 100 not included in this embodiment, if the main surface (off-surface) of the 4H-SiC substrate 101 is tilted in the direction of <11-20> from the (000-1) plane, for example, the height of step 101s (indicated by double arrows) becomes half a unit cell length, and the arrangement directions of Si-C atomic pairs are different between terraces 101t2 and t3 that sandwich step 101s. The arrangement directions of Si-C atomic pairs in the 3C-SiC layer 102 formed on the main surface 101a by epitaxial growth are different, generating twins and forming the grain boundary 102b. Multidomains are formed in the 3C-SiC layer 102.

[0020] Returning to Figure 1, the 3C-SiC layer 12 is preferably less than 200 nm thick, considering the balance between the transistor's transconductance and the generated electron concentration. As explained in Figure 2(a), a 3C-SiC layer 12 with good crystallinity can be formed in a single domain on the main surface of the 4H-SiC substrate, so a thickness of 2 nm to 100 nm is more preferable.

[0021] The 4H or 6H single-crystal SiC substrate 11 is semi-insulating, and the 3C-SiC layer 12 epitaxially grown thereon, as described in the examples, induces a two-dimensional electron gas at room temperature without applying a voltage to the interface with the SiC substrate 11.

[0022] At room temperature, the 3C-SiC layer 12 has a hole mobility of 400 cm² at the interface with the SiC substrate 11. 2 A value of / Vs or higher is preferable from the standpoint of increasing the operating speed of the transistor.

[0023] As explained in Figure 2(a), the 3C-SiC layer 12 can be formed on the main surface of the 4H-SiC substrate as a single domain with good crystallinity, so it is preferable that the twinning ratio is 10% or less. The twinning ratio is determined by measuring the diffraction signal intensity of the 113 reflection of the 3C-SiC layer by X-ray diffraction φ scan and calculating the ratio using the following equation 1. Contamination ratio (%) = (113 reflection diffraction signal intensity from one twin) / (sum of 113 reflection diffraction signal intensities from both twins / 2) × 100 ... (1)

[0024] In terms of good crystallinity, it is preferable that the 3C-SiC layer 12 has a full width at half maximum (FWHM) of the rocking curve (ω scan) in the 111 reflection of 3C-SiC measured by an X-ray diffractometer of 70 seconds or less.

[0025] Figure 3 is a flowchart of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. The method for manufacturing a semiconductor device according to the first embodiment will be explained with reference to Figure 3 in conjunction with Figures 1 and 2.

[0026] First, a 4H or 6H single-crystal SiC substrate 11 is prepared (S100). Specifically, the 4H or 6H single-crystal SiC substrate 11 has a main surface that is an off-plane tilted from the (000-1) plane (C plane) in a predetermined direction at a predetermined angle. The main surface has a predetermined orientation within ±10 degrees from the <01-10> direction, and a predetermined angle within 0.05 degrees to 0.24 degrees from the (000-1) plane. Such a 4H or 6H single-crystal SiC substrate can be obtained by splicing and polishing an ingot with a wire saw so that it has the above orientation and angle.

[0027] Next, the main surface of the SiC substrate 11 is etched under a hydrogen-containing gas atmosphere (S110). Specifically, after cleaning the single-crystal SiC substrate prepared in S100 (for example, RCA cleaning), the single-crystal SiC substrate is placed in the reaction furnace of a thermal CVD apparatus, hydrogen gas is introduced while reducing the pressure inside the reaction furnace (for example, so that the pressure is 5kPa to 50kPa (preferably 15kPa to 25kPa)), the substrate temperature is set to a range of, for example, 1280°C to 1470°C, preferably 1300°C to 1450°C, more preferably 1320°C to 1430°C, and most preferably 1340°C to 1410°C, and the substrate temperature is held for a period of 1 minute to 2 hours, preferably 5 minutes to 1 hour, more preferably 10 minutes to 45 minutes, and most preferably 15 minutes to 30 minutes, and the main surface (off-surface) is etched by thermal etching.

[0028] As a result of this etching process, steps are formed on the main surface (off-surface) 11a with a step height of 4H or 6H, which corresponds to the length of one unit cell in the crystal structure of the single-crystal SiC substrate, as shown in Figure 2(a).

[0029] Next, a single-crystal 3C-SiC layer 12 is epitaxially grown on the main surface 11a of the SiC substrate by thermal CVD (S120). Specifically, after exhausting the atmospheric gas from the etching process in S110 (preferably immediately after), the raw material gas is introduced into the reaction furnace of the hot-wall type thermal CVD apparatus. SiH4 and Si2H6 can be used as the silicon (Si) source, and C3H8 can be used as the carbon (C) source. H2 is introduced as the carrier gas, and for example, the substrate temperature can be selected from the range of 1280°C to 1470°C, preferably from the range of 1300°C to 1450°C, more preferably from the range of 1320°C to 1430°C, and most preferably from the range of 1340°C to 1410°C, to heat the SiC substrate and the inner wall of the reaction furnace and epitaxially grow the 3C-SiC layer 12. The ratio of C atoms to Si atoms in the raw material gas (C / Si ratio) is preferably set to a range of 0.8 to 5. The C / Si ratio can be controlled by the flow rate ratio of the raw material gas, and there is no limit to the total flow rate, but it is preferable to set the growth rate of the 3C-SiC layer 12 to a range of 1 μm / Hr to 6 μm / Hr. The thickness of the 3C-SiC layer 12 is controlled, for example, by the reaction time. The raw material gas may be CH3, C2H5, or H2SiCl2, and the carrier gas may be Ar. As a result, the 3C-SiC layer 12 is formed on the main surface of a 4H or 6H single-crystal SiC substrate, with the arrangement direction of Si-C atom pairs (thick arrows) aligned on terraces 11t1 and 11t2 sandwiching step 11s, as shown in Figure 2(a), and a single-domain 3C-SiC layer 12 of the single crystal is formed.

[0030] Furthermore, when forming transistors or diodes on such 4H or 6H-SiC single crystal substrates / 3C-SiC single crystal layers on epitaxial wafers, known semiconductor processes can be used.

[0031] [Examples 1 and 2] A 4H-SiC single crystal substrate (size 5mm × 5mm) was prepared with the main plane (off-plane) tilted 0.14° from the (000-1) plane in the [01-10] direction. The semi-insulating 4H-SiC single crystal substrate was sonicated in acetone for 10 minutes, followed by RCA cleaning. The cleaned 4H-SiC substrate was placed in the reactor of a hot-wall type thermal CVD apparatus, hydrogen gas was introduced, and the substrate temperature was set to 1380°C for 30 minutes of hydrogen etching. While maintaining the amount of hydrogen gas introduced into the reactor, C3H8 and SiH4 were immediately introduced as raw material gases, with the flow rate ratio set to a C / Si ratio of 0.85. A 3C-SiC layer was epitaxially grown at a substrate temperature of 1380°C for 1 minute and 20 seconds, obtaining epitaxial wafers with 3C-SiC layer thicknesses of 30nm (Example 1) and 10nm (Example 2).

[0032] [Comparative Example 1] Comparative Example 1 was formed in the same manner as the example, except that a 4H-SiC substrate (size 5mm x 5mm) was used in which the main plane (off-plane) was tilted 0.14° from the (000-1) plane in the [11-20] direction. Comparative Example 1 was defined as having a 3C-SiC single crystal layer thickness of 30nm.

[0033] Figure 4 shows the AFM image (top) and cross-sectional profile (bottom) of the main surface (off-surface) of the 4H-SiC substrate after hydrogen etching. Figure 4(a) is an example, and Figure 4(b) is a comparative example.

[0034] Referring to Figure 4(a), it can be seen that a step with a height of 1 nm is formed on the main surface (off-surface) tilted 0.14° in the [01-10] direction after hydrogen etching in the example. Since the length of the c axis of the 4H-SiC single crystal is 1.008 nm, it can be seen that the step has a height of 1 unit cell length. On the other hand, referring to Figure 4(b), it can be seen that a step with a height of 0.5 nm is formed on the main surface (off-surface) tilted 0.14° in the [11-20] direction after hydrogen etching in the comparative example, and the step has a height of 0.5 unit cell length.

[0035] Figure 5 shows the X-ray diffraction φ scan graph for the 113 reflection of the 3C-SiC layer. Figure 5(a) is Example 1, and Figure 5(b) is Comparative Example 1. The rocking curve was measured using an X-ray diffractometer (source: Cu, crystal monochromator: Ge220, Cu Kα rays), and an in-plane scan (φ scan) was performed on the 3C-SiC 113 reflection while changing the tilt (ψ) angle from 29.29° to 29.69° in 0.2° increments to obtain the φ scan graph.

[0036] Referring to Figure 5(a), the φ scan of the 113 reflection of the 3C-SiC layer in Example 1 showed peaks at 61°, 181°, and 301°, with three peaks observed. The 113 reflection of a 3C-SiC single crystal has 3-fold rotational symmetry. Since only three peaks were observed, it can be seen that the 3C-SiC layer in Example 1 is formed as a single domain, meaning that twinning is suppressed. On the other hand, referring to Figure 5(b), the φ scan of the 113 reflection of the 3C-SiC single crystal layer in Comparative Example 1 showed peaks at 2°, 62°, 122°, 182°, 242°, and 302°, with six peaks observed. This indicates that the 3C-SiC single crystal layer in Comparative Example 1 is formed as a multi-domain structure rotated 60° relative to each other, meaning that twinning is formed.

[0037] The rocking curve (ω scan) of the 111 reflection of the 3C-SiC layer was measured. The full width at half maximum (FMAX) of Example 1 was 8.7 seconds, which is extremely small and indicates that a very high-quality single-crystal 3C-SiC layer was formed on the 4H-SiC single-crystal substrate.

[0038] Figure 6 is a cross-sectional TEM image of Example 2. Figure 6 is a cross-sectional view in the [000-1] direction of a 4H-SiC single crystal substrate (indicated as "4H") and a 3C-SiC layer (indicated as "3C") on top of it. Referring to Figure 6, it can be seen that a heterointerface is formed at the boundary between the 4H-SiC single crystal substrate and the 3C-SiC layer. Furthermore, the 3C-SiC layer has Si atoms (or Si-C atom pairs) arranged in an orderly manner, appearing like individual grains. This indicates that even though the 3C-SiC single crystal layer is extremely thin, its crystallinity is of extremely high quality. Conventionally, a thick film of several μm was formed to obtain high-quality 3C-SiC crystals, but this is no longer necessary.

[0039] Figure 7 shows the temperature dependence of the hole mobility and sheet carrier concentration of the 3C-SiC layers in Example 1 and Comparative Example 1. The hole mobility and sheet carrier concentration were measured using a Hall effect measuring device (Model ResiTest8300, manufactured by Toyo Technica Co., Ltd.).

[0040] Referring to Figure 7, the hole mobility μ H At room temperature (297K), Example 1 (indicated by ●) was 780 cm². 2 / Vs, and Comparative Example 1 (indicated by ○) is 190cm 2 It can be seen that it is significantly higher than / Vs.

[0041] The sheet carrier concentration in Example 1 (indicated by ▲) is found to be almost constant in the measurement range of 20K to 560K. This indicates that the majority carriers are degenerate electrons. Measured hole mobility μ in Example 1. H At room temperature (297K), it is 780cm 2 / Vs and typical values ​​of the hole mobility of electrons present in the impurity band (maximum 10cm) 2 Considering that the electron density is extremely high (approximately / Vs), it can be inferred that a two-dimensional electron gas is induced in the 3C-SiC layer at the interface with the 4H-SiC single crystal substrate.

[0042] [Examples 3-7 and Comparative Examples 2-3] Using 4H-SiC single crystal substrates with different tilt orientations and tilt angles from the (000-1) plane, 3C-SiC layers were epitaxially grown on the 4H-SiC single crystal substrates in the same manner as in Example 1. The twinning ratio of the 3C-SiC layer and the full width at half maximum of the 111 reflection rocking curve were measured in the same manner as in Example 1. [Table 1]

[0043] Examples 3-7 showed significantly lower twinning ratios and significantly lower full width at half maximum (FMAX) values ​​of the 111 reflection rocking curves compared to Comparative Examples 2-3. In Examples 3-5, the minimum tilt angle was 0.14° in the range of 0.05-0.24°, indicating that the range around 0.14° (e.g., 0.11° to 0.17°) is the most preferable.

[0044] In Examples 1-7 and Comparative Examples 1-3, 4H-SiC single crystal substrates were used, but it is presumed that similar results could be obtained if 6H-SiC single crystal substrates were used instead.

[0045] [Second Embodiment] Figure 8 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention. Referring to Figure 8, the semiconductor device 20 comprises a 4H or 6H single-crystal SiC substrate 21 and a single-crystal 3C-SiC layer 22 on its main surface 21a. The main surface (off-surface) 21a of the SiC substrate 21 is an off-surface tilted at a predetermined angle in a predetermined direction from the (0001) plane (Si plane). The predetermined orientation is within ±10 degrees from the <01-10> direction, and the predetermined angle is in the range of 0.05 degrees or more and 0.24 degrees or less from the (000-1) plane. A step is formed on the main surface 21a of the SiC substrate 21 at the boundary of the 3C-SiC layer 12. The height of the step is the length of one unit cell in the crystal structure of the SiC substrate. In other words, if the SiC substrate 11 is a 4H-SiC single crystal substrate, the unit cell length is 1.0 nm, and if the SiC substrate 11 is a 6H-SiC single crystal substrate, the unit cell length is 1.5 nm.

[0046] The semiconductor device 20 according to the second embodiment is the same as the semiconductor device 10 according to the first embodiment shown in Figure 1, except that the off-plane is a plane that is inclined from the (0001) plane (Si plane) in a predetermined direction at a predetermined angle as described above, and its manufacturing method is also the same. Hereinafter, only the differences from the first embodiment will be described, and the explanation of similar matters will be omitted.

[0047] The 3C-SiC layer 22 is preferably 200 nm or less in thickness, and more preferably 2 nm to 100 nm in thickness, considering the balance between the transconductance and electron concentration of the transistor.

[0048] A 4H or 6H single-crystal SiC substrate 21 is semi-insulating, and a 3C-SiC layer 22 epitaxially grown on it exhibits a P-type conductivity at room temperature. The 3C-SiC layer 22 has a hole mobility of 15 cm at room temperature. 2 The Vs is greater than or equal to 30,000 Ω / □, and the sheet resistance is 30,000 Ω / □ or less. The 3C-SiC layer 22 shows an increase in sheet carrier concentration of 500% or less at 100°C compared to room temperature.

[0049] [Example 8] A 4H-SiC single crystal substrate (size 5mm x 5mm) was prepared with the main plane (off-plane) tilted 0.08° from the (0001) plane in the [01-10] direction. The semi-insulating 4H-SiC single crystal substrate was sonicated in acetone for 10 minutes, followed by RCA cleaning. The cleaned 4H-SiC substrate was placed in the reactor of a hot-wall type thermal CVD apparatus, hydrogen gas was introduced, and the substrate temperature was set to 1370°C for 30 minutes of hydrogen etching. While maintaining the amount of hydrogen gas introduced into the reactor, C3H8 and SiH4 were immediately introduced as raw material gases, with the flow rate ratio set to a C / Si ratio of 1. A 3C-SiC layer was epitaxially grown at a substrate temperature of 1370°C for 22 seconds to obtain an epitaxial wafer with a 3C-SiC layer thickness of 30nm.

[0050] Separately from this process, a substrate with the same properties was prepared, subjected to hydrogen etching using the same procedure as above, cooled, and then removed to obtain a hydrogen-etched 4H-SiC single crystal substrate.

[0051] [Comparative Example 4] In the comparative example, an epitaxial wafer was formed in the same manner as in Example 8, except that a 4H-SiC substrate (size 5mm x 5mm) was used in which the main plane (off-plane) was tilted 0.076° from the (0001) plane in the [11-20] direction. Comparative Example 4 was a 3C-SiC single crystal layer with a thickness of 30nm. Separately from this process, a substrate with the same properties was prepared, hydrogen-etched using the same procedure as above, cooled, and then removed to prepare a hydrogen-etched 4H-SiC single crystal substrate.

[0052] After hydrogen etching, the step height formed on the surface of the hydrogen-etched 4H-SiC single crystal substrate, which was cooled and removed, was 1 nm in Example 8 and 0.5 nm in Comparative Example 4. These correspond to a 1-unit cell height and a 0.5-unit cell height, respectively.

[0053] The twinning ratio in the 3C-SiC layer was 0.22% in Example 8 and 48% in Comparative Example 4.

[0054] [Third Embodiment] Figure 9 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. Referring to Figure 9, the semiconductor device 30 comprises a 4H-SiC or 6H-SiC substrate 11, a single-crystal 3C-SiC layer 12 on its main surface 11a, and ohmic electrodes 31, 32 and a Schottky electrode 33 on the 3C-SiC layer 12. The bonding of the 4H-SiC or 6H-SiC substrate 11 and the 3C-SiC layer 12 at the main surface 11a is the same as that of the semiconductor device 10 in the first embodiment, with the C-plane of the 4H-SiC or 6H-SiC substrate 11 and the Si-plane of the 3C-SiC layer 12 being bonded. A two-dimensional electron gas is generated on the 3C-SiC layer 12 side of the main surface 11a. The semiconductor device 30 can be configured as a transistor in which the current flowing from the source electrode 31 through the two-dimensional electron gas to the drain electrode 32 is controlled by the gate electrode 33, by using the ohmic electrode 31 as the source electrode, the ohmic electrode 32 as the drain electrode, and the Schottky electrode 33 as the gate electrode.

[0055] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the present invention as described in the claims. [Explanation of Symbols]

[0056] 10, 20, 30 Semiconductor equipment 11,21 SiC substrates 12,22 3C-SiC layer

Claims

1. A 4H or 6H single crystal SiC substrate having a first main surface, The first main surface comprises a single-crystal 3C-SiC layer, The first main surface has steps formed on it that are inclined from the (000-1) plane in a predetermined direction at a predetermined angle, and the height of the steps is the length of one unit cell in the crystal structure of the SiC substrate. The first principal surface is an off-surface inclined from the (000-1) surface in the predetermined direction at the predetermined angle, The predetermined direction is within ±10 degrees from the <01-10> direction, A semiconductor device in which the predetermined angle is in the range of 0.05 degrees or more and 0.24 degrees or less from the (000-1) plane.

2. The semiconductor device according to claim 1, wherein the SiC substrate is a 4H-SiC substrate.

3. The semiconductor device according to claim 2, wherein the 3C-SiC layer is formed by inducing a two-dimensional electron gas at the interface with the 4H-SiC substrate at room temperature without applying a voltage.

4. The 3C-SiC layer has a hole mobility of 400 cm at room temperature at the interface with the 4H-SiC substrate. 2 The semiconductor device according to claim 2, wherein the value is greater than or equal to / Vs.

5. The semiconductor device according to claim 1, wherein the 3C-SiC layer has a twinning ratio of 10% or less.

6. The semiconductor device according to claim 1, wherein the 3C-SiC layer has a thickness of 200 nm or less.

7. The semiconductor device according to claim 1, wherein the 3C-SiC layer has a full width at half maximum of 70 seconds or less of the rocking curve in 111 reflection.

8. A 4H or 6H single crystal SiC substrate having a first main surface, The first main surface comprises a single-crystal 3C-SiC layer, The first main surface has steps formed on it that are inclined from the (0001) plane at a predetermined angle in a predetermined direction, and the height of the steps is the length of one unit cell in the crystal structure of the SiC substrate. The first principal surface is an off-surface inclined from the (0001) surface in the predetermined direction at the predetermined angle, The predetermined direction is within ±10 degrees from the <01-10> direction, A semiconductor device in which the predetermined angle is in the range of 0.05 degrees or more and 0.24 degrees or less from the (0001) plane.

9. The semiconductor device according to claim 8, wherein the SiC substrate is a 4H-SiC substrate.

10. The semiconductor device according to claim 8 or 9, wherein the 3C-SiC layer exhibits a P-type conductivity at room temperature.

11. The 3C-SiC layer has a hole mobility of 15 cm at room temperature. ２ The semiconductor device according to claim 8 or 9, wherein the coefficient of force is greater than or equal to / Vs and the sheet resistance is less than or equal to 30,000 Ω / □.

12. The semiconductor device according to claim 8 or 9, wherein the 3C-SiC layer exhibits an increase in sheet carrier concentration of 500% or less at 100°C compared to room temperature.

13. The semiconductor device according to claim 8 or 9, wherein the 3C-SiC layer has a thickness of 200 nm or less.

14. A step of preparing a 4H or 6H single crystal SiC substrate having a first main plane inclined at a predetermined angle in a predetermined direction from the (000-1) plane, A step of etching the first main surface of the SiC substrate under a gas atmosphere containing hydrogen so that the step height on the first main surface is the length of one unit cell in the crystal structure of the SiC substrate, The process includes the step of epitaxially growing a single-crystal 3C-SiC layer on the first main surface after the etching process, The first main surface is an off-surface inclined from the (000-1) surface in the predetermined direction at the predetermined angle, The predetermined direction is within ±10 degrees from the <01-10> direction, A method for manufacturing a semiconductor device, wherein the predetermined angle is in the range of 0.05 degrees or more and 0.24 degrees or less from the (000-1) plane.

15. A step of preparing a 4H or 6H single crystal SiC substrate having a first main plane inclined at a predetermined angle in a predetermined direction from the (0001) plane, A step of etching the first main surface of the SiC substrate under a gas atmosphere containing hydrogen so that the step height on the first main surface is the length of one unit cell in the crystal structure of the SiC substrate, The process includes the step of epitaxially growing a single-crystal 3C-SiC layer on the first main surface after the etching process, The first principal surface is an off-surface inclined from the (0001) surface in the predetermined direction at the predetermined angle, The predetermined direction is within ±10 degrees from the <01-10> direction, A method for manufacturing a semiconductor device, wherein the predetermined angle is in the range of 0.05 degrees or more and 0.24 degrees or less from the (0001) plane.

16. The method for manufacturing a semiconductor device according to claim 14 or 15, wherein the etching process includes holding the etching process at 35 kPa.

17. The method for manufacturing a semiconductor device according to claim 14 or 15, wherein the SiC substrate is a 4H-SiC substrate.

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