Semiconductor image CR device

Abstract

Provided is a semiconductor image sensor device in which the occurrence of leakage current due to interface states is prevented and which operates stably without a decrease in the detection sensitivity of a photodiode.　On the surface side of a silicon support substrate (101), there are provided a first buried well layer (102-1) having a first impurity concentration of a second conductivity type at a first position (A) which becomes a back gate of a MOS transistor element (114), a second buried well layer (102-2) having the first impurity concentration of the second conductivity type at a second position (B) which is spaced apart from the first position (A) and does not face the back gate, a third buried well layer (103) having a second impurity concentration of a first conductivity type that is separated from the first buried well layer (102-1) by a predetermined distance in the first direction and second direction and formed close to the second buried well layer (102-2) to surround the first buried well layer (102-1) from both sides, and a fourth buried well layer (104) having a third impurity concentration of the first conductivity type that is formed at a deeper position than the first buried well layer (102-1) and in contact with the bottom surfaces of the first buried well layer (102-1) and the third buried well layer (103).

Description

Technical Field

[0001] The present invention relates to a semiconductor image sensor device for detecting charged particles such as alpha rays and beta rays, and light including X-rays, gamma rays, ultraviolet and infrared (hereinafter referred to as charged particles and light).

Background Art

[0002] In general, in a semiconductor image sensor device, a photodiode for detecting charged particles or light and a transistor element are formed on the same semiconductor substrate. As this type of semiconductor image sensor device, a device using SOI (Silicon On Insulator) in which an insulating layer such as an oxide film called a so-called BOX (Buried Oxide) is embedded in a silicon substrate is generally known.

[0003] FIG. 4 is a cross-sectional view showing a basic configuration of a semiconductor image sensor device using an SOI layer. A photodiode for detecting charged particles or light is formed in a first silicon substrate 401, and a processing circuit including a transistor element for amplifying and processing the detected signal is formed in a second silicon layer 402 separated by a buried oxide film layer 403. By adopting such a structure, the fill factor with respect to the unit pixel of the photodiode is sufficiently increased, and a circuit of a certain scale can be arranged in the pixel which is the pixel unit.

[0004] When the conductivity type of the first silicon substrate 401 is, for example, P-type, the photodiode can be realized as a PN junction diode by ion-implanting phosphorus with a desired dose amount into a diffusion layer 404 formed on the lower surface of the buried oxide film layer 403 of the first silicon substrate 401 to make it N-type. Reference numeral 405 indicates a gate electrode of a transistor element formed in the second silicon layer 402, reference numeral 406 indicates an interlayer insulating film, and reference numeral 407 indicates a metal wiring.

[0005] When a reverse bias is applied to form a depletion layer for detecting charged particles and light between the diffusion layer 404 and the first silicon substrate 401, the depletion layer expands into the first silicon substrate 401 and the diffusion layer 404, as shown by the dashed line in the figure. At the interface between the embedded oxide film layer 403 and the first silicon substrate 401, it extends along this layer. Because interface states exist at the interface, leakage current flows through these interface states, which becomes the dark current and degrades the sensor characteristics. In addition, a high voltage is applied to the first silicon substrate 401 to increase the detection sensitivity of charged particles and light. In this case, since the first silicon substrate 401 acts as the back gate of the transistor element formed in the second silicon layer 402, the characteristics of the transistor element change depending on the applied voltage, causing malfunctions in the processing circuit composed of the transistor element.

[0006] Therefore, in configuring the semiconductor image sensor device, it is necessary to (1) ensure that the depletion layer does not extend as far as possible along the interface between the first silicon substrate 401 and the embedded oxide film layer 403, and (2) implement structural measures to suppress the back gate effect of the transistor elements formed in the second silicon layer 402. Furthermore, (3) in order to improve sensor sensitivity, it is desirable to use the PN junction surface of the detection photodiode in a completely depleted state, and therefore structural modifications are necessary for this purpose.

[0007] The following Patent Documents 1 to 3 are known prior art documents that incorporate the structural improvements described above.

[0008] Figure 5 is a cross-sectional view of a semiconductor device described in Patent Document 1, in which a photodiode and a transistor element are formed on the same semiconductor substrate with an insulating film in between. In this semiconductor device (100), an embedded well (14) formed of impurities with the opposite conductivity type to the sense node (182) of the PN junction, which is the photodiode (30), is formed below the transistor circuit (40), fixing the potential of the region that will become the back gate and suppressing the back gate effect. In addition, the embedded well (14) is positioned close to the photodiode (30) so that the depletion layer does not extend along the interface. However, this structure has the disadvantage that the parasitic capacitance of the sense node (182) increases because the embedded well (14) is connected to the sense node (182), which reduces the sensitivity of the photodiode (30).

[0009] Figure 6 is a cross-sectional view of the semiconductor device described in Patent Document 2. In this semiconductor device, the potential of the first embedded well (114), which is formed below the transistor circuit (40) and acts as a back gate, is fixed to suppress the back gate effect. Furthermore, the region containing this first embedded well (114) is separated by a second embedded well (116, 118, 119) of the opposite conductivity to the substrate (11). This increases the width of the depletion layer between the second implantation wells (116, 118, 119) and the first implantation well (114), thereby reducing the parasitic volume.

[0010] However, in this structure, the depletion layer of the photodiode (30) is formed to extend along the interface (151), so the dark current is not reduced. Furthermore, because the conductivity types of the sense node (232) and the second embedding wells (116, 118, 119) are the same, the carriers generated by the photoelectric effect in the photodiode (30) are absorbed not only by the sense node (232) but also by the second embedding wells (116, 118, 119). Consequently, this structure has the disadvantage of reduced sensitivity.

[0011] Figure 7 is a cross-sectional view of the semiconductor device described in Patent Document 3. This semiconductor device (11) includes: a p-type electrode (24) provided in a second region different from the first region corresponding to the element region, formed on a support substrate (14) in contact with a second surface opposite to the first surface of a BOX layer (20) in contact with an SOI substrate (22); a p-type hole integration layer (18) with neutralized potential, provided in a part of the support substrate (14) in contact with the second surface of the BOX layer (20), and including at least the first region and the region covering the electrode (24); an n-type detection electrode (30) formed on the support substrate (14) in contact with the second surface of the BOX layer (20); and an n-type potential barrier layer (16) provided between the second surface of the BOX layer (20) in the portion where the electrode (24), the hole integration layer (18), and the detection electrode (30) are provided, and the support substrate (14), forming a potential barrier.

[0012] In this structure, the depletion layer extending across the interface is minimized, and the back gate formed beneath the pixel circuit (50) can be fixed by the potential of the hole integration layer (18), which is an embedded well. However, in this structure, current is easily leaked from the hole integration layer (18) through the potential barrier layer (16) to the support substrate (14), and in order to prevent this, the impurity concentration of the potential barrier layer (16) must be sufficiently high. Also, since the potential barrier layer (16) and the detection electrode (30) have the same conductivity type, there is a possibility of leakage between adjacent pixels.

[0013] Incidentally, in order to separate adjacent pixels at the potential barrier layer (16), the gap between the hole integration layer (18) and the potential barrier layer (16), and the gap between the support substrate (14) and the potential barrier layer (16) are reverse-biased, and the depletion layer formed in the potential barrier layer (16) completely depletes the inside of the potential barrier layer (16). Therefore, there was a problem in that the bias voltage applied to the hole integration layer (18) and the support substrate (14) was limited. [Prior art documents] [Patent Documents]

[0014] [Patent Document 1] Japanese Patent Publication No. 2013-69924 [Patent Document 2] Japanese Patent Publication No. 2014-130920 [Patent Document 3] Japanese Patent Publication No. 2019-106519 [Overview of the project] [Problems that the invention aims to solve]

[0015] The present invention has been made in view of the aforementioned prior art, and aims to provide a semiconductor image sensor device that suppresses the generation of leakage current due to interface states, allows the support substrate to be easily depleted even when the applied voltage limit is relaxed, and does not reduce the sensitivity of the photodiode formed in the support substrate. [Means for solving the problem]

[0016] Figure 1 shows a semiconductor image sensor device of the present invention. The semiconductor image sensor device of the present invention is formed by laminating an SOI layer (110) on which MOS transistor elements (114) constituting a pixel circuit are formed in contact with a first surface of an insulating layer (107), and a silicon support substrate (101) having a first impurity concentration of a first conductivity type on which a photodiode for detecting charged particles and light is formed in contact with a second surface of the SOI layer (110) opposite to the first surface, and in a region (P) corresponding to one pixel,

[0017] i: On the surface side of the silicon support substrate (101), there is a first embedded well layer (102-1) having a first impurity concentration of a second conductivity type at a first position (A) that is in contact with the second surface of the insulating layer (107) and serves as the back gate of the MOS transistor element (114), and a second embedded well layer (102-2) having a first impurity concentration of a second conductivity type at a second position (B) that is separated from the first position (A) and does not face the back gate,

[0018] ii: A third embedded well layer (103) having a second impurity concentration of a first conductivity type is formed such that it is separated from the first embedded well layer (102-1) by a predetermined distance in the first and second directions, and is close to the second embedded well layer (102-2) and surrounds the first embedded well layer (102-1) from both sides,

[0019] iii: A fourth embedded well layer (104) having a third impurity concentration of the first conductivity type is formed at a position deeper than the first embedded well layer (102-1) and in contact with the bottom surface of the first embedded well layer (102-1) and the third embedded well layer (103),

[0020] iv: comprising a contact diffusion layer (105) having a second impurity concentration of a second conductivity type formed at a desired position in the first embedded well layer (102-1) and the second embedded well layer (102-2),

[0021] v: A backside diffusion layer (106) having a fourth impurity concentration of the first conductivity type is formed on the back side of the silicon support substrate (101). Between the contact diffusion layer (105) and the back surface diffusion layer (106) of the first embedded well layer (102-1), there is a potential (V) necessary to completely deplete the silicon support substrate (101). BB ) is applied, The contact diffusion layer (105) of the second embedded well layer (102-2) is characterized in that it is used as a means to transmit signals generated in the depletion layer of the silicon support substrate (101) in connection with the detection of charged particles or light to the MOS transistor element (114).

[0022] Furthermore, in the semiconductor image sensor device of the present invention, the first conductivity type is P-type, and the first impurity concentration of the silicon support substrate (101) is 1 × 10⁻¹⁶ in terms of dopant concentration. 12 cm -3 ~1 × 10 14 cm -3The range, the second impurity concentration of the third buried well layer (103) is ion implantation energy 110 to 150 eV, dose amount 1×10 12 cm -2 ~5×10 13 cm -2 The concentration determined within the range, the third impurity concentration of the fourth buried well layer (104) is ion implantation energy 360 to 400 eV, dose amount 1×10 12 cm -2 ~5×10 13 cm -2 The concentration determined within the range, the fourth impurity concentration of the back surface diffusion layer (106) is a concentration higher than the third impurity concentration,

[0023] The second conductivity type is N-type, and the first impurity concentration of the first buried well layer (102-1) and the second buried well layer (102-2) is ion implantation energy 280 to 32 keV, dose amount 0.5×10 12 cm -2 ~5×10 13 cm -2 The concentration determined within the range, the second impurity concentration of the contact diffusion layer (105) is energy 10 to 50 keV, dose amount 1×10 15 cm -2 ~1×10 16 cm -2 It is characterized in that it is the concentration determined within the range.

[0024] Furthermore, in the semiconductor image sensor device of the present invention, the silicon support substrate (101) has a thickness of 700 to 800 μm, the insulating layer (107) has a thickness of 10 to 200 nm, and the SOI layer (110) has a thickness of 10 to 1000 nm.

Effect of the Invention

[0025] According to the structure of the present invention, for example, the pixel size is 20×20 μm 2In this case, compared to the normal structure shown in Figure 4, it is possible to reduce the area in contact between the depletion layer and the interface between the silicon support substrate 101 and the insulating layer 107 to about 7%, and the dark current can also be reduced to about 7%. Furthermore, all electrons generated in the depletion layer formed in the silicon support substrate 101 by the photodiode can be collected in the second embedded well layer 102-2, which acts as a detection node, thus enabling a highly sensitive sensor. In addition, the second embedded well layer 102-2, which suppresses the formation of a surface depletion layer, can also be used as an electrode that can suppress the back gate effect of the MOS transistor element 114, thus ensuring stable operation. Structurally, by forming essentially only two types of embedded well layers within the silicon support substrate 101 on which the photodiode is formed, the number of additional steps is reduced, resulting in lower manufacturing costs.

[0026] Therefore, it is possible to suppress the generation of leakage current due to interface states, easily deplete the support substrate even when the applied voltage limit is relaxed, and realize a semiconductor image sensor device that does not reduce the sensitivity of the photodiode formed in the support substrate. [Brief explanation of the drawing]

[0027] [Figure 1] A cross-sectional view of a semiconductor image sensor device according to an embodiment of the present invention. [Figure 2(1)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (Part 1). [Figure 2(2)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 2). [Figure 2(3)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 3). [Figure 2(4)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 4). [Figure 2(5)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 5). [Figure 2(6)]A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 6). [Figure 2(7)] A cross-sectional diagram illustrating the manufacturing method of a semiconductor image sensor device according to the present invention (part 7). [Figure 2(8)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 8). [Figure 2(9)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 9). [Figure 2(10)] A cross-sectional diagram illustrating the manufacturing process of a semiconductor image sensor device according to the present invention (part 10). [Figure 2(11)] A cross-sectional diagram illustrating the manufacturing method of a semiconductor image sensor device according to the present invention (part 11). [Figure 3] Concentration profile obtained by simulation of the embedded well layer fabricated according to the present invention. [Figure 4] A cross-sectional view showing the basic configuration of a semiconductor image sensor device using an SOI layer. [Figure 5] Cross-sectional view of the semiconductor device described in Patent Document 1. [Figure 6] Cross-sectional diagram of the semiconductor device described in Patent Document 2. [Figure 7] Cross-sectional diagram of the semiconductor device described in Patent Document 3. [Modes for carrying out the invention]

[0028] First, the configuration of the semiconductor image apparatus according to the present invention will be described. Figure 1 shows the cross-sectional structure of region P corresponding to one pixel of the image sensor. Region P is the area enclosed by the XX line and the YY line in the figure, and it appears repeatedly in the first direction (left) and second direction (right) of Figure 1 at the same pitch. These pixels are then arranged in a two-dimensional manner to form the imaging area of ​​a semiconductor image sensor. Here, each pixel has the function of detecting the charge generated within the pixel and modulating it in the time domain; these pixels are called lock-in pixels.

[0029] As shown in Figure 1, the semiconductor image sensor device 1000 of this embodiment has a silicon support substrate 101 having a first impurity concentration of a first conductivity type, on which a silicon on insulator (SOI) layer 110 is stacked, with MOS transistor elements 114 constituting a pixel circuit formed via an insulating layer 107 called a buried oxide (BOX) layer. Note that the MOS transistor element 114 that constitutes the pixel circuit is composed of multiple elements, but only one transistor element is shown in Figure 1 as a representative example, with 112 representing the gate insulating film and 113 representing the gate electrode.

[0030] On the surface side of the silicon support substrate 101, a first embedded well layer 102-1 having a first impurity concentration of the second conductivity type is formed at position A, which is in contact with the insulating layer 107 and will serve as the back gate of the MOS transistor element 114. Furthermore, a second embedded well layer 102-2 having a first impurity concentration of the second conductivity type is formed at position B, which is separated from position A and does not face the back gate.

[0031] A third embedded well layer 103 having a second impurity concentration of the first conductivity type is formed at a position adjacent to the second embedded well layer 102-2, separated from the first embedded well layer 102-1 by a predetermined distance in the first direction and the second direction (left and right), and surrounding the first embedded well layer 102-1 from both sides. Furthermore, a fourth embedded well layer 104 having a third impurity concentration of the first conductivity type is formed at a deeper position than the first embedded well layer 102-1, so as to be in contact with the bottom surface of the first embedded well layer 102-1 and the third embedded well layer 103. A contact diffusion layer 105 having a second impurity concentration of the second conductivity type is formed at desired positions in the first embedded well layer 102-1 and the second embedded well layer 102-2.

[0032] A backside diffusion layer 106 having a fourth impurity concentration of the first conductivity type is formed on the back side of the silicon support substrate 101. Between the contact diffusion layer 105 and the back surface diffusion layer 106 of the first embedded well layer 102-1, there is a potential V required to completely deplete the silicon support substrate 101. BB It is applied. The contact diffusion layer 105 of the second embedded well layer 102-2 is used as a means to transmit signals generated in the depletion layer of the silicon support substrate 101 in response to the detection of charged particles or light to the MOS transistor element 114. Note that 108 indicates an interlayer insulating film and 109 indicates a metal wiring.

[0033] Here, the first conductivity type is P-type, and the first impurity concentration of the silicon support substrate 101 is 1 × 10⁻¹⁶ dopant concentration. 12 cm -3 ~1 × 10 14 cm -3 Within this range, the second impurity concentration in the third embedded well layer 103 is such that the ion implantation energy is 110 to 150 eV and the dose is 1 × 10⁻¹⁶. 12 cm -2 ~5×10 13 cm -2 The concentration is determined within the range of the third impurity in the fourth embedded well layer 104, with an ion implantation energy of 360 to 400 eV and a dose of 1 × 10⁻¹⁴ eV. 12 cm -2 ~5×10 13 cm -2 The concentration is determined within the range of the fourth impurity concentration in the back diffusion layer 106, the concentration of the fourth impurity is higher than the concentration of the third impurity, the second conductivity type is N-type, and the first impurity concentration in the first embedded well layer 102-1 and the second embedded well layer 102-2 is ion implantation energy 280 to 320 eV, dose 0.5 × 10 12 cm -2 ~5×10 13 cm -2 The concentration is determined within the range, the second impurity concentration of the contact diffusion layer 105 is for an energy of 10 to 50 keV, and a dose of 1 × 10 15 cm -2 ~1 × 10 16 cm -2 The concentration is determined within this range. Furthermore, the silicon support substrate 101 has a thickness of 700-800 μm, the insulating layer 107 has a thickness of 10-200 nm, and the SOI layer 110 has a thickness of 10-1000 nm.

[0034] In the semiconductor image sensor shown in Figure 1, the second embedded well layer 102-2 functions as a sense node for collecting carriers, but is formed to the minimum dimensions permitted by semiconductor manufacturing technology. As a result, the parasitic capacitance of the sense node is kept low, achieving high sensitivity. Furthermore, the first embedded well layer 102-1 of the same conductivity type is formed at a distance sufficient to ensure sufficient voltage resistance from the second embedded well layer 102-2, minimizing the area in contact between the depletion layer (shown as a dotted line in the figure) extending from the PN junction of the photodiode and the interface between the silicon support substrate 101 and the insulating layer 107, thereby suppressing the generation of dark current.

[0035] Since the third and fourth embedded well layers 103 and 104 are formed in reverse conductivity to surround the first embedded well layer 102-1, the carriers generated by charged particles and the photoelectric effect due to light within the depletion layer of the photodiode are not collected in the third and fourth embedded well layers 103 and 104 as shown in the figure, but are all collected in the second embedded well layer 102-2, which acts as a sense node, thus preventing a decrease in detection sensitivity.

[0036] Furthermore, in order to make the depletion layer of the silicon support substrate 101 as wide as possible, preferably completely depleted, a very low dopant concentration (1 × 10⁻¹⁰) is used. 12 cm -3 ~1 × 10 14 cm -3 It is preferable to use a P-type silicon substrate. The second embedded well layer 102-2, which will serve as the sense node, should have a moderate concentration (1 × 10⁻¹⁰). 15 cm -3 ~1 × 10 18 cm -3 It is formed as an N-type diffusion layer. Furthermore, a high concentration (1 × 10⁻¹⁰) is formed within the second embedded well layer 102-2. 18 cm -3 ~1 × 10 21 cm -3 A contact diffusion layer 105 is placed. Furthermore, this contact diffusion layer 105 enables ohmic connection with the metal wiring 109.

[0037] Furthermore, in order to reduce dark current and avoid the depletion layer extending to the interface between the silicon support substrate 101 and the insulating layer 107, a medium concentration (1 × 10) is used. 15 cm -3 ~1 × 10 18 cm -3 A first N-type embedded well layer 102-1 is placed. The first N-type embedded well layer 102-1 acts as an electrode to suppress the back gate effect of the MOS transistor element 114 formed in the SOI layer 110, and can therefore be fixed at a fixed potential, mostly at ground (GND) level. In this state, a desired voltage V is applied between the first embedded well layer 102-1 and the back surface diffusion layer 106. BB When applied, the depletion layer expands as shown by the dotted line in Figure 1.

[0038] At this time, of the electron-hole pairs generated in this depletion layer, some electrons may be collected in the second embedded well layer 102-2, which acts as a detection node, while others may be collected in the first embedded well layer 102-1. In this case, there is a concern that the detection sensitivity may decrease. In this invention, in order to suppress this decrease in sensitivity, by arranging a P-type fourth embedded well layer 104 and a P-type third embedded well layer 103, in which the first embedded well layer 102-1 is formed at a deeper position, the depletion layer from the first embedded well layer 102-1 other than the detection node and the depletion layer from the second embedded well layer 102-2, which acts as a detection node, can be separated as shown by the dotted line.

[0039] Furthermore, since all electrons (-) generated in the depletion layer within the silicon support substrate 101 are collected in the second embedded well layer 102-2, which is a detection node, it is possible to suppress the generation of dark current while maintaining high sensitivity to charged particles and light. In the embodiment described above, a P-type silicon was used as the silicon support substrate 101. However, if an N-type silicon is used, the conductivity type of the embedded well layer should be set to P-type.

[0040] Next, a method for manufacturing a semiconductor image sensor device according to the present invention will be described. The semiconductor image sensor device according to the present invention, shown in Figure 1, is manufactured according to the process-by-process manufacturing method shown in Figures 2(1) to 2(11). The initial material used in manufacturing is a standard SOI wafer as shown in Figure 2(1). This SOI wafer has a thickness of 700-800 μm and an extremely low concentration (1 × 10⁻¹⁶). 12 cm -3 ~1 × 10 14 cm -3 A 10-200 nm oxide film layer 207 is formed on a P-type substrate 201, and a 10-1000 nm silicon layer 210 is formed on top of that. The dopant concentration of the upper silicon layer 210 is not specified.

[0041] This silicon layer 210 is patterned as shown in Figure 2(2) using known device isolation methods such as LOCOS or STI. Then, as shown in Figure 2(3), a photoresist 214 is formed in the region where the embedded N-well layer 202 is not to be formed using known photolithography techniques, and phosphorus is injected using this photoresist 214 as a mask. The injection conditions are an energy of 280 to 320 keV, preferably 300 keV, and a dose of 0.5 × 10⁻¹⁶. 12 ~5×10 13 cm -2 Preferably 1.0 × 10 12 cm -2 After ion implantation, the photoresist 214 is removed.

[0042] Similarly, as shown in Figure 2(4), boron ion implantation is performed using known photolithography techniques and a photoresist 214 as a mask to form the embedded P-well layer 203. The implantation conditions are an energy of 110 to 150 keV, preferably 130 keV, and a dose of 1 × 10⁻¹⁶. 12 ~5×10 13 cm -2 Preferably 5 x 10 12 cm -2After ion implantation, the photoresist 214 is removed. Furthermore, as shown in Figure 2(5), boron ion implantation is performed using known photolithography techniques and the photoresist 214 as a mask to form the embedded P-well layer 204. The implantation conditions are such that the ion implantation can be formed in a portion deeper than the embedded N-well layer 202, with an energy of 360 to 400 keV, preferably 380 keV, and a dose of 1 × 10⁻¹⁶. 12 ~5×10 13 cm -2 Preferably 5 x 10 12 cm -2 After ion implantation, the photoresist 214 is removed.

[0043] At this time, the ion implantation conditions for the embedded P-well layer 203 and the embedded P-well layer 204 are adjusted so that they are connected at a higher concentration than that of the silicon support substrate 201. Subsequently, the MOSFET manufacturing process begins. As shown in Figure 2(6), first, the SOI layer 210 is oxidized in an oxidizing atmosphere at 700 to 900°C to form an oxide film of 1 to 5 nm that will become the gate insulating film 212. Then, polysilicon that will become the gate electrode is deposited over the entire surface to a thickness of 100 to 300 nm, and doped with phosphorus or the like to reduce resistance. Furthermore, the polysilicon is patterned by known photolithography and etching to form the gate electrode 213.

[0044] Using the gate electrode 213 as a mask, the MOSFET is completed by ion implanting Group 5 impurities such as arsenic into the N-type MOSFET and Group 3 impurities such as boron into the P-type MOSFET, thereby forming the diffusion layer 211 that serves as the source and drain of the MOSFET. At this time, the MOSFET is placed on the embedded N-well layer 202, and the embedded N-well layer 202 functions as the back gate of the MOSFET.

[0045] In the next step, an opening is formed in the embedded oxide layer 207 using known photolithography and etching techniques, as shown in Figure 2(7), in order to form a high-concentration N+ layer 205 in the detection node. This opening is formed to prevent the embedded oxide layer 207 from being implanted into the silicon when it is thick, such as 100-200 nm, because a high-current ion implanter is used to form a high-concentration diffusion layer, but in that case the implantation energy is limited.

[0046] Next, phosphorus is ion-implanted into the opening using the embedded oxide film 207 as a mask. The implantation conditions are an energy of 10 to 50 keV, preferably 30 keV, and a dose of 1 × 10⁻¹⁶. 15 〜1×10 16 cm -2 Preferably 5 x 10 15 cm -2 Following this ion implantation, a rapid thermal annealing (RTA) is performed on the implanted well and the surrounding material to activate the ion-implanted impurities at 900 to 1100°C, preferably 1000°C, for 10 to 100 seconds, preferably 30 seconds.

[0047] Furthermore, as shown in Figure 2(8), an interlayer insulating film 208 is deposited to a thickness of approximately 500 to 700 nm. To make electrical contact with the detection node, contacts are formed using known photolithography and etching techniques. Although not shown in the figure, a barrier metal is formed and tungsten is deposited within the contacts. Excess tungsten deposited on top of the interlayer insulating film 208 is removed by chemical mechanical polishing (CMP), thereby forming tungsten-embedded contacts as shown in Figure 2(9).

[0048] Furthermore, to electrically transmit the signal from the detection node, metal wiring 209 is formed using conventional aluminum sputtering, photolithography, and etching techniques, as shown in Figure 2(10). Although not shown in the figure, the upper wiring layer is then formed as needed by forming an insulating film layer, via holes, and metal wiring, followed by protective film formation and pad openings. After grinding the back surface, a high-concentration P+ layer 206 is formed on the back surface by ion implantation and laser annealing from the back surface, as shown in Figure 2(11).

[0049] Figure 3 shows the concentration profiles (by simulation) of each key location obtained using the manufacturing method under these recommended conditions. The embedded N well 102-1 is reliably formed, and the embedded P well 104, which acts as an electron barrier, is formed below it. Furthermore, the embedded P wells 103 and 104 are in contact at a concentration sufficiently higher than the substrate concentration. In addition, the depth profiles of the embedded N well 102-1 and the embedded P well 104 are similar, confirming that the target structure has been achieved. [Explanation of symbols]

[0050] 101: First silicon support substrate 102-1: First embedded well layer, first N-type embedded well layer 102-2: Second embedded well layer 103: Third embedded well layer, P-type third embedded well layer 104: Fourth embedded well layer, P-type fourth embedded well layer 105: Diffusion layer for contact lenses 106: Backside diffusion layer 110:SOI layer 114: MOS transistor element

Claims

1. A semiconductor image sensor device comprising a laminate of an SOI layer (110) on which a MOS transistor element (114) constituting a pixel circuit is formed, in contact with a first surface of an insulating layer (107), and a silicon support substrate (101) containing a first conductivity type impurity on which a photodiode for detecting charged particles and light is formed, in contact with a second surface of the insulating layer (107) opposite to the first surface, i: On the surface side of the silicon support substrate (101), a first embedded well layer (102-1) containing impurities of a second conductivity type, which is opposite to the first conductivity type, is located at a first position (A) that is in contact with the second surface of the insulating layer (107) and serves as the back gate of the MOS transistor element (114), and a second embedded well layer (102-2) containing impurities of the second conductivity type is located at a second position (B) that is separated from the first position (A) and does not face the back gate, ii: A third embedded well layer (103) containing the first conductive type of impurity is formed adjacent to the second embedded well layer (102-2) and surrounded the first embedded well layer (102-1) from both sides, separated from the first embedded well layer (102-1) by a predetermined distance in a first direction which is an in-plane direction perpendicular to the stacking direction and a second direction which is opposite to the first direction, iii: A fourth embedded well layer (104) containing the first conductive type impurity is formed at a position deeper than the first embedded well layer (102-1) and in contact with the bottom surface of the first embedded well layer (102-1) and the third embedded well layer (103), iv: comprising the first embedded well layer (102-1) and the second embedded well layer (102-2), a contact diffusion layer (105) containing the second conductive type of impurity formed at a desired position in the first embedded well layer (102-1), v: A back surface diffusion layer (106) containing the first conductivity type impurity is formed on the back surface side of the silicon support substrate (101). The impurity concentration of the silicon support substrate (101) is 1 × 10⁻¹⁶ in terms of dopant concentration. １２ cm －３ ~1 x 10 １４ cm －３ It is within the range, The concentration of impurities in the first embedded well layer (102-1) is determined by an ion implantation energy of 280 to 320 eV and a dose of 0.5 × 10⁻¹⁶. １２ cm －２ ~5 x 10 １３ cm －２ It is within the range, The impurity concentration of the second buried well layer (102-2) is within the range of an ion implantation energy of 280 to 320 eV and a dose amount of 0.5×10 １２ cm －２ to 5×10 １３ cm －２ and is within the range of The concentration of impurities in the third embedded well layer (103) is determined by an ion implantation energy of 110 to 150 eV and a dose of 1 × 10⁻¹⁶. １２ cm －２ ~5 x 10 １３ cm －２ It is within the range, The concentration of impurities in the fourth embedded well layer (104) is determined by an ion implantation energy of 360 to 400 eV and a dose of 1 × 10⁻¹⁶. １２ cm －２ ~5 x 10 １３ cm －２ It is within the range, The concentration of impurities in the aforementioned contact diffusion layer (105) is such that the energy is 10 to 50 keV and the dose is 1 × 10⁻¹⁶. １５ cm －２ ~1 x 10 １６ cm －２ It is within the range, The concentration of impurities in the back surface diffusion layer (106) is higher than the concentration of impurities in the fourth embedded well layer (104). Between the contact diffusion layer (105) and the back surface diffusion layer (106) of the first embedded well layer (102-1), a potential (V BB) necessary to completely deplete the silicon support substrate (101) is applied. The semiconductor image sensor device is characterized in that the contact diffusion layer (105) of the second embedded well layer (102-2) is used as a means to transmit signals generated in the depletion layer of the silicon support substrate (101) in connection with the detection of charged particles or light to the MOS transistor element (114).

2. The first conductivity type is P-type, The semiconductor image sensor apparatus according to claim 1, wherein the second conductivity type is N-type.

3. The semiconductor image sensor apparatus according to claim 1 or 2, characterized in that the silicon support substrate (101) has a thickness of 700 to 800 μm, the insulating layer (107) has a thickness of 10 to 200 nm, and the SOI layer (110) has a thickness of 10 to 1000 nm.

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