Ceramic electronic components, circuit board structures, and methods for manufacturing ceramic electronic components
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TAIYO YUDEN KK
- Filing Date
- 2022-03-10
- Publication Date
- 2026-08-04
Smart Images
Figure 0007900163000002 
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Abstract
Description
Technical Field
[0001] The present invention relates to a ceramic electronic component, a circuit board structure, and a method for manufacturing a ceramic electronic component.
Background Art
[0002] With the miniaturization and high functionality of electronic devices, there is a demand for smaller and larger multilayer ceramic capacitors. To manufacture a smaller and larger multilayer ceramic capacitor, it is conceivable to thin the ceramic dielectric layer and increase the number of ceramic dielectric layers and internal electrode layers. However, in this method, delamination may occur, which may lead to a decrease in the characteristics and reliability of the multilayer ceramic capacitor.
[0003] Patent Document 1 discloses a multilayer ceramic capacitor having a capacitor body with a side surface curved in a concave shape along the height direction and a residual compressive stress of 250 MPa or more. Patent Document 2 discloses a chip-type electronic component in which at least one surface in the stacking direction of a ceramic body is a first curved surface curved in a convex shape, the expansion rate in the stacking direction of the ceramic body is 5% or more in absolute value, and the radius of curvature of the first curved surface is 5.2 mm or less.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Patent Document 2
Patent Document 3
Summary of the Invention
[0005] However, in the configurations disclosed in Patent Documents 1 and 2, the residual stress around the stacked internal electrodes that accumulate charge is large. As a result, when the multilayer ceramic capacitor is subjected to external shock or electrical load, cracks may occur in the multilayer ceramic capacitor, leading to a decrease in insulation resistance and reliability.
[0006] Therefore, the present invention aims to provide a ceramic electronic component that can reduce the thickness of the dielectric layer while suppressing a decrease in reliability, a circuit board structure having a ceramic electronic component, and a method for manufacturing a ceramic electronic component.
[0007] According to one aspect of the present invention, a ceramic electronic component is provided having a substrate having a dielectric, at least one first internal electrode, and at least one second internal electrode laminated on the first internal electrode via a dielectric interposed between the first and second internal electrodes, a first external electrode, and a second external electrode. The substrate has a top surface, a bottom surface, a pair of side surfaces, a first end surface, and a second end surface, thereby having a substantially rectangular parallelepiped shape. The first internal electrode is exposed at the first end surface, the second internal electrode is exposed at the second end surface, both side surfaces of the substrate are concavely curved along the longitudinal direction, and the substrate has a longitudinal central portion having a width smaller than the width between the first and second end surfaces. The first external electrode is formed at the first end surface and electrically connected to the first internal electrode, and the second external electrode is formed at the second end surface and electrically connected to the second internal electrode.
[0008] Both sides of the base body may be concavely curved along the height direction, and each side may have a radius of curvature along the height direction, the radius of curvature along the height direction being smallest at the longitudinal center of the base body and increasing toward the end face.
[0009] The aforementioned element is 0 < (W3 - W1) / W3 ≤ 0.15 % The following conditions may be met, where W1 is the width at the center of the longitudinal direction of the base body in the height direction, and W3 is the width of the end face at the center of the height direction of the base body.
[0010] The aforementioned base body is 0.04 % <(W3-W1) / W3≦0.12 % It may satisfy the following conditions.
[0011] The upper and lower surfaces of the base body may be curved convexly along the longitudinal direction, and the longitudinal central portion of the base body may have a thickness greater than the thickness of the end faces.
[0012] The upper and lower surfaces of the base body may be curved convexly along the width direction, and the lateral central portion of the base body may have a thickness greater than the thickness on both sides in the lateral direction.
[0013] The aforementioned base body is 3.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦30 % The following conditions may be met, where W1 is the width of the body at the center of the longitudinal direction in the height direction, W2 is the width of the body at the center of the longitudinal direction in both upper and lower ends, T1 is the thickness of the body at the center of the longitudinal direction in the width direction, and T2 is the thickness of the body at the center of the longitudinal direction in both lateral sides.
[0014] The aforementioned base body is 5.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦20 % It may satisfy the following conditions.
[0015] The ceramic electronic component may further include a sealing resin layer covering the top surface of the base body, the top surfaces of the first external electrode and the second external electrode, the upper parts of both sides of the base body, and the upper parts of both sides of the first external electrode and the second external electrode.
[0016] The ceramic electronic component may have a length ranging from 0.25 mm to 0.4 mm, a width ranging from 0.125 mm to 0.2 mm, and a height ranging from 0.125 mm to 0.2 mm.
[0017] The dielectric between the first internal electrode and the second internal electrode may have a thickness in the range of 0.2 μm to 0.5 μm.
[0018] The dielectric of the element body may have an average crystal grain size in the range of 80 nm to 200 nm.
[0019] The first internal electrode and the second internal electrode may have a thickness in the range of 0.2 μm to 0.8 μm.
[0020] The ceramic electronic component may have a capacitance within the range of 10 μF to 1000 μF.
[0021] The main component of the material of the first external electrode and the second external electrode may be Ni.
[0022] According to another aspect of the present invention, a circuit board structure is provided. The circuit board structure has a circuit board and a ceramic electronic component mounted on the circuit board. The ceramic electronic component is connected to the circuit board via a solder layer adhered to the first external electrode and the second external electrode. On the end face of the first external electrode or the second external electrode, each solder layer wets, and on the upper surface of the element body, each solder layer does not exist.
[0023] According to another aspect of the present invention, a method for manufacturing a ceramic electronic component is provided. This method includes forming a body having a dielectric, internal electrodes, and a cover layer, having an upper surface, a lower surface, a pair of side surfaces, and a pair of end faces, having a substantially rectangular parallelepiped shape, each of the internal electrodes being exposed at one of the end faces, the cover layer forming the upper surface and the lower surface, the cover layer being formed of a material having a shrinkage temperature higher than the shrinkage temperature of the material of the internal electrodes; firing the body; forming an underlayer of an external electrode disposed at both ends in the longitudinal direction of the body, covering the upper surface, the lower surface, both side surfaces, and the corresponding end faces of the body; and forming a plating layer on each underlayer.
[0024] The shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer may satisfy 1.20 ≤ Tx / Ta ≤ 1.85.
[0025] The shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer may satisfy 1.30 ≤ Tx / Ta ≤ 1.60.
[0026] The shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer may satisfy 1.30 ≤ Tx / Ta ≤ 1.40.
[0027] According to an aspect of the present invention, it is possible to reduce the thickness of the dielectric layer while suppressing a decrease in reliability.
Brief Description of the Drawings
[0028] [Figure 1] It is a perspective view showing a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2A] It is a cross-sectional view of the multilayer ceramic capacitor cut along line B1-B2 in FIG. 1. [Figure 2B] It is a cross-sectional view of the multilayer ceramic capacitor cut along line B3-B4 in FIG. 1. [Figure 3] It is a cross-sectional view of the multilayer ceramic capacitor cut along line C1-C2 in FIG. 1. [Figure 4] It is a cross-sectional view of the multilayer ceramic capacitor cut along line A1-A2 in FIG. 1. [Figure 5] It is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. [Figure 6A] It is a cross-sectional view for explaining a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. [Figure 6B] It is a view showing the steps after FIG. 6A. [Figure 6C] It is a view showing the steps after FIG. 6B. [Figure 6D] It is a view showing the steps after FIG. 6C. [Figure 6E] This figure shows the steps after Figure 6D. [Figure 6F] This figure shows the steps after Figure 6E. [Figure 6G] This figure shows the steps after Figure 6F. [Figure 6H] This figure shows the steps after Figure 6G. [Figure 6I] This figure shows the steps after Figure 6H. [Figure 7] This graph shows the relationship between the deformation of each material in the multilayer ceramic capacitor according to the first embodiment and temperature as the temperature rises. [Figure 8A] This is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present invention, cut in the same manner as in Figure 2A. [Figure 8B] This is a cross-sectional view of a multilayer ceramic capacitor according to the second embodiment, cut in the same manner as in Figure 2B. [Figure 8C] This is a cross-sectional view of a multilayer ceramic capacitor according to the second embodiment, cut in the same manner as in Figure 4. [Figure 9] This is a cross-sectional view showing a structure in which a multilayer ceramic capacitor according to a third embodiment of the present invention is mounted on a circuit board. [Figure 10] This is a perspective view showing a ceramic electronic component according to a fourth embodiment of the present invention. [Figure 11] This table shows the relationship between dimensions, crack occurrence, and durability of different samples of a multilayer ceramic capacitor according to the first embodiment. [Figure 12] This table shows the relationship between dimensions, crack occurrence, and durability of different samples of a multilayer ceramic capacitor according to the first embodiment. [Modes for carrying out the invention]
[0029] The embodiments of the present invention will be described in detail below with reference to the attached drawings. The following embodiments are not intended to limit the present invention, and not all combinations of features described in the embodiments are essential to the configuration of the present invention. The configuration of the embodiments may be modified or changed as appropriate depending on the specifications and various conditions (usage conditions, usage environment, etc.) of the device to which the present invention is applied. The technical scope of the present invention is defined by the claims and is not limited by the individual embodiments below. In addition, the drawings used in the following description may differ in scale and shape from the actual structure in order to make each configuration easier to understand.
[0030] First Embodiment Figure 1 is a perspective view showing a multilayer ceramic capacitor according to a first embodiment of the present invention. Figure 2A is a cross-sectional view of a multilayer ceramic capacitor cut along the line B1-B2 in Figure 1. Figure 2B is a cross-sectional view of a multilayer ceramic capacitor cut along the line B3-B4 in Figure 1. Figure 3 is a cross-sectional view of a multilayer ceramic capacitor cut along the line C1-C2 in Figure 1. Figure 4 is a cross-sectional view of a multilayer ceramic capacitor cut along the line A1-A2 in Figure 1.
[0031] As shown in Figures 1, 2A, 2B, 3, and 4, the multilayer ceramic capacitor 1A comprises a base body 2 and external electrodes 6A and 6B. The base body 2 comprises a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. The laminate 2A has an internal electrode layer 3A, another internal electrode layer 3B, and a dielectric layer 4 interposed between adjacent internal electrode layers 3A and 3B. In Figures 2A, 2B, and 3, the boundaries between the lower cover layer 5A and the laminate 2A, and the boundaries between the upper cover layer 5B and the laminate 2A are shown by dotted lines. However, after firing, as described later, these boundaries become indistinguishable.
[0032] The lower surface of the laminate 2A is covered with a lower cover layer 5A, and the upper surface of the laminate 2A is covered with an upper cover layer 5B. The internal electrode layers 3A and 3B are stacked alternately with a dielectric layer 4 interposed between them. Figures 1, 2A, 2B, and 3 show an example in which a total of seven internal electrode layers 3A and 3B are stacked, but the number of internal electrode layers 3A and 3B that are stacked is not limited.
[0033] In the following explanation, the direction passing vertically through the end faces MA and MB of base body 2 may be referred to as the longitudinal direction DL of base body 2. The direction perpendicular to the longitudinal direction DL and parallel to the internal electrode layers 3A and 3B may be referred to as the width direction DW of base body 2. Furthermore, the direction perpendicular to the longitudinal direction DL and the width direction DW may be referred to as the stacking direction (height direction) DH of base body 2. The internal electrode layers 3A and 3B are stacked in the height direction DH with the dielectric layer 4 in between. The left end face MA is on the opposite side of the right end face MB in the longitudinal direction DL.
[0034] Multilayer ceramic capacitor 1A is mounted on a circuit board and used for purposes such as removing noise applied to semiconductor chips mounted on the circuit board. A pair of surfaces of the element 2 that are nearly parallel to the circuit board and on opposite sides are sometimes called the top surface TS and the bottom surface BS. A pair of surfaces of the element 2 that are nearly perpendicular to the circuit board and on opposite sides where the internal electrode layers 3A and 3B are not exposed are sometimes called the pair of side surfaces SA and SB. The width direction DW passes through the side surfaces SA and SB of the element 2 nearly vertically. In this specification, terms such as "top," "bottom," "side," "height," "thickness," and "width" are used for ease of understanding and are not intended to limit the orientation of the multilayer ceramic capacitor 1A when mounted on a circuit board.
[0035] As shown in Figure 4, the sides SA and SB of the base body 2 are curved concavely along the longitudinal direction DL, and the base body 2 has a central portion C1 in the longitudinal direction DL where the width W1 is smaller than the width W3 at the end faces MA and MB. This means that at least one portion of the central portion C1 in the longitudinal direction DL is the narrowest when comparing the width at the same height level compared to other portions in the longitudinal direction DL. In the illustrated embodiment, the distance between the sides SA and SB of the body 2 (the width of the body 2) gradually decreases from the end faces MA and MB toward points Q1 and Q1' on the sides SA and SB of the central part C1. Each side may be symmetrical with respect to the center line Ce1 of the body 2 shown in Figure 4, which is located in the center of the longitudinal direction DL of the body 2 and passes along the width direction DW. The longitudinal center C1 is defined, for example, as the midpoint of the element 2 in the longitudinal direction DL when the element 2 is divided into (2N+1) equal parts along the longitudinal direction DL. N is a positive integer. For example, the longitudinal center C1 is defined as the midpoint of the element 2 in the longitudinal direction DL when the element 2 is divided into 3 equal parts along the longitudinal direction DL.
[0036] As shown in Figures 2A and 2B, the sides SA and SB of the body 2 are curved concavely along the height direction DH, and the body 2 has central parts CA3 and CB3 in the height direction DH that are narrower than the width of the other parts. Each side may be symmetrical with respect to the center lines Ce2 and Ce3 of the body 2 shown in Figures 2A and 2B, which are located in the center of the body 2 in the height direction DH and pass through the width direction DW. As can be seen by comparing Figure 2A and Figure 2B, the radius of curvature of each side along the height direction DH is minimum at the longitudinal center C1 and may gradually increase toward both longitudinal ends of the body 2. Points Q1 and Q1' in Figure 4 are points in the longitudinal direction DL where the radius of curvature of each side along the height direction DH is minimum, and are located within the range of the longitudinal center C1. The concave shape of each side along the height direction DH may also be symmetrical with respect to the center line Ce1 of the body 2 shown in Figure 4.
[0037] As shown in Figure 2B, the width W1 of the central part C1 of the base body 2 is precisely defined as the width of the longitudinal central part C1 in the height direction DH. As shown in Figure 2A, the width W3 of the end faces MA and MB of the base body 2 is precisely defined as the width of the end faces MA and MB in the height direction DH in the central part. As will be explained later, 0 < (W3 - W1) / W3 ≤ 0.15 % Preferably, 0.04 % <(W3-W1) / W3≦0.12 % It is even more preferable that this be the case.
[0038] As shown in Figure 3, the upper surface TS and lower surface BS of the base body 2 are curved convexly along the longitudinal direction DL, and the base body 2 has a central portion C2 in the longitudinal direction DL where the thickness (height) T1 is greater than the thickness (height) T3 at the end faces MA and MB. This means that at least one portion of the central portion C2 in the longitudinal direction DL is the thickest when comparing the thickness on the same vertical plane compared to other portions in the longitudinal direction DL. In the illustrated embodiment, the distance between the upper surface TS and the lower surface BS of the base body 2 (the thickness of the base body 2) gradually increases from the end faces MA and MB toward the center in the longitudinal direction. The longitudinal center C2 is defined, for example, as the midpoint of the element 2 in the longitudinal direction DL when the element 2 is divided into (2N+1) equal parts along the longitudinal direction DL. N is a positive integer. For example, if the element 2 is divided into 3 equal parts along the longitudinal direction DL, the midpoint of the element 2 in the longitudinal direction DL is defined as the longitudinal center C2. The center C2 may or may not coincide with the center C1.
[0039] As is clear from the above, the base body 2 has an upper surface TS and a lower surface BS that are convexly curved along the longitudinal direction DL, and a central portion C2 that is thicker than the end surfaces MA and MB. The upper and lower surfaces may be symmetrical with respect to the center line Ce4 of the base body 2 shown in Figure 3, which is located in the center of the base body 2 in the longitudinal direction DL and passes along the height direction DH. In the cross-section shown in Figure 3, the thickest part of the base body 2 is located in the central part C2.
[0040] In Figures 2A and 2B, in the cross-section of the base body 2 parallel to the end faces MA and MB, the central part of the height direction DH at both ends of the longitudinal direction DL of the base body 2 will be called the central part CA3. The central part of the height direction DH at the center of the longitudinal direction DL of the base body 2 will be called the central part CB3. Furthermore, in the cross-section of the base body 2 parallel to the end faces MA and MB, the central part of the width direction DW at both ends of the longitudinal direction DL of the base body 2 will be called the central part CA4, and the central part of the width direction DW at the center of the longitudinal direction DL of the base body 2 will be called the central part CB4. Since the sides SA and SB of base body 2 are curved concavely along the longitudinal direction DL (because the width W1 of the longitudinal center of base body 2 is smaller than the width W3 of the longitudinal end), the width of the height-direction center CB3 at the longitudinal center of base body 2 is smaller than the width of the height-direction center CA3 at the longitudinal end of base body 2. This means that at least one portion of the center CB3 in the height-direction DH at the longitudinal center is the narrowest when comparing widths at the same height level, for example, at an intermediate height level, compared to other portions in the longitudinal direction DL. The height-direction center CB3 is defined, for example, as the midpoint of the element 2 in the height-direction DH when the element 2 is divided into (2N+1) equal parts in the height-direction DH. N is a positive integer. For example, the height-direction center CB3 is defined as the midpoint of the element 2 in the height-direction DH when the element 2 is divided into 3 equal parts in the height-direction DH.
[0041] Since the top surface TS and bottom surface BS of body 2 are curved convexly along the longitudinal direction DL (because the thickness T1 of the longitudinal center of body 2 is greater than the thickness T3 of both longitudinal ends), the thickness of the lateral center CB4 in the longitudinal center of body 2 is greater than the thickness of the lateral center CA4 at the longitudinal ends of body 2. This means that at least one portion of the central CB4 in the width direction DW in the longitudinal center is the thickest when comparing the thickness at the same lateral position, for example, in the middle of the width direction DW, compared to other portions in the longitudinal direction DL. The horizontal center CB4 is defined as the center of the element 2 in the width direction DW when the element 2 is divided into (2N+1) equal parts in the width direction DW. N is a positive integer. For example, the height center CB3 is defined as the middle part of the element 2 in the width direction DW when the element 2 is divided into 3 equal parts in the width direction DW.
[0042] As shown in Figures 2A and 2B, the body 2 has an upper surface TS and a lower surface BS that are convexly curved along the width direction DW, and a lateral central portion CA4 and CB4 that are thicker than the lateral sides of the body 2. The upper and lower surfaces may be symmetrical with respect to the centerlines Ce5 and Ce6 of the body 2 shown in Figures 2A and 2B, which are located in the center of the body 2 in the width direction DW and pass through the height direction DH. As can be seen by comparing Figure 2A and Figure 2B, the radii of curvature of the upper and lower surfaces along the width direction DW are minimum at the longitudinal center C1 or C2 and may gradually increase toward both longitudinal ends of the base body 2. Points Q1 and Q1' in Figure 4 are points in the longitudinal direction DL where the radii of curvature of the upper and lower surfaces along the width direction DW are minimum, and are located within the range of the longitudinal center C1 or C2. The convex shape along the width direction DW may also be symmetrical with respect to the center line Ce1 of the base body 2 shown in Figure 4.
[0043] As shown in Figure 2B, the thickness T1 of the body 2 at its longitudinal center C1 or C2 is precisely defined as the thickness at the center CB4 in the width direction DW of the cross-section of the body 2 at its longitudinal center C1 or C2. The thickness on both sides of the body 2 in the width direction DW of the cross-section of the body 2 at its longitudinal center C1 or C2 is called the thickness T2. The width W1 of the body 2 at its longitudinal center C1 or C2 is precisely defined as the width at the center CB3 in the height direction DH of the cross-section of the body 2 at its longitudinal center C1 or C2. The width at both the upper and lower ends in the height direction DH of the cross-section of the body 2 at its longitudinal center C1 or C2 is called the width W2. 3.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦30 %It is preferable that this be the case, 5.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦20 % It is even more preferable that this be the case.
[0044] The contour of the base body 2 shown in Figures 2A, 2B, 3, and 4 can be confirmed by observing the cross-sectional surfaces obtained by cutting along the cross-sections shown in Figures 2A, 2B, 3, and 4, and then polishing those surfaces. Furthermore, the dimensions of the base body 2 can be confirmed by measuring them on those cross-sectional surfaces.
[0045] Since the external electrodes 6A and 6B are located at opposite ends of the base body 2, they are spaced apart (separated) from each other in the longitudinal direction DL. Each of the external electrodes 6A and 6B continuously covers the top surface TS, bottom surface BS, side surfaces SA and SB, and the corresponding end surface MA or MB of the base body 2.
[0046] As shown in Figure 3, in the laminate 2A, internal electrode layers 3A and 3B are alternately arranged at different positions in the longitudinal direction DL. Internal electrode layer 3A may be positioned closer to the left end face MA of the base body 2 than internal electrode layer 3B, and internal electrode layer 3B may be positioned closer to the right end face MB of the base body 2 than internal electrode layer 3A. The left end of the internal electrode layer 3A is exposed at the left end of the dielectric layer 4 on the left end face MA and is connected to the external electrode 6A. The right end of the internal electrode layer 3B is exposed at the right end of the dielectric layer 4 on the right end face MB and is connected to the external electrode 6B. On the other hand, as shown in Figure 4, in the width direction DW, the sides of the internal electrode layers 3A and 3B are covered with the dielectric material that forms the dielectric layer 4. In the width direction DW, both sides of the internal electrode layer 3A may coincide with both sides of the internal electrode layer 3B. Therefore, the element 2 is made of a dielectric material and has side margin portions 10 that cover the internal electrode layers 3A and 3B in the width direction DW. The element 2 may be chamfered along each of its edges.
[0047] The thickness of the internal electrode layers 3A and 3B may be in the range of 0.2 μm to 0.8 μm. The main components of the materials for the internal electrode layers 3A and 3B may be metals such as Cu (copper), Fe (iron), Zn (zinc), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or alloys containing at least one of these metals. Preferably, the main components of the materials for the internal electrode layers 3A and 3B are Ni or Cu.
[0048] The thickness of the dielectric layer 4 may be in the range of 0.2 μm to 0.5 μm. The average crystal grain size of the dielectric material contained in the dielectric layer 4 may be in the range of 80 nm to 200 nm. The main component of the material used in the dielectric layer 4 may be, for example, a ceramic material having a perovskite structure. The main component may be present in a proportion of 50 at% or more. The ceramic material of the dielectric layer 4 may be, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, barium calcium zirconate titanate, or titanium oxide.
[0049] The main components of the materials for the lower cover layer 5A and the upper cover layer 5B may be, for example, ceramic materials. The main components of the ceramic materials for the lower cover layer 5A and the upper cover layer 5B may be the same as the main components of the ceramic material for the dielectric layer 4.
[0050] The convex curved shape of the upper surface TS and lower surface BS of the base body 2, and the concave curved shape of the side surfaces SA and SB of the base body 2, can be obtained by the distribution of internal stress acting on the base body 2. This occurs during the firing of the base body 2, as described later, due to the difference between the shrinkage temperature of the laminate 2A (see Figures 2A and 3) and the shrinkage temperature of the cover layers 5A and 5B. Increasing this difference increases the internal stress generated in the base body 2, and therefore the curvature of the convex and concave shapes also increases. To change the shrinkage temperature of the cover layers 5A and 5B, the grain size of the dielectric, i.e., ceramic material, contained in the cover layers 5A and 5B may be changed, the amount of glass phase additives (e.g., Si) contained in the materials of the cover layers 5A and 5B may be changed, or the amount of binder mixed into the materials of the cover layers 5A and 5B may be changed.
[0051] The main component of the material for the external electrodes 6A and 6B may be a metal such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or an alloy containing at least one of these metals. From the viewpoint of electrical connectivity with the internal electrodes 3A and 3B, the main component of the material for the external electrodes 6A and 6B is preferably Ni.
[0052] As shown in Figure 6I, each of the external electrodes 6A and 6B has a base layer 7 as a conductive layer formed on the substrate 2 and a plating layer 9 formed on the base layer 7. The underlayment layers 7 for the external electrodes 6A and 6B are positioned at opposite ends of the body 2, and are spaced apart (separated) from each other in the longitudinal direction DL. Each underlayment layer 7 for the external electrodes 6A and 6B continuously covers the top surface TS, bottom surface BS, sides SA and SB, and corresponding end surfaces MA or MB of the body 2.
[0053] The conductive material of the base layer 7 may be a metal such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or an alloy containing at least one of these metals. The base layer 7 may also further contain particles of a co-material dispersed in the metal. Here, "particles" includes not only individual small particles but also blocks formed by combinations of multiple small particles after the firing step described later. By dispersing the co-material in an island-like manner in the base layer 7, the difference in thermal expansion coefficients between the base material 2 and the base layer 7 is reduced, thereby mitigating the thermal stress generated in the base layer 7. The co-material is, for example, the ceramic component which is the main component of the dielectric layer 4. The base layer 7 may also contain a glass component. The glass component contained in the base layer 7 can densify the base layer 7. The glass components may be oxides of, for example, Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), B (boron), etc.
[0054] The base layer 7 is preferably formed from a sintered body of a conductive paste containing metal. This ensures adhesion between the base body 2 and the base layer 7 while also allowing the base layer 7 to be made thicker, thereby ensuring the strength of the external electrodes 6A and 6B and the conductivity between the base layer 7 and the internal electrode layers 3A and 3B.
[0055] Each plating layer 9 of the external electrodes 6A and 6B continuously covers the corresponding underlayer 7. The plating layer 9 is electrically connected to the internal electrode layer 3A or 3B via the corresponding underlayer 7. In addition, each plating layer 9 of the external electrodes 6A and 6B is electrically connected to the electrode on the circuit board via solder.
[0056] The main component of the plating layer 9 material may be a metal such as Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, or Sn, or an alloy containing at least one of these metals. The plating layer 9 may be a single layer of a single metal component or multiple layers of different metal components. Each plating layer 9 of the external electrodes 6A and 6B may have a three-layer structure consisting of, for example, a Cu plating layer formed on the underlayer 7, a Ni plating layer formed on the Cu plating layer, and a Sn plating layer formed on the Ni plating layer. The Cu plating layer can improve the adhesion between the plating layer 9 and the underlayer 7, the Ni plating layer can improve the heat resistance of the external electrodes 6A and 6B during soldering, and the Sn plating layer can improve the wettability of the solder to the plating layer 9.
[0057] In this embodiment, as shown in Figure 4, the sides SA and SB of the base body 2 are curved concavely along the longitudinal direction DL. This allows for the mitigation of local residual stress in the laminate 2A (see Figures 2A and 2B), particularly in the region RE (shown as dashed lines in Figures 2A and 2B) near the boundary between the lower cover layer 5A and the laminate 2A, and the boundary between the upper cover layer 5B and the laminate 2A. This makes it difficult for the cover layers 5A and 5B to separate from the laminate 2A, preventing cracks in the base body 2, a decrease in mechanical strength, a decrease in insulation resistance, and a decrease in reliability. The phenomenon of the cover layers 5A and 5B separating from the laminate 2A is called delamination.
[0058] Furthermore, by adjusting the crystal grain size of the dielectric (ceramic) material contained in cover layers 5A and 5B, the amount of glass phase additives and / or binder contained in cover layers 5A and 5B, it is possible to obtain a convex curved shape on the upper surface TS and lower surface BS of the base body 2, and a concave curved shape on the side surfaces SA and SB of the base body 2. This eliminates the need to perform processing to obtain the convex or concave curved shape after firing the base body 2, thereby suppressing an increase in the cost of the base body 2.
[0059] The external dimensions of the multilayer ceramic capacitor 1A are preferably within the range of Japanese Industrial Standards (JIS) "0201" (length = 0.25 mm, width = 0.125 mm, height = 0.125 mm) to JIS "3225" (length = 3.2 mm, width = 2.5 mm, height = 2.5 mm). Furthermore, the external dimensions are even more preferably within the range of JIS "0201" to "0402" (length = 0.4 mm, width = 0.2 mm, height = 0.2 mm). The above dimensional values are design values, and the actual product will have dimensional values including dimensional tolerances. When the external dimensions of the multilayer ceramic capacitor 1A are within the range of "0201" to "0402", the multilayer ceramic capacitor 1A can be miniaturized while maintaining high capacitance.
[0060] The capacitance of the multilayer ceramic capacitor 1A is preferably in the range of 10μF to 1000μF. More preferably, the capacitance of the multilayer ceramic capacitor 1A is in the range of 470μF to 1000μF. When the capacitance of the multilayer ceramic capacitor 1A is in the range of 470μF to 1000μF, the multilayer ceramic capacitor 1A can be miniaturized, used as a smoothing capacitor in a power supply circuit, and can effectively reduce ripple current.
[0061] Figure 5 is a flowchart showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. Figures 6A to 6I are cross-sectional views showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. Figures 6C to 6I show, for illustrative purposes, a configuration in which only three internal electrode layers 3A and three internal electrode layers 3B are alternately stacked with a dielectric layer 4 interposed between them.
[0062] In step S1 (mixing step) of Figure 5, an organic binder and organic solvent, acting as a dispersant and molding aid, are added to the dielectric material powder, and the mixture is pulverized and mixed to produce a slurry. The dielectric material powder may include, for example, ceramic powder. The dielectric material powder may contain additives. The additives may be, for example, oxides of any of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), Y (yttrium), Sm (samarium), Eu (europium), Gd (cadmium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium), or Si, or glass. The organic binder may be, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvents are, for example, ethanol or toluene.
[0063] Next, in step S2 (slurry coating step) in Figure 5, a green sheet 24 is manufactured as shown in Figure 6A. Specifically, a slurry containing ceramic powder is coated onto a sheet-shaped carrier film and dried to produce the green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry can be coated using, for example, a doctor blade method, a die coater method, or a gravure coater method. Step S2 is repeated to prepare multiple green sheets 24.
[0064] Next, in step S3 (electrode printing step) in Figure 5, as shown in Figure 6B, a conductive paste that will form the internal electrode layer is applied in a predetermined pattern to each of the green sheets 24 on which the internal electrode layer 3A or 3B shown in Figure 2B is to be placed, from among the green sheets prepared in step S1, thereby forming an internal electrode pattern 23 on the green sheet 24. In step S3, multiple internal electrode patterns 23 may be formed on a single green sheet 24 such that the internal electrode patterns 23 are separated from each other in the longitudinal direction of the green sheet 24. The conductive paste for the internal electrode layers contains metal powder used as the material for the internal electrode layers 3A and 3B. For example, if the metal used as the material for the internal electrode layers 3A and 3B is Ni, the conductive paste for the internal electrode layers contains Ni powder. The conductive paste for the internal electrode layers also contains a binder, a solvent, and optionally an auxiliary agent. The conductive paste for the internal electrode layers may contain, as a co-material, a ceramic material having the same main component composition as the main component of the dielectric layer 4. The conductive paste for the internal electrode layer may be applied using screen printing, inkjet printing, gravure printing, or the like. Therefore, step S3 may be called the electrode printing step. In this way, multiple green sheets 24 with internal electrode patterns 23 formed on them are prepared.
[0065] Next, in step S4 (lamination step) in Figure 5, as shown in Figure 6C, a green sheet 24 with an internal electrode pattern 23 formed on it and green sheets 25A and 25B without an internal electrode pattern 23 are laminated in a predetermined order to create a green sheet block 30. The green sheets 25A and 25B without an internal electrode pattern 23 are used as the outer layers (lower cover layer 5A and upper cover layer 5B). Green sheets 24 having internal electrode patterns 23A or 23B are classified into two groups: green sheets 24 having internal electrode pattern 23A (forming internal electrode layer 3A) and green sheets 24 having internal electrode pattern 23B (forming internal electrode layer 3B). Green sheets 24 having internal electrode pattern 23A and green sheets 24 having internal electrode pattern 23B are stacked alternately in the stacking direction. The internal electrode pattern 23A of one green sheet 24 and the internal electrode pattern 23B of the next green sheet 24 are stacked alternately, offset in the longitudinal direction of the green sheet 24. Furthermore, three types of parts are defined for the green sheet block 30. Specifically, the green sheet block 30 has a part in which only the internal electrode pattern 23A is stacked in the stacking direction, a part in which the internal electrode patterns 23A and 23B are stacked alternately in the stacking direction, and a part in which only the internal electrode pattern 23B is stacked in the stacking direction.
[0066] The green sheets 25A and 25B for the lower cover layer 5A and upper cover layer 5B are thicker than the green sheet 24 on which the internal electrode pattern 23 is formed. As described above, in order to change the shrinkage temperature of the cover layers 5A and 5B, the grain size of the dielectric (ceramic) material contained in the cover layers 5A and 5B may be changed, the amount of glass phase additive (e.g., Si) contained in the material for the cover layers 5A and 5B may be changed, or the amount of binder mixed into the material for the cover layers 5A and 5B may be changed. If the average crystal grain size of the dielectric powder contained in green sheets 25A and 25B is larger than the average crystal grain size of the dielectric powder contained in green sheet 24, the shrinkage temperature of the cover layers 5A and 5B during firing can be adjusted to be higher than the shrinkage temperature of the laminate 2A. By increasing the amount of glass phase additive in the dielectric powder contained in green sheets 25A and 25B, the shrinkage temperature of cover layers 5A and 5B during firing can be adjusted to be lower. Increasing the amount of binder in the dielectric powder contained in green sheets 25A and 25B increases the distance between dielectric particles in green sheets 25A and 25B before firing, thereby slowing down the solidification of dielectric particles during firing. As a result, the shrinkage temperature of cover layers 5A and 5B during firing becomes higher than the shrinkage temperature of laminate 2A.
[0067] Next, in step S5 (compression step) in Figure 5, as shown in Figure 6D, the laminated block 30 obtained in the lamination step S4 in Figure 5 is pressurized so that the green sheets 24, 25A, and 25B are pressurized and bonded together. The pressurization of the laminated block 30 may be performed, for example, by applying hydrostatic pressure to the laminated block 30 surrounded by the resin film.
[0068] In step S6 of Figure 5 (cutting step), as shown in Figure 6E, the pressurized laminated block 30 is cut so as to separate it into a plurality of rectangular parallelepiped bodies. Each body has six surfaces. The cutting of the laminated block 30 is carried out in two parts, as indicated by the plurality of vertical dotted lines 27, where only the internal electrode pattern 23A is laminated in the lamination direction and where only the internal electrode pattern 23B is laminated in the lamination direction. The cutting of the laminated block 30 can be carried out by methods such as blade dicing.
[0069] The obtained substrate 2' is shown in an enlarged view in Figure 6F. As shown in Figure 6F, the internal electrode layers 3A and 3B are alternately stacked in each of the individual substrates 2' such that the dielectric layer 4 is interposed between them. The internal electrode layer 3A is exposed at one end face MA of each substrate 2', and the internal electrode layer 3B is exposed at the other end face MB of each substrate 2'. A lower cover layer 5A and an upper cover layer 5B are formed on each body 2'.
[0070] Next, in step S7 (binder removal step) in Figure 5, the binder contained in each element 2' separated in step S6 of Figure 5 is removed. Binder removal is performed, for example, by heating element 2' to approximately 350°C in an N2 atmosphere.
[0071] Next, in step S8 of Figure 5 (step for applying the base layer paste), as shown in Figure 6G, the conductive paste 7' for the base layer is applied to both end faces MA and MB of each substrate 2 from which the binder was removed in step S7, and also to the remaining four faces (top, bottom, and both sides) adjacent to the end faces MA and MB. For example, a dipping method can be used to apply the conductive paste 7' for the base layer. After that, the conductive paste 7' is allowed to dry. The conductive paste 7' for the base layer contains metal powder or filler used as the conductive material for the base layer 7. For example, if the metal used as the conductive material for the base layer 7 is Ni, the conductive paste 7' for the base layer contains Ni powder or filler. The conductive paste 7' for the base layer also contains, as a co-material, a ceramic component which is the main component of the co-material of the dielectric layer 4. The conductive paste 7' for the base layer contains, as a co-material, particles of oxide ceramic mainly composed of barium titanate (for example, D50 particle size of 0.1 μm to 4 μm). The conductive paste 7' for the base layer further contains a binder and a solvent. However, the conductive paste 7' for the base layer may be applied and fired after the base body 2 has been fired (step S9). In this case, the conductive paste 7' may be fired, for example, in an N2 atmosphere at a temperature of 780°C for about 10 to 30 minutes.
[0072] Next, in step S9 (firing step) in Figure 5, as shown in Figure 6H, the substrate 2 to which the conductive paste for the base layer 7 was applied in step S8 is subjected to a firing step so that the internal electrode layers 3A and 3B are integrated with the dielectric layer 4 of each substrate 2, and the base layer 7 is integrated with the substrate 2. The firing of the substrate 2 and the conductive paste 7' is carried out, for example, in a firing furnace at a temperature range of 1000°C to 1400°C for 10 minutes to 2 hours. When using base metals such as Ni or Cu as the material for the internal electrode layers 3A and 3B, the firing step may be performed in a reducing atmosphere inside the firing furnace to prevent oxidation of the internal electrode layers 3A and 3B. As described above, in the firing step, the shrinkage temperature of the laminate 2A and the shrinkage temperatures of the cover layers 5A and 5B are different. As a result, the internal stress changes depending on the position of the base body 2, causing the top surface TS and bottom surface BS of the base body 2 to curve in a convex shape, while the sides SA and SB of the base body 2 to curve in a concave shape. During the firing step, some oxide components in the dielectric material of element 2 may decrease; therefore, a re-oxidation step may be performed after the firing step. The re-oxidation step may be performed in an N2 atmosphere at a temperature range of 600°C to 1000°C.
[0073] Next, in step S10 (plating layer formation step) in Figure 5, a plating layer 9 is formed on the underlayer 7 as shown in Figure 6I. When forming the plating layer 9, for example, a Cu plating layer, a Ni plating layer, and a Sn plating layer may be formed sequentially. The plating layer can be formed by placing the substrate 2 on which the underlayer 7 has been formed into a barrel, immersing it in the plating solution in the barrel, and applying an electric current while rotating the barrel.
[0074] Figure 7 shows the relationship between the deformation of the material of the multilayer ceramic capacitor 1A according to the first embodiment and temperature during heating. Figure 7 shows the results obtained by Thermal Mechanical Analysis (TMA) of the material of multilayer ceramic capacitor 1A. In the graph, curve M1 corresponds to the thermal shrinkage behavior of the materials in the internal electrode layers 3A and 3B of the laminate 2A, while curves M2 to M4 show the thermal shrinkage behavior of the different materials in the cover layers 5A and 5B. As shown in each curve, the rate of contraction increases significantly with increasing temperature. The temperature at which contraction begins can be called the contraction start temperature, and the temperature at which contraction ends can be called the contraction end temperature. Furthermore, the temperature at which the shrinkage rate is maximum (the temperature at which the slope angle of the curve is maximum) can be called the shrinkage temperature. In curve M1, the shrinkage temperature of the materials of the internal electrode layers 3A and 3B is Ta (°C). In curve M3, the shrinkage temperature of the materials of the cover layers 5A and 5B is Tx (°C).
[0075] Since the shrinkage temperature of the cover layers 5A and 5B is higher than that of the internal electrode layers 3A and 3B, the internal electrode layers 3A and 3B begin to shrink before the cover layers 5A and 5B begin to shrink. As the shrinkage of the internal electrode layers 3A and 3B mainly occurs in the width direction DW, the sides SA and SB of the element body 2 deform to curve concavely along the height direction DH, as shown in Figures 2A and 2B, and as a result the inner portion of the laminate 2A is greatly compressed. Due to the compressive internal stress, the upper surface TS and lower surface BS of the element body 2 curve convexly along the width direction DW, and the compressive internal stress itself is released. If the shrinkage temperature of the cover layers 5A and 5B is significantly higher than that of the internal electrode layers 3A and 3B, the internal electrode layers 3A and 3B will shrink faster than the deformation of the cover layers 5A and 5B, increasing the stress within the laminate 2A. As a result, the concave and convex curvatures on the outer surface of the base body 2 will increase.
[0076] However, if the stress within the element 2 is too high, the durability of the element 2 against mechanical and / or electrical fatigue will decrease, and the reliability of the multilayer ceramic capacitor 1A will decline. On the other hand, if the shrinkage temperatures of the cover layers 5A and 5B are too close to those of the internal electrode layers 3A and 3B, delamination is likely to occur between the laminate 2A and the cover layers 5A and 5B. The inventors conducted experiments to confirm the occurrence and reliability of delamination in different samples of the multilayer ceramic capacitor 1A. Table 1 shows the shrinkage temperature Ta (°C) of the internal electrode layers 3A and 3B and the shrinkage temperature Tx (°C) of the cover layers 5A and 5B for each sample. These samples have different TA and Tx values. The shrinkage temperatures Ta and Tb are obtained by TMA. The TMA conditions were a heating rate of 10°C / min and an atmosphere consisting of a mixed gas of nitrogen (99%) and hydrogen (1%). The reliability of the samples was confirmed by sample durability testing (HALT (Highly Accelerated Life Testing)).
[0077] [Table 1]
[0078] In sample 1, delamination occurred after the firing step, but it was at an acceptable level. Post-manufacturing durability tests yielded good results. In sample 2, delamination occurred after the firing step, but it was at an acceptable level. Post-manufacturing durability tests yielded good results. In sample 3, almost no delamination occurred after the firing step. Good results were obtained in post-manufacturing durability tests. In sample 4, no delamination occurred after the firing step. Good results were obtained in post-manufacturing durability tests. In sample 5, almost no delamination occurred after the firing step. Good results were obtained in post-manufacturing durability tests. In sample 6, no delamination occurred after the firing step. Good results were obtained in post-manufacturing durability tests. In sample 7, no delamination occurred after the firing step. Good results were obtained in post-manufacturing durability tests. In sample 8, problematic delamination occurred after the firing step. Post-manufacturing durability tests yielded unsatisfactory results. In sample 9, problematic delamination occurred after the firing step. However, good results were obtained in post-manufacturing durability tests. Based on the experimental results above, it is preferable that 1.20 ≤ Tx / Ta ≤ 1.85, and even more preferable that 1.30 ≤ Tx / Ta ≤ 1.60. Furthermore, it is even more preferable that 1.30 ≤ Tx / Ta ≤ 1.40.
[0079] As described above, as shown in Figure 4, the sides SA and SB of the base body 2 are curved concavely along the longitudinal direction DL. As shown in Figure 3, the top surface TS and bottom surface BS of the base body 2 are curved convexly along the longitudinal direction DL. As shown in Figures 2A and 2B, the sides SA and SB are curved concavely along the height direction DH, and the top surface TS and bottom surface BS are curved convexly along the width direction DW.
[0080] The preferred shapes of the upper surface TS, lower surface BS, and side surfaces SA,SB of the base body 2 can be obtained by adjusting at least one of (i) the grain size of the dielectric (ceramic) material contained in the cover layers 5A, 5B, (ii) the amount of glass phase additive contained in the material of the cover layers 5A, 5B, and (iii) the amount of binder mixed into the dielectric powder contained in the cover layers 5A, 5B. (i) By increasing the grain size of the dielectric material contained in the cover layers 5A and 5B, the shrinkage start temperature of the cover layers 5A and 5B during firing can be raised, and as a result, the amount of concave curvature of the side surfaces SA and SB (see Figure 4), which are curved concavely along the longitudinal direction DL, can be increased. (ii) Increasing the amount of glass phase additive added to the dielectric material powder contained in the cover layers 5A and 5B can lower the shrinkage start temperature and shrinkage temperature of the cover layers 5A and 5B during firing, thereby reducing the amount of concave curvature of the side surfaces SA and SB (see Figure 4) which are curved concavely along the longitudinal direction DL. (iii) By increasing the amount of binder mixed into the dielectric powder contained in the cover layers 5A and 5B, the shrinkage start temperature of the cover layers 5A and 5B during firing can be raised, thereby increasing the amount of concave curvature of the side surfaces SA and SB (see Figure 4) which are curved concavely along the longitudinal direction DL, and increasing the amount of convex curvature of the upper surface TS and lower surface BS (see Figure 3) which are curved convexly along the longitudinal direction DL.
[0081] Second Embodiment Figure 8A is a cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment of the present invention, cut in the same manner as in Figure 2A. Figure 8B is a cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment, cut in the same manner as in Figure 2B. Figure 8C is a cross-sectional view of the multilayer ceramic capacitor 1B according to the second embodiment, cut in the same manner as in Figure 4. As shown in Figures 8A to 8C, the multilayer ceramic capacitor 1B has a sealing resin layer 8 in addition to the base body 2 and external electrodes 6A and 6B. Except for the sealing resin layer 8, the multilayer ceramic capacitor 1B is the same as the multilayer ceramic capacitor 1A.
[0082] The sealing resin layer 8 covers the top surface TS of the base body 2, the top surfaces of the external electrodes 6A and 6B, the upper parts of the sides SA and SB of the base body 2, and the upper parts of the sides of the external electrodes 6A and 6B. The sealing resin layer 8 may cover the entire multilayer ceramic capacitor 1B, except for the bottom surfaces of the external electrodes 6A and 6B which are electrically connected to the electrodes on the circuit board. The resin layer 8 may be formed from a thermoplastic resin, a thermosetting resin, a UV-curable resin, or the like. The material for the resin layer 8 may be applied by spraying or by dipping.
[0083] By applying the resin layer 8 to the base body 2 and the external electrodes 6A and 6B, moisture can be prevented from entering the charge storage area within the base body 2, improving impact resistance and thus enhancing the reliability of the multilayer ceramic capacitor 1B. Furthermore, when mounting the multilayer ceramic capacitor 1B onto a circuit board using solder to connect the external electrodes 6A and 6B to electrodes on the circuit board, the sealing resin layer 8 prevents the solder from wetting the upper surface of the external electrodes 6A and 6B. This prevents the height of the multilayer ceramic capacitor 1B from increasing after mounting on the board.
[0084] As shown in Figures 8A and 8B, the sides SA and SB of the base body 2 are curved concavely along the height direction DH. Therefore, it is possible to prevent the uncured resin from falling along the sides SA and SB. In addition, by making the sealing resin layer 8 thicker in the height direction center of each side SA and SB of the base body 2, it is possible to prevent moisture from entering the charge storage region within the base body 2. This ensures the reliability of the multilayer ceramic capacitor 1B.
[0085] Third Embodiment Figure 9 is a cross-sectional view showing a structure according to a third embodiment of the present invention in which a multilayer ceramic capacitor is mounted on a circuit board. As shown in Figure 9, land electrodes 12A and 12B are formed on the circuit board 11. The circuit board 11 may be a printed circuit board or, for example, a semiconductor substrate made of Si. The multilayer ceramic capacitor 1A is connected to the land electrodes 12A and 12B via solder layers 13A and 13B attached to the plating layers 9 of the external electrodes 6A and 6B, respectively.
[0086] Each of the solder layers 13A and 13B wets up to the end faces of the corresponding external electrodes 6A and 6B. If the multilayer ceramic capacitor 1A has a small height, each of the solder layers 13A and 13B may wet up to the top surface of the corresponding external electrode 6A or 6B.
[0087] However, because the top surface TS of the base body 2 is curved convexly along the longitudinal direction DL, the height of each external electrode 6A, 6B gradually decreases towards the end faces MA, MB of the base body 2. Therefore, even if the solder layers 13A, 13B wet up to the top surface of the external electrodes 6A, 6B, it is difficult for the solder layers 13A, 13B to reach the top surface TS of the base body 2. As a result, it is possible to prevent an increase in height when mounting the multilayer ceramic capacitor 1A.
[0088] Fourth Embodiment Figure 10 is a perspective view showing a ceramic electronic component according to a fourth embodiment of the present invention. In Figure 10, a chip inductor is given as an example of the ceramic electronic component. The chip inductor 61 has a base body 62 and two external electrodes 66A and 66B. The base body 62 has a coil pattern 63 with two end pieces 63A and 63B formed at both ends and a magnetic material 64. The portion of the coil pattern 63 including the end pieces 63A and 63B is formed in a thin, flat shape, while the entire coil pattern 63 is formed in a spiral shape. The magnetic material 64 is used as a dielectric to insulate the internal electrode layer formed by the coil pattern 63. A lower cover layer 65A, similar to the lower cover layer 5A, is provided on the lower part of the base body 62, and an upper cover layer 65B, similar to the upper cover layer 5B, is provided on the upper part of the base body 62. The shrinkage temperature of the cover layers 65A and 65B is higher than that of the coil pattern 63.
[0089] The shape of base model 62 can be approximately a rectangular prism. However, the sides SA and SB of the base body 62 are curved concavely along the longitudinal direction DL, and the base body 62 has a longitudinal central portion with a width smaller than the width of the longitudinal ends.
[0090] The upper surface TS and lower surface BS of the base body 62 are curved convexly along the longitudinal direction DL, and the base body 62 has a longitudinal central portion that is thicker than the thickness of the longitudinal ends.
[0091] Furthermore, the sides SA and SB of the base body 62 are curved concavely along the height direction DH, and the base body 62 has a central part in the height direction with a width smaller than the width of the ends in the height direction. The radius of curvature of each side along the height direction DH is smallest at the central part in the longitudinal direction and may gradually increase toward both ends in the longitudinal direction of the base body 62 (similar to the comparison in Figures 2A and 2B above).
[0092] The upper surface TS and lower surface BS of the base body 62 are curved convexly along the width direction DW, and the base body 62 has a lateral central portion that is thicker than the thickness of both lateral sides. The radius of curvature of the upper and lower surfaces along the width direction DW is smallest at the longitudinal central portion and may gradually increase toward both longitudinal ends of the base body 62 (similar to the comparison in Figures 2A and 2B above).
[0093] The coil pattern 63 is embedded in the magnetic material 64. However, one end piece 63A is exposed from the magnetic material 64 at one end face MA of the base body 62 and is connected to the external electrode 66A. On the other hand, the other end piece 63B is exposed from the magnetic material 64 at the other end face MB of the base body 62 and is connected to the external electrode 66B.
[0094] The material of the coil pattern 63 and end pieces 63A, 63B may be, for example, metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, W, or alloys containing at least one of these metals. The magnetic material 64 is, for example, ferrite.
[0095] The external electrodes 66A and 66B are positioned on opposite sides of the base body 62, respectively, so as to be spaced apart from each other in the longitudinal direction DL. Each of the external electrodes 66A and 66B extends continuously from the corresponding end face MA or MB of the base body 62 to the side, top, and bottom surfaces of the base body 62.
[0096] experiment The inventor conducted experiments to confirm the occurrence of cracks and durability of different samples of the multilayer ceramic capacitor 1A. Figures 11 and 12 show the relationship between dimensions, crack occurrence, and durability (HALT results) of different samples of the multilayer ceramic capacitor according to the first embodiment. The sample in Figure 11 corresponds to JIS "3225". The dielectric layer 4 is made of barium titanate, and the thickness of each dielectric layer 4 between the internal electrode layers 3A and 3B is 1.5 μm. The internal electrode layers 3A and 3B are made of nickel, with a thickness of 1.0 μm for each layer, and the total number of internal electrode layers 3A and 3B is 200. The sample in Figure 12 corresponds to JIS "1608" (length = 1.6 mm, width = 0.8 mm, height = 0.8 mm). The dielectric layer 4 is made of barium titanate, and the thickness of each dielectric layer 4 between the internal electrode layers 3A and 3B is 0.8 μm. The internal electrode layers 3A and 3B are made of nickel, with a thickness of 0.6 μm for each layer, and the total number of internal electrode layers 3A and 3B is 200. The samples used in the experiment had different dimensions (W1, W2, W3, T1, T2, T3). Furthermore, these samples satisfied the condition 1.20 ≤ Tx / Ta ≤ 1.85. Figures 11 and 12, "HALT Results," show the lifetime at which 50% of the samples would fail during HALT. Based on the crack occurrence and HALT results, the samples were classified into good and defective products. Samples A-I and L-T were good, while samples J, K, U, and V were defective.
[0097] If the concave curvature in the width direction DW on the sides SA and SB of base body 2 is large, the difference between widths W2 and W1 is large, so the above ratio {(W2-W1) / W2} / {(T1-T2) / T2} is large (see Figure 2B). Also, if the concave curvature in the longitudinal direction DL on the sides SA and SB of base body 2 is large, the difference between widths W3 and W1 is large, so the above ratio (W3-W1) / W3 is large (see Figure 2A). If the concave curvature in the width direction DW on the sides SA and SB of the base body 2 is large, and the concave curvature in the longitudinal direction DL on the sides SA and SB of the base body 2 is also large, it is possible to suppress the occurrence of cracks, extend the lifespan of the multilayer ceramic capacitor 1A, and ensure the reliability of the multilayer ceramic capacitor 1A.
[0098] However, if the concave curvature in the width direction DW on the sides SA and SB of the base body 2 is too large, the durability of the multilayer ceramic capacitor 1A will decrease. Therefore, 3.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦30 % It is preferable that this be the case, 5.5 % ≦{(W2-W1) / W2} / {(T1-T2) / T2}≦20 % It is even more preferable that this be the case.
[0099] Furthermore, if the concave curvature in the width direction DW on the sides SA and SB of the base body 2 is too large, the durability of the multilayer ceramic capacitor 1A will decrease. Therefore, 0 < (W3 - W1) / W3 ≤ 0.15 % Preferably, 0.04 % <(W3-W1) / W3≦0.12 % It is even more preferable that this be the case.
[0100] In the embodiments described above, multilayer ceramic capacitors and chip inductors were given as examples of ceramic electronic components, but the ceramic electronic components according to the present invention may be chip resistors or sensor chips. Also, in the embodiments described above, each ceramic electronic component includes two external electrodes, but the ceramic electronic components may include three or more external electrodes. [Explanation of Symbols]
[0101] 1. Multilayer ceramic capacitor 2. Base body 2A laminate 3A, 3B Internal electrode layer 4. Dielectric layer 5A, 5B Cover layer 6A, 6B external electrode 7 Base layer 9 Plating layer
Claims
1. A substrate having a dielectric, at least one first internal electrode, and at least one second internal electrode laminated on the first internal electrode with a dielectric interposed between the first internal electrode and the second internal electrode, The first external electrode and, It has a second external electrode, The body has an upper surface, a lower surface, a pair of side surfaces, a first end surface, and a second end surface, and thereby the body has a substantially rectangular parallelepiped shape. The first internal electrode is exposed at the first end face, and the second internal electrode is exposed at the second end face. Both sides of the body are curved concavely along the longitudinal direction, and the body has a longitudinal central portion having a width smaller than the width of the first end face and the second end face. The first external electrode is formed on the first end face and electrically connected to the first internal electrode, and the second external electrode is formed on the second end face and electrically connected to the second internal electrode. Both sides of the aforementioned body are curved concavely along the height direction, and each side has a radius of curvature along the height direction, the radius of curvature along the height direction is smallest at the longitudinal center of the body and increases towards the end faces. Ceramic electronic components.
2. A substrate having a dielectric, at least one first internal electrode, and at least one second internal electrode laminated on the first internal electrode with a dielectric interposed between the first internal electrode and the second internal electrode, The first external electrode and, It has a second external electrode, The body has an upper surface, a lower surface, a pair of side surfaces, a first end surface, and a second end surface, and thereby the body has a substantially rectangular parallelepiped shape. The first internal electrode is exposed at the first end face, and the second internal electrode is exposed at the second end face. Both sides of the body are curved concavely along the longitudinal direction, and the body has a longitudinal central portion having a width smaller than the width of the first end face and the second end face. The first external electrode is formed on the first end face and electrically connected to the first internal electrode, and the second external electrode is formed on the second end face and electrically connected to the second internal electrode. The base body satisfies 0 < (W3 - W1) / W3 ≤ 0.15%, where W1 is the width of the base body at the center of the longitudinal direction in the height direction, and W3 is the width of the end face at the center of the base body in the height direction. A ceramic electronic component characterized by the following features.
3. The ceramic electronic component according to claim 2, characterized in that the substrate satisfies 0.04% < (W3 - W1) / W3 ≤ 0.12%.
4. The upper and lower surfaces of the base body are curved convexly along the longitudinal direction, and the longitudinal central portion of the base body has a thickness greater than the thickness of the end faces. A ceramic electronic component according to any one of claims 1 to 3.
5. The upper and lower surfaces of the base body are curved convexly along the width direction, and the lateral central portion of the base body has a thickness greater than the thickness on both sides in the lateral direction. A ceramic electronic component according to any one of claims 1 to 4.
6. The base body satisfies 3.5% ≤ {(W2 - W1) / W2} / {(T1 - T2) / T2} ≤ 30%, where W1 is the width of the base body at the center of its longitudinal direction in the height direction, W2 is the width of the base body at the center of its longitudinal direction at both upper and lower ends, T1 is the thickness of the base body at the center of its longitudinal direction in the width direction, and T2 is the thickness of the base body at the center of its longitudinal direction on both lateral sides. The ceramic electronic component according to feature 5.
7. The ceramic electronic component according to claim 6, characterized in that the element satisfies 5.5% ≤ {(W2 - W1) / W2} / {(T1 - T2) / T2} ≤ 20%.
8. The ceramic electronic component according to any one of claims 1 to 7, further comprising a sealing resin layer covering the upper surface of the base body, the upper surfaces of the first external electrode and the second external electrode, the upper parts of both sides of the base body, and the upper parts of both sides of the first external electrode and the second external electrode.
9. The ceramic electronic component according to any one of claims 1 to 8, characterized in that it has a length in the range of 0.25 mm to 0.4 mm, a width in the range of 0.125 mm to 0.2 mm, and a height in the range of 0.125 mm to 0.2 mm.
10. The ceramic electronic component according to any one of claims 1 to 9, characterized in that the dielectric between the first internal electrode and the second internal electrode has a thickness in the range of 0.2 μm to 0.5 μm.
11. The ceramic electronic component according to any one of claims 1 to 10, characterized in that the dielectric of the substrate has an average crystal grain size in the range of 80 nm to 200 nm.
12. The ceramic electronic component according to any one of claims 1 to 11, characterized in that the first internal electrode and the second internal electrode have a thickness in the range of 0.2 μm to 0.8 μm.
13. The ceramic electronic component is characterized by having a capacitance in the range of 10 μF to 1000 μF, as described in any one of claims 1 to 12.
14. The ceramic electronic component according to any one of claims 1 to 13, characterized in that the main component of the material of the first external electrode and the second external electrode is Ni.
15. Circuit board and The circuit board has a ceramic electronic component according to any one of claims 1 to 14, The ceramic electronic component is connected to the circuit board via solder layers bonded to the first and second external electrodes, with the solder layers wetting the end faces of the first or second external electrodes, and no solder layers present on the upper surface of the component. A circuit board structure characterized by the following features.
16. The substrate has a dielectric, internal electrodes, and a cover layer, and has an upper surface, a lower surface, a pair of side surfaces, and a pair of end faces, and has a substantially rectangular parallelepiped shape, each of the internal electrodes being exposed at one of the end faces, the cover layer forming the upper surface and the lower surface, and the cover layer is formed of a material having a shrinkage temperature higher than the shrinkage temperature of the material of the internal electrodes. To fire the aforementioned body, The external electrodes are positioned at both ends in the longitudinal direction of the base body to form an underlayer covering the top surface, bottom surface, both sides, and corresponding end faces of the base body, and The process involves forming a plating layer on each of the underlying layers. A method for manufacturing ceramic electronic components, characterized by the following:
17. The method according to 16, characterized in that the shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer satisfy 1.20 ≤ Tx / Ta ≤ 1.
85.
18. The method according to 17, characterized in that the shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer satisfy 1.30 ≤ Tx / Ta ≤ 1.
60.
19. The method according to 18, characterized in that the shrinkage temperature Ta (°C) of the material of the internal electrode and the shrinkage temperature Tx (°C) of the material of the cover layer satisfy 1.30 ≤ Tx / Ta ≤ 1.40.