Nitride semiconductor devices and their manufacturing methods

Abstract

To provide a nitride semiconductor device in which a decrease in breakdown voltage is suppressed.SOLUTION: A nitride semiconductor device 1 includes: a conductive layer 11; a protruding region 12 of a nitride semiconductor provided on at least a part of an upper surface of the conductive layer; an n-type drift layer 13 provided above the conductive layer, the drift layer including a tapered region 13b tapered upward above the protruding region; and a p-type body layer 14 adjacent to the tapered region of the drift layer. The drift layer and the body layer are an epitaxial layer 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technologies disclosed herein relate to nitride semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Nitride semiconductor devices have a structure in which a p-type body layer is partially provided on an n-type drift layer. To form the p-type body layer, either ion implantation or re-epitaxial growth can be selected. However, it is difficult to form a highly active p-type diffusion region in a semiconductor layer made of nitride semiconductors using ion implantation. For this reason, Patent Documents 1 and 2 propose a technique for forming a body layer on a drift layer using re-epitaxial growth. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-60985 [Patent Document 2] Japanese Patent Publication No. 2021-90015 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, our studies have shown that the initial layer of the re-epitaxial layer incorporates many impurities, such as silicon, oxygen, and carbon, resulting in a high-concentration n-type region. The presence of such a high-concentration n-type region can reduce the breakdown voltage of a nitride semiconductor device. This specification provides a nitride semiconductor device in which breakdown voltage reduction is suppressed and a method for manufacturing the same. [Means for solving the problem]

[0005] The nitride semiconductor devices (1,2,3,4,5,6,7,8) disclosed herein may comprise a conductive layer (11,22,103), a convex region (12,112,212) of a nitride semiconductor provided on at least a portion of the upper surface of the conductive layer, an n-type drift layer (13) provided above the conductive layer, the drift layer including a tapered region (13b) that tapers upward above the convex region, and a p-type body layer (14) adjacent to the tapered region of the drift layer. The conductive layer may be a semiconductor containing impurities, or it may be a metal. The drift layer and the body layer may be epitaxial layers (10). In this nitride semiconductor device, since the drift layer and the body layer are composed of epitaxial layers, the high-density n-type region formed in the initial layer when these epitaxial layers are re-epitaxially grown is formed at least around the convex region. In this nitride semiconductor device, the drift layer is provided above the convex region, so the drift layer is interposed between the high-density n-type region and the p-type body layer. Furthermore, the drift layer includes the tapered region above the convex region. Therefore, the body layer adjacent to the tapered region is inclined toward moving away from the convex region. Thus, the nitride semiconductor device disclosed herein has a structure in which a distance is secured between the high-density n-type region and the p-type body layer, thereby suppressing a decrease in breakdown voltage.

[0006] One method for manufacturing a nitride semiconductor device (1,2,3,6,7,8) disclosed herein may include: a convex region formation step of etching the upper surface of an n-type nitride semiconductor layer (11) to form a convex region (12,212); a drift layer deposition step of growing crystals from the upper surface of the nitride semiconductor layer to form an n-type drift layer (13) with a lower n-type impurity concentration than the nitride semiconductor layer, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region; and a body layer deposition step of growing crystals from the upper surface of the drift layer to form a p-type body layer (14), wherein the body layer is adjacent to the tapered region of the drift layer. According to this manufacturing method, a nitride semiconductor device having a structure in which a decrease in breakdown voltage is suppressed can be manufactured.

[0007] One method for manufacturing a nitride semiconductor device (4) disclosed herein is a mask layer formation step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11,103), wherein the mask layer has an opening (42a); and a convex region formation step of forming a convex region (112) by crystal growth from the upper surface of the nitride semiconductor layer exposed from the opening of the mask layer. The manufacturing method may include: a mask layer removal step of removing the mask layer; a drift layer deposition step of growing crystals from the upper surface of the nitride semiconductor layer to form an n-type drift layer (13), wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region; and a body layer deposition step of growing crystals from the upper surface of the drift layer to form a p-type body layer (14), wherein the body layer is adjacent to the tapered region of the drift layer. According to this manufacturing method, a nitride semiconductor device having a structure in which a decrease in breakdown voltage is suppressed can be manufactured.

[0008] One method for manufacturing a nitride semiconductor device (4, 5) disclosed herein may include: a mask layer formation step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11, 103), wherein the mask layer has an opening (42a); a convex region formation step of forming a convex region (112) by crystal growth from the upper surface of the nitride semiconductor layer exposed from the opening of the mask layer; a drift layer deposition step of forming an n-type drift layer (13) by crystal growth from the convex region, wherein the drift layer is provided above the nitride semiconductor layer and includes an upwardly tapering region (13b) above the convex region; and a body layer deposition step of forming a p-type body layer (14) by crystal growth from the upper surface of the drift layer, wherein the body layer is adjacent to the tapering region of the drift layer. According to this manufacturing method, a nitride semiconductor device having a structure in which a decrease in breakdown voltage is suppressed can be manufactured. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic cross-sectional view of a key part of one embodiment of a nitride semiconductor device is shown. [Figure 2] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 3] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 4] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 5] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 6] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 7] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 8] Figure 1 schematically shows a cross-sectional view of the key components in the manufacturing process of a nitride semiconductor device. [Figure 9]Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 10] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 11] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 12] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 13] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 14] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 1. [Figure 15] Schematically shows a cross-sectional view of a main part of an embodiment of the nitride semiconductor device. [Figure 16] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 15. [Figure 17] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 15. [Figure 18] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 15. [Figure 19] Schematically shows a cross-sectional view of a main part of a modified example of the nitride semiconductor device shown in FIG. 15. [Figure 20] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 19. [Figure 21] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 19. [Figure 22] Schematically shows a cross-sectional view of a main part of an embodiment of the nitride semiconductor device. [Figure 23] Schematically shows a cross-sectional view of a main part of an embodiment of the nitride semiconductor device. [Figure 24] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 23. [Figure 25] Schematically shows a cross-sectional view of a main part in the manufacturing process of the nitride semiconductor device shown in FIG. 23. [Figure 26] Figure 23 schematically shows a cross-sectional view of a modified nitride semiconductor device. [Figure 27] Figure 23 schematically shows a cross-sectional view of a modified nitride semiconductor device. [Figure 28] Figure 23 schematically shows a cross-sectional view of a modified nitride semiconductor device. [Figure 29] A schematic cross-sectional view of a key part of one embodiment of a nitride semiconductor device is shown. [Figure 30] Figure 29 schematically shows a cross-sectional view of the main components in the manufacturing process of nitride semiconductor devices. [Figure 31] Figure 29 schematically shows a cross-sectional view of the main components in the manufacturing process of nitride semiconductor devices. [Figure 32] Figure 29 schematically shows a cross-sectional view of the main components in the manufacturing process of nitride semiconductor devices. [Figure 33] A schematic cross-sectional view of a key part of one embodiment of a nitride semiconductor device is shown. [Figure 34] A schematic cross-sectional view of a key part of one embodiment of a nitride semiconductor device is shown. [Figure 35] A schematic cross-sectional view of a key part of one embodiment of a nitride semiconductor device is shown. [Modes for carrying out the invention]

[0010] Hereinafter, a semiconductor device to which the technology disclosed herein is applied and a method for manufacturing the same will be described with reference to the drawings. In the following description, components that are substantially common throughout the drawings will be denoted by the same reference numerals, and their descriptions may be omitted. Also, for the purpose of clarity in the illustrations, only some of the repeatedly arranged structures will be denoted by reference numerals.

[0011] The term "nitride semiconductor" as used in this specification refers to In X Al Y Ga 1-X-Y It is a compound defined as N (where 0 ≤ X ≤ 1 and 0 ≤ Y ≤ 1).

[0012] (Nitride Semiconductor Device 1 of the First Embodiment) As shown in FIG. 1, the nitride semiconductor device 1 includes an n + -type nitride semiconductor layer 11, an n + -type convex region 12 of the nitride semiconductor, an n - -type drift layer 13 of the nitride semiconductor, a p - -type body layer 14 of the nitride semiconductor, and an n ++ -type source layer 15 of the nitride semiconductor. In this example, each of these layers and regions is made of gallium nitride (GaN). The drift layer 13, the body layer 14, and the source layer 15 are layers formed by using the regrowth technology from the upper surface of the nitride semiconductor layer 11 as described in the manufacturing method to be described later, and are also referred to as the epi layer 10.

[0013] The nitride semiconductor layer 11 is a GaN self-supporting substrate in this example. The nitride semiconductor layer 11 may be a base substrate on which the nitride semiconductor can grow epitaxially from its upper surface. Instead of the GaN self-supporting substrate, for example, a GaN-on-Si substrate, a GaN-on-SiC substrate, or a GaN-on-sapphire substrate may be used. The n-type impurity concentration of the nitride semiconductor layer 11 is not particularly limited, but may be, for example, 1×10 17 ~1×10 22 cm -3 . The nitride semiconductor layer 11 is also referred to as a drain layer from the function in the nitride semiconductor device 1. Note that the nitride semiconductor layer 11 is an example of a conductive layer.

[0014] The convex region 12 is provided on at least a portion of the upper surface of the nitride semiconductor layer 11 and protrudes upward from the upper surface of the nitride semiconductor layer 11. The convex region 12 is a region formed by etching the upper surface of the nitride semiconductor layer 11, as will be explained later in the manufacturing method, and is also a part of the nitride semiconductor layer 11. When viewed from above, the convex region 12 may extend long in one direction or may be dispersed in an island-like manner. The convex region 12 may be made of a nitride semiconductor, and its conductivity type and impurity concentration are not particularly limited. For example, the convex region 12 may be a p-type nitride semiconductor. Also, the convex region 12 does not have to be made of a single layer. For example, the convex region 12 may be made of multiple layers stacked with different impurity concentrations, or of layers stacked with different conductivity types, or of layers stacked including an undoped layer.

[0015] The drift layer 13 covers the convex region 12 and is located above the nitride semiconductor layer 11. The n-type impurity concentration of the drift layer 13 is lower than that of the nitride semiconductor layer 11. The n-type impurity concentration of the drift layer 13 is not particularly limited, but for example, 1 × 10⁻⁶ 15 ~1 × 10 18 cm -3 That's fine.

[0016] The drift layer 13 has a flat region 13a and a tapered region 13b. The flat region 13a has a flat shape that extends on the nitride semiconductor layer 11 in the direction of the epitaxial layer 10, that is, parallel to the upper surface of the nitride semiconductor layer 11. In this example, the flat region 13a is in contact with the upper surface of the nitride semiconductor layer 11 and the top and side surfaces of the convex region 12, and has a predetermined thickness. The tapered region 13b is provided on a part of the upper surface of the flat region 13a and has a shape that tapers upward above the convex region 12. The tapered region 13b extends to the upper surface of the epitaxial layer 10. The side surface of the tapered region 13b is continuously inclined from the position in contact with the upper surface of the flat region 13a to the position of the upper surface of the epitaxial layer 10. Thus, the tapered region 13b has a trapezoidal cross-section.

[0017] In the drift layer 13, a high-density n-type region 13c exists in the portion that is in contact with the upper surface of the nitride semiconductor layer 11 and the top and side surfaces of the convex region 12. Alternatively, a high-density n-type region 13c can be said to be interposed between the upper surface of the nitride semiconductor layer 11 and the top and side surfaces of the convex region 12 and the drift layer 13. As will be explained in the manufacturing method described later, this high-density n-type region 13c is the initial layer during re-epitaxial growth.

[0018] The body layer 14 is provided on the drift layer 13. More specifically, the body layer 14 is located on the flat region 13a of the drift layer 13, adjacent to the side surface of the tapered region 13b of the drift layer 13. A portion of the body layer 14 is positioned to be exposed on the upper surface of the epitaxial layer 10. Thus, the body layer 14 has a shape that tapers downwards. The lower end 14a of the body layer 14 is located above the upper end 12a of the convex region 12. Alternatively, the lower end 14a of the body layer 14 may be located below the upper end 12a of the convex region 12. That is, the body layer 14 may be configured such that its lower end 14a penetrates the region between adjacent convex regions 12.

[0019] The source layer 15 is located on the body layer 14 and is positioned to be exposed on the upper surface of the epitaxial layer 10. The source layer 15 is separated from the drift layer 13 by the body layer 14.

[0020] The nitride semiconductor device 1 further includes a drain electrode 22, a source electrode 24, and a planar insulated gate 30.

[0021] The drain electrode 22 is positioned in contact with the lower surface of the nitride semiconductor layer 11 and is in ohmic contact with the nitride semiconductor layer 11. The source electrode 24 is positioned above the epitaxial layer 10 so as to cover the insulating gate 30. The source electrode 24 has a contact portion 24a that extends from the upper surface of the epitaxial layer 10, through the source layer 15, and reaches the body layer 14. The contact portion 24a of the source electrode 24 is in ohmic contact with the body layer 14 and the source layer 15.

[0022] The insulated gate 30 is provided on a portion of the upper surface of the epitaxial layer 10 and has a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 is in contact with the upper surface of the epitaxial layer 10. The gate electrode 34 faces the upper surface of the epitaxial layer 10 via the gate insulating film 32. In particular, the gate electrode 34 is provided so as to face the body layer 14 that separates the tapered region 13b of the drift layer 13 from the source layer 15 via the gate insulating film 32. The gate electrode 34 is also insulated from the source electrode 24 by an interlayer insulating film 36.

[0023] Next, the operation of the nitride semiconductor device 1 will be explained. During use, for example, a voltage is applied such that the drain electrode 22 is more positive than the source electrode 24. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 34, an inversion layer is formed in the body layer 14 separating the tapered region 13b of the drift layer 13 from the source layer 15, and the nitride semiconductor device 1 turns on. At this time, electrons flow from the source layer 15 to the tapered region 13b via the inversion layer. The electrons that flow into the tapered region 13b flow vertically through the tapered region 13b toward the nitride semiconductor layer 11. As a result, the drain electrode 22 and the source electrode 24 become conductive.

[0024] When the gate electrode 34 is brought to the same potential as the source electrode 24, the inversion layer disappears, and the nitride semiconductor device 1 turns off. At this time, a depletion layer extends from the pn junction surface of the drift layer 13 and the body layer 14 into the drift layer 13. In particular, the tapered region 13b of the drift layer 13 is substantially completely depleted. In the nitride semiconductor device 1, a high-concentration n-type region 13c is formed at a position away from the pn junction surface of the drift layer 13 and the body layer 14. In the nitride semiconductor device 1, the drift layer 13 is provided so as to cover the upper surface of the nitride semiconductor layer 11 and the top and side surfaces of the convex region 12, so a drift layer 13 with a low n-type impurity concentration is interposed between the high-concentration n-type region 13c and the body layer 14. Furthermore, the drift layer 13 includes a tapered region 13b above the convex region 12. For this reason, the body layer 14 adjacent to the tapered region 13b is inclined away from the convex region 12. Thus, in the nitride semiconductor device 1, a distance is maintained between the highly concentrated n-type region 13c and the body layer 14, thereby suppressing the extension of the depletion layer extending from the pn junction surface of the drift layer 13 and the body layer 14. As a result, the nitride semiconductor device 1 can have a high breakdown voltage.

[0025] (Method for manufacturing nitride semiconductor device 1) First, as shown in Figure 2, a nitride semiconductor layer 11, which is a GaN self-supporting substrate, is prepared. Next, as shown in Figure 3, a portion of the upper surface of the nitride semiconductor layer 11 is removed using etching technology to form a convex region 12.

[0026] Next, as shown in Figures 4 and 5, the drift layer 13 is grown using epitaxial growth technology from the top surface of the nitride semiconductor layer 11 and from the top and side surfaces of the convex region 12. At this time, by adjusting the growth temperature, gas flow rate, pressure, etc., a tapered region 13b can be formed above the convex region 12. In addition, the initial layer of the drift layer 13, which is a re-epitaxial layer, incorporates many impurities such as silicon, oxygen, and carbon, forming a high-concentration n-type region 13c. In this example, a high-concentration n-type region 13c is formed in the portion of the drift layer 13 that is in contact with the top surface of the nitride semiconductor layer 11 and the side and top surfaces of the convex region 12. In this example, the drift layer 13 was grown using epitaxial growth technology from the top surface of the nitride semiconductor layer 11 and from the top and side surfaces of the convex region 12, but instead of this example, the drift layer 13 may be grown after growing a high-concentration n-type epitaxial layer.

[0027] Next, as shown in Figure 6, the body layer 14 is grown from the upper surface of the drift layer 13 using epitaxial growth technology. At this time, by adjusting the growth temperature, gas flow rate, pressure, etc., irregularities corresponding to the shape of the tapered region 13b of the drift layer 13 can be formed on the upper surface of the body layer 14.

[0028] Next, as shown in Figure 7, the source layer 15 is grown from the upper surface of the body layer 14 using epitaxial growth technology. At this time, by adjusting the growth temperature, gas flow rate, and pressure, the upper surface of the source layer 15 can be formed flat. Alternatively, by adjusting the growth temperature, gas flow rate, and pressure, the source layer 15 may be formed so that irregularities are created on its upper surface. The drift layer 13, the body layer 14, and the source layer 15 are formed by continuous growth in the same chamber, constituting the epitaxial layer 10.

[0029] Next, as shown in Figure 8, the upper surface of the epitaxial layer 10 is flattened using CMP (Chemical Mechanical Polishing) or anisotropic wet etching technology to expose the tapered region 13b of the drift layer 13.

[0030] Next, as shown in Figure 9, a gate insulating film 32 and a gate electrode 34 are deposited on the upper surface of the epitaxial layer 10 using a film deposition technique.

[0031] Next, as shown in Figure 10, a portion of the gate electrode 34 is removed using etching technology to form an insulated gate 30.

[0032] Next, as shown in Figure 11, an interlayer insulating film 36 is formed on the epitaxial layer 10 to cover the gate electrode 34 using film deposition technology.

[0033] Next, as shown in Figure 12, etching is used to remove a portion of the interlayer insulating film 36 and the gate insulating film 32, exposing the upper surface of the epitaxial layer 10. Furthermore, etching is used to form a contact hole that penetrates the source layer 15 from the upper surface of the epitaxial layer 10 and reaches the body layer 14.

[0034] Finally, by forming a drain electrode 22 on the lower surface of the nitride semiconductor layer 11 and a source electrode 24 on the upper surface of the epitaxial layer 10, the nitride semiconductor device 1 can be manufactured.

[0035] (Modified example of the manufacturing method of nitride semiconductor device 1) First, as shown in Figure 13, a nitride semiconductor layer 11, which is a GaN self-supporting substrate, is prepared. Next, an n-type epitaxial layer 11a is grown from the top surface of the nitride semiconductor layer 11 using epitaxial growth technology. The n-type impurity concentration of the n-type epitaxial layer 11a is lower than the n-type impurity concentration of the nitride semiconductor layer 11. Alternatively, an undoped epitaxial layer may be formed instead of the n-type epitaxial layer 11a.

[0036] Next, as shown in Figure 14, etching is used to penetrate the n-type epitaxial layer 11a and remove a portion of the upper surface of the nitride semiconductor layer 11 to form a convex region 12. Thus, the convex region 12 formed by this manufacturing method is composed of a laminate in which a layer with a relatively high concentration of n-type impurities is placed on the lower side, and a layer with a relatively low concentration of n-type impurities (or an undoped layer) is placed on the upper side.

[0037] Subsequently, the nitride semiconductor device 1 can be manufactured by carrying out the process described in Figures 4 to 12. According to this manufacturing method, when the drift layer 13 is crystallized (see Figures 4 and 5), the n-type impurities contained in the initial layer, the high-concentration n-type region 13c, diffuse into the low-concentration n-type epitaxial layer 11a (or undoped layer) of the convex region 12, and the concentration of n-type impurities in the n-type region 13c can decrease. Therefore, according to this manufacturing method, a nitride semiconductor device 1 with a higher breakdown voltage can be manufactured.

[0038] (Nitride semiconductor device 2 of the second embodiment) As shown in Figure 15, the nitride semiconductor device 2 is characterized by having a contact layer 16. The contact layer 16 is provided on the body layer 14 and is positioned to be exposed on the upper surface of the epitaxial layer 10. The p-type impurity concentration of the contact layer 16 is higher than that of the body layer 14. With this configuration, the body layer 14 and the source electrode 24 are connected via the contact layer 16 with low contact resistance. Furthermore, when the contact layer 16 is provided, the contact portion 24a of the source electrode 24 (see Figure 1) is unnecessary. The nitride semiconductor device 2, like the nitride semiconductor device 1, can have a high breakdown voltage.

[0039] (Method for manufacturing nitride semiconductor device 2) The process up to the deposition of the body layer 14 is the same as the manufacturing method of the nitride semiconductor device 1 (see Figures 2 to 6 and 13 to 14). Next, as shown in Figure 16, the contact layer 16 is grown from the upper surface of the body layer 14 using epitaxial growth technology. At this time, by adjusting the growth temperature, gas flow rate, and pressure, the upper surface of the contact layer 16 can be formed flat. Alternatively, by adjusting the growth temperature, gas flow rate, and pressure, the contact layer 16 may be deposited so that irregularities are formed on the upper surface of the contact layer 16. The drift layer 13, the body layer 14, and the contact layer 16 are formed by continuous growth in the same chamber, constituting the epitaxial layer 10.

[0040] Next, as shown in Figure 17, the upper surface of the epitaxial layer 10 is flattened using CMP or anisotropic wet etching technology to expose the tapered region 13b of the drift layer 13.

[0041] Next, as shown in Figure 18, n-type impurities are implanted into a portion of the surface of the epitaxial layer 10 using ion implantation technology to form the source layer 15.

[0042] Subsequently, the nitride semiconductor device 2 can be manufactured by forming the insulating gate 30, interlayer insulating film 36, drain electrode 22, and source electrode 24 using the same process as the manufacturing method for the nitride semiconductor device 1.

[0043] (Modified example of nitride semiconductor device 2) As shown in Figure 19, the modified nitride semiconductor device 2 is characterized in that, instead of ion implantation, a source layer 15 is deposited on a portion of the upper surface of the epitaxial layer 10 using a film deposition technique. The modified nitride semiconductor device 2 can also have a high breakdown voltage, similar to the nitride semiconductor device 1.

[0044] (Manufacturing method for a modified example of nitride semiconductor device 2) The process up to planarizing the upper surface of the epitaxial layer 10 is the same as the manufacturing method for the nitride semiconductor device 2 (see Figures 16-17). Next, as shown in Figure 20, a mask 82 is formed on the upper surface of the epitaxial layer 10. The mask 82 has openings corresponding to the formation area of ​​the source layer 15. Next, etching is used to etch the upper surface of the epitaxial layer 10 exposed through the openings in the mask 82 to form depressions 15a. Note that these depressions 15a are formed to improve the connection between the source layer 15 and the channel, and are not necessarily required.

[0045] Next, as shown in Figure 21, a source layer 15 is deposited using a film deposition technique. The source layer 15 is formed to a predetermined thickness within the depression 15a of the epitaxial layer 10. Next, the mask 82 is lifted off and the GaN deposits deposited on the mask 82 are removed. After that, a modified example of the nitride semiconductor device 2 can be manufactured by the same process as the other nitride semiconductor device manufacturing method described above.

[0046] (Third embodiment of nitride semiconductor device 3) As shown in Figure 22, the nitride semiconductor device 3 is characterized by having a trench-type insulated gate 130. The insulated gate 130 is provided in a trench that penetrates from the upper surface of the epitaxial layer 10 through the source layer 15 and the body layer 14 and reaches the tapered region 13b of the drift layer 13. The gate insulating film 132 is provided on the inner wall of the trench. The gate electrode 134 is provided in the trench and faces the source layer 15, the body layer 14, and the tapered region 13b of the drift layer 13 via the gate insulating film 132. The gate electrode 134 is insulated from the source electrode 24 by an interlayer insulating film 36. The nitride semiconductor device 3 can have a high breakdown voltage, similar to the nitride semiconductor device 1. The nitride semiconductor device 3 may also have a contact layer 16, similar to the nitride semiconductor device 2.

[0047] (Method for manufacturing nitride semiconductor device 3) The process up to the deposition of the source layer 15 is the same as the manufacturing method for the nitride semiconductor device 1 (see Figures 2 to 7). When deposition of the source layer 15, the upper surface of the source layer 15 may be made flat by adjusting the growth temperature, gas flow rate, and pressure, or the source layer 15 may be deposited so that irregularities are formed on its upper surface. Next, a trench is formed using etching technology, penetrating from the upper surface of the epitaxial layer 10 through the source layer 15 and the body layer 14 to the tapered region 13b of the drift layer 13. Next, an insulating gate 130 is formed in the trench using known manufacturing technology. The nitride semiconductor device 3 can be manufactured by the same process as the manufacturing methods for other nitride semiconductor devices described above. The contact portion 24a of the source electrode 24 may be formed at the same time as the trench for the insulating gate 130 is formed, or it may be formed in a separate process.

[0048] (Nitride semiconductor device 4 of the fourth embodiment) As shown in Figure 23, the nitride semiconductor device 4 is characterized by having an insulating mask layer 42 between the nitride semiconductor layer 11 and the drift layer 13. The mask layer 42 is not particularly limited, but may be silicon oxide, silicon nitride, or DLC, for example. An opening 42a is formed in the mask layer 42, and a convex region 112 is positioned to pass through the opening 42a. The convex region 112 is an epitaxial layer formed by crystal growth from the upper surface of the nitride semiconductor layer 11 exposed to the opening 42a of the mask layer 42, as will be explained in the manufacturing method described later. The convex region 112 is formed wider than the opening 42a on the mask layer 42. In other words, the convex region 112 has a narrow portion 112b at its lower end, and the narrow portion 112b is positioned to pass through the opening 42a of the mask layer 42. In this example, the cross-sectional shape of the convex region 112 is triangular. The cross-sectional shape of the convex region 112 can be various depending on the growth conditions when it is formed by epitaxial growth. Furthermore, the convex region 11 may be formed to a size such that adjacent convex regions 112 are connected. The n-type impurity concentration in the convex region 112 is higher than the n-type impurity concentration in the drift layer 13. The n-type impurity concentration in the convex region 112 is not particularly limited, but for example, 1 × 10⁻⁶16 ~1 × 10 20 cm -3 That's fine.

[0049] (Method for manufacturing nitride semiconductor device 4) First, as shown in Figure 24, a nitride semiconductor layer 11, which is a GaN self-supporting substrate, is prepared. Next, a mask layer 42 is deposited on the upper surface of the nitride semiconductor layer 11 using film deposition technology. Then, a portion of the mask layer 42 is removed using etching technology to form an opening 42a.

[0050] Next, as shown in Figure 25, a convex region 112 is grown from the upper surface of the nitride semiconductor layer 11 exposed at the opening 42a of the mask layer 42 using epitaxial growth technology. As described above, the cross-sectional shape of the convex region 112 can be various depending on the growth conditions at this time, and the convex regions 112 can be formed to a size that connects adjacent convex regions 112. After that, the nitride semiconductor device 4 is manufactured by the same process as the other nitride semiconductor device manufacturing methods described above. With this manufacturing method, the mask layer 42 suppresses the propagation of dislocations present in the nitride semiconductor layer 11 to the drift layer 13. For this reason, the nitride semiconductor device 4 can have low leakage current characteristics. In the nitride semiconductor device 4, the current path is blocked by the mask layer 42. However, since the n-type impurity concentration of the convex region 112 is adjusted to be high, the increase in on-resistance is suppressed.

[0051] The above describes an example in which a nitride semiconductor layer 11, which is a GaN freestanding substrate, is used as the base substrate. Alternatively, as shown in Figure 26, a nitride semiconductor device 4 may be constructed using a GaN-on-Si substrate 100 as the base substrate. The GaN-on-Si substrate 100 is constructed by stacking a silicon layer 101, a buffer layer 102, and a GaN layer 103, and is formed by crystal growth of the GaN layer 103 on the silicon layer 101 via the buffer layer 102. The nitride semiconductor device 4 equipped with a mask layer 42 can suppress dislocation propagation. Therefore, even if a GaN-on-Si substrate 100 with many dislocations is used as the base substrate, the nitride semiconductor device 4 can have good characteristics. The same can be achieved if a GaN-on-SiC substrate or a GaN-on-sapphire substrate is used as the base substrate instead of the GaN-on-Si substrate 100. By using a GaN-on-Si substrate, a GaN-on-SiC substrate, or a GaN-on-Sapphire substrate as the base substrate, nitride semiconductor devices 4 can be manufactured at low cost.

[0052] The buffer layer 102 of the GaN-on-Si substrate 100 has high resistance. Therefore, as shown in Figure 27, etching techniques may be used to remove a portion of the silicon layer 101 and buffer layer 102 so that the drain electrode 22 and the GaN layer 103 are in contact. In this case, a portion of the silicon layer 101 and buffer layer 102 may be removed so that the drain electrode 22 is positioned below the opening 42a of the mask layer 42. In this example, the drain electrode 22 is positioned in accordance with the current path passing through the opening 42a of the mask layer 42, so the effect of reducing resistance is high. The remaining silicon layer 101 and buffer layer 102 ensure strength during wafer handling while reducing resistance.

[0053] As shown in Figure 28, the nitride semiconductor device 4 may have the mask layer 42 removed. In this example, the nitride semiconductor device 4 is manufactured by removing the mask layer 42 using etching techniques after forming the convex region 112 and before depositing the drift layer 13, as shown in Figure 25.

[0054] (Nitride semiconductor device 5 of the fifth embodiment) As shown in Figure 29, the nitride semiconductor device 5 is characterized by the removal of the nitride semiconductor layer 11. A convex region 112 is provided on a part of the upper surface of the drain electrode 22. A drift layer 13 is provided so as to cover the convex region 112 and to be in contact with the upper surface of the drain electrode 22. Note that the drain electrode 22 is an example of a conductive layer.

[0055] (Method for manufacturing nitride semiconductor device 5) As shown in Figure 30, the process of forming various structures on the nitride semiconductor layer 11 is the same as the method for manufacturing the nitride semiconductor device 4.

[0056] Next, as shown in Figure 31, the nitride semiconductor layer 11 is removed using CMP technology, wet etching technology, or laser stripping technology.

[0057] Next, as shown in Figure 32, the mask layer 42 is removed using wet etching technology.

[0058] Subsequently, the nitride semiconductor device 5 is manufactured by depositing a drain electrode 22 on the lower surface of the drift layer 13 and the convex region 112.

[0059] Like the nitride semiconductor device 4, the nitride semiconductor device 5 can also be manufactured using a GaN-on-Si substrate, a GaN-on-SiC substrate, or a GaN-on-Sapphire substrate as the base substrate. In particular, in the nitride semiconductor device 5, the GaN-on-Si substrate, GaN-on-SiC substrate, or GaN-on-Sapphire substrate is ultimately removed, so there is no high-resistance buffer layer. A nitride semiconductor device 5 using a GaN-on-Si substrate, GaN-on-SiC substrate, or GaN-on-Sapphire substrate as the base substrate can have low on-resistance and be manufactured at low cost.

[0060] The nitride semiconductor devices of each embodiment described above can be modified as described below.

[0061] The cross-sectional shape of the convex regions 12,112 is not particularly limited and may be, for example, trapezoidal, semicircular, or triangular. Furthermore, as shown in the nitride semiconductor device 6 in Figure 33, adjacent convex regions 212 may be connected. That is, there may be no flat surface on the upper surface of the nitride semiconductor layer 11, and the convex regions 212 may be formed across the entire upper surface of the nitride semiconductor layer 11.

[0062] In each of the above embodiments, a structure in which the inversion layer formed in the body layer 14 serves as a channel is illustrated. Alternatively, the technology disclosed herein can also be applied to a structure in which a two-dimensional electron gas layer serves as a channel. The nitride semiconductor device 7 shown in Figure 34 is characterized by having a heterojunction layer 50 between a planar insulated gate 30 and an epitaxial layer 10. The heterojunction layer 50 has a lower nitride semiconductor layer 52 and an upper nitride semiconductor layer 54. The lower nitride semiconductor layer 52 is in contact with the upper surface of the epitaxial layer 10. The lower nitride semiconductor layer 52 may be, for example, gallium nitride. The upper nitride semiconductor layer 54 is in contact with the lower nitride semiconductor layer 52 and faces the upper surface of the epitaxial layer 10 via the lower nitride semiconductor layer 52. The upper nitride semiconductor layer 54 is a nitride semiconductor with a wider band gap than the lower nitride semiconductor layer 52, and may be, for example, aluminum gallium nitride. As a result, a two-dimensional electron gas layer is formed near the heterojunction surface of the lower nitride semiconductor layer 52 and the upper nitride semiconductor layer 54. The electron density of the two-dimensional electron gas layer can be controlled by the voltage applied to the gate electrode 34. Thus, the nitride semiconductor device 7 has a structure in which the two-dimensional electron gas layer acts as a channel, and can operate as a switching element. In the nitride semiconductor device 7, no inversion layer channel is formed in the body layer 14. For this reason, the nitride semiconductor device 7 may have a higher concentration of p-type impurities in the body layer 14 compared to other examples. Furthermore, the gate insulating film 32 of the insulating gate 30 may be replaced with a p-type nitride semiconductor. In this case, the nitride semiconductor device can also have similar functions.

[0063] The technology disclosed herein can also be applied to the nitride semiconductor device 8 shown in Figure 35. The nitride semiconductor device 8 is characterized in that the gate electrode 234 is in ohmic contact with the upper surface of the body layer 14. In the nitride semiconductor device 8, the width of the depletion layer formed at the tapered region 13b of the drift layer 13 and the pn junction of the body layer 14 can be controlled based on the voltage applied to the gate electrode 234. This makes it possible to control the current density flowing through the tapered region 13b of the drift layer 13 based on the voltage applied to the gate electrode 234. The nitride semiconductor device 8 can operate as a switching element. Similar to the nitride semiconductor device 7, the nitride semiconductor device 8 does not have an inversion layer channel formed in the body layer 14. For this reason, the nitride semiconductor device 8 may also have a higher concentration of p-type impurities in the body layer 14 compared to other examples.

[0064] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0065] (Feature 1) Nitride semiconductor devices (1,2,3,4,5,6,7,8), Conductive layers (11, 22, 103), A convex region (12,112,212) of the nitride semiconductor is provided on at least a part of the upper surface of the conductive layer, An n-type drift layer (13) provided above the conductive layer, the drift layer including a tapered region (13b) that tapers upward above the convex region, The drift layer comprises a p-shaped body layer (14) adjacent to the tapered region of the drift layer, A nitride semiconductor device in which the drift layer and the body layer are epitaxial layers (10).

[0066] (Feature 2) The conductive layer is an n-type nitride semiconductor layer (11,103), The nitride semiconductor device according to feature 1, wherein the n-type impurity concentration of the drift layer is lower than the n-type impurity concentration of the nitride semiconductor layer.

[0067] (Feature 3) The nitride semiconductor device according to feature 2, wherein the convex region (12,212) is composed of a part of the nitride semiconductor layer.

[0068] (Feature 4) The nitride semiconductor device according to feature 1 or 2, wherein the convex region has a narrow portion (112b) at its lower end.

[0069] (Feature 5) The nitride semiconductor device according to feature 4, further comprising a mask layer (42) provided on the upper surface of the conductive layer and having an opening (42a), wherein the narrow portion of the convex region is positioned through the opening.

[0070] (Feature 6) The nitride semiconductor device according to feature 5, wherein the convex region has a higher n-type impurity concentration than the drift layer.

[0071] (Feature 7) The nitride semiconductor device according to any one of features 1 to 6, wherein the lower end (14a) of the body layer is located above the upper end (12a) of the convex region.

[0072] (Feature 8) A method for manufacturing nitride semiconductor devices (1,2,3,6,7,8), A convex region formation step involves etching the upper surface of an n-type nitride semiconductor layer (11) to form a convex region (12,212), A step of forming an n-type drift layer (13) with a lower n-type impurity concentration than the nitride semiconductor layer by growing crystals from the upper surface of the nitride semiconductor layer, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A method for manufacturing a nitride semiconductor device, comprising: a body layer deposition step, wherein a p-type body layer (14) is formed by crystal growth from the upper surface of the drift layer, the body layer being adjacent to the tapered region of the drift layer.

[0073] (Feature 9) A method for manufacturing a nitride semiconductor device (4), A mask layer formation step comprising forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11,103), wherein the mask layer has an opening (42a), A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed from the opening of the mask layer to form a convex region (112), A mask layer removal step to remove the aforementioned mask layer, A step of forming an n-type drift layer (13) by crystal growth from the upper surface of the nitride semiconductor layer, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A method for manufacturing a nitride semiconductor device, comprising: a body layer deposition step, wherein a p-type body layer (14) is formed by crystal growth from the upper surface of the drift layer, the body layer being adjacent to the tapered region of the drift layer.

[0074] (Feature 10) A method for manufacturing nitride semiconductor devices (4,5), A mask layer formation step comprising forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11,103), wherein the mask layer has an opening (42a), A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed from the opening of the mask layer to form a convex region (112), A step of forming an n-type drift layer (13) by growing crystals from the convex region, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A method for manufacturing a nitride semiconductor device, comprising: a body layer deposition step, wherein a p-type body layer (14) is formed by crystal growth from the upper surface of the drift layer, the body layer being adjacent to the tapered region of the drift layer.

[0075] (Feature 11) A method for manufacturing a nitride semiconductor device according to any one of features 8 to 10, further comprising a source layer formation step of growing crystals from the upper surface of the body layer to form an n-type source layer (15).

[0076] (Feature 12) A method for manufacturing a nitride semiconductor device according to any one of features 8 to 10, further comprising a contact layer formation step of growing crystals from the upper surface of the body layer to form a p-type contact layer (16).

[0077] (Feature 13) The method for manufacturing a nitride semiconductor device according to feature 9 or 10, wherein the convex region has a higher n-type impurity concentration than the drift layer.

[0078] (Feature 14) A method for manufacturing a nitride semiconductor device according to any one of features 8 to 13, wherein the lower end (14a) of the body layer is located above the upper end (12a) of the convex region.

[0079] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of symbols]

[0080] 1,2,3,4,5,6,7,8: Nitride semiconductor device, 10: Epitaxial layer, 11: Nitride semiconductor layer, 12,112,212: Convex region, 13: Drift layer, 14: Body layer, 15: Source layer, 16: Contact layer, 22: Drain electrode, 24: Source electrode, 30,130: Insulated gate, 32,132: Gate insulating film, 34,134,234: Gate electrode

Claims

1. Nitride semiconductor devices (1, 2, 3, 6, 7, 8), Conductive layer (11, 103), A convex region (12, 212) of the nitride semiconductor provided on at least a part of the upper surface of the conductive layer, An n-type drift layer (13) provided above the conductive layer, the drift layer including a tapered region (13b) that tapers upward above the convex region, The drift layer comprises a p-shaped body layer (14) adjacent to the tapered region of the drift layer, The drift layer and the body layer are epitaxial layers (10), The conductive layer is an n-type nitride semiconductor layer, The n-type impurity concentration in the drift layer is lower than the n-type impurity concentration in the nitride semiconductor layer. The aforementioned convex region is composed of a part of the nitride semiconductor layer, wherein the nitride semiconductor device is a nitride semiconductor device.

2. Nitride semiconductor device (4, 5), Conductive layer (22, 103), A convex region (112) of the nitride semiconductor provided on at least a part of the upper surface of the conductive layer, An n-type drift layer (13) provided above the conductive layer, the drift layer including a tapered region (13b) that tapers upward above the convex region, The drift layer comprises a p-shaped body layer (14) adjacent to the tapered region of the drift layer, The drift layer and the body layer are epitaxial layers (10), The aforementioned convex region has a narrow portion (112b) at its lower end, wherein the nitride semiconductor device is provided with the above-mentioned convex region.

3. The nitride semiconductor device according to claim 2, further comprising a mask layer (42) provided on the upper surface of the conductive layer and having an opening (42a), wherein the narrow portion of the convex region is positioned through the opening.

4. The nitride semiconductor device according to claim 3, wherein the convex region has a higher n-type impurity concentration than the drift layer.

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein the lower end (14a) of the body layer is located above the upper end (12a) of the convex region.

6. A method for manufacturing nitride semiconductor devices (1, 2, 3, 6, 7, 8), A convex region formation step involves etching the upper surface of an n-type nitride semiconductor layer (11) to form a convex region (12, 212), A step of forming an n-type drift layer (13) with a lower n-type impurity concentration than the nitride semiconductor layer by growing crystals from the upper surface of the nitride semiconductor layer, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A method for manufacturing a nitride semiconductor device, comprising: a body layer deposition step, wherein a p-type body layer (14) is formed by crystal growth from the upper surface of the drift layer, the body layer being adjacent to the tapered region of the drift layer.

7. A method for manufacturing a nitride semiconductor device (4), A step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11, 103), wherein the mask layer has an opening (42a), and a mask layer formation step, A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed through the opening of the mask layer to form a convex region (112), A mask layer removal step to remove the aforementioned mask layer, A step of forming an n-type drift layer (13) by crystal growth from the upper surface of the nitride semiconductor layer, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A method for manufacturing a nitride semiconductor device, comprising: a body layer deposition step, wherein a p-type body layer (14) is formed by crystal growth from the upper surface of the drift layer, the body layer being adjacent to the tapered region of the drift layer.

8. A method for manufacturing a nitride semiconductor device according to claim 6 or 7, further comprising a source layer formation step of growing crystals from the upper surface of the body layer to form an n-type source layer (15).

9. A method for manufacturing a nitride semiconductor device according to claim 6 or 7, further comprising a contact layer formation step of growing crystals from the upper surface of the body layer to form a p-type contact layer (16).

10. The method for manufacturing a nitride semiconductor device according to claim 7, wherein the convex region has a higher n-type impurity concentration than the drift layer.

11. The method for manufacturing a nitride semiconductor device according to claim 6 or 7, wherein the lower end (14a) of the body layer is located above the upper end (12a) of the convex region.

12. A method for manufacturing nitride semiconductor devices (4, 5), A step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11, 103), wherein the mask layer has an opening (42a), and a mask layer formation step, A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed through the opening of the mask layer to form a convex region (112), A step of forming an n-type drift layer (13) by growing crystals from the convex region, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A body layer deposition step comprising a step of forming a p-type body layer (14) by crystal growth from the upper surface of the drift layer, wherein the body layer is adjacent to the tapered region of the drift layer, A method for manufacturing a nitride semiconductor device, comprising a contact layer formation step of growing crystals from the upper surface of the body layer to form a p-type contact layer (16).

13. A method for manufacturing nitride semiconductor devices (4, 5), A step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11, 103), wherein the mask layer has an opening (42a), and a mask layer formation step, A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed through the opening of the mask layer to form a convex region (112), A step of forming an n-type drift layer (13) by growing crystals from the convex region, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A body layer deposition step comprising a step of forming a p-type body layer (14) by crystal growth from the upper surface of the drift layer, wherein the body layer is adjacent to the tapered region of the drift layer, A method for manufacturing a nitride semiconductor device, wherein the convex region has a higher n-type impurity concentration than the drift layer.

14. A method for manufacturing nitride semiconductor devices (4, 5), A step of forming a mask layer (42) on the upper surface of a nitride semiconductor layer (11, 103), wherein the mask layer has an opening (42a), and a mask layer formation step, A convex region formation step in which crystal growth is performed from the upper surface of the nitride semiconductor layer exposed through the opening of the mask layer to form a convex region (112), A step of forming an n-type drift layer (13) by growing crystals from the convex region, wherein the drift layer is provided above the nitride semiconductor layer and includes a tapered region (13b) that tapers upward above the convex region, and a drift layer formation step, A body layer deposition step comprising a step of forming a p-type body layer (14) by crystal growth from the upper surface of the drift layer, wherein the body layer is adjacent to the tapered region of the drift layer, A method for manufacturing a nitride semiconductor device, wherein the lower end (14a) of the body layer is located above the upper end (12a) of the convex region.

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