Semiconductor equipment

Abstract

To provide a highly reliable semiconductor device.SOLUTION: A semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer disposed between the first electrode and the second electrode, the first semiconductor layer being of a first conductivity type; a third electrode disposed in the first semiconductor layer, the third electrode facing the first semiconductor layer via a portion of an insulating body; a second semiconductor layer disposed between the first semiconductor layer and the second electrode, the second semiconductor layer including a lower surface positioned at the first electrode side and being electrically connected to the second electrode, the second semiconductor layer being of a second conductivity type; a third semiconductor layer extending from the second semiconductor layer toward the first electrode side, a lower end of the third semiconductor layer positioned at the first electrode side being positioned further toward the first electrode side than the lower surface of the second semiconductor layer, the third semiconductor layer being separated from the insulating body and being of the second conductivity type; a fourth electrode facing the second semiconductor layer via an other portion of the insulating body; and a fourth semiconductor layer disposed between the second semiconductor layer and the second electrode and electrically connected to the second electrode, the fourth semiconductor layer being of the first conductivity type.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices. [Background technology]

[0002] In power control semiconductor devices, when avalanche breakdown occurs, parasitic NPN bipolar transistors may conduct, leading to secondary breakdown. This can potentially destroy the semiconductor device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-038240 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The objective of this embodiment is to provide a highly reliable semiconductor device. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode, a third electrode provided within the first semiconductor layer and facing the first semiconductor layer via a part of an insulator, a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second electrode, having a lower surface located on the first electrode side and electrically connected to the second electrode, a third semiconductor layer of a second conductivity type extending from the second semiconductor layer toward the first electrode, with its lower end located toward the first electrode side being further toward the first electrode than the lower surface of the second semiconductor layer, separated from the insulator, and being of a second conductivity type, a fourth electrode facing the second semiconductor layer via another part of the insulator, and a fourth semiconductor layer of a first conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view taken along the line A-A' shown in Figure 1. [Figure 3] Figure 3 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing the operation of a semiconductor device according to a comparative example. [Figure 5] Figure 5 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 6] Figure 6 is a cross-sectional view taken along the line D-D' shown in Figure 5. [Figure 7] Figure 7 is a cross-sectional view taken along the line E-E' shown in Figure 5. [Figure 8] Figure 8 is a perspective view showing the trench contact of a semiconductor device according to the second embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a semiconductor device according to the first modified example of the second embodiment. [Figure 10] Figure 10 is a cross-sectional view showing a semiconductor device according to a second modified example of the second embodiment. [Figure 11] Figures 11(a) and (b) show the semiconductor device, distances, and variables assumed in the test example, and (c) shows the capacitances. [Figure 12] Figures 12(a) and (b) show the current density of hole current when avalanche decay occurs. [Figure 13] Figure 13 shows the electric field strength distribution within a semiconductor portion, with the horizontal axis representing the position in the Z direction and the vertical axis representing the electric field strength. [Figure 14] Figure 14 is a graph showing the effect of the position of the lower end of the trench contact on the pressure resistance, with distance D on the horizontal axis and pressure resistance on the vertical axis. [Figure 15]FIG. 15 is a graph showing the influence of the position of the lower end of the trench contact on the output capacitance Coss, with the distance D on the horizontal axis and the output capacitance Coss on the vertical axis. [Figure 16] FIG. 16 is a graph showing the influence of the position of the lower end of the trench contact on the feedback capacitance Crss, with the distance D on the horizontal axis and the feedback capacitance Crss on the vertical axis. [Figure 17] FIG. 17 is a graph showing the influence of the position of the lower end of the trench contact on the output charge amount Qoss, with the distance D on the horizontal axis and the output charge amount Qoss on the vertical axis.

MODE FOR CARRYING OUT THE INVENTION

[0007] <First Embodiment> FIG. 1 is a cross-sectional view showing the semiconductor device according to this embodiment. FIG. 2 is a cross-sectional view taken along the line A-A' shown in FIG. 1. FIG. 1 corresponds to a cross-section taken along the line B-B' shown in FIG. 2.

[0008] The semiconductor device according to this embodiment is a vertical semiconductor device for power control, for example, a MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor). Note that the semiconductor device according to the present invention is not limited to this, and for example, it may be an IGBT (insulated gate bipolar transistor). In this embodiment, a MOSFET will be described as an example.

[0009] As shown in FIGS. 1 and 2, in the semiconductor device 1 according to this embodiment, a drain electrode 11 (first electrode), a semiconductor portion 20, an insulator 30, a field plate electrode 12 (fourth electrode, hereinafter referred to as "FP electrode 12"), a gate electrode 13 (third electrode), an insulating film 36, a source electrode 14 (second electrode), and a trench contact 15 (fifth electrode) are provided.

[0010] Hereafter, for the sake of explanation, the XYZ Cartesian coordinate system will be adopted in this specification. The direction from the drain electrode 11 toward the source electrode 14 will be referred to as the "Z direction," the direction in which the gate electrode 13 extends will be referred to as the "Y direction," and the direction perpendicular to the Z and Y directions will be referred to as the "X direction." Furthermore, within the Z direction, the direction from the drain electrode 11 toward the source electrode 14 will also be referred to as "up," and the opposite direction will be referred to as "down," but this expression is also for convenience and is unrelated to the direction of gravity.

[0011] In the semiconductor device 1, the drain electrode 11, semiconductor portion 20, insulating film 36, and source electrode 14 are stacked in this order from bottom to top. The drain electrode 11 and source electrode 14 are plate-shaped, extending along the XY plane. The insulator 30 is located within the semiconductor portion 20. The FP electrode 12 and gate electrode 13 are located within the insulator 30.

[0012] The semiconductor portion 20 is made of a semiconductor material, for example, silicon (Si), and for example, impurities are locally introduced into single-crystal silicon so that the conductivity type is p-type or n-type. In the semiconductor portion 20, the conductivity type is n + Drain layer 21 of type n - A drift layer 22 of type p, a first base layer 23 (second semiconductor layer) of type p, a second base layer 24 (third semiconductor layer) of type p, and n + A source layer 25 (fourth semiconductor layer) of the type is provided.

[0013] Note that "n + ``type'', ``n type'', ``n - The notation "type" indicates the relative magnitude of carrier concentrations, and "n + The "n-type" indicates that the carrier concentration is higher than that of the "n-type". - The "n-type" designation indicates a lower carrier concentration than "n-type." "Carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor material. If a region contains both donor and acceptor impurities, it corresponds to the net impurity concentration after deducting the canceling-out portion.

[0014] The drain layer 21 is disposed on the drain electrode 11 and is in contact with the drain electrode 11. Therefore, the drain layer 21 is connected to the drain electrode 11. In this specification, "connection" means electrical connection. The drift layer 22 is disposed on the drain layer 21 and is in contact with the drain layer 21. The carrier concentration of the drift layer 22 is lower than the carrier concentration of the drain layer 21. The drain layer 21 and the drift layer 22 constitute the first semiconductor layer.

[0015] The first base layer 23 is disposed on the drift layer 22. The second base layer 24 is in contact with the lower surface 23a of the first base layer 23 and extends downward from the lower surface 23a of the first base layer 23 into the drift layer 22. The carrier concentration of the second base layer 24 is higher than the carrier concentration of the first base layer 23. For example, the carrier concentration of the first base layer 23 is about 1×10 13 cm -3 , and the carrier concentration of the second base layer 24 is about 1×10 15 cm -3 . The source layer 25 is disposed on the first base layer 23 and is in contact with the first base layer 23.

[0016] Trenches 28 and 29 are formed on the upper surface of the semiconductor portion 20 and are arranged alternately in the X direction. Each of the trenches 28 and 29 extends in the Y direction. An insulator 30 is disposed in the trench 28. Therefore, the insulator 30 is disposed in the semiconductor portion 20, and the upper surface of the insulator 30 is exposed on the upper surface of the semiconductor portion 20.

[0017] In the semiconductor portion 20, a plurality of insulators 30 are arranged along the X direction. Each insulator 30 extends in the Y direction. The upper surface of the insulator 30 is exposed on the upper surface of the semiconductor portion 20, and the lower end of the insulator 30 is located in the drift layer 22. Therefore, the insulator 30 does not penetrate the semiconductor portion 20 in the Z direction. The insulator 30 is separated from the drain layer 21 and is in contact with the drift layer 22, the first base layer 23, and the source layer 25.

[0018] Each insulator 30 contains one FP electrode 12 and two gate electrodes 13. Both the FP electrode 12 and the gate electrodes 13 extend in the Y direction. Within each insulator 30, the FP electrode 12 is positioned below the gate electrodes 13, and the upper end 12a of the FP electrode 12 is located below the lower end 13a of the gate electrodes 13. Viewed from above, the FP electrode 12 is located between the two gate electrodes 13 in the X direction.

[0019] Multiple trench contacts 15 are provided and are arranged along the X direction. Each trench contact 15 extends in the Y direction. The upper end of each trench contact 15 is in contact with the source electrode 14, the upper part of the trench contact 15 penetrates the insulating film 36, and the lower part is located within the trench 29. The lower end 15a (end) of the trench contact 15 is second base Within layer 24, the first base It is located below the lower surface 23a of layer 23 and the lower end 13a of gate electrode 13, and above the upper end 12a of FP electrode 12.

[0020] The trench contact 15 is in contact with the insulating film 36, the source layer 25, the first base layer 23, and the second base layer 24. Therefore, the trench contact 15 is in contact with the source electrode 14, the source layer 25 It is connected to the first base layer 23 and the second base layer 24. On the other hand, the trench contact 15 is separated from the drain layer 21 and the drift layer 22.

[0021] The second base layer 24 is separated from the insulator 30 via the drift layer 22. The lower end 24a of the second base layer 24 is located below the lower surface 23a of the first base layer 23 and above the upper end 12a of the FP electrode 12. Preferably, the lower end 24a of the second base layer 24 is located below the lower end 13a of the gate electrode 13. The lower surface 23a of the first base layer 23 is located above the lower end 13a of the gate electrode 13. The interface between the first base layer 23 and the source layer 25 is located below the upper end 13b of the gate electrode 13. The upper surface of the source layer 25 is located above the upper end 13b of the gate electrode 13.

[0022] As a result, the FP electrode 12 faces the drift layer 22 via portion 31 of the insulator 30. The gate electrode 13 faces the upper part of the drift layer 22, the entire first base layer 23, and the lower part of the source layer 25 via portion 32 of the insulator 30.

[0023] In the semiconductor device 1, multiple insulators 30, FP electrodes 12, gate electrodes 13, trench contacts 15, a first base layer 23, a second base layer 24, and a source layer 25 are provided. The portion of the semiconductor part 20 located between adjacent insulators 30, i.e., the upper part of the drift layer 22, the first base layer 23, the second base layer 24, and the source layer 25, is partitioned by adjacent insulators 30 and extends in the Y direction.

[0024] The drain electrode 11, source electrode 14, and trench contact 15 are made of a conductive material, for example, a metal. For example, the drain electrode 11 and source electrode 14 are made of aluminum (Al), and the trench contact 15 is made of tungsten (W). A barrier metal layer (not shown) may be provided on the lower surface of the source electrode 14 and on the side and lower surface of the trench contact 15. The barrier metal layer is, for example, a layer in which a titanium layer (Ti) and a titanium nitride layer (TiN) are laminated. The FP electrode 12 and gate electrode 13 are made of a conductive material, for example, polysilicon containing impurities. The insulator 30 and insulating film 36 are made of an insulating material, for example, silicon oxide (SiO2).

[0025] Next, the operation and effects of the semiconductor device according to this embodiment will be described. Figure 3 is a cross-sectional view showing the operation of the semiconductor device according to this embodiment. Figure 3 shows the region corresponding to region C in Figure 2.

[0026] As shown in Figure 3, in the semiconductor device 1, when an excessive voltage is applied between the drain electrode 11 and the source electrode 14 during the off state, avalanche decay occurs in the semiconductor portion 20, causing a hole current 201 to flow from the drain electrode 11 to the source electrode 14. In the semiconductor device 1, a second base layer 24 is provided at a position away from the insulator 30, and the carrier concentration of the second base layer 24 is higher than that of the first base layer 23. Therefore, the hole current 201 flowing through the drift layer 22 is more likely to flow into the second base layer 24 than into the first base layer 23. Consequently, most of the hole current 201 flows from the drift layer 22 through the second base layer 24 to the trench contact 15 and is discharged through the source electrode 14.

[0027] This suppresses the inflow of hole current 201 into the first base layer 23. As a result, fluctuations in the potential of the first base layer 23 are suppressed, and the turn-on of the parasitic NPN transistor consisting of the drift layer 22, the first base layer 23, and the source layer 25 is suppressed. Therefore, the occurrence of secondary decay caused by current flowing through the turned-on portion of the parasitic NPN transistor is suppressed. For this reason, the semiconductor device 1 is highly reliable.

[0028] <Comparative Example> Figure 4 is a cross-sectional view showing the operation of the semiconductor device according to this comparative example. Figure 4 shows the region corresponding to Figure 3.

[0029] As shown in Figure 4, the semiconductor device 101 according to this comparative example differs from the semiconductor device 1 according to the first embodiment in that it does not have a second base layer 24 and the lower end 15a of the trench contact 15 is located above the lower surface 23a of the first base layer 23.

[0030] In the semiconductor device 101, when avalanche breakdown occurs, hole current 201 flows from the drift layer 22 through the first base layer 23 to the trench contact 15. As a result, the potential of the first base layer 23 rises, and the parasitic NPN transistor consisting of the drift layer 22, the first base layer 23, and the source layer 25 turns on. This causes electron current 202 to flow from the source layer 25 through the first base layer 23 to the drift layer 22. As a result, secondary decay occurs, and the semiconductor device 101 may be damaged.

[0031] <Second Embodiment> Figure 5 is a cross-sectional view showing a semiconductor device according to this embodiment. Figure 6 is a cross-sectional view taken along the line D-D' shown in Figure 5. Figure 7 is a cross-sectional view taken along the line E-E' shown in Figure 5. Figure 8 is a perspective view showing the trench contact of the semiconductor device according to this embodiment. Figure 5 corresponds to the cross-section along the line F-F' shown in Figures 6 and 7.

[0032] As shown in Figures 5 to 8, the semiconductor device 2 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that the trench contact 15 has a core 15c that extends continuously in the Y direction and a plurality of protrusions 15d that protrude downward from the core 15c, and a plurality of second base layers 24 are provided between adjacent insulators 30.

[0033] Each trench contact 15 is provided with one core 15c and multiple protrusions 15d. The multiple protrusions 15d are arranged spaced apart from each other along the Y direction. Multiple second base layers 24 are also arranged spaced apart from each other along the Y direction. Each second base layer 24 covers each protrusion 15d of the trench contact 15. As shown in Figure 7, the lower end of the core 15c is located above the lower end 13a of the gate electrode 13. As shown in Figure 6, the lower end of the protrusion 15d is located below the lower end 13a of the gate electrode 13 and above the upper end 12a of the FP electrode 12.

[0034] Furthermore, in semiconductor device 2, the positions of the protrusions 15d of the trench contacts 15 in the Y direction are the same on both sides of the insulator 30 in the X direction. Therefore, the positions of the second base layer 24 in the Y direction are the same on both sides of the insulator 30 in the X direction.

[0035] Next, the operation and effects of this embodiment will be described. In the semiconductor device 2, in the upper part of the portion between adjacent insulators 30 in the semiconductor portion 20, n - A p-type drift layer 22 and a p-type second base layer 24 are arranged alternately along the Y direction. This realizes a superjunction structure. When an off-potential is input to the gate electrode 13 and the semiconductor device 2 turns off, the depletion layer starts from the interface between the drift layer 22 and the second base layer 24 and extends not only in the Z direction but also in the Y direction. Direction This also extends to other areas. As a result, the upper part of the portion between adjacent insulators 30 in the semiconductor portion 20 becomes depleted. This makes it possible to increase the breakdown voltage of the semiconductor device 2. The configuration, operation, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0036] <First modified example of the second embodiment> Figure 9 is a cross-sectional view showing a semiconductor device according to this modified example.

[0037] As shown in Figure 9, the semiconductor device 2a according to this modified example differs from the semiconductor device 2 according to the second embodiment in the arrangement of the protrusions 15d of the trench contact 15 and the second base layer 24. That is, on both sides of the insulator 30 in the X direction, the positions of the protrusions 15d of the trench contact 15 in the Y direction are different from each other. Therefore, on both sides of the insulator 30 in the X direction, the positions of the second base layer 24 in the Y direction are also different from each other. In other words, when viewed from above, the protrusions 15d and the second base layer 24 are arranged in a staggered pattern. The configuration, operation, and effects of this modified example other than those described above are the same as those of the second embodiment.

[0038] <Second modified example of the second embodiment> Figure 10 is a cross-sectional view showing a semiconductor device according to this modified example. Figure 10 corresponds to the cross-section along the line E-E' shown in Figure 5. In this modified example, the cross-section corresponding to the section along line D-D' shown in Figure 5 is the same as that in Figure 6.

[0039] As shown in Figure 10, the semiconductor device 2b according to this modified example differs from the semiconductor device 2 according to the second embodiment in that the second base layer 24 covers not only the protruding portion 15d of the trench contact 15 but also the lower end of the main body 15c. The shape of the trench contact 15 in this modified example is the same as that of the second embodiment (see Figure 8). Therefore, in this modified example, the second base layer 24 extends in the Y direction while reciprocating displacement in the Z direction along the lower edge of the trench contact 15.

[0040] In this modified example, the portion of the second base layer 24 that covers the lower end of the main body 15c of the trench contact 15 is located inside the first base layer 23. The portion of the second base layer 24 that covers the protruding portion 15d of the trench contact 15 protrudes downward from the lower surface 23a of the first base layer 23, similar to the second embodiment. The configuration, operation, and effects of this modified example other than those described above are the same as those of the second embodiment.

[0041] <Example Test> Next, we will describe a test example demonstrating the effects of the first embodiment. Figures 11(a) and (b) show the semiconductor device, distances, and variables assumed in this test example, and (c) shows the capacitances.

[0042] As shown in Figures 11(a) and (b), in this test example, the semiconductor device 1 according to the first embodiment described above and the semiconductor device 101 according to the comparative example were assumed. In the Z direction, the distance from the upper surface of the semiconductor portion 20 to the lower end 13a of the gate electrode 13 is defined as distance D1, the distance from the upper surface of the semiconductor portion 20 to the lower end 15a of the trench contact 15 is defined as distance D, and the distance from the upper surface of the semiconductor portion 20 to the upper end 12a of the FP electrode 12 is defined as distance D2.

[0043] Furthermore, the capacitance between the gate electrode 13 and the FP electrode 12, and the capacitance between the gate electrode 13 and the trench contact 15 are defined as capacitance Cgs, the capacitance between the gate electrode 13 and the drift layer 22 is defined as capacitance Cgd, and the capacitance between the drift layer 22 and the trench contact 15 is defined as capacitance Cds. In addition, as shown in Figure 11(c), the sum of capacitance Cgd and capacitance Cgs is defined as the input capacitance Ciss, the sum of capacitance Cds and capacitance Cgd is defined as the output capacitance Coss, and capacitance Cgd is defined as the feedback capacitance Crss.

[0044] Then, simulations were performed with varying distances D from the upper surface of the semiconductor portion 20 to the lower end 15a of the trench contact 15, and the current density of the hole current, the breakdown voltage in the off state, the output capacitance Coss, the feedback capacitance Crss, and the output charge Qoss when avalanche decay occurred were calculated.

[0045] (Current density of hole current) Figures 12(a) and (b) show the current density of hole current when avalanche decay occurs.

[0046] As shown in Figure 12(a), in the semiconductor device 1 according to the first embodiment, the current density of hole current was high near the lower end 15a of the trench contact 15, that is, in the second base layer 24 and the surrounding drift layer 22. In contrast, as shown in Figure 12(b), in the semiconductor device 101 according to the comparative example, the current density of hole current was high in the first base layer 23. Thus, it was shown that the semiconductor device 1 is less prone to secondary decay even when avalanche decay occurs compared to the semiconductor device 101.

[0047] (Pressure resistant) Figure 13 shows the electric field strength distribution within the semiconductor portion 20, with the horizontal axis representing the position in the Z direction and the vertical axis representing the electric field strength. In the horizontal axis of Figure 13, the left side represents the upper side of the semiconductor device, i.e., the source electrode 14 side, and the right side represents the lower side of the semiconductor device, i.e., the drain electrode 11 side. Figure 14 is a graph showing the effect of the position of the lower end of the trench contact on the pressure resistance, with distance D on the horizontal axis and pressure resistance on the vertical axis. As mentioned above, distance D is the distance from the upper surface of the semiconductor portion 20 to the lower end 15a of the trench contact 15.

[0048] As shown in Figure 13, the peak P of the electric field strength in semiconductor device 101 101 The position was near the lower end 13a of the gate electrode 13, but the position of the electric field strength peak P1 in the semiconductor device 1 was peak P 101 It was located below the specified position. As a result, semiconductor device 1 is more reliable than semiconductor device 101 because the electric field concentration near the gate electrode 13 is mitigated. Furthermore, the breakdown voltage of semiconductor device 1, i.e., the integral value of the electric field strength, was about the same as that of semiconductor device 101. Also, as shown in Figure 14, when distance D was in the range between distance D1 and distance D2, the breakdown voltage was approximately constant.

[0049] (Output capacity Coss) Figure 15 is a graph showing the effect of the position of the lower end of the trench contact on the output capacitance Coss, with distance D on the horizontal axis and output capacitance Coss on the vertical axis.

[0050] As shown in Figure 15, the output capacitance Coss decreased as the distance D increased. This is thought to be because the trench contact 15 extends downward, causing the second base layer 24 to also extend downward. As a result, the capacitance Cgd between the gate electrode 13 and the drift layer 22 is reduced, as is the capacitance Cds between the drift layer 22 and the trench contact 15.

[0051] (Feedback capacity Crss) Figure 16 is a graph showing the effect of the position of the lower end of the trench contact on the feedback capacitance Crss, with distance D on the horizontal axis and feedback capacitance Crss on the vertical axis.

[0052] As shown in Figure 16, the larger the distance D, the smaller the feedback capacitance Crss. This is thought to be because the trench contact 15 extends downward, causing the second base layer 24 to also extend downward, and thus reducing the capacitance Cgd between the gate electrode 13 and the drift layer 22.

[0053] (Output charge Qoss) Figure 17 is a graph showing the effect of the position of the lower end of the trench contact on the output charge quantity Qoss, with distance D on the horizontal axis and output charge quantity Qoss on the vertical axis. As shown in Figure 17, the output charge quantity Qoss decreased as the distance D increased. This is thought to be due to the trench contact 15 extending downwards, which reduced the output capacitance Coss.

[0054] Thus, according to this test example, the semiconductor device 1 according to the first embodiment was shown to be more reliable than the semiconductor device 101 according to the comparative example because secondary decay is less likely to occur during avalanche decay and the breakdown voltage is equivalent. Furthermore, it was shown that the semiconductor device 1 can operate at high speed because it has smaller output capacitance, feedback capacitance, and output charge compared to the semiconductor device 101.

[0055] According to the embodiments described above, a highly reliable semiconductor device can be realized.

[0056] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0057] The present invention includes the following embodiments.

[0058] (Note 1) First electrode and, The second electrode and A first semiconductor layer of a first conductivity type is provided between the first electrode and the second electrode, A third electrode is provided within the first semiconductor layer and faces the first semiconductor layer via a portion of an insulator, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the second electrode, has a lower surface located on the first electrode side, and is electrically connected to the second electrode, A third semiconductor layer, which extends from the second semiconductor layer toward the first electrode, has a lower end located toward the first electrode that is further toward the first electrode than the lower surface of the second semiconductor layer, is separated from the insulator, and is of the second conductivity type. A fourth electrode facing the second semiconductor layer via another portion of the insulator, A fourth semiconductor layer of first conductivity type is provided between the second semiconductor layer and the second electrode and is electrically connected to the second electrode, A semiconductor device equipped with the following features.

[0059] (Note 2) The semiconductor device according to Appendix 1, wherein the third semiconductor layer is located on the second electrode side of the upper end of the third electrode that is located on the second electrode side.

[0060] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein the lower end of the third semiconductor layer is located closer to the first electrode than the lower end of the fourth electrode located on the first electrode side.

[0061] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the carrier concentration of the third semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

[0062] (Note 5) The semiconductor device according to any one of appendices 1 to 4, further comprising a fifth electrode extending in the direction toward the first electrode and in contact with the fourth semiconductor layer and the second semiconductor layer.

[0063] (Note 6) The semiconductor device described in Appendix 5, wherein the lower end of the fifth electrode located on the first electrode side is located on the first electrode side of the lower surface of the second semiconductor layer and is in contact with the third semiconductor layer.

[0064] (Note 7) The semiconductor device according to Appendix 5 or 6, wherein the fifth electrode extends in the first direction in which the fourth electrode extends.

[0065] (Note 8) The third semiconductor layer is the semiconductor device described in Appendix 7, extending in the first direction.

[0066] (Note 9) The fifth electrode is, The main body extends in the first direction from which the fourth electrode extends, Multiple protrusions extending from the main body toward the first electrode, It has, The semiconductor device according to appendix 5 or 6, wherein the plurality of protrusions are arranged along the first direction.

[0067] (Note 10) Multiple third semiconductor layers are provided, Each of the third semiconductor layers covers each of the protruding portions, as described in Appendix 9 of the semiconductor device. [Explanation of symbols]

[0068] 1, 2, 2a, 2b Semiconductor equipment 11 Drain electrode 12. Field plate electrodes (FP electrodes) Upper end of 12a FP electrode 13 gates 13a Lower end of gate electrode 13b Upper end of gate electrode 14 Source electrodes 15 Trench Contact 15a bottom end 15c Core 15d protrusion 20 Semiconductor part 21 Drain layer 22 Drift Layers 23. First Base Layer 23a Lower surface of the first base layer 24. Second Base Layer 24a Lower end of the second base layer 25 Source Layers 28, 29 Trench 30 Insulator 31, 32 Insulator portion 36 Insulating Film 101 Semiconductor Equipment 201 Hole current 202 Electron current Ciss Input Capacity Coss output capacity CRSS feedback capacity D, D1, D2 distance P1, P 101 peak Qoss output charge amount

Claims

1. First electrode and, The second electrode and A first semiconductor layer of a first conductivity type is provided between the first electrode and the second electrode, A third electrode is provided within the first semiconductor layer and faces the first semiconductor layer via a portion of an insulator, A second semiconductor layer of a second conductivity type is provided between the first semiconductor layer and the second electrode, has a lower surface located on the first electrode side, and is electrically connected to the second electrode. A third semiconductor layer, which extends from the second semiconductor layer toward the first electrode, has a lower end located toward the first electrode that is further toward the first electrode than the lower surface of the second semiconductor layer, is separated from the insulator, and is of the second conductivity type. A fourth electrode facing the second semiconductor layer via another part of the insulator, A fourth semiconductor layer of a first conductivity type is provided between the second semiconductor layer and the second electrode and is electrically connected to the second electrode, Equipped with, The third semiconductor layer is a semiconductor device located on the second electrode side of the upper end of the third electrode that is located on the second electrode side.

2. The semiconductor device according to claim 1, wherein the lower end of the third semiconductor layer is located closer to the first electrode than the lower end of the fourth electrode located on the first electrode side.

3. The semiconductor device according to claim 1, wherein the carrier concentration of the third semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a fifth electrode extending in the direction toward the first electrode and in contact with the fourth semiconductor layer and the second semiconductor layer.

5. The semiconductor device according to claim 4, wherein the lower end of the fifth electrode located on the first electrode side is located on the first electrode side of the lower surface of the second semiconductor layer and is in contact with the third semiconductor layer.

6. The semiconductor device according to claim 4, wherein the fifth electrode extends in the first direction in which the fourth electrode extends.

7. The semiconductor device according to claim 6, wherein the third semiconductor layer extends in the first direction.

8. The fifth electrode is, The main body extends in the first direction from which the fourth electrode extends, Multiple protrusions extending from the main body toward the first electrode, It has, The semiconductor device according to claim 4, wherein the plurality of protrusions are arranged along the first direction.

9. Multiple third semiconductor layers are provided, Each of the third semiconductor layers covers each of the protruding portions, as described in claim 8.

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