Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing a gate-drain capacitance.SOLUTION: A semiconductor device includes: a first electrode; a first conductivity type first semiconductor layer connected to the first electrode and including silicon and carbon; a plurality of second conductivity type second semiconductor layers located on a part of the first semiconductor layer and including silicon and carbon; a first conductivity type third semiconductor layer located on a part of the second semiconductor layer and including silicon and carbon; a second conductivity type fourth semiconductor layer located in a portion of the first semiconductor layer between the second semiconductor layers and including silicon and carbon; a second electrode facing the second semiconductor layer via an insulating film; and a third electrode connected to the second and third semiconductor layers.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The embodiments relate to semiconductor devices.

Background Art

[0002] In semiconductor devices for power control, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) incorporating an SBD (Schottky Barrier Diode) may be used to safely conduct a reflux current. In such semiconductor devices, in order to achieve faster operation, it is required to reduce the capacitance between the gate and the drain.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the embodiments is to provide a semiconductor device capable of reducing the capacitance between the gate and the drain.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer connected to the first electrode and containing silicon and carbon, having a first conductivity type, a plurality of second semiconductor layers disposed on a part of the first semiconductor layer and containing silicon and carbon, having a second conductivity type, a third semiconductor layer disposed on a part of the second semiconductor layer and containing silicon and carbon, having a first conductivity type, a fourth semiconductor layer disposed in the portion of the first semiconductor layer between the second semiconductor layers and containing silicon and carbon, having a second conductivity type, a second electrode facing the second semiconductor layer via an insulating film, and a third electrode connected to the second and third semiconductor layers. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a perspective view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a top view showing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a top view showing region A in Figure 2. [Figure 4] Figure 4 is a cross-sectional view taken along the line B-B' shown in Figure 3. [Figure 5] Figure 5(a) is a cross-sectional view showing the operation of a semiconductor device according to the first embodiment, and Figure 5(b) is a cross-sectional view showing the operation of a semiconductor device according to a comparative example. [Figure 6] Figure 6 is a top view showing a semiconductor device according to the second embodiment. [Figure 7] Figure 7 is a cross-sectional view taken along the line C-C' shown in Figure 6. [Figure 8] Figure 8 is a cross-sectional view showing the operation of the semiconductor device according to the second embodiment. [Figure 9] Figure 9 is a top view showing a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0007] <First Embodiment> Figure 1 is a perspective view showing a semiconductor device according to this embodiment. Figure 2 is a top view showing a semiconductor device according to this embodiment. Figure 3 is a top view showing region A in Figure 2. Figure 4 is a cross-sectional view taken along the line B-B' shown in Figure 3.

[0008] In Figure 1, the drain electrode 11, drain layer 21, source electrode 12, Schottky metal layer 15, source contact layer 26, and p-type layer 27, which will be described later, are omitted from the illustration. In Figure 2, only the semiconductor portion 20, gate electrode 13, ohmic conductive layer 14, and Schottky metal layer 15 are shown. In Figure 3, the source electrode 12 and insulating film 30 are omitted, and the gate electrode 13 and Schottky metal layer 15 are shown by dashed lines.

[0009] As shown in Figures 1 to 4, the semiconductor device 1 according to this embodiment is provided with a drain electrode 11 (first electrode), a source electrode 12 (third electrode), a gate electrode 13 (second electrode), an ohmic conductive layer 14 (conductive layer), a Schottky metal layer 15 (metal layer), a semiconductor portion 20, and an insulating film 30.

[0010] The semiconductor portion 20 has a shape that is, for example, a rectangular plate. The drain electrode 11 is provided over the entire surface of the lower surface 20a of the semiconductor portion 20. The source electrode 12 is provided over substantially the entire surface of the upper surface 20b of the semiconductor portion 20. The semiconductor portion 20 is made of a semiconductor material containing silicon (Si) and carbon (C), for example, a single crystal of silicon carbide (SiC). Each part of the semiconductor portion 20 has its conductivity type set to p-type or n-type by the introduction of impurities. The semiconductor portion 20 is provided with a drain layer 21, a drift layer 22, a base layer 23, a base contact layer 24, a source layer 25, a source contact layer 26, and a p-type layer 27 (fourth semiconductor layer).

[0011] The conductivity type of the drain layer 21 is n + It is of type n and is connected to the drain electrode 11. In this specification, “connection” means an electrical connection. The drain layer 21 constitutes the lower surface 20a of the semiconductor portion 20. The conductivity type of the drift layer 22 is n -It is of a type. That is, the carrier concentration of the drift layer 22 is lower than the carrier concentration of the drain layer 21. The drift layer 22 is disposed on the drain layer 21 and is in contact with the drain layer 21. The drain layer 21 and the drift layer 22 constitute the first semiconductor layer.

[0012] A plurality of base layers 23 are provided and are disposed on a part of the drift layer 22. The conductivity type of the base layer 23 is p-type. The shape of each base layer 23 is a strip extending in one direction.

[0013] In this specification, for convenience of explanation, an XYZ orthogonal coordinate system is adopted. The direction from the drain electrode 〖11〗 to the source electrode 〖12〗 is defined as the "Z direction", the direction in which each base layer 23 extends is defined as the "Y direction", and the direction orthogonal to the Z direction and the Y direction is defined as the "X direction". Note that the Z direction is also referred to as "up", and the opposite direction is also referred to as "down", but this expression is also for convenience and has nothing to do with the direction of gravity.

[0014] The plurality of base layers 23 are arranged along the X direction, and each base layer 23 extends in the Y direction. A portion 22a of the drift layer 22 is interposed between adjacent base layers 23. A plurality of openings 23a are formed in each base layer 23 and are arranged in a row along the Y direction. A portion 22b of the drift layer 22 enters the openings 23a. Among the drift layer 22, the portion 22a disposed between adjacent base layers 23 and the portion 22b that has entered the openings 23a reach the upper surface 20b of the semiconductor portion 20. In the base layers 23 adjacent in the X direction, the positions of the openings 23a in the Y direction are shifted from each other. For this reason, when viewed from the Z direction, the openings 23a are arranged in a staggered pattern.

[0015] As shown in FIG. 2, in the semiconductor device 1, a plurality of ohmic connection regions Ro and a plurality of Schottky barrier diode regions Rs are set and arranged in a checker pattern. That is, the ohmic connection regions Ro and the Schottky barrier diode regions Rs are alternately arranged along the X direction and the Y direction. In FIG. 2, for easy viewing of the figure, the ohmic connection regions Ro and the Schottky barrier diode regions Rs are each hatched.

[0016] An ohmic conductive layer 14 is disposed in the ohmic connection region Ro. The ohmic conductive layer 14 is disposed on the semiconductor portion 20, contacts the upper surface 20b of the semiconductor portion 20, and is ohmically connected to the semiconductor portion 20. The ohmic conductive layer 14 is made of a conductive material, for example, nickel silicide (NiSi).

[0017] The Schottky barrier diode region Rs corresponds to the opening 23a of the base layer 23. A Schottky metal layer 15 is disposed in the Schottky barrier diode region Rs. The Schottky metal layer 15 is disposed on the semiconductor portion 20 and contacts a portion 22b of the drift layer 22, a portion disposed around the portion 22b of the drift layer 22 in the base layer 23, and a part of the source layer 25.

[0018] The Schottky metal layer 15 forms a Schottky barrier diode with the portion 22b of the drift layer 22. The Schottky metal layer 15 is formed of a material that forms a Schottky junction with the n - -type drift layer 22 made of silicon carbide, for example, formed of titanium (Ti).

[0019] As shown in FIGS. 3 and 4, in the semiconductor portion 20, the source layer 25 is disposed on a part of the base layer 23 and contacts the base layer 23. Further, the source layer 25 is separated from the drift layer 22, and the base layer 23 is interposed between the source layer 25 and the drift layer 22. The conductivity type of the source layer 25 is n +This is a type. For example, one source layer 25 is placed on top of one base layer 23.

[0020] Viewed from the Z direction, the source layer 25 has a ladder-like shape, with multiple openings 25a and 25b formed therein. The openings 25a are located in the ohmic connection region Ro, and the openings 25b are located in the Schottky barrier diode region Rs. Therefore, in each source layer 25, the openings 25a and 25b are arranged alternately in a line along the Y direction. For multiple source layers 25 arranged on multiple base layers 23, the openings 25a and 25b are arranged alternately along the X direction.

[0021] The ohmic conductive layer 14 is located inside the opening 25a of the source layer 25. A source contact layer 26 is located between the source layer 25 and the ohmic conductive layer 14. The conductivity type of the source contact layer 26 is n ++ This is the type. That is, the carrier concentration of the source contact layer 26 is higher than the carrier concentration of the source layer 25. The source contact layer 26 is in contact with the source layer 25 and the ohmic conductive layer 14. The source layer 25 and the source contact layer 26 constitute the third semiconductor layer.

[0022] Furthermore, a base contact layer 24 is positioned between the base layer 23 and the ohmic conductive layer 14. The conductivity type of the base contact layer 24 is p ++ This is the type. That is, the carrier concentration of the base contact layer 24 is higher than the carrier concentration of the base layer 23. The base contact layer 24 is in contact with the ohmic conductive layer 14, the base layer 23, and the source contact layer 26. The base layer 23 and the base contact layer 24 constitute the second semiconductor layer.

[0023] The Schottky metal layer 15 is located directly above the opening 25b of the source layer 25. Viewed from the Z direction, the opening 23a of the base layer 23 is located inside the opening 25b of the source layer 25. The Schottky metal layer 15 is in contact with a portion 22b of the drift layer 22 within the opening 23a of the base layer 23, in contact with the base layer 23 within the opening 25b of the source layer 25, and in contact with the source layer 25 around the opening 25b.

[0024] The p-type layer 27 is located within a portion 22a between the base layers 23 in the drift layer 22 and is in contact with portion 22a. The conductivity type of the p-type layer 27 is p-type, and its carrier concentration is approximately equal to that of the base layer 23. The p-type layer 27 is separated from the upper surface 20b of the semiconductor portion 20. The upper surface of the p-type layer 27 is located below the upper surface of the base layer 23, i.e., below the interface between the base layer 23 and the insulating film 30, and the lower surface of the p-type layer 27 is located above the lower surface of the base layer 23, i.e., above the interface between the base layer 23 and the drift layer 22.

[0025] In this embodiment, the p-type layer 27 is positioned on the Schottky barrier diode region Rs side of portion 22a and is in contact with the side surface of the portion of the base layer 23 corresponding to the Schottky barrier diode region Rs. Therefore, portion 22a of the drift layer 22 is interposed between the p-type layer 27 and the ohmic conductive layer 14.

[0026] The gate electrode 13 is located on the semiconductor portion 20 and extends in the Y direction. In the X direction, the gate electrode 13 is located in the region directly above portion 22a between the drift layer 22 and the base layer 23, in the region directly above portion of the base layer 23 between the drift layer 22 and the source layer 25, and in the region directly above portion of the source layer 25 located on the side of portion 22a. The p-type layer 27 is located directly below the gate electrode 13.

[0027] The source electrode 12 is positioned over almost the entire surface of the semiconductor portion 20 and covers the gate electrode 13. The source electrode 12 is in contact with the ohmic conductive layer 14 and the Schottky metal layer 15 and is ohmic connected to them.

[0028] The insulating film 30 is placed between the gate electrode 13 and the semiconductor portion 20, and between the gate electrode 13 and the source electrode 12. As a result, the gate electrode 13 is insulated from the semiconductor portion 20 and the source electrode 12 by the insulating film 30.

[0029] Next, the operation of the semiconductor device according to this embodiment will be described. Figure 5(a) is a cross-sectional view showing the operation of the semiconductor device according to this embodiment, and Figure 5(b) is a cross-sectional view showing the operation of the semiconductor device according to a comparative example.

[0030] As shown in Figures 4 and 5(a), in the semiconductor device 1, when a voltage is applied between the drain electrode 11 and the source electrode 12, with the drain electrode 11 as the positive electrode and the source electrode 12 as the negative electrode, a depletion layer (not shown) expands starting from the interface between the drift layer 22 and the base layer 23. In this state, when a potential higher than the threshold is applied to the gate electrode 13, an inversion layer (not shown) is formed in the portion of the base layer 23 facing the gate electrode 13 via the insulating film 30, and an electron current 200 flows through the path of the source electrode 12, ohmic conductive layer 14, source contact layer 26, source layer 25, inversion layer of base layer 23, drift layer 22, drain layer 21, and drain electrode 11. As a result, current flows from the drain electrode 11 to the source electrode 12. On the other hand, when a potential lower than the threshold is applied to the gate electrode 13, the inversion layer disappears, and the current is interrupted.

[0031] In semiconductor device 1, a freewheeling current may flow from the source electrode 12 to the drain electrode 11 due to external inductance. In this case, in the ohmic connection region Ro, a hole current flows through the path of the source electrode 12, ohmic conductive layer 14, base contact layer 24, base layer 23, drift layer 22, drain layer 21, and drain electrode 11. Also, an electron current flows through the path of the drain electrode 11, drain layer 21, drift layer 22, Schottky metal layer 15, and source electrode 12. In the Schottky barrier diode region Rs, an electron current flows through the path of the drain electrode 11, drain layer 21, drift layer 22, Schottky metal layer 15, and source electrode 12.

[0032] Furthermore, since the semiconductor device 1 has a p-type layer 27 within a portion 22a of the drift layer 22, the area between the gate electrode 13 and the drift layer 22 is reduced, and the gate-drain capacitance Cgd is reduced. The portion of the drift layer 22 between the p-type layer 27 and the insulating film 30 is filled with a depletion layer.

[0033] Furthermore, as described above, the electron current 200 when the semiconductor device 1 is turned on flows through both the ohmic connection region Ro and the Schottky barrier diode region Rs. Since the p-type layer 27 is located on the Schottky barrier diode region Rs side in portion 22a, it may have some effect on the electron current 200 flowing through the Schottky barrier diode region Rs, but it does not have much effect on the electron current 200 flowing through the ohmic connection region Ro. For this reason, even with the provision of the p-type layer 27, the increase in the on-resistance Ron of the semiconductor device 1 can be suppressed. Note that during a short circuit, a larger current flows compared to the normal on state, so the vicinity of the current path generates more heat and becomes hotter. For this reason, the resistance increases and the short-circuit current is suppressed.

[0034] In contrast, as shown in Figure 5(b), the semiconductor device 101 in the comparative example does not have a p-type layer 27. Therefore, the area between the gate electrode 13 and the drift layer 22 is large, and the gate-drain capacitance Cgd is large.

[0035] Next, the effects of this embodiment will be described. In the semiconductor device 1 according to this embodiment, a p-type layer 27 is provided on the Schottky barrier diode region Rs side of portion 22a of the drift layer 22. This allows for a reduction in gate-drain capacitance Cgd while suppressing an increase in on-resistance Ron. As a result, the semiconductor device 1 has a good balance between gate-drain capacitance Cgd and on-resistance Ron.

[0036] Furthermore, in the semiconductor device 1, a Schottky barrier diode region Rs is set and a Schottky metal layer 15 is provided. When a freewheeling current flows, an electron current flows through the Schottky barrier diode region Rs. The potential change caused by this electron current suppresses the effective bias applied to the pn junction. This suppresses the flow of bipolar current through the MOSFET and prevents the expansion of defects in the silicon carbide forming the semiconductor portion 20, thereby preventing an increase in electrical resistance.

[0037] Furthermore, in semiconductor device 1, the ohmic connection region Ro and the Schottky barrier diode region Rs are arranged in a checkerboard pattern, which improves the arrangement density of gate electrodes 13 in the X direction. This reduces the on-resistance of semiconductor device 1 and increases the on-current. In contrast, if the ohmic connection region Ro and the Schottky barrier diode region Rs were arranged in a stripe pattern, gate electrodes 13 could not be placed in the Schottky barrier diode region Rs, thus reducing the maximum on-current.

[0038] <Second Embodiment> Figure 6 is a top view showing a semiconductor device according to this embodiment. Figure 7 is a cross-sectional view taken along the line C-C' shown in Figure 6. In Figure 6, the source electrode 12 and insulating film 30 are omitted, and the gate electrode 13 and Schottky metal layer 15 are shown by dashed lines. The same applies to Figure 9, which will be described later.

[0039] As shown in Figures 6 and 7, the semiconductor device 2 according to this embodiment has a different position of the p-type layer 27 compared to the semiconductor device 1 according to the first embodiment. In the semiconductor device 2, the p-type layer 27 is located on the ohmic connection region Ro side of portion 22a of the drift layer 22. That is, the p-type layer 27 is in contact with the side surface of the portion of the base layer 23 corresponding to the ohmic connection region Ro. For this reason, portion 22a of the drift layer 22 is interposed between the p-type layer 27 and the Schottky metal layer 15.

[0040] Next, the operation and effects of the semiconductor device 2 according to this embodiment will be described. Figure 8 is a cross-sectional view showing the operation of the semiconductor device according to this embodiment. As shown in Figure 8, in this embodiment as well, similar to the first embodiment, a p-type layer 27 is provided within portion 22a of the drift layer 22, so the area of ​​contact between the gate electrode 13 and the drift layer 22 is reduced, and the gate-drain capacitance Cgd is reduced.

[0041] Furthermore, because the p-type layer 27 is located on the ohmic connection region Ro side, it may have some effect on the electron current 200 flowing through the ohmic connection region Ro, but it does not have much effect on the electron current 200 flowing through the Schottky barrier diode region Rs. Thus, there is a trade-off relationship between the electron current 200 flowing through the ohmic connection region Ro and the electron current 200 flowing through the Schottky barrier diode region Rs, depending on the position of the p-type layer 27. In this way, the short-circuit withstand capability of the semiconductor device 2 is also improved by this embodiment. The configuration, operation, and effects of this embodiment other than those described above are the same as in the first embodiment.

[0042] <Third Embodiment> Figure 9 is a top view showing a semiconductor device according to this embodiment. As shown in Figure 9, in the semiconductor device 3 according to this embodiment, the p-type layer 27 is located on one side in the X direction of portion 22a of the drift layer 22. Therefore, the p-type layer 27 extends in the Y direction along one side surface of the base layer 23.

[0043] In this embodiment as well, the gate-drain capacitance Cgd can be reduced. Furthermore, the on-resistance Ron and the short-circuit current that flows during a short circuit are intermediate in effect between the first and second embodiments. The configuration, operation, and effects of this embodiment other than those described above are the same as in the first embodiment.

[0044] In the embodiments described above, examples were shown in which the p-type layer 27 is in contact with the base layer 23, but the p-type layer 27 may be separated from the base layer 23. Also, in the embodiments described above, examples were shown in which the p-type layer 27 is separated from the upper surface 20b of the semiconductor portion 20, but the p-type layer 27 may reach the upper surface 20b and be in contact with the insulating film 30.

[0045] According to the embodiments described above, a semiconductor device capable of reducing gate-drain capacitance can be realized.

[0046] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0047] The present invention includes the following embodiments.

[0048] (Note 1) First electrode and, Connected to the first electrode, comprising a first semiconductor layer of first conductivity type containing silicon and carbon, A plurality of second semiconductor layers are arranged on a portion of the first semiconductor layer, contain silicon and carbon, and have a second conductivity type, Displaced on a portion of the second semiconductor layer, comprising silicon and carbon, and a third semiconductor layer of the first conductivity type, Displaced in the portion between the second semiconductor layers in the first semiconductor layer, a fourth semiconductor layer comprising silicon and carbon, and of a second conductivity type, A second electrode facing the second semiconductor layer via an insulating film, A third electrode connected to the second semiconductor layer and the third semiconductor layer, A semiconductor device equipped with the following features.

[0049] (Note 2) The second semiconductor layer, the third semiconductor layer, and the conductive layer ohmic-connected to the third electrode, A metal layer disposed on the first semiconductor layer and formed a Schottky junction with the first semiconductor layer, Furthermore, The second semiconductor layer extends in a first direction, and a plurality of first openings are arranged along the first direction. The third semiconductor layer extends in the first direction, and the second and third apertures are arranged alternately along the first direction. The conductive layer is disposed within the second opening, The semiconductor device according to Appendix 1, wherein the metal layer is in contact with a portion of the first semiconductor layer located within the third opening.

[0050] (Note 3) The semiconductor device according to Appendix 2, wherein the metal layer and the conductive layer are arranged alternately along a second direction intersecting the first direction.

[0051] (Note 4) The semiconductor device according to Appendix 2 or 3, wherein the first semiconductor layer is interposed between the conductive layer and the fourth semiconductor layer.

[0052] (Note 5) The semiconductor device according to Appendix 2 or 3, wherein the first semiconductor layer is interposed between the metal layer and the fourth semiconductor layer.

[0053] (Note 6) The semiconductor device described in any one of the appendices 1 to 5, wherein the fourth semiconductor layer is separated from the upper surface of the first semiconductor layer.

[0054] (Note 7) The fourth semiconductor layer is in contact with the second semiconductor layer, and is a semiconductor device according to any one of the appendices 1 to 6.

[0055] (Note 8) The semiconductor device according to any one of the appendices 1 to 7, wherein the upper surface of the fourth semiconductor layer is located below the upper surface of the second semiconductor layer, and the lower surface of the fourth semiconductor layer is located above the lower surface of the second semiconductor layer.

[0056] (Note 9) The aforementioned metal layer contains titanium, as described in any one of the appendices 1 to 8.

[0057] (Note 10) The conductive layer comprises nickel and silicon, as described in any one of the appendices 1 to 9.

[0058] (Note 11) First electrode and, Connected to the first electrode, a first semiconductor layer of first conductivity type, A second semiconductor layer of the second conductivity type is disposed on a portion of the first semiconductor layer, Displaced on a portion of the second semiconductor layer, a third semiconductor layer of the first conductivity type, Displaced on the side surface of the second semiconductor layer in the first semiconductor layer, a fourth semiconductor layer of second conductivity type, A second electrode is arranged in a region including the area directly above the fourth semiconductor layer and facing the second semiconductor layer, A third electrode connected to the second semiconductor layer and the third semiconductor layer, A semiconductor device equipped with the following features.

[0059] (Note 12) The semiconductor device described in Appendix 11, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer include silicon and carbon. [Explanation of Symbols]

[0060] 1, 2, 3 Semiconductor equipment 11 Drain electrode 12 Source electrodes 13 gates 14 Ohmic conductive layer 15 Schottky metal layer 20 Semiconductor part 20a Bottom side 20b Top side 21 Drain layer 22 Drift Layers 22a, 22b Drift layer portion 23 Base Layer 23a opening 24 Base contact layer 25 Source Layers 25a, 25b opening 26 Source Contact Layer 27 p-type layer 30 insulating film 101 Semiconductor Equipment 200 electron current Cgd gate-drain capacity Ro ohmic connection area Rs Schottky barrier diode region

Claims

1. First electrode and, Connected to the first electrode, a first semiconductor layer comprising silicon and carbon and having a first conductivity type, A plurality of second semiconductor layers are arranged on a portion of the first semiconductor layer, contain silicon and carbon, and have a second conductivity type, Displaced on a portion of the second semiconductor layer, comprising silicon and carbon, and having a first conductivity type, Displaced in the portion between the second semiconductor layers in the first semiconductor layer, a fourth semiconductor layer comprising silicon and carbon, and of a second conductivity type, A second electrode facing the second semiconductor layer via an insulating film, A third electrode connected to the second semiconductor layer and the third semiconductor layer, Equipped with, A semiconductor device in which the upper surface of the fourth semiconductor layer is located below the upper surface of the second semiconductor layer, and the lower surface of the fourth semiconductor layer is located above the lower surface of the second semiconductor layer.

2. The aforementioned second semiconductor layer, the aforementioned third semiconductor layer, and a conductive layer ohmically connected to the aforementioned third electrode, A metal layer disposed on the first semiconductor layer and formed a Schottky junction with the first semiconductor layer, Furthermore, The second semiconductor layer extends in a first direction, and a plurality of first openings are arranged along the first direction. The third semiconductor layer extends in the first direction, and the second and third openings are arranged alternately along the first direction. The conductive layer is disposed within the second opening, The semiconductor device according to claim 1, wherein the metal layer is in contact with a portion of the first semiconductor layer disposed within the first opening within the third opening.

3. The semiconductor device according to claim 2, wherein the metal layer and the conductive layer are arranged alternately along a second direction intersecting the first direction.

4. The semiconductor device according to claim 2, wherein the first semiconductor layer is interposed between the conductive layer and the fourth semiconductor layer.

5. The semiconductor device according to claim 2, wherein the first semiconductor layer is interposed between the metal layer and the fourth semiconductor layer.

6. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is separated from the upper surface of the first semiconductor layer.

7. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is in contact with the second semiconductor layer.

8. First electrode and, Connected to the first electrode, a first semiconductor layer comprising silicon and carbon and having a first conductivity type, A plurality of second semiconductor layers are arranged on a portion of the first semiconductor layer, contain silicon and carbon, and have a second conductivity type, Displaced on a portion of the second semiconductor layer, comprising silicon and carbon, and having a first conductivity type, Displaced in the portion between the second semiconductor layers in the first semiconductor layer, a fourth semiconductor layer comprising silicon and carbon, and of a second conductivity type, A second electrode facing the second semiconductor layer via an insulating film, A third electrode connected to the second semiconductor layer and the third semiconductor layer, Equipped with, The fourth semiconductor layer is a semiconductor device that is in contact with one of the two second semiconductor layers that sandwich the fourth semiconductor layer, and is separated from the other second semiconductor layer.

9. The semiconductor device according to claim 2, wherein the metal layer comprises titanium.

10. The semiconductor device according to claim 2, wherein the conductive layer comprises nickel and silicon.

11. First electrode and, Connected to the first electrode, a first semiconductor layer of a first conductivity type, A second semiconductor layer of the second conductivity type is disposed on a portion of the first semiconductor layer, Displaced on a portion of the second semiconductor layer, a third semiconductor layer of the first conductivity type, Displaced on the side surface of the second semiconductor layer in the first semiconductor layer, a fourth semiconductor layer of second conductivity type, A second electrode is arranged in a region including the area directly above the fourth semiconductor layer and facing the second semiconductor layer, A third electrode connected to the second semiconductor layer and the third semiconductor layer, A semiconductor device equipped with the following features.

12. The semiconductor device according to claim 11, wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer include silicon and carbon.

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