Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing a breakdown in a termination region.SOLUTION: A semiconductor device includes: a silicon carbide layer including a first surface, a second surface, a third surface positioned at a side opposite to the first and second surfaces in a first direction, and a side surface, the second surface being positioned between the first surface and the side surface in a direction orthogonal to the first direction, the second surface being at a position recessed further toward the third surface side than the first surface; a first electrode provided at the first surface; a second electrode provided at the third surface; a gate electrode provided in the silicon carbide layer between the first surface and the third surface; a gate insulating film provided between the gate electrode and the silicon carbide layer; an inter-layer insulating film provided on the second surface, and having a thickness being greater than a difference in heights in the first direction between the first surface and the second surface; and a field plate provided in the inter-layer insulating film and having a lower resistivity than that of the inter-layer insulating film.SELECTED DRAWING: Figure 2

Description

Technical Field

[0005] , ,

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] The development of power devices using silicon carbide (SiC) has been underway. For SiC devices, an approach to development from a different perspective than silicon devices is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device capable of suppressing breakdown in a termination region.

Means for Solving the Problems

[0005] According to an embodiment, a semiconductor device includes a silicon carbide layer having a first surface, a second surface, a third surface located on the opposite side of the first surface and the second surface in a first direction, and a side surface, wherein the second surface is located between the first surface and the side surface in a direction orthogonal to the first direction and is recessed toward the third surface side from the first surface, the silicon carbide layer, a first electrode provided on the first surface, a second electrode provided on the third surface, a gate electrode provided in the silicon carbide layer between the first surface and the third surface, a gate insulating film provided between the gate electrode and the silicon carbide layer, an interlayer insulating film provided on the second surface and thicker than a height difference in the first direction between the first surface and the second surface, and a field plate provided in the interlayer insulating film and having a lower resistivity than the interlayer insulating film.

Brief Description of the Drawings

[0006] [Figure 1] This is a schematic plan view of the semiconductor device according to the embodiment. [Figure 2] This is a cross-sectional view of AA in Figure 1. [Figure 3] This is a schematic cross-sectional view of a semiconductor device according to a modified embodiment. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] This is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals. In the following embodiments, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type as n-type.

[0008] As shown in Figure 2, the semiconductor device 1 of the embodiment includes a silicon carbide layer 10. The silicon carbide layer 10 has a first surface 101, a second surface 102, a third surface 103, and a side surface 104. The third surface 103 is located on the opposite side of the first surface 101 and the second surface 102 in the first direction Z. The first direction Z is the direction connecting the first surface 101 and the third surface 103 by the shortest distance, or the direction connecting the second surface 102 and the third surface 103 by the shortest distance. Two directions perpendicular to the first direction Z are denoted as the second direction X and the third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0009] The second surface 102 is located between the first surface 101 and the side surface 104 in a direction perpendicular to the first direction Z, and is recessed toward the third surface 103 than the first surface 101. In other words, a step is formed between the first surface 101 and the second surface 102. This step between the first surface 101 and the second surface 102 is represented by H in Figure 2. This step H is also the difference in height between the first surface 101 and the second surface 102 in the first direction Z.

[0010] As shown in Figure 1, in a plan view, the second surface 102 continuously surrounds the first surface 101. In this specification, the region on which the second surface 102 is provided is referred to as the termination region TR of the semiconductor device 1. Inside the termination region TR, the silicon carbide layer 10 is formed in a mesa shape.

[0011] The semiconductor device 1 further comprises a first electrode 41 provided on a first surface 101 and a second electrode 42 provided on a third surface 103. For example, a metal such as aluminum can be used as the material for the first electrode 41. For example, a metal such as nickel silicide, titanium, nickel, or gold can be used as the material for the second electrode 42.

[0012] The semiconductor device 1 further includes a gate electrode 43 and a gate insulating film 31. The gate electrode 43 has a so-called trench gate structure provided in the silicon carbide layer 10 between the first surface 101 and the third surface 103. The gate electrode 43 extends in the third direction Y. A plurality of gate electrodes 43 are arranged side by side in the second direction X. As the material of the gate electrode 43, for example, polycrystalline silicon can be used.

[0013] The gate insulating film 31 is provided between the gate electrode 43 and the silicon carbide layer 10. As the gate insulating film 31, for example, a silicon oxide film can be used.

[0014] The semiconductor device 1 further includes an interlayer insulating film 32 provided on the second surface 102. The thickness T2 of the interlayer insulating film 32 on the second surface 102 is greater than the thickness T1 of the interlayer insulating film 32 on the first surface 101. Each of the thicknesses T1 and T2 represents the maximum thickness in the first direction Z. The thickness T2 of the interlayer insulating film 32 on the second surface 102 is greater than the height difference H in the first direction Z between the first surface 101 and the second surface 102. The upper surface of the interlayer insulating film 32 is at a higher position in the first direction Z than the position of the first surface 101. The interlayer insulating film 32 is also provided between the first surface 101 and the first electrode 41. The interlayer insulating film 32 is also provided between the upper surface of the gate insulating film 31 and the first electrode 41. Further, the interlayer insulating film 32 covers the boundary surface 一百零五 between the first surface 101 and the second surface

[0015] The semiconductor device 1 further includes a field plate 50 provided in the interlayer insulating film 32 on the second surface 102. The interlayer insulating film 32 covers the upper surface, lower surface, and side surfaces of the field plate 50.

[0016] As shown in FIG. 1, the field plate 50 is formed in a plurality of ring shapes in a plan view and continuously surrounds the first surface 101.

[0017] The resistivity of the field plate 50 is lower than that of the interlayer insulating film 32. For example, polycrystalline silicon can be used as the material for the field plate 50. The field plate 50 is electrically floating, for example. In this case, when a voltage is applied to the first electrode 41 and the second electrode 42, the potential of the field plate 50 is set to a potential between the potential of the first electrode 41 and the potential of the second electrode 42. Alternatively, the field plate 50 may be electrically connected to the first electrode 41.

[0018] The semiconductor device 1 may further include an insulating protective film 33. The protective film 33 covers the first electrode 41 and the interlayer insulating film 32. As the protective film 33, for example, a resin such as polyimide can be used.

[0019] The silicon carbide layer has an n-type first layer 11, a p-type second layer 12, and an n-type third layer 13. The semiconductor device 1 has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) structure. The first layer 11 functions as a drift layer in the MOSFET or IGBT. The second layer 12 functions as a base layer in the MOSFET or IGBT. The third layer 13 functions as a source layer in the MOSFET or an emitter layer in the IGBT.

[0020] The first layer 11 is continuously provided between the first surface 101 and the third surface 103, and between the second surface 102 and the third surface 103. The second layer 12 is provided on the first layer 11 and faces the side surface of the gate electrode 43 via the gate insulating film 31. The third layer 13 is provided on the second layer 12 and is electrically connected to the first electrode 41. The n-type impurity concentration of the third layer 13 is higher than that of the first layer 11.

[0021] The silicon carbide layer 10 further includes a fourth layer 14 provided between the first layer 11 and the second electrode 42. The fourth layer 14 is electrically connected to the second electrode 42. In a MOSFET, the fourth layer 14 functions as an n-type drain layer. In this case, the n-type impurity concentration of the fourth layer 14 is higher than that of the first layer 11. In an IGBT, the fourth layer 14 functions as a p-type collector layer. In this case, the p-type impurity concentration of the fourth layer 14 is higher than that of the second layer 12.

[0022] Furthermore, the silicon carbide layer 10 has a p-type seventh layer 17 provided on the second layer 12 and in contact with the first electrode 41. The p-type impurity concentration of the seventh layer 17 is higher than that of the second layer 12. The second layer 12 is electrically connected to the first electrode 41 via the seventh layer 17.

[0023] When the semiconductor device 1 is turned on, a potential above a threshold is applied to the gate electrode 43, and an inversion layer (n-type channel) is formed in the region of the second layer 12 facing the side surface of the gate electrode 43. The first electrode 41 is given a potential lower than that of the second electrode 42, and the second electrode 42 is given a potential higher than that of the second electrode 41. In this state, current flows between the first electrode 41 and the second electrode 42 through the third layer 13, the n-type channel, the first layer 11, and the fourth layer 14.

[0024] When the potential of the gate electrode 43 falls below a threshold, the n-type channel is cut off, and the semiconductor device 1 enters an off state. In this off state, a depletion layer spreads within the first layer 11 (drift layer) from the pn junction between the n-type first layer 11 (drift layer) in the silicon carbide layer 10 and the p-type layer in contact with the first layer 11, and the breakdown voltage of the semiconductor device 1 is maintained.

[0025] In a trench gate structure, the electric field tends to concentrate at the bottom of the gate electrode 43. Furthermore, since the dielectric breakdown field of SiO2 used in the gate insulating film 31 is smaller than that of silicon carbide (SiC), there is a concern that the gate insulating film 31 may break down before the SiC breaks down. Therefore, in this embodiment, the silicon carbide layer 10 further has a p-type fifth layer 15. The fifth layer 15 is located below the gate electrode 43 within the first layer 11 and is in contact with the gate insulating film 31 provided on the bottom surface of the gate electrode 43. The fifth layer 15 is electrically connected to the first electrode 41. The p-type impurity concentration of the fifth layer 15 is higher than that of the second layer 12. This fifth layer 15 can mitigate the electric field concentration on the gate insulating film 31 provided on the bottom surface of the gate electrode 43 and suppress the breakdown of the gate insulating film 31.

[0026] Furthermore, in order to facilitate the expansion of the depletion layer in the terminal region TR, it is preferable to provide a p-type layer at the same height as the fifth layer 15 in the terminal region TR as well. In this embodiment, the silicon carbide layer 10 further comprises a p-type sixth layer 16. The sixth layer 16 is located below the second surface 102 within the first layer 11 and is at the same height as the fifth layer 15 in the first direction Z. The same height means that at least a portion of the sixth layer 16 is located on the extension along the second direction X (or third direction Y) of the range formed by the fifth layer 15 in the first direction Z. The p-type impurity concentration of the sixth layer 16 is higher than that of the second layer 12. The sixth layer 16 is electrically connected to the first electrode 41.

[0027] In the example shown in Figure 2, the sixth layer 16 includes multiple guard ring layers 16A. The guard ring layers 16A continuously surround the region inside the second surface 102.

[0028] Alternatively, the p-type sixth layer 16B shown in Figure 3 may be provided at the same height as the fifth layer 15 in the termination region TR. The sixth layer 16B is located below the second surface 102 within the first layer 11 of the termination region TR, for example, in continuation of the p-type eighth layer 18 described later. The p-type impurity concentration of the sixth layer 16B is higher than that of the second layer 12. The sixth layer 16B is electrically connected to the first electrode 41.

[0029] The sixth layer 16B has a so-called RESURF (REduced Surface Field) structure. The sixth layer 16B has a p-type impurity concentration gradient in which the p-type impurity concentration on the side closer to the side 104 is lower than the p-type impurity concentration on the side closer to the gate electrode 43. The p-type impurity concentration of the sixth layer 16B gradually decreases from the eighth layer 18 side toward the side 104.

[0030] Impurities in SiC are less susceptible to thermal diffusion than impurities in Si. Therefore, in this embodiment, by removing a portion of the upper surface of the silicon carbide layer 10 as described later, the sixth layer 16 can be distributed from the same depth as the fifth layer 15 to the second surface 102, which is the surface of the silicon carbide layer 10 in the terminal region TR.

[0031] By forming an interlayer insulating film 32 to fill the space on the second surface 102 formed by removing a portion of the upper surface of the silicon carbide layer 10, a thick interlayer insulating film 32 can be formed. This thick interlayer insulating film 32 suppresses the intrusion of moisture from the outside and improves moisture resistance. For example, it can suppress structural abnormalities such as oxidation of the first electrode 41 due to a reaction between moisture and the metal of the first electrode 41, and the resulting deterioration of the protective film 33. As a result, the reliability of the semiconductor device 1 can be increased.

[0032] Furthermore, by utilizing the space on the second surface 102 to increase the thickness of the interlayer insulating film 32, the overall height of the semiconductor device 1 can be made uniform. This improves flatness and increases mechanical strength.

[0033] Furthermore, a field plate 50 is provided utilizing the space on the second surface 102. The field plate 50 facilitates the expansion of the depletion layer within the silicon carbide layer 10 of the terminal region TR. This suppresses localized electric field concentration in the terminal region TR and reduces breakdown voltage fluctuations. As a result, the reliability of the semiconductor device 1 can be increased. Even when there is a large amount of charge present in the interlayer insulating film 32 and at the interface between the interlayer insulating film 32 and the second surface 102, and the expansion of the depletion layer is insufficient with only the sixth layer 16, the field plate 50 facilitates the expansion of the depletion layer.

[0034] It is preferable that the field plate 50 is located within the range from the height of the second surface 102 to the height of the first surface 101 (within the range of the step H). That is, in the first direction Z, it is preferable that the position of the upper surface of the field plate 50 is at the same height as or lower than the position of the first surface 101. As a result, the field plate 50 approaches the interface (second surface 102) between the silicon carbide layer 10 and the interlayer insulating film 32, thereby increasing the influence of the field plate 50 on the interface and suppressing breakdown voltage fluctuations due to the influence of interfacial charge. In addition, the flatness of the upper surface of the semiconductor device 1 is improved compared to when the upper surface of the field plate 50 is at a position higher than the height of the first surface 101, which can suppress process defects and improve mechanical strength.

[0035] Preferably, the silicon carbide layer 10 has a p-type eighth layer 18 located between the fifth layer 15 and the sixth layer 16 at the same height. This makes it easier to spread the depletion layer in the silicon carbide layer 10 between the region where the gate electrode 43 is provided (the active region where current mainly flows in the ON state) and the terminal region TR, thereby suppressing localized electric field concentration. The p-type impurity concentration of the eighth layer 18 is higher than that of the second layer 12.

[0036] A p-type ninth layer 19 is provided on the eighth layer 18. The upper surface of the ninth layer 19 is included in the first surface 101. A p-type tenth layer 20 is provided within the ninth layer 19. The p-type impurity concentration of the ninth layer 19 is lower than that of the eighth layer 18 and the tenth layer 20. The p-type impurity concentration of the tenth layer 20 is higher than that of the eighth layer 18. The tenth layer 20 is in contact with the first electrode 41. The ninth layer 19 is electrically connected to the first electrode 41 via the tenth layer 20.

[0037] Of the multiple gate electrodes 43, the outermost gate electrode 43A, which is located closest to the termination region TR, is a dummy electrode that does not function as a gate electrode that conducts current through the aforementioned path when ON. The gate insulating film 31 provided on the side of the outermost gate electrode 43A is in contact with the p-type seventh layer 17 and the p-type eleventh layer 21. The gate insulating film 31 provided on the bottom surface of the outermost gate electrode 43A is in contact with the eighth layer 18. The lower end of the eleventh layer 21 is in contact with the eighth layer 18. The eighth layer 18 is electrically connected to the first electrode 41 via the seventh layer 17 and the eleventh layer 21. The p-type impurity concentration of the eleventh layer 21 is lower than that of the seventh layer 17 and higher than that of the eighth layer 18.

[0038] The silicon carbide layer 10 may further have an n-type 12th layer 22. The 12th layer 22 is located at the corner between the second surface 102 and the side surface 104 on the first layer 11 of the termination region TR. The 12th layer 22 is located away from the 6th layer 16 in the second direction X and the third direction Y, and is provided in a ring shape along the outer edge of the semiconductor device 1. The n-type impurity concentration of the 12th layer 22 is higher than that of the first layer 11. The 12th layer 22 is given the same potential as the second electrode 42. The 12th layer 22 functions as a field stop layer that suppresses the excessive spreading of the depletion layer and prevents the depletion layer from reaching the side surface 104. This suppresses leakage current at the side surface 104. The 12th layer 22 is located at the same height as the 6th layer 16 in the first direction Z. This makes it easier to stop the depletion layer that has spread from the pn junction between the 6th layer 16 and the 1st layer 11.

[0039] Next, a method for manufacturing the semiconductor device 1 according to an embodiment will be described with reference to Figures 4 to 14.

[0040] As shown in Figure 4, for example, an n-type layer 11A is formed on the fourth layer 14, which is prepared as a SiC substrate. The n-type layer 11A is epitaxially grown on the fourth layer 14 (SiC substrate).

[0041] For example, p-type impurities are implanted into the surface of the n-type layer 11A by ion implantation, forming the fifth layer 15, the eighth layer 18, and the sixth layer 16 on the surface of the n-type layer 11A, as shown in Figure 5. Aluminum can be used as the p-type impurity, for example. Furthermore, n-type impurities are implanted into the surface of the n-type layer 11A to form the twelfth layer 22. Nitrogen or phosphorus can be used as the n-type impurity, for example.

[0042] After forming the 5th layer 15, the 8th layer 18, the 6th layer 16, and the 12th layer 22, as shown in Figure 6, an n-type layer 11B and a p-type layer 19A are formed on the surface of the n-type layer 11A. First, the n-type layer 11B is formed by epitaxial growth over the entire surface of the n-type layer 11A, and then p-type impurities are implanted into the n-type layer 11B by ion implantation to form the p-type layer 19A. The implantation depth of the p-type impurities implanted into the active region where the gate electrode 43 is located is shallower than the implantation depth of the p-type impurities implanted into the region outside the active region. The n-type layer 11B remains on the active region. In the region outside the active region, the p-type layer 19A is in contact with the 8th layer 18 and the 6th layer 16. The thickness of the p-type layer 19A on the n-type layer 11B remaining in the active region is thinner than the thickness of the p-type layer 19A in the region outside the active region. n-type layer 11A and n-type layer 11B constitute the first layer 11.

[0043] After forming the p-type layer 19A, a portion of the p-type layer 19A is removed, and a first surface 101 and a second surface 102 are formed on the upper surface of the silicon carbide layer 10, as shown in Figure 7. By removing a portion of the p-type layer 19A, the second surface 102 is formed in a recessed position from the first surface 101. For example, a portion of the p-type layer 19A can be removed by the RIE (Reactive Ion Etching) method. The remaining p-type layer 19A on the eighth layer 18 becomes the ninth layer 19.

[0044] In the active region, n-type impurities are implanted into the p-type layer 19A by ion implantation from the first surface 101, forming the third layer (source layer or emitter layer) 13. The p-type layer 19A remaining beneath the third layer 13 becomes the second layer (base layer) 12. Additionally, the implantation of p-type impurities from the first surface 101 forms the seventh layer 17 and the tenth layer 20, which have a higher concentration of p-type impurities than the p-type layer 19A.

[0045] Next, as shown in Figure 8, a plurality of trenches t having openings on the first surface 101 are formed in the silicon carbide layer 10. For example, the trenches t can be formed by the RIE method. The bottom of the trenches t reaches the fifth layer 15. The bottom of the outermost trench tA, which is located on the outermost side, reaches the eighth layer 18.

[0046] After forming trenches t, resist is embedded in the trenches t other than the outermost trench tA, and ion implantation is performed on the side surface of the outermost trench tA. p-type impurities are implanted obliquely into the side surface of the outermost trench tA, and a p-type 11th layer 21 with a higher p-type impurity concentration than the 2nd layer 12 and the 9th layer 19 is formed in the region adjacent to the side surface of the outermost trench tA.

[0047] After this, a resist is embedded in the outermost trench tA, and a first layer 32A, which will become part of the interlayer insulating film 32, is formed over the entire surface of the first surface 101 and the second surface 102. For example, the first layer 32A can be formed by the CVD (Chemical Vapor Deposition) method. The first layer 32A is patterned, and as shown in Figure 9, the first layer 32A on the first surface 101 is removed, leaving the first layer 32A on the second surface 102.

[0048] After this, the resist in the trench t is removed, and as shown in Figure 10, a gate insulating film 31 is formed on the side surface of the trench t, ​​the bottom surface of the trench t, ​​the first surface 101, the top surface of the first layer 32A, and the interface 105 connecting the first surface 101 and the second surface 102. For example, the gate insulating film 31 can be formed by the CVD method.

[0049] Subsequently, as shown in Figure 11, the gate electrode 43 and the field plate 50 are formed. For example, a polycrystalline silicon layer is formed on the gate insulating film 31 by CVD so as to fill the trench t, ​​and then patterned. After patterning, the polycrystalline silicon layer remaining in the trench t becomes the gate electrode 43, and the polycrystalline silicon layer remaining in the first layer portion 32A becomes the field plate 50.

[0050] In the following drawings, the gate insulating film 31 on the first surface 101 and the gate insulating film 31 on the first layer 32A are considered to be part of the interlayer insulating film 32 and are therefore not shown.

[0051] Subsequently, as shown in Figure 12, the second layer 32B of the interlayer insulating film 32 is formed on the first surface 101, the gate electrode 43, and the first layer 32A, for example, by CVD. The field plate 50 is embedded within the interlayer insulating film 32.

[0052] After forming the interlayer insulating film 32, as shown in Figure 13, the interlayer insulating film 32 in the region above the first surface 101 where the first electrode 41 is formed is thinned, for example, by the RIE method. This improves the flatness of the upper surface of the semiconductor device 1 after the first electrode 41 is formed.

[0053] Next, as shown in Figure 14, multiple openings 61 are formed in the interlayer insulating film 32. For example, the openings 61 can be formed by the RIE method using a resist mask. The upper surfaces of the third layer 13 and the seventh layer 17 are exposed at the openings 61. The upper surface of the tenth layer 20 is also exposed at the openings 61.

[0054] As shown in Figure 2, a first electrode 41 is formed inside the opening 61 and on the interlayer insulating film 32. In addition, a second electrode 42 is formed on the back surface of the fourth layer 14.

[0055] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0056] 1...Semiconductor device, 10...Silicon carbide layer, 11...First layer, 12...Second layer, 13...Third layer, 14...Fourth layer, 15...Fifth layer, 16...Sixth layer, 16A...Guard ring layer, 31...Gate insulating film, 32...Interlayer insulating film, 33...Protective film, 41...First electrode, 42...Second electrode, 43...Gate electrode, 50...Field plate, 101...First surface, 102...Second surface, 103...Third surface, 104...Side surface, TR...Terminal region

Claims

1. A silicon carbide layer having a first surface, a second surface, a third surface located opposite the first and second surfaces in a first direction, and a side surface, wherein the second surface is located between the first surface and the side surface in a direction perpendicular to the first direction, and is recessed toward the third surface than the first surface, The first electrode provided on the first surface, The second electrode provided on the third surface, A gate electrode provided in the silicon carbide layer between the first surface and the third surface, A gate insulating film is provided between the gate electrode and the silicon carbide layer, An interlayer insulating film is provided on the second surface and is thicker than the difference in height between the first surface and the second surface in the first direction, A field plate provided within the interlayer insulating film, having a lower resistivity than the interlayer insulating film and being electrically floating, A semiconductor device equipped with the following features.

2. A silicon carbide layer having a first surface, a second surface, a third surface located opposite the first and second surfaces in a first direction, and a side surface, wherein the second surface is located between the first surface and the side surface in a direction perpendicular to the first direction, and is recessed toward the third surface than the first surface, The first electrode provided on the first surface, The second electrode provided on the third surface, A gate electrode provided in the silicon carbide layer between the first surface and the third surface, A gate insulating film is provided between the gate electrode and the silicon carbide layer, An interlayer insulating film is provided on the second surface and is thicker than the difference in height between the first surface and the second surface in the first direction, A field plate provided within the interlayer insulating film, having a lower resistivity than the interlayer insulating film, and electrically connected to the first electrode, A semiconductor device equipped with the following features.

3. The semiconductor device according to claim 1 or 2, wherein the field plate is located within the range from the height of the second surface to the height of the first surface.

4. The aforementioned silicon carbide layer is A first conductive type first layer is continuously provided between the first surface and the third surface, and between the second surface and the third surface, A second layer of second conductivity type is provided on the first layer and faces the side surface of the gate electrode via the gate insulating film, A third layer of first conductivity type is provided on the second layer, has a higher concentration of first conductivity type impurities than the first layer, and is electrically connected to the first electrode. A fourth layer is provided between the first layer and the second electrode and is electrically connected to the second electrode, A fifth layer of second conductivity type is located below the gate electrode within the first layer and is in contact with the gate insulating film provided on the bottom surface of the gate electrode, A semiconductor device according to claim 1 or 2, having the following features.

5. The semiconductor device according to claim 4, wherein the silicon carbide layer further comprises a sixth layer of second conductivity type located below the second surface within the first layer and at the same height as the fifth layer in the first direction.

6. The semiconductor device according to claim 5, wherein the sixth layer includes a plurality of guard ring layers.

7. The semiconductor device according to claim 5, wherein the sixth layer has a concentration gradient of second conductivity type impurities such that the concentration of second conductivity type impurities on the side closer to the side surface is lower than the concentration of second conductivity type impurities on the side closer to the gate electrode.

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