Modeling the effects of process variability on superconducting and semiconductor devices using physical device measurements.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SYNOPSYS INC
- Filing Date
- 2022-04-27
- Publication Date
- 2026-08-04
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Abstract
Description
Technical Field
[0001] Exemplification Regarding Rights of the U.S. Government This invention was made with U.S. government support under contract W911NF-17-9-0001 awarded by the Office of the Director of National Intelligence, Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Laboratory. The U.S. government has certain rights in this invention.
[0002] This disclosure generally relates to modeling systems. In particular, this disclosure relates to systems and methods for modeling and simulating devices, such as superconducting devices and semiconductor devices, from the perspective of process variations during manufacturing. (variations)
Background Art
[0003] As technology advances, superconducting and semiconductor products are becoming increasingly complex. Transistors, Josephson junctions, and other devices are getting smaller, die sizes are getting larger, and the number of devices on a die is increasing. The task of developing these products has become more complex, but market pressures are shortening the time available to bring new products to market. If there are defects in the design, it is costly to start manufacturing new products. As a result, simulation of these devices has become even more important but also more difficult.
[0004] The technologies used to manufacture superconducting and semiconductor products are also becoming more complex and difficult. Any process has variations that result in variations in the final product. Given the strict tolerances, short turnaround times, and cost of errors associated with the products, it is important to account for these process variations in the simulation and modeling of superconducting, semiconductor, and other devices.
Summary of the Invention
[0005] In one embodiment, evaluation metrics measured on a physical device (metrics) The sample set is selected from a larger sample size. Examples of devices include superconducting and semiconductor devices. The measured performance metrics are not all the same and have some distribution. Samples are selected based on the distribution of the measured performance metrics. A set of model instances is constructed corresponding to the selected set of samples. Parameters are set for the model instances so that a simulation of the model instances using the parameters predicts performance metrics that fit the measured performance metrics from the sample set. The principal components of the parameter variances are calculated. The nonlinear model is fitted to the parameter variances as a function of the principal components. The statistical variations of the principal components are adapted to the nonlinear model to introduce statistical variability into the parameters, which are then applied to the simulation of the model instances to give an estimate of the statistical variability of the simulated device.
[0006] Other embodiments include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any of the above.
[0007] This disclosure will be better understood from the detailed description and accompanying drawings of embodiments of this disclosure provided below. The drawings are used to provide knowledge and understanding of embodiments of this disclosure and do not limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily to scale. [Brief explanation of the drawing]
[0008] [Figure 1A] This flowchart illustrates the impact of process variability on device simulations. [Figure 1B]This flowchart illustrates the impact of process variability on device simulations. [Figure 2A] This is a flowchart illustrating the process of converting measurement samples from a physical device into statistical variability in a simulation of such a physical device. [Figure 2B] This is a flowchart illustrating the process of converting measurement samples from a physical device into statistical variability in a simulation of such a physical device. [Figure 3] This figure shows the IV curve for a Josephson junction superconductor device. [Figure 4A] This figure shows the distribution of samples for individual evaluation metrics of superconducting devices across several dies. [Figure 4B] This figure shows the distribution of samples for individual evaluation metrics of superconducting devices across several dies. [Figure 4C] This figure shows the bivariate distribution of two evaluation metrics for superconducting devices across several dies. [Figure 5] This figure shows an excerpt from a table of model parameters {Y} for superconducting devices. [Figure 6] This figure shows a summary screen of the principal component analysis for a superconducting device. [Figure 7] This figure shows a nonlinear model fitted to model parameters as a function of principal components for a Josephson junction superconductor device. [Figure 8A] These figures show a comparison between the measured and simulated evaluation metrics for Josephson junctions. [Figure 8B] These figures show a comparison between the measured and simulated evaluation metrics for Josephson junctions. [Figure 9A] This figure shows the distribution of samples for evaluation metrics of semiconductor devices. [Figure 9B] This figure shows the distribution of samples for evaluation metrics of semiconductor devices. [Figure 10]A diagram showing the two-variable distribution of two evaluation metrics, where one is from a negative-type metal oxide semiconductor (NMOS) transistor and the other is from a positive-type metal oxide semiconductor (PMOS) transistor. [Figure 11] A diagram showing the BSIM4 model parameters extracted for three samples. [Figure 12A] A diagram showing the correction of the extraction of model parameters for semiconductor devices. [Figure 12B] A diagram showing the correction of the extraction of model parameters for semiconductor devices. [Figure 13] A diagram showing a non-linear model fitted to the model parameters as a function of the principal components for NMOS transistor semiconductor devices. [Figure 14A] A diagram showing the comparison of the measured and simulated evaluation metrics for complementary metal oxide semiconductor (CMOS) processes, respectively. [Figure 14B] A diagram showing the comparison of the measured and simulated evaluation metrics for complementary metal oxide semiconductor (CMOS) processes, respectively. [Figure 15] A diagram showing the comparison of the physical parameters and the principal components for CMOS processes. [Figure 16] A flowchart of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure. [Figure 17] A diagram of an exemplary computer system in which embodiments of the present disclosure can operate.
Embodiments for Carrying Out the Invention
[0009] Aspects of the present disclosure relate to modeling the impact of process variations on superconducting and semiconductor devices based on measurements of physical devices. Device simulation is an important part of the design and development of superconducting and semiconductor products. At the same time, any superconducting or semiconductor manufacturing process has process variations, which result in differences between the same device designs manufactured on different dies or wafers. It is desirable to include the impact of these process variations in device simulation.
[0010] However, it can be difficult to understand or quantify process variations in a way that is easily usable in simulation. Manufacturing processes, especially at advanced technology nodes, are not always well understood. In addition, the metrics that can be measured by a fab are often not the quantities used in simulation modeling, and thus it is not clear how the variations in the measured metrics should be modeled in simulation. Furthermore, a fab typically measures a large number of metrics across many different dies and wafers. Analyzing all of these measured samples using an exhaustive approach can be computationally expensive. Also, some measurements may not actually represent normal process variations and can be outliers that distort the analysis unevenly, so it may not lead to the best results.
[0011] In one aspect, a smaller set of samples is selected from a larger number of available samples based on the distribution of the measured metrics. As a result, fewer samples can be used while still appropriately representing the impact of process variations.
[0012] A parameterized model of the device is used for the simulation. A set of model instances is generated by setting model parameters based on measured evaluation metrics in a selected set of samples. Interactions between different model parameters are included by computing the principal components of the variation in the model parameters and then expressing the parameters as nonlinear functions of the principal components. The effects of process variability can then be modeled by considering the statistical variability of the principal components and propagating these variability through the nonlinear model to the model parameters and then through the simulation to the device properties of interest.
[0013] Figures 1 and 2 illustrate an example of this method in more detail. Figure 1A shows the simulation flow. A parameterized model 120 of the device is used in the simulation 190. The parameters for the model are denoted by Y=(y1,y2,...yJ), where yj,j=1...J are individual parameters. A model for a particular device is defined by selecting a value for the parameter Y, which is called a model instance 122. The model instance 122 is used in the simulation 190, which yields several results 192, which are typically the predicted characteristics, behavior, or other properties of the device being simulated.
[0014] As shown in Figure 1B, even if the device may have nominal values for the model parameter 120, process variability 100 causes variability in the parameter value, and therefore there exists a distribution 125 of parameter Y shown as dist(Y) in Figure 1B. This results in the corresponding distribution 125 of the model instance and the distribution 195 of the predicted result dist(result).
[0015] However, dist(Y) is not known a priori and is not readily measurable. Fab can measure certain evaluation metrics, but these are typically not the model parameter Y. Figures 2A and 2B are flowcharts of an exemplary process for estimating the statistical variability of the model parameter Y based on measured evaluation metrics.
[0016] Figure 2A begins with a large number of available sample measurements. The samples include different metrics measured on physical devices, e.g., on different dies and wafers. In some cases, the physical devices may be multiple physical instances of the same device design, all manufactured using the same process (e.g., the same process node). The measured metrics are denoted by M=(m1,m2,...mI), where mi,i=1...I are the different metrics measured. Each sample contains a metric M measured on a physical device. A very large number of samples may exist.
[0017] For example, a smaller but representative set of samples {M} is selected from a larger number of available samples, as described below (210). As a result of process variability, the evaluation index M measured in the available samples are not all the same and have some distribution. Samples are selected to be included in set {M} based on the distribution of the measured evaluation index M. For example, set {M} may include samples representing the lower specification limit (LSL) and upper specification limit (USL) of wafer acceptance test (WAT) or scrap criteria. Set {M} includes +3σ and -3σ displacement values of evaluation index m1. (quantile) The set may also include samples representing the +3σ and -3σ displacement values of the evaluation index m2, and similarly for all other evaluation indices mi. Other displacement values may also be used. Samples can also be selected based on bivariate and other multivariate distributions. For example, the bivariate distributions of evaluation indices m1 and m2 may fit an elliptic distribution with a major axis and a minor axis. Samples representing displacement values along the major and minor axes may also be selected to be included in the set {M}.
[0018] The evaluation metrics M in a sample set are measures of process variability, but they are typically not the same as the model parameters Y and cannot be readily used in device simulations. Rather, a set of model instances {Y} corresponding to a selected set of samples {M} is generated by setting parameters such that a simulation of the model instances using parameters {Y} yields or predicts an evaluation metric that fits the measured evaluation metric {M} from the selected set of samples (220). Accurate fitting may not always be possible. In one method, the predicted evaluation metric falls within a certain threshold of the measured evaluation metric. In an alternative method, parameters are used that yield the evaluation metric closest to the measured evaluation metric. This process may be called model extraction. Model parameters {Y} are extracted from the sample set {M}. Because there is variability in the measured evaluation metric {M}, there is also variability in the corresponding model parameters {Y}.
[0019] When complex physical models are used, variability in the model parameters {Y} can be explained by the variability of the corresponding physical quantities. However, this can be complex and incomplete. Instead, the principal component method is used. The parameters {Y} are reduced by their mean (230), resulting in parameter variation {ΔY}, where ΔY = Y - average(Y). Different estimates of the mean can be used.
[0020] The principal components of these variations {ΔY} are calculated (240). The principal components are denoted by P=(p1,p2,...pK), where each pk is one principal component (e.g., an eigenvector). The set of principal components P may be cut off at some number K rather than using the complete basis set. The variation of the parameters {ΔY} can be expressed as a linear combination of the principal components P, which ignores any interactions between the components pk. Instead, a nonlinear model is fitted to the variation of the parameters {ΔY} as a function of the principal components P (250). That is, ΔY=F(P), where F() is nonlinear. This can be expressed as a set of nonlinear relations for each model parameter, i.e., Δyj=fj(P), where j is the index of the model parameter. Since there is variation in the model parameters {ΔY}, there is also variation in the principal components. For convenience, the principal components can be normalized such that this variation has a mean = 0 and a standard deviation = 1.
[0021] As evidenced by the measured evaluation index {M}, the effects of process variability can now be explained during the simulation, as shown in Figure 2B. The principal component P can be assumed to have some kind of statistical distribution dist(P), preferably a Gaussian distribution with mean = 0 and standard deviation = 1, by appropriately scaling the principal component. The statistical variability of the principal component is then applied to the nonlinear model ΔY=F(P) (260), and by adding the mean, the statistical variability of the model parameters dist(ΔY) and dist(Y) can be obtained. This can then be applied to the simulation of a model instance (290) to yield the statistical variability dist(result)295 of the desired properties of the simulated device.
[0022] For example, a Monte Carlo simulation of a device can be performed to determine how the device behaves in terms of variability. In a Monte Carlo simulation, many instances of the device are simulated by selecting the values of the principal components according to the distribution dist(P). Each instance produces a Result, and the collection of Results from the simulation yields the distribution dist(Result)295.
[0023] Examples of superconducting devices Figures 3–8 show an example for Josephson junction superconductor devices. For these types of devices, measured performance metrics can be obtained based on IV curves, process control monitors, wafer acceptance tests, and various circuit performance metrics. Figure 3 shows current-voltage (IV) curves for 100 Monte Carlo samples of Josephson junctions, illustrating various performance metrics. An exemplary performance metric is icrit(I C )=critical current, rnorm(R n ) = normal resistance, Rsg = subgap resistance, Vgap = gap voltage, and delV = gap width. Additional evaluation metrics may include ring oscillator delay (however, the ring in this case is the ring of a Josephson junction, different from the ring of an inverter or other static complementary logic gate used in CMOS), passive transmission line + driver / receiver combinations for various lengths and other geometric considerations, probed path delay, measured inductance, and various superconducting quantum interference devices (SQUIDs). In the examples in Figures 3 to 8, eight different evaluation metrics were considered, namely icrit, rnorm, Rsg, Vgap, delV, Rshunt, Lshunt, and JJ cap. These evaluation metrics describe the electrical characteristics of the Josephson junction. Approximately 80 samples were selected from a total of 200 available samples.
[0024] Figures 4A-4C illustrate selection step 210 in Figure 2A. Figure 4A shows a histogram of the distribution of 200 samples for the evaluation index icrit. The m_prefix in the evaluation index name indicates the measured evaluation index (e.g., m_icrit). From this distribution, samples representing the upper and lower limits of the process are selected, i.e., the LSL and USL in Figure 4A. This is repeated for each evaluation index. For each process limit, multiple samples may be selected. In Figure 4B, samples representing the mean and the + / -1σ and + / -2σ displacement values are selected for each evaluation index. For example, if multiple samples are close to that displacement value, multiple samples may be selected for each displacement value. If more samples are available, a sample representing + / -3σ may also be used, as it is a common cutoff for rejecting devices during production. Alternatively, samples may be selected for + / -3σ, + / -2σ, and + / -1σ. The 10th and 90th percentiles or other displacement values may also be used. Extreme maximum and minimum values are undesirable because they may be abnormal and often lead to data being discarded.
[0025] Figure 4C shows the bivariate distributions of two evaluation indices, icrit and rnorm. Additional samples are selected based on this distribution. In one method, the bivariate distribution is fitted to an ellipse of equally probable density, shown as the blue ellipse in Figure 4C. Figure 4C has a probability ellipse at 0.41624, and therefore slightly less than half of the sample bits lie inside the ellipse. This technique is used to match the bivariate normal ellipse to the respective -1σ and +1σ displacement values of a univariate distribution (assuming they are correlated). This shows the joint probability. For non-Gaussian distributions, a box-Cox transform may be applied to the samples before fitting the probability ellipse. Box-Cox is a method known in statistics to take a non-Gaussian distribution (where skewness is present) and transform them into a Gaussian distribution.
[0026] The ellipse has a major axis and a minor axis, and samples approaching the major and minor axes just outside the ellipse are also selected. In Figure 4C, samples are selected for dies 45, 92, 165, and 175. These samples are different from the samples selected in Figure 4A (which, in the case of icrit, are dies 95 and 170) and also different from the samples selected in Figure 4B. Based on the bivariate distribution, the samples selected in Figure 4C represent different aspects of process variability that include correlations between different evaluation metrics. This selection can be repeated for the bivariate distribution of all pairs of evaluation metrics. Alternatively, it may be repeated only for pairs that show a correlation of a certain amount.
[0027] The selection process yields a set of samples {M} that is smaller than the starting point for all available samples, but still represents the variability of the process. Model parameters Y are fitted to each sample M, yielding a set of model parameters {Y} corresponding to the evaluation metric {M}. For example, if the model is HSPICE, we solve a multivariate optimization problem to find HSPICE parameters {Y} that predict an evaluation metric that fits the measured evaluation metric {M}.
[0028] In one approach, this is performed by Synopsys' Mystic tool, which performs a kind of model fitting / model extraction that aligns HSPICE parameters (.model card coefficient values) so that the evaluation metrics predicted in HSPICE align with the same measured evaluation metrics. Possible techniques for this multi-objective multivariate optimization problem include less classical methods such as Design of Experiments (DoE), Response Surface Modeling (RSM), and Surrogate-Based Optimization (SBO).
[0029] Note that each sample in set {M} is selected according to a certain criterion (e.g., a +1σ point for a specific evaluation metric mi), but all evaluation metrics for that sample are used to fit the corresponding model parameter Y. The number of evaluation metrics should be large enough to enable good model fit performance. If many different model parameters {Y} can be found that fit the measured evaluation metric {M}, the number of evaluation metrics may be too small to adequately constrain the solution {Y}. For example, in the Mystic tool, the user may change the DoE patterning (pseudo-RNG seed). If different seeds produce the same solution (equivalent .modelcard), this is an indication that the evaluation metrics are sufficiently diverse.
[0030] In this example, the model is a SPICE model, e.g., BSIM4 or BSIM-CMG from the BSIM group for CMOS devices, or a Josephson junction model for superconducting electronics. Examples of model parameters yj for a Josephson junction device include critical current (xj), normal resistance (icrn), subgap resistance (vm), Josephson junction capacitance (xc), gap voltage (vgap), gap width (delv), series inductance (lser), and shunt resistor (xr, lsh0, lsh1 - lsh = kinetic inductance of the resistor, i.e., the Drude model of electrons due to electron mass / momentum / kinetic energy).
[0031] Figure 5 shows an excerpt from the table of model parameters {Y}. In this example, the parameters yj include icrn, vm, lsh0, lsh1, etc., as indicated by the labels in each column. The first row of the table is the mean value for each parameter. Each of the other rows represents a different sample, and the value in the cell is the variation from the mean. Figure 5 is a table of the variation {ΔY} of the model parameters. This is the result of steps 220 and 230 in Figure 2A.
[0032] Step 240 of Figure 2A, principal component analysis, is applied to the set of variations {ΔY}. Figure 6 shows a summary screen of this analysis. The graph in the upper left lists the intensity (eigenvalue) of each principal component (eigenvector) in descending order. The strongest principal component p1 has an eigenvalue of 1.30, component p2 has an intensity of 1.12, component p3 has an intensity of 1.08, and so on. The curve shows the percentage of the system "encapsulated" by each of the PCA terms. The curve is cumulative as a function of the PCA terms. The other two plots in Figure 6 show the correlation between component p1 and component p2.
[0033] Not all principal components need to be used. The K strongest components may be used as the basis for fitting the nonlinear model, and the remaining principal components may be discarded. For example, principal components with eigenvalues greater than 0.1 (or some other threshold) may be retained. PCA is a method that takes an original set of n variables that are likely to be related to each other, and replaces them with m uncorrelated variables ("in the alternative eigenspace") as a linear combination of the original variables, so that the majority of the variability can be explained using only a few principal components. Typically, an eigenvalue of 1.0 is used as the cutoff, but here a lower cutoff of 0.1 is used in this case to capture not only the major effects but also the Nth-order effects, as well as the nonlinear relationships. Other predetermined minimum number of principal components or criteria for selecting principal components may be used.
[0034] In the final step 250 of Figure 2A, the model parameter Y is fitted to the nonlinear model as a function of the principal component P. Other variables, such as device geometry, may also be used in addition to the principal component P. For example, icrn may be expressed as a function of the principal component and may also be the diameter of the Josephson junction. Figure 7 shows two examples. The upper equation is the model parameter icrn as a function of the principal components pca1, pca2, and pca7. This equation is a quadratic equation using the seven strongest principal components. In this equation, icrn_mean is the mean, and the remaining terms are the variation Δicrn, expressed as a quadratic polynomial function of the principal components. The lower equation is for the model parameter vm, which takes a similar form. The principal components may be modeled as Gaussian distributions with mean = 0 and standard deviation = 1. These statistical variability can then be propagated through the nonlinear model and simulation, as shown in Figure 2B, thereby generating the simulated result distribution.
[0035] Figures 8A and 8B show a comparison of measured and simulated evaluation metrics, respectively. In each figure, the 5x5 grids 810A and 810B, named “Scatter Plot Matrix,” show the bivariate distributions of the five evaluation metrics icrit, rnorm, vgap, rsg, and rsg2. The second boxes in the first row, 812A and 812B, show the bivariate distributions of icrit and rnorm, the third boxes in the first row, 813A and 813B, show the bivariate distributions of icrit and vgap, and so on. Tables 820A and 820B, named “Correlation” at the top, show the correlations between pairs of evaluation metrics. Figure 8A is the original measured evaluation metric. Figure 8B is the simulated bivariate distribution using the flow in Figure 2B. The simulated bivariate distribution fits well to the actual physical measurements.
[0036] The measured physical devices may also appear in the simulated netlist. The probes and measurement configurations used to measure the evaluation metrics in the fab may be simulated using the process variability taken into account by the simulated evaluation metrics described above.
[0037] Example of a CMOS device Figures 9 to 14 show an example for CMOS devices. For these types of devices, the measured evaluation metrics can be based on IV curves, process control monitors, wafer acceptance tests, and various circuit evaluation metrics. For NMOS and PMOS devices, evaluation metrics may include IdSat - drain current saturation region, IdLin - drain current linear region, VtSat - threshold voltage saturation region, VtLin - threshold voltage linear region, Id_subVt - drain leakage current subthreshold voltage region, Igate - gate leakage current, gm(dIds / dVgs) - transconductance, gds(dIds / dVds) - output conductance, gmb(dIds / dVbs) - bulk transconductance, gain(gm / gds) - intrinsic gain, gm_eff(gm / Ids) - transconductor efficiency, ft(gm / Cgs) - transition frequency, Cgate - intrinsic gate capacitance, Cd / s - drain / source capacitance, Cj - diffusion capacitance, and Cov(Miller good / bad) - overlap capacitance. For ring oscillators, example evaluation metrics include ring oscillators of various sizes: FO1, FO4, FO8, FO16, and FO32. FO16 is a ring oscillator with a fan-out of 16. For static noise margin, exemplary evaluation metrics include static complementary gates. These evaluation metrics can be repeated for devices of different sizes and layout configurations. In this example, 10 different evaluation metrics were considered, and approximately 100 samples were selected from a total of 10,000 available samples.
[0038] Figures 9A, 9B, and 10 illustrate selection step 210 of Figure 2A. Figures 9A and 9B show histograms of the sample distribution for the evaluation index n_sat0. From these distributions, samples representing the upper and lower process limits (USL and LSL) are selected in Figure 9A, and samples representing different displacement values are selected in Figure 9B. Figure 10 shows the bivariate distributions for the two evaluation indices n_sat0 and p_sat0. Additional samples, namely dies 295, 411, 2649, and 9607, are selected based on this distribution.
[0039] In step 220 of Figure 2A, the model parameter {Y} is extracted corresponding to the sample {M}. In this example, the model is a SPICE model. Figure 11 shows the model parameters extracted for the average die, as well as for the samples corresponding to the +3σ displacement value for the evaluation index IdSat and the -3σ displacement value for the evaluation index IdSat. The average die may be a single actual sample. One method calculates the average value for each evaluation index, and the die closest to those average values is the average die. Alternatively, the average die may not be an actual sample. It may be a composite sample calculated from several different samples.
[0040] In this example, the model parameters include the following n-type parameters: ncf - fringing field capacitance, ncgdo - drain-gate overlap capacitance, ncgso - source-gate overlap capacitance, ndlc - CV length offset, ndwc - CV width offset, ndwj - S / D junction width offset, nk1 - first body bias coefficient, nk2 - second body bias coefficient, nlint - channel length offset, nndep - channel dopant concentration, ntoxe - electrical gate equivalent oxide film thickness, ntoxm - gate equivalent oxide film thickness of extracted parameters, nvth0 - long channel threshold voltage @ VBS=0, nwint - channel width offset, and the corresponding p-type parameters.
[0041] Figures 12A and 12B show the correction of the extraction process. Due to the ambiguity of the model, the extraction process results in a non-monotonic trend of the model parameters for samples progressing from -3σ to +3σ. Figure 12A plots the extracted parameter nvth0 for selected samples for the displacement values from -3σ to +3σ for n_sat0. The extraction of sample 1210 does not match the other samples, and therefore the extraction is rerun, but constrained nvth0, resulting in a more matched point 1211 shown in Figure 12B.
[0042] Steps 230-250 in Figure 2A are performed as described above. Figure 13 shows an exemplary nonlinear curve fitted for the model parameter vth0 as a function of the principal components pca1, pca2, ... pca8. This formula is a quadratic formula using the eight strongest principal components. The first term is the mean, the next eight terms are linear terms for each component, and the remaining terms are quadratic terms for the product of two components. Figures 14A and 14B show a comparison of the original measured evaluation metric in Figure 14A and the simulated evaluation metric in Figure 14B.
[0043] Additional considerations The quality of results from this method depends on the number of samples in the sample set {M} and the diversity of the sample set. The minimum number of samples N required to fit a system with degrees of freedom (DoF) to a polynomial of degree (O) is: N=(DoF+O)! / (DoF! * O!) (1) It is given by . In the example above, DoF is the number of principal components and O is the degree of the nonlinear polynomial. Equation (1) assumes that the number of samples is a good representation of the underlying system. In many physical systems, the principal components of the physical system can be described by about 7 degrees of freedom (DoF=7). For semiconductor devices, degrees of freedom in the manufacturing process may include oxide thickness, dopant concentration, limiting dimension (CD) linewidth control, flatband voltage, drain-source resistance, etc. At least a quadratic polynomial (O=2) is required to model higher-order effects. This results in N=36, and the more, the better, generally. Selecting a sample set {M} having at least twice this number of samples (72) or even more (e.g., greater than 100) can help mitigate some of the randomness of errors in the data. In addition, it is preferable that the samples be selected from at least 5 candidate samples (i.e., the +3σ sample is selected from at least 5 samples around the +3σ displacement value). The probability of a single sample exhibiting the 3σ state is approximately 1 / 740. To obtain five candidates for each of the two samples, we need 5 × 2 × 740 = 7400 available samples to choose from. From the original 7400 samples, a set of 72 samples is selected.
[0044] In another embodiment, assuming that I is the number of evaluation indices measured, the number of samples N required to obtain a good estimate of the principal components is: N=DoF * I (2) The number is given by, or more than twice this number.
[0045] In some cases, principal components can also be related to physical parameters. Figure 15 contains a grid of bivariate distributions. Each row in Figure 15 represents a physical parameter P1-P8, and each column represents one of the eight strongest principal components pca1-pca8. Each box in the 8x8 grid shows the bivariate distribution of each physical parameter for each principal component. If the distribution is a circular cloud, the two quantities are not very correlated. If the distribution is a straight line, the two quantities are correlated. It can be seen that the first eight principal components are well correlated with respect to the physical parameters.
[0046] The above principles are explained using superconducting and semiconductor devices as examples. However, they can also be applied to other devices. This technique is not limited to electronics, but can be applied to any manufacturing process with variations that also include mechanical, structural, chemical, nuclear, optical, pharmaceutical, biological, and other systems.
[0047] EDA flow Figure 16 shows an exemplary set of processes 1600 used during the design, verification, and manufacture of products such as integrated circuits to translate and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and made available as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the generation of a product idea 1610 using information provided by the designer, which is then translated to produce a product using a set of EDA processes 1612. When the design is complete, the design is tapeped out 1634, when the artwork (e.g., geometric patterns) for the integrated circuit is sent to a manufacturing facility to produce a mask set, which is then used to manufacture the integrated circuit. After tape-out, superconducting or semiconductor dies are manufactured 1636, and packaging and assembly processes 1638 are performed to produce the completed integrated circuit 1640.
[0048] Specifications for a circuit or electronic structure can range from low-level transistor or Josephson junction material layouts to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ("HDL") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be converted to logic-level register transfer-level ("RTL") descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower-level description, being a more detailed description, adds more useful details to the design description, such as further details about the module containing the description. These lower-level descriptions, being more detailed, can be generated by a computer, retrieved from a design library, or generated by another design automation process. An example of a specification language in a lower-level language specifying a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The descriptions at each level are made available for use by the corresponding tools at the layer (e.g., formal verification tools). The design process can use the sequence shown in Figure 16. The described process can be made available by an EDA product (or tool).
[0049] In system design 1614, the functionality of the integrated circuit to be manufactured is defined. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or code lines), and cost reduction. Dividing the design into different types of modules or components may be done at this stage.
[0050] During logic design and functional verification, modules or components in a circuit are specified in one or more descriptive languages, and the specifications are checked for functional accuracy. For example, components of a circuit may be verified to produce outputs that meet the specifications of the circuit or system being designed. Functional verification can be performed using simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components called an "emulator" or "prototyping system" is used to speed up functional verification.
[0051] During synthesis and design for testing (1618), the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, where the edges of the graph structure represent the components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical products that can be used by EDA products to verify that the integrated circuit performs according to a specific design during manufacturing. The netlist can be optimized for the target semiconductor manufacturing technology. Furthermore, the finished integrated circuit can be tested to verify that the integrated circuit satisfies the requirements of the specification.
[0052] During netlist verification 1620, the netlist is checked for compliance with timing constraints and correspondence with the HDL code. During design planning 1622, an overall floor plan for the integrated circuit is constructed and timing and top-level routing are analyzed.
[0053] During layout or physical implementation 1624, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components with multiple wires) may be performed, and cells may be selected from a library to enable specific logical functions. As used herein, the term 'cell' can refer to a set of transistors, other components, and interconnects that give Boolean logic functions (e.g., AND, OR, NOT, XOR) or memory functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components, and both are made available as physical structures and in simulation. Parameters such as size are specified for selected cells (based on 'standard cells') and made accessible in a database for use by EDA products.
[0054] During analysis and extraction 1626, circuit functionality is verified at the layout level, thereby enabling refinement of the layout design. During physical verification 1628, the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, and lithography constraints are correct, and that the circuit functionality conforms to the HDL design specifications. During resolution enhancement 1630, the layout geometry is transformed to improve how the circuit design is manufactured.
[0055] During tape-out, the data is generated to be used for the production of lithography masks (after lithography enhancements are applied, if necessary). During mask data preparation 1632, the 'tape-out' data is used to produce lithography masks, which are then used to produce the finished integrated circuits.
[0056] The storage subsystem of the computer system (such as the computer system 1700 in Figure 17) may be used to store programs and data structures used by some or all of the EDA products described herein, as well as products used for the development of cells for libraries and for the physical and logical designs that use these libraries.
[0057] Figure 17 shows an exemplary machine of computer system 1700 in which a set of instructions capable of executing one or more of the methodologies described herein can be performed. In alternative implementations, the machine may be connected to (e.g., network-connected) other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine within the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.
[0058] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify the actions to be taken by that machine. Furthermore, although a single machine is shown, the term “machine” may also be interpreted to include any group of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methodologies described herein.
[0059] An exemplary computer system 1700 includes a processing device 1702, main memory 1704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1706 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage devices 1718, which communicate with each other via a bus 1730.
[0060] The processing device 1702 represents one or more processors, such as a microprocessor or a central processing unit. More specifically, the processing device may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1702 may also be one or more purpose-specific processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. The processing device 1702 may be configured to execute instruction 1726, which performs the operations and steps described herein.
[0061] The computer system 1700 may further include a network interface device 1708 that communicates via a network 1720. The computer system 1700 may also include a video display unit 1710 (e.g., a liquid crystal display (LCD) or cathode ray tube (CRT)), a character / number input device 1712 (e.g., a keyboard), a cursor control device 1714 (e.g., a mouse), a graphics processing unit 1722, a signal generation device 1716 (e.g., a speaker), a graphics processing unit 1722, a video processing unit 1728, and an audio processing unit 1732.
[0062] The data storage device 1718 may include a machine-readable storage medium 1724 (also called a non-temporary computer-readable medium) in which one or more instruction sets 1726 or software that embody any one or more methodologies or functions described herein are stored. The instructions 1726 may reside entirely or at least partially in the main memory 1704 and / or in the processing device 1702 during their execution by the computer system 1700, the main memory 1704 and the processing device 1702 also constitute the machine-readable storage medium.
[0063] In some implementations, Instruction 1726 includes an instruction to perform a function corresponding to the present disclosure. Although the machine-readable storage medium 1724 is shown in exemplary implementations to be a single medium, the term “machine-readable storage medium” should be understood to include a single or multiple mediums that store one or more instruction sets (e.g., a centralized or distributed database, and / or associated caches and servers). The term “machine-readable storage medium” should also be understood to include any medium that can store or encode instruction sets for machine execution and cause a machine and processing device 1702 to perform one or more of the methodologies of the present disclosure. Accordingly, the term “machine-readable storage medium” should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.
[0064] Some parts of the detailed description above are presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. These descriptions and representations of algorithms are the methods used by those skilled in data processing to most efficiently convey the content of their research to others skilled in the art. An algorithm can be a sequence of operations that produce a desired result. Operations require the physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, synthesized, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, digits, and so on.
[0065] However, it should be noted that all these and similar terms should be in relation to appropriate physical quantities and are merely convenient labels applied to those quantities. As will be apparent from this disclosure, unless otherwise specifically stated, throughout this description certain terms will be understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, represented as physical (electronic) quantities in the registers and memory of a computer system, to other data, similarly represented as physical quantities in the memory or registers or other such information storage devices of a computer system.
[0066] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for the intended purpose, or it may include a computer that is selectively started or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, for example, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each connected to a computer system bus, for example.
[0067] The algorithms and representations presented herein are not substantially related to any particular computer or other device. Various other systems may be used with the program in accordance with the teachings herein, or it may prove that they are convenient for constructing more specialized devices to perform this method. Furthermore, this disclosure does not describe any particular programming language. It will be understood that various programming languages may be used to carry out the teachings of this disclosure as described herein.
[0068] This disclosure may be provided as a computer program product or software which may include a machine-readable medium storing instructions thereon that can be used to program a computer system (or other electronic device) to perform the processes described herein. The machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer) storage media such as read-only memory ("ROM"), random-access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.
[0069] In the aforementioned disclosures, the implementation of the disclosure has been described with reference to specific exemplary implementations of the disclosure. It will be apparent that various modifications may be made therewith without departing from the broader intent and scope of the implementation of the disclosure as described in the following claims. Where the disclosure refers to several elements in the singular, two or more elements may be shown in the figures, and similar elements are labeled with similar reference numerals. Thus, the disclosure and drawings should be considered illustrative, not restrictive.
Claims
1. A step of selecting a set of samples from a larger number of samples, including evaluation metrics measured on a physical device which is a semiconductor device or a superconducting device, wherein the measured evaluation metrics represent the electrical properties of the physical device which vary as a result of process variability in the manufacture of the physical device, and the step of selecting the set of samples is based on the distribution of the measured evaluation metrics, A step of setting parameters for a set of model instances of a SPICE model of the physical device corresponding to the set of samples, wherein the parameters are parameters of the physical device used in the SPICE model, the SPICE model predicts one or more outputs as a function of one or more inputs, the outputs include the evaluation metric, and the parameters are set so that a simulation of the set of model instances of the SPICE model using the parameters predicts as an output an evaluation metric that matches the measured evaluation metric from the set of samples; A step of calculating the principal components of the variation of the aforementioned parameter, The process involves a processor fitting the nonlinear model as a function of the principal components to the variation of the parameters, The steps include applying the statistical variability of the principal components to the nonlinear model so as to introduce statistical variability to the parameters, The steps include: applying statistical variability to the parameters to result in statistical variability in the properties of the simulated device, in order to account for process variability in the manufacturing of the physical device; Methods that include...
2. The method according to claim 1, wherein the step of selecting the set of samples includes selecting the samples based on the process limits of the distribution of the individual measured evaluation metrics.
3. The method according to claim 1, wherein the step of selecting the set of samples includes selecting the samples based on the displacement values of the distribution of the individual measured evaluation indices.
4. The method according to claim 1, wherein the step of selecting the set of samples includes selecting the samples based on the displacement values of the bivariate distribution of individual measured evaluation index pairs.
5. The method according to claim 1, wherein the step of fitting the nonlinear model to the variation of the parameters includes fitting the nonlinear model to the variation of the parameters as a basis function that includes only principal components having eigenvalues above a threshold.
6. The method according to claim 1, wherein the applicable statistical variability of the principal component is a Gaussian distribution.
7. The method according to claim 1, wherein the selected set comprises N samples, N ≥ 2 × DoF × I, where DoF = degrees of freedom of the parameter due to process variability, and I = number of measured evaluation indices.
8. The method according to claim 1, wherein the selected set comprises N samples, N ≥ 2 × (DoF + O)! / (DoF! * O!), where DoF = degrees of freedom of the parameter due to process variability, and O = order of the nonlinear model.
9. It is a system, Memory for storing instructions, The system comprises a processor coupled to the memory and executing the instruction, and when the instruction is executed, the processor, Selecting a set of samples from a larger sample size, including evaluation metrics measured on a physical device which is a semiconductor device or a superconducting device, wherein the measured evaluation metrics represent the electrical properties of the physical device which vary as a result of process variability in the manufacturing of the physical device, and selecting the set of samples is equivalent to selecting a set of samples based on the distribution of the measured evaluation metrics. Setting parameters for a set of model instances of a SPICE model of the physical device corresponding to the set of samples, wherein the parameters are parameters of the physical device used in the SPICE model, the SPICE model predicts one or more outputs as a function of one or more inputs, the outputs include the evaluation metric, and the parameters are set such that a simulation of the set of model instances of the SPICE model using the parameters predicts as an output an evaluation metric that matches the measured evaluation metric from the set of samples. To calculate the principal components of the variation in the aforementioned parameters, The nonlinear model is fitted to the variation of the parameters as a function of the principal components, Applying the statistical variability of the principal components to the nonlinear model so as to introduce statistical variability to the parameters, In order to account for process variability in the manufacturing of the physical device, statistical variability of the parameters is applied to result in statistical variability of the simulated device properties. A system that executes an action.
10. The system according to claim 9, wherein the nonlinear model is also a function of the geometry of the device.
11. The system according to claim 9, wherein a larger number of samples are measured on physical devices on multiple different dies, the dies being from multiple different wafers, but all wafers being processed using the same process node.
12. The system according to claim 9, wherein the device is a CMOS device, and the evaluation index includes drain current saturation region, drain current linear region, threshold voltage saturation region, threshold voltage linear region, gate leakage current, transconductance, output conductance, intrinsic gate capacitance, and drain / source capacitance.
13. The system according to claim 9, wherein the device is a superconducting device, and the evaluation index includes critical current, normal resistance, subgap resistance, gap voltage, and gap width.
14. A non-temporary computer-readable medium containing stored instructions, wherein, when the stored instructions are executed by the processor, the processor receives A set of samples is selected from a larger number of samples, including evaluation metrics measured on a physical device which is a semiconductor device or a superconducting device, wherein the measured evaluation metrics represent the electrical properties of the physical device which vary as a result of process variability in the manufacturing of the physical device, and the samples are selected for the set based on the distribution of the measured evaluation metrics. Parameters are set for a set of model instances of the SPICE model of the physical device corresponding to the set of samples, wherein the parameters are parameters of the physical device used in the SPICE model, the SPICE model predicts one or more outputs as a function of one or more inputs, the outputs include the evaluation metric, and the parameters are set so that a simulation of the set of model instances of the SPICE model using the parameters predicts an evaluation metric as an output that matches the measured evaluation metric from the set of samples. The principal components of the variation in the aforementioned parameters are calculated. The nonlinear model is fitted to the variation of the parameters as a function of the principal components. The statistical variability of the principal components is applied to the nonlinear model so as to introduce statistical variability to the parameters. A non-temporary computer-readable medium that applies statistical variability to the parameters to result in statistical variability in the properties of a simulated device, in order to account for process variability in the manufacturing of the physical device.
15. The selected set comprises at least 72 samples, the non-temporary computer-readable medium according to claim 14.
16. The non-temporary computer-readable medium according to claim 14, wherein the samples are selected for the set based on the displacement values of the distribution of the individual measured evaluation indices.
17. The non-temporary computer-readable medium according to claim 14, wherein the samples are selected for the set based on the displacement values of the bivariate distribution of individual measured evaluation index pairs.
18. The non-temporary computer-readable medium according to claim 17, wherein the bivariate distribution is characterized by a major axis and a minor axis, and the samples are selected for the set based on displacement values along the major axis and displacement values along the minor axis.
19. The non-temporary computer-readable medium according to claim 14, wherein the set of samples further comprises a composite sample calculated as the average value of a plurality of samples.