Substrate and method for manufacturing the same

Abstract

To provide a substrate that has entirely uniformly improved adhesive strength and can transmit signals efficiently even when high-frequency power is applied and embodies an electrically conductive layer, and a method for manufacturing the same.SOLUTION: A substrate 100 includes a glass core 10 having an upper surface 11. The upper surface of the glass core has an Rs / z value which is a value of the rate of the degree of asymmetry to the roughness in the following formula 1 and ranges from -5 nm-2 to 50 nm-2. In formula 1, the Rsk value is the degree of asymmetry, and the Rz value is the maximum height roughness (nm in unit). Such a substrate can embody an electrically conductive layer having substantially uniformly improved adhesion force to a glass core. The electrically conductive layer can transmit signals efficiently even when high frequency power is applied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The concrete examples relate to substrates and their manufacturing methods. [Background technology]

[0002] In the manufacturing of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers into a state where they can be used in actual products is called the back-end process (BE), and the packaging process is included in this back-end process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as line widths in the nanoscale (below the micron), cells exceeding 10 million, high-speed operation, and significant heat dissipation, but relatively speaking, the technology to perfectly package these is not yet supported. Therefore, the electrical performance of a semiconductor is sometimes determined more by the packaging technology and the resulting electrical connections than by the performance of the semiconductor technology itself.

[0004] Ceramics or resins are used as materials for packaging substrates. In the case of ceramic substrates, it is not easy to mount high-performance high-frequency semiconductor elements due to their high resistance or dielectric constant. In the case of resin substrates, it is relatively possible to mount high-performance high-frequency semiconductor elements, but there are limitations to the reduction of the wiring pitch.

[0005] Recently, research has been progressing on applying silicon and glass to high-end packaging substrates. By forming through-holes in silicon or glass substrates and applying conductive materials to these holes, the length of wiring between the device and the motherboard can be shortened, resulting in superior electrical characteristics. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-201446 [Patent Document 2] International Patent Application Publication No. 2018 / 221379 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] An object of an embodiment is to provide a substrate capable of embodying an electrically conductive layer that is substantially uniform, has an improved bonding strength, and can efficiently transmit signals even when high-frequency power is applied, and a method for manufacturing the same. [Means for Solving the Problems]

[0008] The substrate according to an embodiment of the present specification includes a glass core having an upper surface. The value of the ratio of the asymmetry with respect to the roughness of the following formula 1 on the upper surface of the glass core is R ,

[0015] The value is -5 nm -2 ~50 nm -2 It is.

[0009] JPEG0007900445000001.jpg1594 '

[0010] In the formula 1, the Rsk value is a value of asymmetry, and the Rz value is the maximum height roughness (unit: nm). <000​​​​​​​​​​​​​​​​​​The standard deviation of the Rz values ​​in each of the aforementioned measurement regions may be 1.5 nm or less.

[0016] The substrate may include an electrically conductive layer disposed on the glass core.

[0017] The electrical conductive layer may include a seed layer and a conductive layer disposed on the seed layer.

[0018] The thickness of the seed layer may be 50 nm to 1500 nm.

[0019] The electrical conductive layer may have a patterned shape.

[0020] The width of the electrical conductive layer may be 1 μm to 5 μm.

[0021] The thickness of the electrical conductive layer may be 1 μm to 5 μm.

[0022] The electrical conductive layer may include a first electrical conductive layer formed in contact with the upper surface of the glass core.

[0023] When observed in cross-section of the first electrical conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first electrical conductive layer and the glass core, may be 5 nm to 200 nm or less.

[0024] The bonding force between the first electrical conductive layer and the glass core, as measured by a 180° peel test, may be 0.2 kgf to 3 kgf.

[0025] The substrate can be used for semiconductor packaging applications.

[0026] A method for manufacturing a substrate according to other embodiments of this specification includes a preparation step of providing a base glass plate and a roughening step of providing a substrate including a glass core formed by roughening the upper surface of the base glass plate.

[0027] The glass core has an upper surface.

[0028] R is the value of the ratio of the asymmetry to the roughness of the upper surface of the glass core, as shown in the following formula 1. s / z Value -5nm -2 ~50nm -2 That is the case.

[0029] JPEG0007900445000002.jpg1594

[0030] In Equation 1 above, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

[0031] The surface roughening step may include a process of plasma treatment of the upper surface of the base glass plate to form a glass core. [Effects of the Invention]

[0032] In the example substrate, an electrically conductive layer with substantially uniformly improved bonding strength to the glass core can be realized. The electrically conductive layer can efficiently transmit signals even when high-frequency power is applied. [Brief explanation of the drawing]

[0033] [Figure 1] This is a plan view illustrating a substrate according to one embodiment of this specification. [Figure 2] This is a plan view illustrating a substrate according to another embodiment of this specification. [Figure 3] This is a plan view illustrating a substrate according to yet another embodiment of this specification. [Figure 4] This is a plan view illustrating a substrate according to yet another embodiment of this specification. [Best Mode for Carrying Out the Invention]

[0034] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. However, the present invention can be realized in a variety of different forms and is not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0035] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0036] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0038] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0039] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0040] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0041] In this specification, the form, relative size, angles, etc., of each component in the drawings are illustrative and may be exaggerated for illustrative purposes, and the rights shall not be construed as being limited to the drawings.

[0042] In this specification, "adjacent to A and B" means that A and B are located touching each other, or that A and B are not touching but are located close to each other. In this specification, the expression "adjacent to A and B" is not construed to mean that A and B are located touching each other unless otherwise specified.

[0043] In this specification, "high frequency" means frequencies between approximately 1 GHz and approximately 300 GHz. Specifically, it may mean frequencies between approximately 1 GHz and approximately 30 GHz, or frequencies between approximately 1 GHz and approximately 15 GHz.

[0044] In this specification, unless otherwise specified, a fine line means a line with a width of 5 μm or less, and more specifically, a line with a width of 1 to 4 μm or less.

[0045] The inventors of the embodiment confirmed that by controlling the surface roughness characteristics of the glass core, the electrical conductive layer has substantially uniformly improved bonding strength to the glass core, and that the electrical conductive layer can efficiently transmit signals by suppressing an excessive increase in the resistance of the electrical conductive layer when high-frequency power is applied, thus completing the embodiment.

[0046] The following provides a detailed explanation of specific examples.

[0047] Figure 1 is a plan view illustrating a substrate according to one embodiment of this specification. The substrate of the embodiment will be described with reference to Figure 1.

[0048] glass core A substrate 100 according to one embodiment of this specification includes a glass core 10 having an upper surface 11.

[0049] The glass core 10 serves as a support on the substrate 100. The glass core 10 is distinguished from a core distribution layer (not shown) or bumps (not shown) disposed above or below the glass core 10.

[0050] In an embodiment, by applying a core made of a glass material, it is possible to suppress the generation of parasitic elements and power loss in the core due to the application of high-frequency power.

[0051] Examples of the material of the glass core 10 include, by way of example, alkali borosilicate, non-alkali borosilicate, non-alkali alkaline earth borosilicate, etc., and any plate glass material applicable to electronic components can be used.

[0052] The thickness of the glass core 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. When applying the glass core 10 having such a thickness, it can have excellent utilization as a core for semiconductor packaging.

[0053] R, which is the value of the ratio of the asperity of the upper surface 11 of the glass core to the roughness of Formula 1 below s / z The value is -5 nm -2 ~50 nm -2 is.

[0054] JPEG0007900445000003.jpg1594

[0055] In Formula 1, the Rsk value is the value of asperity, and the Rz value is the maximum height roughness (unit: nm).

[0056] If the roughness of the upper surface 11 of the glass core is simply increased to improve the bonding strength of the electrical conductive layer formed on the upper surface 11 of the glass core, the height deviation of the metal layer deposited on the upper surface of the core may become excessively large, or the contact area between the upper surface of the core and the electrical conductive layer may decrease. As a result, the electrical conductive layer formed on the upper surface may exhibit an overall uneven bonding strength.

[0057] Furthermore, the electrical conductive layer formed on the upper surface 11 of the glass core having the aforementioned characteristics may exhibit excessively high resistance in environments where high-frequency power is supplied. Specifically, when high-frequency power is applied to the substrate 100 to improve the signal transmission speed and transmission amount, a skin effect may occur in the electrical conductive layer. As a result, current may concentrate and flow on the surface of the electrical conductive layer.

[0058] When an electrical conductive layer is formed on the upper surface 11 of a glass core with excessively high roughness, the cross-sectional profile of the electrical conductive layer may be rough and have an irregular shape. When a high-frequency current flows through an electrical conductive layer with such a shape, the area over which the current can substantially flow within the electrical conductive layer decreases, and the resistance of the electrical conductive layer may become considerably higher. The degree of increase in the resistance of the electrical conductive layer due to the skin effect may become even more pronounced as the electrical conductive layer becomes thinner.

[0059] An example of this is R, which is the value of the ratio of the degree of asymmetry to the roughness of the upper surface 11 of the glass core. s / z The value can be controlled. In such a case, the roughness of the upper surface 11 of the glass core 10 is not excessively increased, and a more stable interlocking structure is formed between the glass core 10 and the electrical conductive layer on the entire upper surface 11 of the glass core, thereby effectively improving the bonding strength of the electrical conductive layer. Along with this, the substrate 100 having the above characteristics can efficiently transmit signals without generating excessive heat, even when high-frequency power is applied.

[0060] R s / zThe value is measured by the following method.

[0061] Three measurement areas (not shown) are arbitrarily selected on the upper surface 11 of the glass core. Each measurement area is 5 μm wide and 5 μm high, and each measurement area is selected so as not to overlap with others.

[0062] In each of the aforementioned measurement areas, the asymmetry value (Rsk) and the maximum height roughness (Rz) are measured in non-contact mode using an atomic force microscope according to the method specified in ISO 4287. For example, the Park Systems XE-100 model atomic force microscope can be used.

[0063] The average value of the Rsk values ​​in each of the aforementioned measurement regions is taken as the Rsk value of the upper surface of the glass core. The average value of the Rz values ​​in each of the aforementioned measurement regions is taken as the Rz value of the upper surface of the glass core.

[0064] From the Rsk and Rz values ​​of the upper surface of the calculated glass core, R in Equation 1 s / z Calculate the value.

[0065] R of the upper surface 11 of the glass core s / z The value is -5nm -2 ~50nm -2 It is possible. The aforementioned R s / z The value is -3nm -2 The above is also acceptable. s / z The value is 0nm -2 The above is also acceptable. s / z The value is 5nm -2 The above is also acceptable. s / z The value is 45nm -2 The following is also acceptable: R s / z The value is 40nm -2 The following is also acceptable: R s / z The value is 30nm -2 The following is also acceptable: R s / z The value is 20nm -2 The following is also acceptable: R s / z The value is 15nm-2 The following is also possible. In this case, when forming a finely wired electrical conductive layer on the glass core 10, the bonding force of the electrical conductive layer to the glass core 10 can be substantially uniformly improved over the entire upper surface 11 of the glass core, and the resistance of the electrical conductive layer can be suppressed from becoming excessively high when high-frequency power is applied.

[0066] In a surface profile, peaks are portions located higher than the baseline (average height of the surface profile), and valleys are portions located lower than the baseline. In the embodiment, the asymmetry Rsk value of the upper surface 11 of the glass core can be adjusted to a range predetermined in the embodiment, thereby controlling the shape and height distribution of peaks and valleys distributed on the upper surface 11 of the glass core. When the glass core 10 has the above characteristics, it is possible to prevent the peaks and valleys from being formed relatively narrow and sharp in the profile of the upper surface 11 of the glass core. Through this, the surface area in contact between the upper surface 11 of the glass core and the metal layer deposited on the upper surface 11 is appropriately adjusted, allowing the metal layer to have a stable bonding force. In addition, a metal layer with an even more uniform height distribution can be formed on the upper surface 11 of the glass core.

[0067] The Rsk value of the upper surface 11 of the glass core may be -0.5 to 1.8. The Rsk value may be -0.2 or higher. The Rsk value may be 0 or higher. The Rsk value may be 0.2 or higher. The Rsk value may be 1.5 or lower. The Rsk value may be 1.2 or lower. The Rsk value may be 1.0 or lower. The Rsk value may be 0.8 or lower. The Rsk value may be 0.6 or lower. In such cases, in particular, by adjusting the shape of the lower surface of the electrical conductive layer in contact with the upper surface of the glass core, smooth signal transmission is possible even if the skin effect occurs in the electrical conductive layer.

[0068] The Rz value of the upper surface 11 of the glass core may be 4 nm to 30 nm. The Rz value may be 5 nm or more. The Rz value may be 20 nm or less. The Rz value may be 10 nm or less. In this case, the peel resistance of the electrical conductive layer to the surface of the glass core 10 can be stably adjusted. At the same time, even when high-frequency power is applied to the electrical conductive layer, it is possible to prevent the resistance characteristics of the electrical conductive layer from becoming excessively high.

[0069] The embodiment can help ensure that the bonding force and resistance characteristics of the electrical conductive layer formed on the glass core 10 are uniform across the entire upper surface 11 of the glass core by controlling the deviations in the roughness characteristics of multiple different regions.

[0070] The standard deviation of the Rsk values ​​in each of the aforementioned measurement regions may be 0.5 or less.

[0071] The standard deviation of the Rz values ​​in each of the aforementioned measurement regions may be 1.5 nm or less.

[0072] The aforementioned standard deviation is the sample standard deviation.

[0073] The standard deviation of the Rsk value in each measurement area may be 0.5 or less. The standard deviation may be 0.4 or less. The standard deviation may be 0.3 or less. The standard deviation may be 0.2 or less. The standard deviation may be 0.001 or more.

[0074] The standard deviation of the Rz value in each measurement area may be 1.5 nm or less. The standard deviation may be 1 nm or less. The standard deviation may be 0.5 nm or less. The standard deviation may be 0.3 nm or less. The standard deviation may be 0.15 nm or less. The standard deviation may be 0.08 nm or less. The standard deviation may be 0.001 nm or more.

[0075] In such cases, a uniform roughness characteristic can be formed on the upper surface 11 of the glass core.

[0076] The lower surface of the glass core can have the same roughness characteristics as the upper surface 11 of the glass core described above. In such a case, an electrically conductive layer with uniformly improved bonding strength can be formed on the lower surface of the glass core, and this electrically conductive layer can efficiently transmit signals by applying high-frequency power.

[0077] The explanation of the roughness characteristics of the underside of the glass core will be omitted as it will overlap with what was previously described.

[0078] Core distribution layer Figure 2 is a plan view illustrating a substrate according to another embodiment of this specification. The substrate of the embodiment will be described with reference to Figure 2.

[0079] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described in Figure 1 above. The differences will be explained below.

[0080] The substrate in this embodiment may include an electrically conductive layer 20 disposed on a glass core. The electrically conductive layer 20 may have a patterned shape. The electrically conductive layer 20 may be formed above and / or below the glass core 10 and may function to transmit signals.

[0081] The width of the electrical conductive layer 20 may be 1 μm to 5 μm. The width may be 4.5 μm or less. The width may be 4 μm or less.

[0082] The thickness of the electrical conductive layer 20 may be 1 μm to 5 μm. The thickness may be 4.5 μm or less. The thickness may be 4 μm or less.

[0083] In such cases, a high-density pattern of the conductive layer 20 can be realized on the substrate 100, which can help enable the conductive layer 20 to have stable resistance characteristics at high-frequency currents.

[0084] Figure 3 is a plan view illustrating a substrate according to yet another embodiment of this specification. The substrate of the embodiment will be described with reference to Figure 3.

[0085] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described in Figures 1 and 2 above. The differences will be explained below.

[0086] The electrical conductive layer 20 may include a seed layer 21 and a conductive layer 22 disposed on the seed layer 21.

[0087] The seed layer 21 can exhibit a bonding force of a certain level or higher to the surface to be bonded (particularly the upper surface 11 of the glass core). The conductive layer 22 can be stably bonded to the surface of the glass core 10 via the seed layer 21.

[0088] The seed layer 21 may contain elements different from the metal elements applied to the conduction layer. The seed layer 21 may contain both the metal elements applied to the conduction layer and metal elements different from those elements. The seed layer 21 may include a first seed layer (not shown) containing elements different from the metal elements applied to the conduction layer, and a second seed layer (not shown) disposed on the first seed layer and containing the same elements as the metal elements applied to the conduction layer. Exemplarily, the first seed layer may contain materials such as titanium, chromium, and nickel, and the second seed layer may contain materials such as copper, nickel, aluminum, gold, or silver.

[0089] At least a portion of the seed layer 21 may be formed through a sputtering process. The seed layer 21 may help facilitate the formation of the conductive layer 22 on the glass core 10.

[0090] In practice, by adjusting the thickness of the seed layer 21, a structure can be formed in which the upper surface 11 of the glass core with controlled roughness characteristics and the seed layer 21 interlock stably.

[0091] The thickness of the seed layer 21 may be 50 nm to 1500 nm. The thickness may be 80 nm or more. The thickness may be 100 nm or more. The thickness may be 150 nm or more. The thickness may be 200 nm or more. The thickness may be 250 nm or more. The thickness may be 300 nm or more. The thickness may be 1200 nm or less. The thickness may be 1000 nm or less.

[0092] In such cases, the seed layer 21 can help ensure that the electrical conductive layer 20 has excellent bonding strength, and the electrical conductive layer 20 can be formed efficiently.

[0093] The conductive layer 22 may be formed on the seed layer 21 through a plating process. An electrically conductive material may be used as the material for the conductive layer 22. Exemplarily, the conductive layer 22 may include at least one of copper, nickel, aluminum, gold, and silver.

[0094] Figure 4 is a plan view illustrating a substrate according to yet another embodiment of this specification. The substrate of the embodiment will be described with reference to Figure 4.

[0095] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described in Figures 1 to 3 above. The differences will be explained below.

[0096] The substrate 100 may include a core distribution layer 50 disposed on the glass core 10. The core distribution layer 50 may include an electrical conductive layer 20 and an insulating layer 30 surrounding at least a portion of the electrical conductive layer 20.

[0097] In the core distribution layer 50, the insulating layer 30 and the electrically conductive layer 20 may be arranged in a mixed manner. The core distribution layer 50 may be formed in a manner in which the electrically conductive layer 20, having a predetermined position and shape, is embedded within the insulating layer 30. The electrically conductive layer 20 may be formed as fine wires in at least a portion of the core distribution layer 50.

[0098] The core distribution layer 50 can be formed by a process of repeatedly forming and removing the insulating layer 30 and the electrically conductive layer 20.

[0099] The insulating layer 30 can be any material that can be applied as an insulating layer to semiconductor elements or packaging substrates. For example, the insulating layer 30 may be an epoxy resin containing a filler. The insulating layer 30 may, but is not limited to, being formed through a build-up layer material such as Ajinomoto's ABF (Ajinomoto Build-up Film) or an undercoat material.

[0100] The insulating layer 30 can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0101] The electrical conductive layer 20 may include a first electrical conductive layer 25 positioned in contact with the surface of the glass core 10. The electrical conductive layer 20 may also include a second electrical conductive layer 26 that is not in contact with the surface of the glass core 10.

[0102] When observed in cross-section of the first electrical conductive layer 25, the Rz value, which is the maximum height roughness of the interface L formed between the first electrical conductive layer and the glass core, may be 5 nm to 200 nm.

[0103] In this embodiment, the roughness characteristics of the interface L formed between the first electrical conductive layer and the glass core can be controlled. Through this, the resistance and heat generation characteristics of the first electrical conductive layer 25 due to the skin effect can be stably controlled, and the bonding force of the first electrical conductive layer 25 to the glass core 10 can be further improved by the anchoring effect.

[0104] The Rz value of the interface L is measured by the following method.

[0105] A cross-section of the first conductive layer 25 is imaged using a TEM (Transmission Electron Microscope). The cross-section of the first conductive layer 25 refers to a cross-section perpendicular to the upper surface 11 of the glass core. If the first conductive layer 25 has a pattern shape, the cross-section of the first conductive layer 25 refers to a cross-section perpendicular to the upper surface 11 of the glass core and perpendicular to the longitudinal direction of the first conductive layer 25. After tracing the profile of the interface L formed between the first conductive layer and the glass core from the cross-sectional image of the first conductive layer 25, the Rz value, which is the maximum height roughness of the interface L, is calculated from the traced profile.

[0106] The Rz value is measured according to the method specified in ISO 4287. Specifically, the Rz value is the sum of the height of the highest peak and the depth of the deepest valley in the traced profile of the interface L.

[0107] The Rz value of the interface L formed between the first electrical conductive layer and the glass core may be 200 nm or less. The Rz value may be 180 nm or less. The Rz value may be 150 nm or less. The Rz value may be 100 nm or less. The Rz value may be 5 nm or more. The Rz value may be 10 nm or more. In such cases, a first electrical conductive layer 25 having excellent peel resistance and suitable for applying high-frequency power can be realized on the surface of the glass core 10.

[0108] One concrete example is that by controlling the bonding force of the first electrical conductive layer 25 to the surface of the glass core to a certain level or higher, it is possible to prevent the peeling of the first electrical conductive layer 25 during the manufacturing and processing of the substrate.

[0109] The bonding strength between the first electrical conductive layer 25 and the glass core 10, as measured by a 180° peel test, is measured using a bond tester. The measurement speed (peel speed) is set to 10 mm / s, and the measurement distance (peel distance) is set to 70 mm. For example, the bonding strength can be measured using a Condor Sigma bond tester from XYZ TEC.

[0110] The bonding force between the first electrical conductive layer 25 and the glass core 10, as measured by a 180° peel test, may be 0.2 kgf or more. The bonding force may be 0.3 kgf or more. The bonding force may be 0.4 kgf or more. The bonding force may be 3 kgf or less. In such cases, it may be helpful in ensuring that the electrical conductive layer 20 is stably bonded to the surface of the glass core 10 during the manufacturing and processing of the substrate.

[0111] Other components within the packaging substrate The glass core 10 may include core vias (not shown) that penetrate the glass core 10 in the thickness direction. The core distribution layer 50 may be formed on the upper surface 11 of the glass core and within the core vias. The core distribution layer 50 may be formed on the upper surface 11 of the glass core, below the lower surface 12 of the glass core, and within the core vias. In such a case, the core distribution layer 50 can connect the upper surface 11 and the lower surface 12 of the glass core over a very short distance. Furthermore, electrical signals can be transmitted more quickly between elements located on the upper part of the substrate 100 and the motherboard located on the lower part of the substrate 100, thereby suppressing the occurrence of signal loss.

[0112] A core via may include an internal space and sides surrounding the internal space. In a core via, an electrical conductive layer may be formed in contact with the sides of the core via. The electrical conductive layer may be formed by filling the internal space of the core via.

[0113] Core vias can be formed by processing a predetermined area within the glass core 10. Specifically, they may be formed by etching the glass core 10 by physical and / or chemical methods. Exemplaryly, as a method for forming core vias, methods such as forming defects on the surface of the glass core 10 with a laser or the like, followed by chemical etching, or laser etching may be applied.

[0114] A cavity region (not shown) in which an element is housed may be provided in the glass core 10. The cavity region may include a housing portion, which is a space formed by recessing a part of the glass core 10. The housing portion may be formed by penetrating the glass core 10 vertically. The housing portion may be formed by recessing a part of the upper or lower part of the glass core 10.

[0115] Elements can be placed in the housing. These elements may include not only semiconductor elements such as CPUs, GPUs, and memory chips, but also capacitor elements, transistor elements, impedance elements, and other modules. In other words, any semiconductor element that can be mounted on a semiconductor device can be used as such without limitation.

[0116] The substrate 100 may further include an upper layer (not shown) on top of the core distribution layer 50 placed on the glass core 10.

[0117] The upper layer may include an upper distribution layer and an upper connection layer disposed on the upper distribution layer. Elements disposed on the substrate 100 may be electrically connected to the substrate 100 via the upper connection layer.

[0118] The upper distribution layer may include an electrical conductive layer and an insulating layer surrounding at least a portion of the electrical conductive layer. The electrical conductive layer and insulating layer of the upper distribution layer may be made of the same materials as the electrical conductive layer and insulating layer of the core distribution layer, respectively. The upper distribution layer can electrically connect the element and the core distribution layer.

[0119] The substrate 100 may further include a lower layer (not shown) below a core distribution layer (not shown) located on the lower surface 12 side of the glass core.

[0120] The lower layer may include a lower distribution layer and a board connector located beneath the lower distribution layer. A main board located beneath the substrate 100 may be electrically connected to the substrate 100 via the board connector. The core distribution layer may be electrically connected to the main board via the lower layer.

[0121] The lower distribution layer may include an electrical conductive layer and an insulating layer surrounding at least a portion of the electrical conductive layer. The electrical conductive layer and insulating layer of the lower distribution layer may be made of the same materials as the electrical conductive layer and insulating layer of the core distribution layer, respectively.

[0122] The substrate 100 can be used for semiconductor packaging applications. The substrate 100 can be used for mounting semiconductor elements, protecting semiconductors, and providing electrical connections between elements and the main board.

[0123] Semiconductor packages A semiconductor package according to yet another embodiment of this specification includes a substrate 100 and a main board (not shown) electrically connected to the substrate.

[0124] The circuit board 100 can be mounted on a main board and electrically connected to the main board. The main board is not limited as long as it is one that is commonly used in the field of semiconductor equipment.

[0125] The explanation of circuit board 100 will be omitted as it will be redundant with the previous explanation.

[0126] Substrate manufacturing method A further embodiment of the present specification relates to a method for manufacturing a substrate, which includes a preparation step of providing a base glass plate and a roughening step of providing a substrate including a glass core formed by roughening the upper surface of the base glass plate.

[0127] The glass core has an upper surface, and the ratio of the asymmetry of the upper surface of the glass core to the roughness of the following formula 1 is R s / z Value -5nm -2 ~50nm -2 That is the case.

[0128] JPEG0007900445000004.jpg1494

[0129] In Equation 1 above, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

[0130] In the preparation step, the basic glass plate can be processed to create a glass core.

[0131] The base glass plate can be any plate glass material used in electronic components. Examples of base glass plates include alkali borosilicate glass plates, alkali-free borosilicate glass plates, and alkali-free alkaline earth borosilicate glass plates. Commercially available products, such as those manufactured by Corning, Schott, and AGC, may also be used as base glass plates.

[0132] The surface roughening step in the embodiment may include a process of plasma treatment of the upper surface of a base glass plate to form a glass core. The surface roughening step may include a process of plasma treatment of the upper surface of a base glass plate through an inactive gas to form a glass core. Through this, a glass core can be provided having an upper surface whose roughness is not excessively high and whose roughness characteristics are adjusted to have an asymmetry within a range predetermined in the embodiment.

[0133] The inactive gas may be any one selected from the group consisting of helium gas, argon gas, xenon gas, krypton gas, and combinations thereof. Argon gas may also be used as the inactive gas. In such a case, it may be helpful to form a glass core having the desired surface roughness characteristics in the embodiment while suppressing chemical modification of the upper surface of the base glass plate during the roughening step.

[0134] In the surface roughening step, the ambient pressure may be 100 mTorr or less. The ambient pressure may be 80 mTorr or less. The ambient pressure may be 50 mTorr or less. The ambient pressure may be 30 mTorr or less. The ambient pressure may be 1 mTorr or more. In such cases, in the surface roughening step, the ionized inactive gas collides with the surface to be roughened without excessive interference, and the roughness characteristics of the upper surface of the glass core can be easily adjusted.

[0135] In the surface roughening step, the flow rate of the inactive gas introduced may be 100 sccm or more. The flow rate may be 150 sccm or more. The flow rate may be 200 sccm or more. The flow rate may be 1000 sccm or less. In such cases, a sufficient amount of ionized inactive gas can impact the upper surface of the base glass plate at an appropriately controlled speed.

[0136] In the surface roughening step, the source power may be 0.1 kW or more. The source power may be 0.3 kW or more. The source power may be 0.5 kW or more. The source power may be 5 kW or less.

[0137] In the surface roughening step, the bias power may be 0.1 kW or more. The bias power may be 0.3 kW or more. The bias power may be 0.5 kW or more. The bias power may be 1 kW or more. The bias power may be 8 kW or less. The bias power may be 5 kW or less.

[0138] In such cases, adjusting the velocity of the ionized, inactive gas within an appropriate range can be helpful in forming a glass core with the desired surface roughness characteristics in the embodiment.

[0139] The roughening step may be performed for 10 seconds or more. The roughening step may be performed for 15 seconds or more. The roughening step may be performed for 30 seconds or more. The roughening step may be performed for 1000 seconds or less. This may help to form the upper surface of the glass core having roughness and asymmetry within a predetermined range in the embodiment.

[0140] The surface roughening step may be performed not only on the top surface of the base glass plate but also on the bottom surface. The surface roughening step described above can be applied to the bottom surface of the base glass plate.

[0141] Core vias can be formed on the glass core as needed. Specifically, defects can be formed at predetermined locations on the surface of the glass core. Core vias can then be formed by physical or chemical etching of these defects. The explanation of the method for forming core vias will be omitted as it will overlap with the content described above.

[0142] The manufacturing method of the substrate in the embodiment may further include a core distribution layer formation step of forming a core distribution layer on a glass core.

[0143] The explanation of the core distribution layer will be omitted as it will overlap with what was previously explained.

[0144] The core distribution layer formation step may include an electrical conduction layer formation process for forming an electrical conduction layer on a glass core, and an insulating layer formation process for forming an insulating layer surrounding at least a portion of the electrical conduction layer.

[0145] In the electrical conductive layer formation process, by applying the sputtering process conditions predetermined in the example to form a seed layer, it is possible to suppress excessive fluctuations in the roughness characteristics of the glass core's upper surface due to collisions of sputtered particles with the glass core's upper surface. Through this, the seed layer formed by sputtering can form a stable interlocking structure with the glass core's surface across its entire upper surface, thereby contributing to improved bonding strength of the electrical conductive layer. In addition, this can help effectively suppress the increase in resistance of the electrical conductive layer due to the skin effect.

[0146] The seed layer may include a first seed layer containing elements different from the metal elements applied to the conduction layer, and a second seed layer placed on the first seed layer and containing the same elements as the metal elements applied to the conduction layer. For example, the first seed layer may contain materials such as titanium, chromium, and nickel, and the second seed layer may contain materials such as copper, nickel, aluminum, gold, or silver.

[0147] The explanation of the seed layer will be omitted as it will overlap with what was previously mentioned.

[0148] In the sputtering process for forming the seed layer, the ambient pressure may be 0.1 Pa or higher. The pressure may be 0.3 Pa or higher. The pressure may be 5 Pa or lower. In such cases, the seed layer can be formed at an even more improved deposition rate.

[0149] The sputtering power applied to the sputtering process for forming the seed layer may be 10 kW or more. The sputtering power may be 15 kW or more. The sputtering power may be 20 kW or more. The sputtering power may be 100 kW or less. The sputtering power may be 50 kW or less. In such cases, the sputtered particles can collide with the surface of the deposition target with controlled kinetic energy. Through this, the seed layer can be formed more firmly on the glass core, and the surface roughness characteristics of the glass core can be prevented from fluctuating excessively.

[0150] In the sputtering process for forming the seed layer, the initial temperature of the bed, which is the substrate mounting platform, may be 180°C or lower. The temperature may also be 150°C or lower. The temperature may also be 30°C or higher. In such cases, the durability of the seed layer can be further improved by adjusting the migration characteristics of the deposited sputtering particles.

[0151] In the sputtering process for forming the seed layer, an inactive gas may be used as the sputtering gas. The inactive gas may be argon.

[0152] The sputtering process for forming the first seed layer may be performed for 1 minute or more. The sputtering process may be performed for 2 minutes or more. The sputtering process may be performed for 20 minutes or less.

[0153] The sputtering process for forming the second seed layer may be performed for 1 minute or more. The sputtering process may be performed for 2 minutes or more. The sputtering process may be performed for 20 minutes or less.

[0154] In such cases, a seed layer can be formed that has a structure that is stably bonded to the upper surface of the glass core.

[0155] After the formation of the seed layer is complete, portions of the seed layer where the formation of the electrical conductive layer is unnecessary can be removed. The portions of the seed layer where the formation of the electrical conductive layer is necessary and those where it is unnecessary can be subjected to plating activation / deactivation treatments. Examples of plating activation / deactivation treatments include light irradiation using a laser of a specific wavelength, chemical treatment, etc. However, the conductive layer can be formed on the seed layer without applying such treatments.

[0156] The explanation of the structure and materials of the seed layer will be omitted as it will overlap with what was previously described.

[0157] An electrically conductive layer can be formed on a seed layer through a plating process. The explanation of the conductive layer material and other details will be omitted as it will overlap with the previously mentioned content. After forming the conductive layer, it can be etched to have a pre-designed pattern shape.

[0158] After forming an electrically conductive layer, an insulating layer can be placed surrounding at least a portion of the electrically conductive layer to form a core distribution layer. The insulating layer may, for example, be made of an epoxy resin containing a filler. The insulating layer may, for example, be formed through a build-up layer material such as Ajinomoto's ABF (Ajinomoto Build-up Film), an undercoat material, etc., but is not limited thereto.

[0159] The insulating layer can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0160] The core distribution layer formation step may be a step of forming a core distribution layer on the glass core. The core distribution layer formation step may be a step of forming a core distribution layer above and below the glass core. The core distribution layer formation step may be a step of forming a core distribution layer above and below the glass core and on the core vias. The explanation of how to form the core distribution layer below the glass core and on the core vias will be omitted as it will overlap with what has been described above.

[0161] If necessary, the manufacturing method of the substrate of the embodiment may further include the step of forming an upper distribution layer on a core distribution layer disposed on a glass core. The upper distribution layer includes an electrical conductive layer and an insulating layer surrounding at least a portion of the electrical conductive layer.

[0162] The manufacturing method of the substrate in the embodiment may further include the step of forming a lower distribution layer and / or bumps beneath a core distribution layer located beneath a glass core. The lower distribution layer includes an electrical conductive layer and an insulating layer surrounding at least a portion of the electrical conductive layer.

[0163] The conductive and insulating layers applied to the upper and lower distribution layers may be made of the same materials and manufactured using the same methods as those applied to the conductive and insulating layers in the core distribution layer.

[0164] The following describes specific examples in more detail. The following examples are merely illustrative to aid in understanding the present invention, and the scope of the present invention is not limited thereto.

[0165] Manufacturing example: Circuit board manufacturing Example 1: A glass core was prepared by treating the surface of a basic glass plate, which is an alkali-free glass plate from Schott, with argon plasma for 10 to 30 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.8 kW, and a bias power of 0.8 kW were applied.

[0166] Example 2: A glass core was formed by treating the surface of a basic glass plate, which was a soda-lime glass plate from Schott, with argon plasma for 10 to 30 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.5 kW, and a bias power of 0.5 kW were applied.

[0167] Example 3: A glass core was formed by argon plasma treatment of the surface of a base glass plate, which was Corning's SG7.8 glass plate, for 20 to 40 seconds. During argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.5 kW, and a bias power of 0.5 kW were applied.

[0168] Example 4: A glass core was formed by treating the surface of a basic glass plate, which is an alkali-free glass plate from Schott, with argon plasma for 20 to 40 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.0 kW, and a bias power of 1.0 kW were applied.

[0169] Example 5: A glass core was prepared by treating the surface of a basic glass plate, which is an alkali-free glass plate from Schott, with argon plasma for 30 to 50 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.2 kW, and a bias power of 1.5 kW were applied.

[0170] Comparative Example 1: A glass core was formed by argon plasma treatment of the surface of a basic glass plate, which was Corning's SG7.8 glass plate, for 90 to 120 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.2 kW, and a bias power of 2.0 kW were applied.

[0171] Comparative Example 2: A glass core was formed by treating the surface of a basic glass plate, which was an alkali-free glass plate from Schott, with argon plasma for 90 to 120 seconds. During the argon plasma treatment, an atmospheric pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.5 kW, and a bias power of 2.5 kW were applied.

[0172] Evaluation example: Measurement of roughness characteristics Three measurement areas measuring 5 μm horizontally and 5 μm vertically were arbitrarily selected on the upper surface of the glass cores of the examples and comparative examples. These measurement areas were selected so as not to overlap with each other.

[0173] The Rsk and Rz values ​​for each of the aforementioned measurement regions were measured in non-contact mode using a Park Systems XE-100 atomic force microscope in accordance with ISO 4287.

[0174] The average Rsk value of each measurement region was taken as the Rsk value of the top surface of the glass core, and the average Rz value of each measurement region was taken as the Rz value of the top surface of the glass core.

[0175] From the Rsk value and Rz value mentioned above, s / z The value was calculated.

[0176] The measurement and calculation results for each example and comparative example are shown in Tables 1 and 2 below.

[0177] Evaluation example: Measurement of roughness uniformity The standard deviations of the Rsk and Rz values ​​were calculated from the Rsk and Rz values ​​measured in each measurement area on the upper surface of the glass core of the example.

[0178] The calculated values ​​for each example are shown in Table 2 below.

[0179] Evaluation example: Evaluation of bonding strength of electrical conductive layers A seed layer was formed on the upper surface of the glass cores of the examples and comparative examples by sputtering a 300 nm thick titanium layer and a 300 nm thick copper layer on the titanium layer. In the sputtering process for forming the seed layer, the ambient pressure was set to 0.4 Pa, the sputtering power to 30 kW, and the substrate temperature to 120 °C. The titanium layer and the copper layer were deposited by sputtering for 3 minutes each under the above conditions. An electrically conductive layer was formed on the seed layer by a copper plating process to create a conductive layer.

[0180] Subsequently, the bonding strength of the electrical conductive layer to the glass core was measured using a 180° peel test with an XYZ TEC Condor Sigma bond tester.

[0181] The measurement results for each example and comparative example are shown in Table 1 below.

[0182] Evaluation example: Evaluation of whether or not the electrical conductive layer is delaminate. A 300 nm thick titanium layer and a 300 nm thick copper layer were deposited on the upper surface of the glass cores of the examples and comparative examples by sputtering to form a seed layer. A 20 μm thick conductive layer was then formed on the seed layer through a copper plating process to provide an electrical conductive layer.

[0183] Singulation was performed on the glass core on which the electrical conductive layer was formed. Specifically, energy was irradiated through a laser device onto the dicing path on the upper surface of the glass core, and the glass core was cut by applying physical force. After that, grinding was performed on the edges of the cut glass core.

[0184] The cross-section of the singulated glass core was examined using an optical microscope to check for delamination of the electrical conductive layer.

[0185] In each example and comparative example, P was rated if no delamination of the electrical conductive layer occurred, and F was rated if delamination of the electrical conductive layer occurred.

[0186] The measurement results for each example and comparative example are shown in Table 1 below.

[0187] JPEG0007900445000005.jpg53164

[0188] JPEG0007900445000006.jpg95165

[0189] In Table 1 above, R s / z Value -5nm -2 ~50nm-2 In the controlled examples 1-5, the electrical conductive layer exhibited a bonding force of 0.2 kgf or more, and no delamination of the electrical conductive layer occurred in the evaluation of whether or not delamination occurred. On the other hand, R s / z Value -5nm -2 Less than or 55nm -2 In the case of Comparative Examples 1 and 2, which were superior, the bonding force of the electrical conductive layer was measured to be 0.15 kgf or less, and delamination of the electrical conductive layer occurred during the evaluation of whether or not delamination occurred.

[0190] In Table 2 above, the standard deviation of the Rsk value in each measurement area of ​​Examples 1 to 5 was calculated to be 0.4 or less, and the standard deviation of the Rz value was calculated to be 0.9 nm or less. This means that the roughness characteristics of the upper surface of the glass cores in the examples are uniform overall.

[0191] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. Various modifications and improvements by those skilled in the art, utilizing the basic concepts of the present invention as defined in the appended claims, also fall within the scope of the present invention. [Explanation of symbols]

[0192] 100 circuit boards 10 glass cores 11 Top surface of the glass core 12. Bottom surface of the glass core 20 Electrical Conductive Layer 21 Seed Layer 22 Conduction layer 25. First electrical conduction layer 26. Second electrical conduction layer 30 Insulating layer 50-core distribution layer L Interface formed between the first electrical conductive layer and the glass core

Claims

1. It includes a glass core having an upper surface, The upper surface of the glass core includes a total of three arbitrarily selected measurement areas. The standard deviation of the Rsk value in each of the aforementioned measurement regions is 0.5 or less. The standard deviation of the Rz values ​​in each of the aforementioned measurement regions is 1.5 nm or less. R is the value of the ratio of the asymmetry to the roughness of the upper surface of the glass core, as shown in the following formula 1. ｓ／ｚ The value is -5 nm －２ ~50nm －２ The Rsk value is -0.5 to 1.8, and the Rz value is 4 nm to 30 nm. The glass core includes an electrically conductive layer disposed on the glass core, The electrical conductive layer includes a first electrical conductive layer formed in contact with the surface of the glass core. The bonding force between the first electrical conductive layer and the glass core, as measured by a 180° peel test, was 0.2 kgf to 3 kgf. A substrate in which, when observed in cross-section of the first conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first conductive layer and the glass core, is 5 nm to 200 nm or less. [Formula 1] In the above formula 1, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

2. The electrical conductive layer includes a seed layer and a conductive layer disposed on the seed layer. The substrate according to claim 1, wherein the thickness of the seed layer is 50 nm to 1500 nm.

3. The electrical conductive layer has a pattern shape, The width of the electrical conductive layer is 1 μm to 5 μm. The substrate according to claim 1, wherein the thickness of the electrical conductive layer is 1 μm to 5 μm.

4. The substrate is the substrate according to claim 1, which is used for semiconductor packaging.

5. Preparation steps for installing the basic glass plate, The process includes a roughening step of providing a substrate containing a glass core formed by plasma treatment of the upper surface of the basic glass plate with an inert gas for 10 to 50 seconds under the conditions of an ambient pressure of 100 mTorr or less, a flow rate of the introduced inert gas of 100 sccm or more, a source power of 0.1 kW or more, and a bias power of 0.1 kW or more. The glass core has an upper surface, The upper surface of the glass core includes a total of three arbitrarily selected measurement areas. The standard deviation of the Rsk value in each of the aforementioned measurement regions is 0.5 or less. The standard deviation of the Rz values ​​in each of the aforementioned measurement regions is 1.5 nm or less. R is the value of the ratio of the asymmetry to the roughness of the upper surface of the glass core, as shown in the following formula 1. ｓ／ｚ The value is -5 nm －２ ~50nm －２ The Rsk value is -0.5 to 1.8, and the Rz value is 4 nm to 30 nm. The glass core includes an electrically conductive layer disposed on the glass core, The electrical conductive layer includes a first electrical conductive layer formed in contact with the surface of the glass core. The bonding force between the first electrical conductive layer and the glass core, as measured by a 180° peel test, was 0.2 kgf to 3 kgf. A method for manufacturing a substrate, wherein, when observed in cross-section of the first electrical conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first electrical conductive layer and the glass core, is 5 nm to 200 nm or less. [Formula 1] In the above formula 1, the Rsk value is the asymmetry value, and the Rz value is the maximum height roughness (unit: nm).

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