Zero-crossing detection circuit

Abstract

To detect a zero-cross of an alternating-current signal without using photocouplers.SOLUTION: A semiconductor integrated circuit device 300 comprises: a zero-cross detection unit 320 that compares a first monitoring object signal V11 and a second monitoring object signal V12 respectively inputted via diodes D11 and D12 from a first node N1 and a second node L1, with an alternating-current signal V0 applied therebetween, and generates a comparison signal SB; a logic unit 330 that counts the cycles of the comparison signal SB, estimates the zero cross of the alternating-current signal V0 using the count value, and generates a zero-cross detection signal SC; and a monitoring unit 310 that makes the first monitoring object signal V11 and the second monitoring object signal V12 adapted for input to the zero-cross detection unit 320. A first chip 300a in which the monitoring unit 310 is integrated is cut out in shape of a rectangle the long and short sides of which are almost equal in a plan view thereof.SELECTED DRAWING: Figure 39

Description

Technical Field

[0001] The invention disclosed in this specification relates to a zero-cross detection circuit.

Background Art

[0002] FIG. 57 is a diagram showing a conventional example of a zero-cross detection circuit. The zero-cross detection circuit DET of this conventional example is a circuit that detects the zero-cross (= the intersection of the AC voltage Vac and the ground potential) of the AC voltage Vac applied between the L (live) terminal and the N (neutral) terminal, and is mounted in home appliances with almost discrete components (in the example of this figure, a total of 11 components including the photocoupler PC, pnp bipolar transistor Qa, resistors Ra to Rd, diodes Da and Db, zener diode ZD, and capacitor Ca).

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, the zero-cross detection circuit DET of this conventional example has the following problems: (1) the power consumption of the photocoupler PC is large, (2) the number of discrete components is large, (3) the detection accuracy is poor due to the temperature characteristics of the photocoupler PC, etc., and (4) the reliability of high withstand voltage components is low (in applications such as washing machines, electrical corrosion of the resistor Ra is likely to occur). However, since the zero-cross detection circuit DET of this conventional example has a long-term usage record and its redesign is difficult, it is currently being used as it is.

[0006] In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed herein aims to provide a zero-cross detection circuit that can detect the zero-cross of an AC signal without using a photocoupler. [Means for solving the problem]

[0007] The zero-cross detection circuit disclosed herein has a configuration comprising: a peak detection unit that detects the peak of a signal to be monitored input via a diode from the AC signal application terminal and generates a peak detection signal; and a zero-cross detection unit that estimates the zero-cross of the AC signal from the peak detection signal and generates a zero-cross detection signal.

[0008] Furthermore, the zero-cross detection circuit disclosed herein has a configuration comprising: a zero-cross detection unit that generates a first comparison signal by comparing a first monitored signal and a second monitored signal input via diodes from a first node and a second node, to which AC signals are applied, respectively, and a logic unit that generates a zero-cross detection signal by estimating the zero-cross of the AC signal from the first comparison signal.

[0009] Furthermore, the zero-cross detection circuit disclosed herein includes a logic unit that generates a zero-cross detection signal by estimating the zero-cross of the AC signal in accordance with at least one of a first monitored signal and a second monitored signal input via diodes from a first node and a second node to which an AC signal is applied between them, and an input stop detection unit that generates an input stop detection signal by adding an offset to one of the first monitored signal and the second monitored signal and comparing them with each other, wherein the logic unit is configured to fix the logic level of the zero-cross detection signal in accordance with the input stop detection signal.

[0010] Further features, elements, steps, advantages, and characteristics will be revealed in the detailed description of the embodiments and the accompanying drawings that follow. [Effects of the Invention]

[0011] According to the invention disclosed in this specification, it is possible to provide a zero-cross detection circuit that can detect the zero-cross of an AC signal without using a photocoupler.

Brief Description of the Drawings

[0012] [Figure 1] Figure showing the first configuration example (normal rectification) of an electronic device [Figure 2] Figure showing the second configuration example (voltage doubler rectification) of an electronic device [Figure 3] Figure showing the relationship between the rectification method and the voltages of each part [Figure 4] Figure showing the first embodiment of a semiconductor integrated circuit device [Figure 5] Figure showing a configuration example of an AC monitoring unit [Figure 6] Figure showing a configuration example of a peak detection unit [Figure 7] Figure showing a configuration example of a first output unit [Figure 8] Timing chart showing an example of zero-cross detection processing [Figure 9] Timing chart showing an example of noise removal processing [Figure 10] Figure showing the second embodiment of a semiconductor integrated circuit device [Figure 11] Timing chart showing an example of AC waveform determination processing [Figure 12] Figure showing an example of normal determination of an AC monitor signal [Figure 13] Figure showing the third embodiment of a semiconductor integrated circuit device [Figure 14] Figure showing the fourth embodiment of a semiconductor integrated circuit device [Figure 15] External view showing the package of a semiconductor integrated circuit device [Figure 16] Figure showing the first example of a package layout [Figure 17] Figure showing the internal configurations of the first chip and the second chip respectively [Figure 18]Figure schematically showing the α-α’ cross-section [Figure 19] Figure showing the second example of package layout [Figure 20] Figure showing the third configuration example (normal rectification) of an electronic device [Figure 21] Figure showing the fourth configuration example (voltage-doubling rectification) of an electronic device [Figure 22] Figure showing the fifth embodiment of a semiconductor integrated circuit device [Figure 23] Figure showing the first embodiment of a zero-cross detection unit [Figure 24] Timing chart showing the first example of zero-cross detection processing [Figure 25] Timing chart showing the second example of zero-cross detection processing [Figure 26] Timing chart showing the third example of zero-cross detection processing [Figure 27] Figure showing the second embodiment of a zero-cross detection unit [Figure 28] Timing chart showing the fourth example of zero-cross detection processing [Figure 29] Timing chart showing the fifth example of zero-cross detection processing [Figure 30] Timing chart showing the sixth example of zero-cross detection processing [Figure 31] Figure showing the fifth configuration example (normal rectification, single-sided relay) of an electronic device [Figure 32] Figure showing the sixth embodiment of a semiconductor integrated circuit device [Figure 33] Timing chart showing an example of output pulse stop processing [Figure 34] Figure showing the third example of package layout [Figure 35] Figure showing the internal configurations of the first chip and the second chip respectively [Figure 36] Figure showing the fourth example of package layout [Figure 37] Figure showing the internal configurations of the first chip and the second chip respectively [Figure 38] Figure showing a configuration example of an AC monitoring unit and a DC monitoring unit [Figure 39]Diagram showing the layout of the first chip. [Figure 40] A longitudinal section diagram showing a structural example in the high-pressure resistance region. [Figure 41] Enlarged top view showing one structural example in the high-pressure resistance region. [Figure 42] Diagram showing the layout of the second chip. [Figure 43] Figure showing the fifth example of a package layout. [Figure 44] Figure showing the sixth example of a package layout. [Figure 45] Plan view showing the pin configuration (7 pins) of a semiconductor integrated circuit device. [Figure 46] Plan view showing the pin configuration (11 pins) of a semiconductor integrated circuit device. [Figure 47] Diagram illustrating the generation process of the comparison signal (no input offset, no signal distortion) [Figure 48] Diagram illustrating the generation process of the comparison signal (no input offset, with signal distortion). [Figure 49] Diagram illustrating the generation process of the comparison signal (with input offset and signal distortion). [Figure 50] A diagram showing the seventh embodiment of a semiconductor integrated circuit device. [Figure 51] Diagram showing the process for suppressing fluctuations in zero-crossing delay time. [Figure 52] A diagram showing the eighth embodiment of a semiconductor integrated circuit device. [Figure 53] This diagram shows an example of arbitrarily setting the target zero-cross delay time. [Figure 54] This figure shows the first output waveform of the ACOUT signal. [Figure 55] This figure shows the second output waveform of the ACOUT signal. [Figure 56] A diagram showing the ninth embodiment of a semiconductor integrated circuit device. [Figure 57] This figure shows a conventional example of a zero-crossing detection circuit. [Modes for carrying out the invention]

[0013] <Electronic Devices (First Configuration Example and Second Configuration Example)> Figures 1 and 2 show a first configuration example (normal rectification method) and a second configuration example (voltage doubling rectification method) of an electronic device that operates by receiving an AC voltage V0, respectively. Each configuration example of the electronic device 10 includes a filter 11, a rectifier 12, an AC / DC converter 13, a DC / DC converter 14, a microcontroller 15, a driver 16, a motor 17, and a zero-crossing detection circuit 18.

[0014] Filter 11 removes noise and surges from the AC voltage V0 (e.g., AC 80V to 264V) input between the L (live) terminal and the N (neutral) terminal, and outputs it between the L1 terminal and the N1 terminal. A protective element such as a fuse may be provided before filter 11.

[0015] The rectifier section 12 is a circuit block that generates a rectified voltage V1 (e.g., DC 100V to 450V) by normally rectifying or voltage-doubler rectifying the filtered AC voltage V0 input via the filter 11, and supplies this to the AC / DC converter 13, the motor 17, and the zero-cross detection circuit 18. It includes diodes 12a to 12d and capacitors 12e (normal rectification method) or capacitors 12f and 12g (voltage-doubler rectification method).

[0016] Note that the standard rectification method (Figure 1) is the mainstream rectification method overseas, where commercial AC power is often 200V. On the other hand, the voltage doubling rectification method (Figure 2) is the mainstream rectification method in Japan, where commercial AC power is 100V.

[0017] The cathode of diode 12a and the anode of diode 12c are both connected to terminal L1. The cathode of diode 12b and the anode of diode 12d are both connected to terminal N1. The cathodes of diodes 12c and 12d are connected to each other, and this connection node corresponds to the output terminal of the rectified voltage V1. The anodes of diodes 12a and 12b are connected to each other, and this connection node is connected to the common ground terminal GND shared with the microcontroller 15 and the zero-crossing detection circuit 18. In this way, diodes 12a to 12d are connected to form a diode bridge, and the filtered AC voltage V0 is full-wave rectified to generate the rectified voltage V1.

[0018] Furthermore, when the rectifier section 12 employs a normal rectification method, a single capacitor 12e is connected between the output terminal of the rectified voltage V1 and the ground terminal GND, as shown in Figure 1. On the other hand, when the rectifier section 12 employs a voltage doubler rectification method, capacitors 12f and 12g are connected in series between the output terminal of the rectified voltage V1 and the ground terminal GND, as shown in Figure 2. The connection node between capacitors 12f and 12g is connected to terminal L1.

[0019] The AC / DC converter 13 rectifies the AC voltage V0 to obtain a rectified voltage V1, from which it generates a desired first DC voltage V3 (for example, DC 13.0V to 18.0V), and outputs this to the DC / DC converter 14, the driver 16, and the zero-crossing detection circuit 18.

[0020] The DC / DC converter 14 generates a desired second DC voltage V4 (for example, DC 5.0V) from the first DC voltage V3 and outputs it to the microcontroller 15 or the like.

[0021] The microcontroller 15 operates upon receiving the second DC voltage V4 and generates a motor control signal S3 to control the drive of the motor 17 according to the detection results (=ACOUT signal S1 and DCOUT signal S2) of the zero-crossing detection circuit 18.

[0022] The driver 16 operates upon receiving a first DC voltage V3 and generates a motor drive signal S4 in accordance with the motor control signal S3.

[0023] Motor 17 is a type of load that operates on a rectified voltage V1 and is rotationally driven according to the motor drive signal S4.

[0024] The zero-cross detection circuit 18 is a circuit block that detects the zero-crossing of the AC voltage V0 (= the intersection of the AC voltage V0 and the ground potential), and comprises a semiconductor integrated circuit device 100 and an externally attached diode D1 and capacitor C1.

[0025] The semiconductor integrated circuit device 100 is an IC or LSI formed by integrating at least a portion (details described later) of the circuit elements that form the zero-cross detection circuit 18, and has seven external terminals (pins 1 to 7) as means for establishing an electrical connection with the outside of the device.

[0026] Pin 1 (ACOUT pin) is the output terminal for the ACOUT signal S1 and is connected to the microcontroller 15. Pin 2 (DCOUT pin) is the output terminal for the DCOUT signal S2 and is connected to the microcontroller 15. Pin 3 (GND pin) is the ground terminal and is connected to the common ground terminal GND shared with the microcontroller 15. In other words, the semiconductor integrated circuit device 100 (and by extension the zero-crossing detection circuit 18 using it) operates with the common ground voltage shared with the microcontroller 15 as the reference. Pin 4 (VCC pin) is the power terminal and is connected to the output terminal of the AC / DC converter 13 (= output terminal of the first DC voltage V3). Capacitor C1 is connected between pin 4 and pin 3.

[0027] Pin 5 (VHDC pin) is a DC input terminal and is connected to the output terminal of the rectifier unit 12 (= the terminal to which the rectified voltage V1 is applied). Pin 6 (NC [non-connection] pin) is an unused terminal and is not connected to anything outside the semiconductor integrated circuit device 100. Pin 7 (VHAC pin) is an AC input terminal and is connected to the cathode of diode D1 (= corresponding to the terminal to which the monitored voltage V2 is applied). The anode of diode D1 is connected to terminal N1 (or terminal L1).

[0028] Thus, unlike the previous conventional example (Figure 38), the zero-crossing detection circuit 18 in this configuration example detects the zero-crossing of the AC voltage V0 using only three mounted components (semiconductor integrated circuit device 100, diode D1, and capacitor C1). Consequently, standby power consumption is reduced (1W → tens of mW), and the printed circuit board size is reduced (hundreds of millimeters). 2 →Several tens of mm 2 ), or improvements in the accuracy of load drive control can be enjoyed, making it possible to provide electronic equipment 10 that is in line with market trends and customer needs.

[0029] However, in order to realize the zero-crossing detection circuit 18 in this example configuration, it is necessary to solve the following technical problems: (1) a photocoupler cannot be used, (2) the zero-crossing fluctuates when monitoring other than between LN terminals, and (3) the zero-crossing detection point differs between the normal rectification method and the voltage doubler rectification method.

[0030] In particular, the technical issues (2) and (3) mentioned above will be described in detail with reference to the drawings. Figure 3 shows the relationship between the rectification method and the voltages of each part, and from top to bottom, the waveforms of the AC voltage V0, the rectified voltage V1, and the monitored voltage V2 are shown.

[0031] For example, when the AC voltage V0 is a sinusoidal waveform fluctuating between +1.41AC and -1.41AC, and the rectifier unit 12 employs a normal rectification method (Figure 1), the rectified voltage V1 becomes a DC waveform pulsating near +1.41AC, as shown on the left side of this figure, and the monitored voltage V2 becomes a half-wave rectified waveform fluctuating between +1.41AC and 0V. On the other hand, when the rectifier unit 12 employs a voltage doubler rectification method (Figure 2), the rectified voltage V1 becomes a DC waveform pulsating near +1.41AC × 2, as shown on the right side of this figure, and the monitored voltage V2 becomes a sinusoidal waveform fluctuating between +1.41AC × 2 and 0V.

[0032] Thus, the monitored voltage V2 has a different waveform from the AC voltage V0, and depending on the load conditions, distortion may occur in that waveform. In other words, it is conceivable that the zero-crossing of the monitored voltage V2 may differ from the zero-crossing of the AC voltage V0. Therefore, in a configuration that detects the zero-crossing of the monitored voltage V2, there is a risk that the zero-crossing of the AC voltage V0 may not be detected correctly.

[0033] Furthermore, when attempting to detect the zero-crossing of the monitored voltage V2, the detection point is the intersection with 0V in the case of a normal rectification method, and the intersection with +1.41AC in the case of a voltage doubling rectification method. Therefore, in a configuration that detects the zero-crossing of the monitored voltage V2, the detection point must be switched according to the rectification method, making it difficult to support both rectification methods.

[0034] In the following, we will explain how all of these technical problems (1) to (3) are solved, using an embodiment of the semiconductor integrated circuit device 100 as an example.

[0035] <Semiconductor integrated circuit device (first embodiment)> Figure 4 shows a first embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment integrates an AC monitoring unit 110, a peak detection unit 120, a zero-crossing detection unit 130, a first output unit 140, a DC monitoring unit 150, a second output unit 160, and a voltage reduction protection unit 170.

[0036] The AC monitoring unit 110 is a high-voltage (e.g., 650V withstand voltage) circuit that generates an AC monitor signal Sa suitable for input to the peak detection unit 120 from the monitored voltage V2 (which corresponds to the monitored signal input via diode D1 from terminal N1 to which AC voltage V0 is applied) input to pin 7 (VHAC pin).

[0037] The peak detection unit 120 detects the peak of the AC monitor signal Sa (and consequently the monitored voltage V2) and generates a peak detection signal Sb.

[0038] The zero-crossing detection unit 130 is a logic circuit that estimates the zero-crossing of the AC voltage V0 from the peak detection signal Sb and generates a zero-crossing detection signal Sc.

[0039] The first output unit 140 receives the zero-crossing detection signal Sc as input, generates the ACOUT signal S1, and outputs it to pin 1 (ACOUT pin).

[0040] The DC monitoring unit 150 is a high-voltage (e.g., 650V withstand voltage) circuit block that generates a DC monitor signal Sx from the rectified voltage V1 input to pin 5 (VHDC pin).

[0041] The second output unit 160 receives the DC monitor signal Sx as input, generates the DCOUT signal S2, and outputs it to pin 2 (DCOUT pin).

[0042] Furthermore, if the DC monitor signal Sx is to be passed through as the DCOUT signal S2, the second output section 160 may be omitted. Also, if the DC monitor function itself is not required, it is possible to omit the DC monitoring section 150, the second output section 160, pin 2 (DCOUT pin), and pin 5 (VHDC pin) entirely.

[0043] The undervoltage protection unit 170 is a protection functional unit (so-called UVLO [under voltage lock-out] protection unit) that prohibits the operation of the semiconductor integrated circuit device 100 when the first DC voltage V3 input to the 4-pin (VCC) is below the lower limit value.

[0044] <AC monitoring unit> FIG. 5 is a diagram showing a configuration example of the AC monitoring unit 110. The AC monitoring unit 110 of this configuration example includes resistors 111 to 115, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor] 116, a PMOSFET [P-channel type MOSFET] 117, and a diode 118.

[0045] The resistors 111 to 115 are connected in series between the 7-pin (VHAC pin) and the 3-pin (GND pin) in the order shown in the figure. Note that the connection node between the resistor 113 and the resistor 114 corresponds to the output terminal of the AC monitor signal Sa. That is, the resistors 111 to 115 function as a voltage dividing circuit that divides the monitored voltage V2 input to the 7-pin to generate the AC monitor signal Sa. For example, if the combined resistance value of the resistors 111 to 113 is Rx (e.g., 10 MΩ) and the combined resistance value of the resistors 114 and 115 is Ry (e.g., 0.1 MΩ), then Sa = {Ry / (Rx + Ry)} × V2 (≈ 0.01 × V2).

[0046] Also, in the example of this figure, among the resistors 111 to 115, the resistance values of the resistors 112 and 115 can be adjusted by trimming or the like. Therefore, the above voltage division ratio {Ry / (Rx + Ry)} can be arbitrarily set.

[0047] Furthermore, it is desirable to use polysilicon resistors with a voltage rating of 100V or higher (for example, 650V) as resistors 111 to 115. In particular, when integrating resistors 111 to 115, it is necessary to increase the voltage rating not only in the path (lateral direction) through resistors 111 to 115, but also between resistors 111 to 115 and the semiconductor substrate (vertical direction). Therefore, it is desirable to form a high-voltage region on the semiconductor substrate on which the AC monitoring unit 110 is integrated, where the voltage rating in the substrate thickness direction (vertical direction) is higher than in other areas, and to form resistors 111 to 115 on this high-voltage region. As the above high-voltage region, the LDMOSFET (lateral double-diffused MOSFET) region, which has a proven track record of high voltage ratings, can be reused.

[0048] The drain of NMOSFET116 is connected to pin 7. The source, gate, and back gate of NMOSFET116 are all connected to pin 3. The drain of PMOSFET117 is connected to pin 3. The source, gate, and back gate of PMOSFET117 are all connected to the output terminal of the AC monitor signal Sa. The cathode of diode 118 is connected to the back gate of PMOSFET117. The drain of PMOSFET117 and the anode of diode 118 are both connected to pin 3. The NMOSFET116, PMOSFET117, and diode 118 connected in this manner all function as electrostatic discharge protection elements.

[0049] The AC monitoring unit 110 is not limited to this configuration example using a voltage divider circuit. For example, it may also be configured to sample the monitored voltage V2 at a predetermined sampling rate and output the sampled value as an AC monitor signal Sa to the peak detection unit 120.

[0050] Furthermore, the DC monitoring unit 150 can basically have the same configuration as the AC monitoring unit 110. That is, by replacing "7-pin (VHAC pin)" with "5-pin (VHDC pin)" and "AC monitor signal Sa" with "DC monitor signal Sx" in the above explanation, the configuration and operation of the DC monitoring unit 150 can be understood.

[0051] <Peak detection unit> Figure 6 shows an example configuration of the peak detection unit 120. As shown in this figure, the peak detection unit 120 in this example configuration includes resistors 121 and 122, capacitors 123 and 124, and a comparator 125.

[0052] The first terminal of resistor 121 is connected to the input terminal of the AC monitor signal Sa. The second terminal of resistor 121 is connected to the first terminal of resistor 122, the first terminal of capacitor 123, and the non-inverting input terminal (+) of comparator 125. The second terminal of resistor 122 is connected to the first terminal of capacitor 124 and the inverting input terminal (-) of comparator 125. The second terminals of capacitors 123 and 124 are both connected to pin 3 (GND pin). The output terminal of comparator 125 corresponds to the output terminal of the peak detection signal Sb.

[0053] Furthermore, resistor 121 (e.g., 2MΩ) and capacitor 123 (e.g., 10pF) function as an RC filter that generates the first AC monitor signal Sa1 by removing noise components superimposed on the AC monitor signal Sa.

[0054] On the other hand, resistor 122 (e.g., 4.7 MΩ) and capacitor 124 (e.g., 20 pF) function as a delay unit that generates a second AC monitor signal Sa2 by introducing a predetermined delay to the first AC monitor signal Sa1.

[0055] Comparator 125 generates a peak detection signal Sb by comparing the first AC monitor signal Sa1 (no delay) and the second AC monitor signal Sa2 (with delay). The peak detection signal Sb becomes high level when the first AC monitor signal Sa1 is higher than the second AC monitor signal Sa2, and low level when the first AC monitor signal Sa1 is lower than the second AC monitor signal Sa2. The peak detection signal Sb generated in this way falls to a low level slightly after a peak occurs in the monitored voltage V2. This point will be explained in detail later with specific examples.

[0056] Note that the circuit configuration shown in this diagram is merely an example, and any circuit configuration may be used as long as it can appropriately detect the peak of the monitored voltage V2 (or AC monitor signal Sa).

[0057] <First Output Section> Figure 7 shows an example configuration of the first output unit 140. In this example configuration, the first output unit 140 includes inverters 141 and 142, an NMOSFET 143, and a resistor 144. The input terminal of inverter 141 is connected to the input terminal of the zero-crossing detection signal Sc. The output terminal of inverter 141 is connected to the input terminal of inverter 142. The output terminal of inverter 142 is connected to the gate of NMOSFET 143. The first terminal of resistor 144 is connected to the power supply terminal (e.g., DC 5V). The second terminal of resistor 144 and the drain of NMOSFET 143 are both connected to pin 1 (ACOUT pin). The source and back gate of NMOSFET 143 are both connected to pin 3 (GND pin).

[0058] In the first output unit 140 of this configuration example, when the zero-crossing detection signal Sc is at a high level, the NMOSFET 143 is turned on, and the ACOUT signal S1 output from pin 1 becomes low level. On the other hand, when the zero-crossing detection signal Sc is at a low level, the NMOSFET 143 is turned off, and the ACOUT signal S1 becomes high level.

[0059] Thus, the ACOUT signal S1 generated by the open-drain first output unit 140 is essentially the logic inversion signal of the zero-crossing detection signal Sc.

[0060] <Zero-crossing detection process> Figure 8 is a timing chart showing an example of the zero-cross detection process in the zero-cross detection unit 130. From top to bottom, it depicts the AC voltage V0, rectified voltage V1, monitored voltage V2 (or AC monitor signal Sa), first AC monitor signal Sa1 and second AC monitor signal Sa2, peak detection signal Sb, and zero-cross detection signal Sc. Below, a detailed explanation will be given using the behavior when the rectifier unit 12 employs a normal rectification method (Figure 1) as an example.

[0061] The waveform of the AC voltage V0 is a sinusoidal waveform that switches between positive and negative at a predetermined period. In this example, zero-crossings from negative to positive occur in the AC voltage V0 at times t1, t5, and t9, while zero-crossings from positive to negative occur at times t3, t7, and t11. Also, in this example, a positive peak occurs in the AC voltage V0 at times t2, t6, and t10, while a negative peak occurs at times t4, t8, and t12.

[0062] The waveform of the rectified voltage V1 is a DC waveform that pulsates near the peak of the full-wave rectified waveform of the AC voltage V0 (see the thin dashed line).

[0063] When the rectifier unit 12 employs a normal rectification method (Figure 1), the waveform of the monitored voltage V2 (or AC monitor signal Sa) is basically a half-wave rectified waveform of the AC voltage V0. That is, when the AC voltage V0 is positive, the monitored voltage V2 is also positive, while even if the AC voltage V0 is negative, the monitored voltage V2 will not fall below 0V.

[0064] Note that, as shown by overlapping the waveform of the monitored voltage V2 (thin dashed line (ideal) and thick solid line (reality)), distortion may occur depending on the load condition or the like. Therefore, even if the zero crossing of the monitored voltage V2 is detected, it is difficult to correctly detect the zero crossing of the AC voltage V0.

[0065] On the other hand, as a result of intensive research, the inventors of the present application have found that the peak timing of the monitored voltage V2 almost coincides with the peak timing of the AC voltage V0 regardless of the load condition or the like. In other words, between the AC voltage V0 and the monitored voltage V2, the timing at which the phases of both can be made to coincide is only the respective peak timings. Based on this finding, the inventors have created a new arithmetic algorithm capable of estimating the zero crossing of the AC voltage V0 from the peak timing of the monitored voltage V2. Hereinafter, while continuing the description of FIG. 8, the above arithmetic algorithm will be specifically described.

[0066] The first AC monitor signal Sa1 (thick solid line) and the second AC monitor signal Sa2 (thick dashed line) obtained by delaying this cross each other at a point in time (for example, time tx) when a predetermined delay time Δ has elapsed from the peak timing of the monitored voltage V2 (for example, time t2). Specifically described in accordance with this figure, the high / low relationship between the first AC monitor signal Sa1 and the second AC monitor signal Sa2 switches from Sa1>Sa2 to Sa1<Sa2 before and after time tx. As a result, the peak detection signal Sb falls from a high level to a low level at time tx.

[0067] That is, it can be said that the falling edge of the peak detection signal Sb indicates the peak timing of the monitored voltage V2 (and thus the positive peak timing of the AC voltage V0). Therefore, the zero crossing detection unit 130 sequentially detects the falling edge of the peak detection signal Sb, counts the period T of the peak detection signal Sb (for example, from time tx to time ty in this figure), and estimates the zero crossing of the AC voltage V0 using the count value.

[0068] More specifically, the zero-crossing detection unit 130, assuming that the period and phase of the AC voltage V0 are constant, determines the rising and falling timings of the zero-crossing detection signal Sc by referring to the period T of the peak detection signal Sb.

[0069] For example, the zero-cross detection unit 130 starts counting a waiting time T1 (for example, T1 = (1 / 4) × T - Δ) corresponding to the previously acquired period T, from the moment the peak detection signal Sb falls to a low level (for example, at time ty), and raises the zero-cross detection signal Sc from a low level to a high level when the waiting time T1 has elapsed. The rising timing of this zero-cross detection signal Sc roughly coincides with the timing when the AC voltage V0 switches from positive to negative (i.e., a zero-cross from positive to negative).

[0070] Furthermore, the zero-cross detection unit 130 lowers the zero-cross detection signal Sc from a high level to a low level when a waiting time T2 (for example, T2 = (3 / 4) × T - Δ) longer than the waiting time T1 has elapsed from the time the peak detection signal Sb falls to a low level (for example, time ty). The falling timing of this zero-cross detection signal Sc almost coincides with the timing when the AC voltage V0 switches from negative to positive (i.e., the zero-cross from negative to positive).

[0071] The count value of period T used to determine the waiting times T1 and T2 may be the count value from the previous period, or the average count value over several periods. The delay time Δ (the difference between the true peak timing and the pulse edge timing of the peak detection signal Sb) used to determine the waiting times T1 and T2 is known from the circuit characteristics of the delay section (resistor 122 and capacitor 124). However, it is also possible to determine the rising and falling timings of the zero-crossing detection signal Sc without correcting for the above delay time Δ.

[0072] Furthermore, while this figure illustrates the zero-crossing detection process during normal rectification (Figure 1), the zero-crossing detection process during voltage-doubler rectification (Figure 2) can be performed in exactly the same way, except that the waveform of the monitored voltage V2 (or AC monitor signal Sa) is different. In other words, the novel calculation algorithm described above can support both the normal rectification method (Figure 1) and the voltage-doubler rectification method (Figure 2).

[0073] However, the zero-cross detection process shown in this figure is merely an example, and any calculation algorithm can be used as long as it can appropriately generate the pulse edge of the zero-cross detection signal Sc from the peak detection signal Sb.

[0074] <Noise reduction processing> Next, we will explain in detail, with reference to the diagrams, the methods for removing noise that is expected to be superimposed on the peak detection signal Sb in actual applications. Figure 9 is a timing chart showing an example of noise reduction processing in the zero-crossing detection unit 130, with the AC monitor signal Sa, peak detection signal Sb, and zero-crossing detection signal Sc depicted from top to bottom. For the sake of explanation, we will ignore the delay time Δ below.

[0075] In the example shown in this figure, the AC monitor signal Sa is at its peak at times t22 and t25, and consequently, the peak detection signal Sb falls from a high level to a low level. Therefore, by determining the rising and falling timings of the zero-crossing detection signal Sc based on the falling edge of the peak detection signal Sb, it becomes possible to correctly estimate the zero-crossing of the AC voltage V0. This point has been explained earlier.

[0076] However, in the electronic device 10, unintended noise (noises N1 to N3 in this figure) is superimposed on the AC monitor signal Sa due to the back electromotive force of the motor 17, etc. Noise N1 is superimposed while the AC monitor signal Sa is rising from zero to its peak value (=times t21 to t22). On the other hand, noise N2 is superimposed while the AC monitor signal Sa is maintained at zero value (=times t23 to t24). Noise N3 is superimposed while the AC monitor signal Sa is falling from its peak value to zero value (=times t25 to t26).

[0077] When noises N1 to N3 are superimposed, the peak detection signal Sb switches to an unintended logic level, making it impossible to correctly detect the peak of the AC monitor signal Sa. Therefore, the zero-crossing detection unit 130 ignores the logic level switch of the peak detection signal Sb if the switched logic level is not maintained for a predetermined mask period (e.g., 1600 μs) after the switch.

[0078] For example, at times t21 to t22, the peak detection signal Sb falls to a low level due to noise N1, but immediately rises to a high level, so this falling edge is ignored. In other words, the zero-crossing detection unit 130 treats the peak detection signal Sb as being maintained at a high level at times t21 to t22.

[0079] Similarly, at times t23-t24, the peak detection signal Sb falls to a low level due to noise N2, but this also rises to a high level immediately, so this falling edge is ignored. In other words, the zero-crossing detection unit 130 treats the peak detection signal Sb as being maintained at a high level at times t23-t24.

[0080] On the other hand, at times t25 to t26, the peak detection signal Sb rises to a high level due to the noise N3, but since it immediately falls to a low level, this rising edge is ignored. That is, the zero-crossing detection unit 130 treats the peak detection signal Sb as being maintained at a low level at times t25 to t26.

[0081] Note that the entity performing the above noise removal process is not necessarily limited to the zero-crossing detection unit 130. It is useful to complete the noise removal process before receiving the input of the peak detection signal Sb and performing any signal processing.

[0082] Also, an analog noise filter or a digital noise filter (such as a FIR [finite impulse response] filter) may be provided between the peak detection unit 120 and the zero-crossing detection unit 130.

[0083] <Semiconductor Integrated Circuit Device (Second Embodiment)> FIG. 10 is a diagram showing a second embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of the present embodiment further includes a comparison unit 180 and an AC waveform determination unit 190 based on the first embodiment (FIG. 4) (in this figure, the description of the AC monitoring unit 110, the first output unit 140, the DC monitoring unit 150, the second output unit 160, and the undervoltage protection unit 170 is omitted). Therefore, for the components similar to those in the first embodiment, the same reference numerals as in FIG. 4 are used to omit the redundant description, and hereinafter, the characteristic parts of the present embodiment will be mainly described.

[0084] The comparison unit 180 includes four comparators 181 to 184, and compares the AC monitor signal Sa with a plurality of threshold values Vth1 to Vth4 (where Vth1 < Vth2 < Vth3 < Vth4) respectively to generate a plurality of comparison signals Sd1 to Sd4.

[0085] More specifically, the comparator 181 generates a comparison signal Sd1 by comparing the AC monitor signal Sa input to the non-inverting input terminal (+) with the threshold Vth1 input to the inverting input terminal (-). Therefore, the comparison signal Sd1 is high level when the AC monitor signal Sa is higher than the threshold Vth1, and low level when the AC monitor signal Sa is lower than the threshold Vth1.

[0086] Comparator 182 generates a comparison signal Sd2 by comparing the AC monitor signal Sa input to the non-inverting input terminal (+) with the threshold Vth2 input to the inverting input terminal (-). Therefore, the comparison signal Sd2 is high level when the AC monitor signal Sa is higher than the threshold Vth2, and low level when the AC monitor signal Sa is lower than the threshold Vth2.

[0087] Comparator 183 generates a comparison signal Sd3 by comparing the AC monitor signal Sa input to the non-inverting input terminal (+) with the threshold Vth3 input to the inverting input terminal (-). Therefore, the comparison signal Sd3 is high level when the AC monitor signal Sa is higher than the threshold Vth3, and low level when the AC monitor signal Sa is lower than the threshold Vth3.

[0088] Comparator 184 generates a comparison signal Sd4 by comparing the AC monitor signal Sa input to the non-inverting input terminal (+) with the threshold Vth4 input to the inverting input terminal (-). Therefore, the comparison signal Sd4 is high level when the AC monitor signal Sa is higher than the threshold Vth4, and low level when the AC monitor signal Sa is lower than the threshold Vth4.

[0089] Note that the comparison unit 180 is not limited to 4 channels; the number of channels can be arbitrary (2 or more).

[0090] The AC waveform determination unit 190 stores whether or not the rising edges and falling edges of each of the comparison signals Sd1 to Sd4 have occurred, and detects whether both a rising edge and a falling edge have occurred in at least one of the comparison signals Sd1 to Sd4 during one cycle of the zero-crossing detection signal Sc to generate a waveform determination signal Se. The waveform determination signal Se becomes the logical level (for example, low level) at the time of normal determination when the waveform of the AC monitor signal Sa is normal, and becomes the logical level (for example, high level) at the time of abnormal determination when the waveform of the AC monitor signal Sa is abnormal.

[0091] Note that the AC waveform determination unit 190 recognizes the logical level as valid only when the logical level of each of the comparison signals Sd1 to Sd4 is maintained for a predetermined period (for example, 40 μs). With such a configuration, noise and chattering of the comparison signals Sd1 to Sd4 can be ignored, so that correct AC waveform determination processing can be performed.

[0092] The zero-crossing detection unit 130 stops the generation or output of the zero-crossing detection signal Sc when the waveform determination signal Se is at the logical level at the time of abnormal determination (for example, high level). For example, when the waveform of the AC monitor signal Sa becomes abnormal during a momentary power failure of the AC power supply, the generation or output of the zero-crossing detection signal Sc is stopped. Therefore, the microcomputer 15 can quickly recognize the occurrence of an abnormality in the AC voltage V0 and stop the driving of the motor 17 without delay, so that the safety and reliability of the electronic device 10 can be improved.

[0093] <AC waveform determination process> FIG. 11 is a timing chart showing an example of the AC waveform determination process in the AC waveform determination unit 190, and the AC monitor signal Sa, the peak detection signal Sb, the zero-crossing detection signal Sc, the comparison signals Sd1 to Sd4, and the waveform determination signal Se are depicted in order from the top.

[0094] At times t31 to t32, the AC monitor signal Sa is input normally. During a predetermined detection period Tdet (corresponding to one cycle of the zero-crossing detection signal Sc), after rising from a zero value (<Vth1) to a peak value (>Vth4), it then decreases again to the zero value. As a result, both rising edges and falling edges occur in all of the comparison signals Sd1 to Sd4. Therefore, it is determined that the waveform of the AC monitor signal Sa is normal, and the waveform determination signal Se is set to the low level (= the logic level at the time of normal determination).

[0095] On the other hand, at times t32 to t33, as a result of an instantaneous power failure of the AC power supply occurring immediately after the AC monitor signal Sa rises from the zero value to the peak value and then turns downward again, the AC monitor signal Sa is maintained at a voltage value higher than the threshold value Vth4. In a conventional configuration (Fig. 20) using a photocoupler with high power consumption, when an instantaneous power failure of the AC power supply occurred, the power supply to the load also stopped without delay, so no particular problem occurred. However, in this configuration without using a photocoupler, since the monitored voltage V2 is not discharged, a state as shown in the figure can occur.

[0096] At this time, if the monitored voltage V2 (and by extension, the AC monitor signal Sa) fluctuates periodically due to some factor, although the power supply from the AC power supply has been cut off, the peak of the AC monitor signal Sa is erroneously detected and the zero-crossing detection signal Sc continues to be output. As a result, the microcomputer 15 may erroneously determine that power is being supplied from the AC power supply, leading to problems such as the motor 17 continuing to rotate with the remaining power.

[0097] In contrast, in a configuration having a comparison unit 180 and an AC waveform determination unit 190, if the AC monitor signal Sa is maintained at a voltage value higher than the threshold Vth4, all comparison signals Sd1 to Sd4 will stick at a high level, so the waveform of the AC monitor signal Sa is determined to be abnormal, and the waveform determination signal Se is raised to a high level (= the logic level at the time of abnormality determination). As a result, the generation and output of the zero-cross detection signal Sc are stopped after time t33, so the microcontroller 15 can quickly recognize the momentary power outage of the AC power supply and stop the motor 17 without delay.

[0098] Furthermore, if the discharge of the monitored voltage V2 progresses slowly, rising and falling edges of the AC monitor signal Sa may occur at a longer period than the detection period Tdet mentioned above. However, if the detection period Tdet is set to one period of the zero-cross detection signal Sc, there is no risk of the waveform of the AC monitor signal Sa being mistakenly judged as normal due to such pulse edges.

[0099] Figure 12 shows an example of normal determination of the AC monitor signal Sa, with the AC monitor signal Sa and comparison signals Sd1 to Sd4 depicted from top to bottom.

[0100] The left side of this figure shows how the AC monitor signal Sa fluctuates across all thresholds Vth1 to Vth4, similar to the time intervals t31 to t32 in Figure 11. In this case, periodic pulse edges occur in all of the comparison signals Sd1 to Sd4, so the AC monitor signal Sa is determined to be normal.

[0101] On the other hand, the center of this figure shows how the AC monitor signal Sa fluctuates, crossing only thresholds Vth1 and Vth2 (in this case, the peak value of the half-wave rectified waveform is below threshold Vth3). In this case, although comparison signals Sd3 and Sd4 are stuck at low levels, periodic pulse edges are generated in both comparison signals Sd1 and Sd2, so the AC monitor signal Sa is determined to be normal.

[0102] Furthermore, the right side of this figure shows how the AC monitor signal Sa fluctuates across thresholds Vth2 to Vth4 (in this case, the lower peak value of the AC waveform exceeds threshold Vth1). In this case, although the comparison signal Sd1 remains at a high level, periodic pulse edges occur in each of the comparison signals Sd2 to Sd4, so the AC monitor signal Sa is determined to be normal.

[0103] In this way, by having multiple channels in the comparison unit 180, it becomes possible to perform appropriate AC waveform determination processing for AC monitor signals Sa that have various normal waveforms.

[0104] Furthermore, the AC waveform determination process described above does not necessarily need to be performed in combination with peak detection or zero-crossing detection processes; it can be performed independently.

[0105] <Semiconductor integrated circuit device (third embodiment)> Figure 13 shows a third embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment is based on the first embodiment (Figure 4) but is characterized by further integrating the AC / DC converter 13. Therefore, for components similar to those of the first embodiment, the same reference numerals as in Figure 4 are used to omit redundant explanations, and the following will focus on the characteristic parts of this embodiment.

[0106] The semiconductor integrated circuit device 100 integrates the following circuit elements that constitute the AC / DC converter 13: resistors 13a and 13b, error amplifier 13c, comparator 13d, RS flip-flop 13e, level shifter 13f, and NMOSFET 13g.

[0107] Furthermore, an external terminal (X pin) has been added to the semiconductor integrated circuit device 100 due to the integration of the AC / DC converter 13. The X pin is connected to two external circuit elements of the AC / DC converter 13: a coil 13h and a diode 13i. Specifically, the first end of coil 13h and the cathode of diode 13i are connected to the X pin. The second end of coil 13h is connected to the output terminal of the first DC voltage V3. The anode of diode 13i is connected to pin 3 (GND pin).

[0108] Inside the semiconductor integrated circuit device 100, resistors 13a and 13b are connected in series between pin 4 (VCC pin) and pin 3 (GND pin), and function as a voltage divider circuit that outputs a feedback signal FB (= divided voltage of the first DC voltage V3) from each other's connection nodes.

[0109] The error amplifier 13c generates an error signal ERR according to the difference between the feedback signal FB input to the non-inverting input terminal (+) and a predetermined reference signal REF input to the inverting input terminal (-). The error signal ERR increases as the difference between the feedback signal FB and the reference signal REF increases, and decreases as the difference between the feedback signal FB and the reference signal REF decreases.

[0110] Comparator 13d generates a reset signal RST by comparing a sawtooth (or triangular) slope signal SLP input to the non-inverting input terminal (+) with an error signal ERR input to the inverting input terminal (-). The reset signal RST is high level when the slope signal SLP is higher than the error signal ERR, and low level when the slope signal SLP is lower than the error signal ERR.

[0111] The RS flip-flop 13e determines the logic level of the pulse width modulation signal PWM in response to both the set signal SET (a square wave clock signal oscillating at a predetermined switching frequency) input to the set terminal (S) and the reset signal RST input to the reset terminal (R), and outputs this level from the output terminal (Q). For example, the pulse width modulation signal PWM is set to a high level when the set signal SET rises to a high level, and reset to a low level when the reset signal RST rises to a high level.

[0112] The level shifter 13f shifts the pulse width modulation signal PWM (H=V3, L=GND) to generate the drive signal DRV (H=Vs+α, L=Vs, where Vs is the source voltage of NMOSFET 13g that appears at the X pin).

[0113] The NMOSFET13g is an output switch element connected between pin 5 (VHDC pin) and pin X, and is switched on / off according to the drive signal DRV.

[0114] In this way, by integrating the AC / DC converter 13 into a single package with the semiconductor integrated circuit device 100, it becomes possible to reduce the number of components.

[0115] In this embodiment, an example based on the first embodiment (Figure 4) is given, but the second embodiment (Figure 10) may also be used as a basis.

[0116] <Semiconductor integrated circuit device (fourth embodiment)> Figure 14 shows a fourth embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment is based on the third embodiment (Figure 13) but is characterized by the further integration of the DC / DC converter 14. In addition, the semiconductor integrated circuit device 100 of this embodiment has an external terminal (Y pin) for outputting a second DC voltage V4, which is added due to the integration of the DC / DC converter 14. In this way, by integrating not only the AC / DC converter 13 but also the DC / DC converter 14 into a single package, it is possible to further reduce the number of components.

[0117] <Package> Figure 15 is an external view showing the package of the semiconductor integrated circuit device 100. This figure illustrates a small outline package (SOP) in which external terminals are derived in two directions from the long side of the package.

[0118] Pins 1 (ACOUT pin), 2 (DCOUT pin), 3 (GND pin), and 4 (VCC pin) are all low-voltage terminals to which the rectifier voltage V1 and the monitored voltage V2 are not applied (pins 1 and 2 have a 5V voltage rating, and pins 3 and 4 have a 30V voltage rating), and are arranged along the first side of the package.

[0119] On the other hand, pins 5 (VHDC pin) and 7 (VHAC pin) are high-voltage terminals (700V withstand voltage) to which the rectified voltage V1 and the monitored voltage V2 are applied, respectively, and are arranged along the second side of the package. By arranging the pins in this way, the creepage distance between pins 1-4 and pins 5 and 7 can be increased, making it easier to ensure insulation between the two sets of pins.

[0120] Furthermore, an external terminal that would normally be present between pin 7 (VHAC pin) and pin 6 (NC pin) has been omitted. Consequently, the distance between pin 7 and its adjacent pin 6 is greater than the distance between pins 1 through 4. Also, if we ignore the unused pin 6, the distance between pin 5 and pin 7 is naturally greater than the distance between pins 1 through 4. By arranging the pins in this way, it is possible to ensure sufficient insulation between the pins lined up on the second side.

[0121] <Package Layout (Example 1)> Figure 16 is a diagram (XZ plan view) showing a first example of a package layout. In the semiconductor integrated circuit device 100 shown in this figure, the first chip 100a and the second chip 100b are mounted on island 100c.

[0122] First, the internal configurations of the first chip 100a and the second chip 100b will be described in detail with reference to the drawings. Figure 17 shows the internal configurations of the first chip 100a and the second chip 100b, and here an example based on the first embodiment (Figure 4) is shown.

[0123] The first chip 100a integrates an AC monitoring unit 110 and a DC monitoring unit 150. The first chip 100a is also provided with pads P1 to P5 as means for establishing electrical connections with the outside of the chip. Inside the first chip 100a, pad P1 is connected to the input terminal of the DC monitoring unit 150. Pad P2 is connected to the input terminal of the AC monitoring unit 110. Pad P3 is connected to the output terminal of the DC monitoring unit 150. Pad P4 is connected to the output terminal of the AC monitoring unit 110. Pad P5 is connected to the ground line.

[0124] On the other hand, the second chip 100b integrates a peak detection unit 120, a zero-crossing detection unit 130, a first output unit 140, a second output unit 160, and a voltage reduction protection unit 170. The second chip 100b is also provided with pads P6 to P12 as means for establishing an electrical connection with the outside of the chip. Inside the second chip 100b, pad P6 is connected to the input terminal of the second output unit 160. Pad P7 is connected to the input terminal of the peak detection unit 120. Pad P8 is connected to the ground line. Pad P9 is connected to the input terminal (=power line) of the voltage reduction protection unit 170. Pad P10 is connected to the ground line. Pad P11 is connected to the output terminal of the second output unit 160. Pad P12 is connected to the output terminal of the first output unit 140.

[0125] Furthermore, if the second embodiment (Figure 10) is used as the basis, the comparison unit 180 and the AC waveform determination unit 190 can also be integrated into the second chip 100b.

[0126] Returning to Figure 16, let's continue the explanation of the package layout. Pad P1 is connected to pin 5 (VHDC pin) via wire W1. Pad P2 is connected to pin 7 (VHAC pin) via wire W2. Pad P3 is connected to pad P6 via wire W3. Pad P4 is connected to pad P7 via wire W4. Pad P5 is connected to pad P8 via wire W5. Pad P9 is connected to pin 4 (VCC pin) via wire W6. Pad P10 is connected to pin 3 (GND pin) via wire W7. Pad P11 is connected to pin 2 (DCOUT pin) via wire W8. Pad P12 is connected to pin 1 (ACOUT pin) via wire W9.

[0127] Furthermore, focusing on the frame area inside the package, pins 1 (ACOUT pin), 4 (VCC pin), 5 (VHDC pin), and 7 (VHAC pin) are all larger than pins 2 (DCOUT pin), 3 (GND pin), and 6 (NC pin).

[0128] In other words, focusing on the X direction (= left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) have portions that protrude more than pins 2 (DCOUT pin) and 3 (GND pin). Similarly, pins 5 (VHDC pin) and 7 (VHAC pin) have portions that protrude more than pin 6 (NC pin).

[0129] Furthermore, focusing on the Z direction (the vertical direction of the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 100c. Similarly, pins 5 (VHDC pin) and 7 (VHAC pin) partially overlap with island 100c.

[0130] Furthermore, support frames 100e and 100f supporting the island 100c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC pin), and between pin 4 (VCC pin) and pin 5 (VHDC pin), respectively.

[0131] In this package layout, the first chip 100a is positioned closer to the second side (closer to pins 5-7) on island 100c, while the second chip 100b is positioned closer to the first side (closer to pins 1-4). By adopting this package layout, it is possible to lay wires W1-W9 as short as possible.

[0132] Next, we will explain why the semiconductor integrated circuit device 100 is configured as a two-chip system rather than a single-chip system. If the AC monitoring unit 110 and DC monitoring unit 150, which handle high voltages, and the other circuit units (120-140, 160, 170) that handle low voltages were to be configured as a single chip, it would be necessary to provide a buffer region between the high-voltage process region and the low-voltage process region. As a result, the chip size would become very large, leading to a significant increase in costs.

[0133] On the other hand, if the semiconductor integrated circuit device 100 is configured as a two-chip system, it becomes unnecessary to provide buffer regions for both the first chip 100a and the second chip 100b, thus reducing the chip size and ultimately lowering costs. Furthermore, since the first chip 100a and the second chip 100b are separated, it is also highly advantageous in terms of voltage resistance.

[0134] Next, let's explain the grounding route of the first chip 100a. Pin 3 (GND pin) is positioned between pin 2 (DCOUT pin) and pin 4 (VCC pin) as a shielding element to block noise propagation from pin 4 (VCC pin) to pin 2 (DCOUT pin) or pin 1 (ACOUT pin). Therefore, if we were to attempt to directly wire bond from pad P5 (=ground pad) of the first chip 100a to pin 3 (GND pin), it would inevitably interfere with wire W8 from pad P11 to pin 2 (DCOUT pin) of the second chip 100b, or wire W9 from pad P12 to pin 1 (ACOUT pin).

[0135] Therefore, the pad P5 (ground pad) of the first chip 100a is not directly bonded to pin 3 (GND pin), but is bonded to the pad P8 of the second chip 100b via wire W5. As shown in Figure 17 above, pad P8 is connected to the pad P10 (ground pad) of the second chip 100b via a GND line laid inside the second chip 100b, and further connected to pin 3 (GND pin) via wire W7. Thus, the ground line of the first chip 100a is connected to pin 3 (GND) via pad P5, wire W5, pad P8, the ground line laid inside the second chip 100b, pad P10, and wire W7. With this ground route, interference with wire W8 or W9 can be avoided.

[0136] Figure 18 is a schematic diagram showing the α-α' cross-section of Figure 16. When the semiconductor integrated circuit device 100 is cut along the α-α' line, it can be seen that a signal path is formed from pin 7 (VHAC pin) to pin 1 (ACOUT pin) via wire W2, pads P2 and P4 of the first chip 100a, wire W4, pads P7 and P12 of the second chip 100b, and wire W9.

[0137] Furthermore, this figure clearly shows that both the first chip 100a and the second chip 100b are placed on a common island 100c and are sealed with molding resin 100d.

[0138] Furthermore, this figure also reveals how the external terminals of the semiconductor integrated circuit device 100 are mounted on the copper wiring 210 of the printed circuit board 200 using solder 220.

[0139] <Package Layout (Example 2)> Figure 19 shows a second example of the package layout. As shown in this figure, the positional relationship between the first chip 100a and the second chip 100b along the Z-axis can be reversed compared to the first example (Figure 16).

[0140] More specifically, in the first example (Figure 16), the first chip 100a is positioned towards the top of the page on island 100c, and the second chip 100b is positioned towards the bottom of the page. In the second example (Figure 19), the first chip 100a is positioned towards the bottom of the page on the same island 100c, and the second chip 100b is positioned towards the top of the page.

[0141] Furthermore, when making the above-mentioned changes to the chip arrangement, it is desirable to appropriately modify the function of the pins and the arrangement of the pads, as shown in the diagram, so as not to interfere with the wire bonding process between the pins and pads.

[0142] Furthermore, focusing on the frame area inside the package, pins 1 (VCC pin), 4 (ACOUT pin), 5 (VHAC pin), and 7 (VHDC pin) are all larger than pins 2 (GND pin), 3 (DCOUT pin), and 6 (NC pin).

[0143] In other words, focusing on the X direction (left-right direction on the paper), pins 1 (VCC pin) and 4 (ACOUT pin) have portions that protrude more than pins 2 (GND pin) and 3 (DCOUT pin). Similarly, pins 5 (VHAC pin) and 7 (VHDC pin) have portions that protrude more than pin 6 (NC pin).

[0144] Furthermore, focusing on the Z direction (the vertical direction of the paper), pins 1 (VCC pin) and 4 (ACOUT pin) partially overlap with island 100c. Similarly, pins 5 (VHAC pin) and 7 (VHDC pin) partially overlap with island 100c.

[0145] Furthermore, support frames 100e and 100f supporting the island 100c are formed between pin 1 (VCC pin) and pin 7 (VHDC pin), and between pin 4 (ACOUT pin) and pin 5 (VHAC pin), respectively.

[0146] <Electronic Devices (Example 3 and Example 4 Configurations)> Figures 20 and 21 show the third configuration example (normal rectification method) and the fourth configuration example (voltage doubling rectification method) of the electronic device 10, respectively. Each configuration example of the electronic device 10 is based on the first configuration example (Figure 1) and the second configuration example (Figure 2), but differs in that the configuration of the zero-crossing detection circuit 18 has been modified and that it has an input reactor 19.

[0147] Therefore, for components similar to those in the first and second configuration examples, redundant explanations will be omitted by using the same reference numerals as in Figures 1 and 2. Below, we will focus on explaining the distinctive features of the third and fourth configuration examples.

[0148] As mentioned earlier, the zero-crossing detection circuit 18 is a circuit block that detects the zero-crossing of the AC voltage V0, and comprises a semiconductor integrated circuit device 300, externally connected diodes D11 and D12, and a capacitor C11.

[0149] The semiconductor integrated circuit device 300 is an IC or LSI formed by integrating at least a portion (details described later) of the circuit elements that form the zero-cross detection circuit 18, and has seven external terminals (pins 1 to 7) as means for establishing an electrical connection with the outside of the device.

[0150] Pin 1 (ACOUT pin) is the output terminal for the ACOUT signal S1 and is connected to the microcontroller 15. Pin 2 (NC pin) is an unused terminal and is not connected to anything outside the semiconductor integrated circuit device 300. Pin 3 (GND pin) is the ground terminal and is connected to the common ground terminal GND shared with the microcontroller 15. That is, the semiconductor integrated circuit device 300 (and by extension the zero-crossing detection circuit 18 using it) operates with the common ground voltage shared with the microcontroller 15 as the reference. Pin 4 (VCC pin) is the power terminal and is connected to the output terminal of the AC / DC converter 13 (= output terminal of the first DC voltage V3). Capacitor C11 is connected between pin 4 and pin 3.

[0151] Pin 5 (NC pin) is an unused terminal and is not connected to anything outside the semiconductor integrated circuit device 300. Pin 6 (VHAC2 pin) is the second AC input terminal and is connected to the cathode of diode D12 (corresponding to the application terminal of the monitored voltage V12). The anode of diode D12 is connected to terminal L1 (corresponding to the second node). Pin 7 (VHAC1 pin) is the first AC input terminal and is connected to the cathode of diode D11 (corresponding to the application terminal of the monitored voltage V11). The anode of diode D11 is connected to terminal N1 (corresponding to the first node).

[0152] Furthermore, if the rectifier section 12 employs a normal rectification method (Figure 20), the terminal voltages appearing at the L1 terminal and the N1 terminal will be equivalent. Therefore, there will be no problem even if the anode connections of diodes D11 and D12 are swapped.

[0153] Furthermore, the anode connections for diodes D11 and D12 are not necessarily limited to terminals L1 and N1. It is possible to draw the monitored voltages V11 and V12 from any node where an AC voltage V0 is applied across the input reactor 19, whether before or after it.

[0154] The input reactor 19 is provided for purposes such as improving the input power factor, reducing harmonics, or reducing motor noise. In this figure, an example is shown in which the input reactor 19 is provided before the filter 11 (on the L terminal side), but its position is not limited to this, and it may also be provided on the N terminal side or after the filter 11.

[0155] <Semiconductor integrated circuit device (5th embodiment)> Figure 22 shows a fifth embodiment of the semiconductor integrated circuit device 300. As shown in this figure, the semiconductor integrated circuit device 300 of this embodiment integrates an AC monitoring unit 310, a zero-crossing detection unit 320, a logic unit 330, a first output unit 340, a comparison unit 350, and a voltage reduction protection unit 360.

[0156] The AC monitoring unit 310 is a high-voltage (e.g., 650V withstand voltage) circuit that generates AC monitor signals SA1 and SA2, respectively, that are suitable for input to the zero-cross detection unit 320, from the monitored voltage V11 input to pin 7 (VHAC1 pin) and the monitored voltage V12 input to pin 6 (VHAC2 pin). The monitored voltages V11 and V12 correspond to the first monitored signal and the second monitored signal, respectively, input from terminals N1 and L1, to which an AC voltage V0 is applied, via diodes D11 and D12.

[0157] The zero-cross detection unit 320 compares the AC monitor signals SA1 and SA2 with each other to generate a comparison signal SB.

[0158] The logic unit 330 estimates the zero-crossing of the AC voltage V0 from the comparison signal SB and generates a zero-crossing detection signal SC. The logic unit 330 also has a function (= AC waveform determination function) that enables it to either stop generating or outputting the zero-crossing detection signal SC depending on the detection result of the comparison signal SD. This AC waveform determination function is basically the same as the function of the AC waveform determination unit 190 described earlier, so a redundant explanation is omitted here.

[0159] The first output unit 340 receives the zero-crossing detection signal SC as input, generates the ACOUT signal S1, and outputs it to pin 1 (ACOUT pin). The first output unit 340 should basically have the same configuration as the first output unit 140 in Figure 7. That is, by replacing "zero-crossing detection signal Sc" in Figure 7 with "zero-crossing detection signal SC," the configuration and operation of the first output unit 340 can be understood.

[0160] The comparison unit 350 generates multiple comparison signals SD by comparing the AC monitor signal SA1 with multiple thresholds. The comparison unit 350 can basically have the same configuration as the comparison unit 180 in Figure 10. That is, by replacing "AC monitor signal Sa" in Figure 10 with "AC monitor signal SA1" and "comparison signals Sd1~Sd4" with "comparison signals SD," the configuration and operation of the comparison unit 350 can be understood. The multiple thresholds compared with the AC monitor signal SA1 can include not only thresholds for instantaneous stop detection, but also, for example, thresholds for UVLO detection.

[0161] The undervoltage protection unit 360 is a protection function unit (so-called UVLO protection unit) that prohibits the operation of the semiconductor integrated circuit device 300 when the first DC voltage V3 input to pin 4 (VCC) falls below a lower limit.

[0162] <Zero-crossing detection unit (first embodiment)> Figure 23 shows a first embodiment of the zero-crossing detection unit 320. The zero-crossing detection unit 320 in this embodiment includes a comparator 321 that compares an AC monitor signal SA1 input to the non-inverting input terminal (+) with an AC monitor signal SA2 input to the inverting input terminal (-) to generate a comparison signal SB. The comparison signal SB becomes high when SA1 > SA2, and SA1 <SA2であるときにローレベルとなる。

[0163] The AC monitoring unit 310, located before the zero-cross detection unit 320, includes resistors 311 to 314. Resistors 311 and 312 are connected in series between pin 7 (VHAC1) and pin 3 (GND), and output an AC monitor signal SA1 (corresponding to the divided voltage of the monitored voltage V11) from their respective connection nodes. Resistors 313 and 334 are connected in series between pin 6 (VHAC2) and pin 3 (GND), and output an AC monitor signal SA2 (corresponding to the divided voltage of the monitored voltage V12) from their respective connection nodes.

[0164] In this diagram, for the sake of simplicity, only resistors 311-314 are shown as components of the AC monitoring unit 310. However, in reality, it is preferable to include various electrostatic protection elements, similar to the AC monitoring unit 110 in Figure 5.

[0165] <Zero-crossing detection process (Examples 1-3)> Next, the zero-crossing detection process of the semiconductor integrated circuit device 300 will be described. Figure 24 is a timing chart showing a first example of the zero-crossing detection process, in which the AC voltage V0, the monitored voltages V11 and V12, and the ACOUT signal S1 are depicted from top to bottom. In particular, this figure depicts the ideal state in which the monitored voltages V11 and V12 cross each other at the zero-crossing of the AC voltage V0.

[0166] The semiconductor integrated circuit device 300 pseudo-monitors the voltages at both ends of the AC voltage V0 (= the terminal voltages of the N1 terminal and the L1 terminal) as the monitored voltages V11 and V12, respectively, and switches the logic level of the ACOUT signal S1 according to the comparison result. Speaking in terms of this figure, the ACOUT signal S1 becomes high level when V11 > V12, and becomes low level when V11 < V12.

[0167] In this case, the rising timing of the ACOUT signal S1 substantially coincides with the timing when the AC voltage V0 switches from negative to positive (i.e., the zero crossing from negative to positive) (refer to times t41, t43, t45). On the other hand, the falling timing of the ACOUT signal S1 substantially coincides with the timing when the AC voltage V0 switches from positive to negative (i.e., the zero crossing from positive to negative) (refer to times t42, t44, t46).

[0168] FIG. 25 is a timing chart showing a second example of the zero-crossing detection process, and depicts, in order from the top, the AC voltage V0, the AC monitor signals SA1 (solid line) and SA2 (dashed line), and the comparison signal SB. Note that this figure shows the behavior when the double voltage rectification method (FIG. 21) is adopted in the rectifying section 12.

[0169] As shown in this figure, in the actual electronic device 10, due to the influence of the input reactor 19, the waveforms of the AC monitor signals SA1 and SA2 are greatly distorted. In particular, since the rising speed of the AC monitor signal SA1 is likely to vary according to the load Z, the rising timing of the comparison signal SB may vary greatly. On the other hand, since the falling speed of the AC monitor signal SA1 is less likely to vary regardless of the load Z, the falling timing of the comparison signal SB has relatively little variation.

[0170] In view of this, it is desirable that the logic section 330 detects the falling timing of the comparison signal SB (= the timing when switching from SA1 > SA2 to SA1 < SA2 as the AC monitor signal SA1 decreases), and estimates the zero crossing of the AC voltage V0 based on this.

[0171] Figure 26 is a timing chart showing a third example of the zero-crossing detection process. From top to bottom, it depicts the AC voltage V0, AC monitor signals SA1 (solid line) and SA2 (dashed line), comparison signal SB, edge detection signal EDGE (= internal signal of logic unit 330), and zero-crossing detection signal SC. Note that this figure shows the behavior when the voltage doubling rectification method (Figure 21) is employed in the rectifier unit 12.

[0172] As shown for each of the times t51 to t55, inside the logic unit 330, pulses of the edge detection signal EDGE are generated at each falling edge timing of the comparison signal SB. The logic unit 330 then counts the pulse interval of the edge detection signal EDGE (= period T of the comparison signal SB) and uses this count value to estimate the zero-crossing of the AC voltage V0.

[0173] More specifically, the logic unit 330, assuming that the period and phase of the AC voltage V0 are constant, determines the rising and falling timings of the zero-crossing detection signal SC by referring to the period T of the comparison signal SB.

[0174] For example, the logic unit 330 lowers the zero-cross detection signal SC from a high level to a low level when the comparison signal SB falls to a low level (for example, at time t53). The falling timing of this zero-cross detection signal SC roughly coincides with the timing when the AC voltage V0 switches from negative to positive (i.e., a zero-cross from negative to positive).

[0175] Furthermore, the logic unit 330 starts counting a waiting time T3 (for example, T3 = T / 2) corresponding to the previously acquired period T, from the moment the comparison signal SB falls to a low level. When the waiting time T3 has elapsed, it raises the zero-cross detection signal SC from a low level to a high level. The rising timing of this zero-cross detection signal SC almost coincides with the timing when the AC voltage V0 switches from positive to negative (i.e., a zero-cross from positive to negative).

[0176] <Zero-crossing detection unit (second embodiment)> Figure 27 shows a second embodiment of the zero-crossing detection unit 320. The zero-crossing detection unit 320 of this embodiment is based on the first embodiment (Figure 23) and further includes a comparator 322. The comparator 322 generates a comparison signal SB2 by comparing the AC monitor signal SA1 input to the non-inverting input terminal (+) with a predetermined threshold VTH (e.g., VTH = 20mV) input to the inverting input terminal (-). The comparison signal SB2 becomes high level when SA1 > VTH, and SA1 <VTHであるときにローレベルとなる。

[0177] The significance of introducing the comparator 322 will be explained below, with reference to the zero-crossing detection process of the semiconductor integrated circuit device 300.

[0178] <Zero-crossing detection process (Examples 4-6)> Figure 28 is a timing chart showing a fourth example of the zero-crossing detection process, depicting the AC voltage V0, AC monitor signals SA1 (solid line) and SA2 (dashed line), comparison signals SB and SB2, edge detection signal EDGE, and zero-crossing detection signal SC from top to bottom. Note that this figure shows the behavior when the voltage doubling rectification method (Figure 21) is employed in the rectifier unit 12.

[0179] As shown in this figure, when both AC monitor signals SA1 and SA2 drop to near 0V, the logic level of the comparison signal SB becomes undefined, which may cause chattering.

[0180] Therefore, when the AC monitor signal SA1 falls below a predetermined threshold VTH, the logic unit 330 counts the period T of the comparison signal SB2 instead of the comparison signal SB, and uses the count value to estimate the zero-crossing of the AC voltage V0.

[0181] Specifically, as shown for each of the times t61 to t65, the logic unit 330 generates pulses of the edge detection signal EDGE at each falling edge timing of the comparison signal SB2. The logic unit 330 then counts the pulse interval of the edge detection signal EDGE (= period T of the comparison signal SB2) and uses this count value to estimate the zero-crossing of the AC voltage V0.

[0182] For example, the logic unit 330 lowers the zero-crossing detection signal SC from a high level to a low level when the comparison signal SB2 falls to a low level (for example, at time t63). The falling timing of this zero-crossing detection signal SC approximately coincides with the timing when the AC voltage V0 switches from negative to positive (i.e., the zero-cross from negative to positive).

[0183] Furthermore, the logic unit 330 starts counting a waiting time T3 (for example, T3 = T / 2) corresponding to the previously acquired period T, from the moment the comparison signal SB2 falls to a low level. When the waiting time T3 has elapsed, it raises the zero-cross detection signal SC from a low level to a high level. The rising timing of this zero-cross detection signal SC almost coincides with the timing when the AC voltage V0 switches from positive to negative (i.e., a zero-cross from positive to negative).

[0184] Figures 29 and 30 are timing charts showing the fifth and sixth examples of the zero-crossing detection process, respectively. From top to bottom, they depict the AC voltage V0, AC monitor signals SA1 (solid line) and SA2 (dashed line), comparison signals SB and SB2, edge detection signal EDGE, and zero-crossing detection signal SC. Note that each figure shows the behavior when the voltage doubling rectification method (Figure 21) is employed in the rectifier unit 12.

[0185] As shown in both figures, the logic unit 330 is equipped with a masking function to prevent chattering of the comparison signal SB2. Specifically, the logic unit 330 ignores the falling edge of the comparison signal SB2 if, after the comparison signal SB2 falls from a high level to a low level, the comparison signal SB is not maintained at a low level for a predetermined masking period Tm.

[0186] By implementing this masking function, even if chattering occurs in the comparison signal SB2, unnecessary pulses are not generated in the edge detection signal EDGE, thus preventing interference with the zero-cross detection process of the AC voltage V0.

[0187] The length of the mask period Tm should be appropriately adjusted within the logic unit 330. Furthermore, the count start timing for the waiting time T3 may be set to the pulse generation timing of the edge detection signal EDGE instead of the falling edge timing of the comparison signal SB2. In this case, by setting the waiting time T3 to (T / 2-Tm), the rising edge timing of the zero-cross detection signal SC can be aligned with the zero-cross of the AC voltage V0.

[0188] <Electronic equipment (5th configuration example)> Figure 31 shows a fifth configuration example of the electronic device 10 (normal rectification method, single-sided relay). This configuration example of the electronic device 10 is based on the third configuration example (Figure 20), but differs in that it has a relay switch 20 on the N terminal side. Therefore, for components that are the same as in the third configuration example, the same reference numerals as in Figure 20 are used to omit redundant explanations, and the following will focus on explaining the distinctive features of the fifth configuration example.

[0189] As shown in this figure, in the electronic device 10 of this configuration example, the relay switch 20 is turned off and the N terminal is opened when the power supply is cut off. At this time, if the L1 terminal and the N1 terminal are completely isolated, even if an AC voltage V0 is continuously applied to the L1 terminal, the N1 terminal will remain in a high impedance state, so the monitored voltages V11 and V12 will not be at the same potential.

[0190] However, in reality, some kind of leakage path (=resistive component R) exists between terminals L1 and N1. Therefore, after the relay switch 20 is turned off, the monitored voltages V11 and V12 become the same potential (in phase), which can cause chattering in the comparison signal SB and potentially produce an unintended pulse output in the ACOUT signal S1.

[0191] Although this diagram uses the case where the rectifier unit 12 employs a normal rectification method as an example, the same problems described above may occur even if the rectifier unit 12 employs a voltage doubler rectification method.

[0192] <Semiconductor integrated circuit device (6th embodiment)> Figure 32 shows a sixth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the fifth embodiment (Figure 22) described earlier, but further includes an input stop detection unit 370. Therefore, for components similar to those of the fifth embodiment, the same reference numerals as in Figure 22 are used to omit redundant explanations, and the following will focus on describing the characteristic parts of this embodiment.

[0193] The input stop detection unit 370 includes an offset power supply 371 and a comparator 372.

[0194] The offset power supply 371 raises the AC monitor signal SA1 by a predetermined offset voltage Vofs (for example, Vofs = 20V to 40V) and outputs it to the comparator 372.

[0195] Comparator 372 generates an input stop detection signal SE by comparing the offset AC monitor signal (SA1+Vofs) input to the non-inverting input terminal (+) with the AC monitor signal SA2 input to the inverting input terminal (-). Therefore, the input stop detection signal SE becomes high when (SA1+Vofs) > SA2, and (SA1+Vofs) <SA2であるときにローレベルとなる。

[0196] In other words, after the relay switch 20 is turned off, when the AC monitor signals SA1 and SA2 are in phase (or at the same potential), (SA1 + Vofs) > SA2 will always be true, so the input stop detection signal SE will not fall to a low level.

[0197] The logic unit 330 detects that the input stop detection signal SE is maintained at a high level and fixes the zero-cross detection signal SC at a high level. As a result, even if unintended chattering occurs in the comparison signal SB, the ACOUT signal S1 can be fixed at a low level. Therefore, it is possible to reliably stop the pulse output of the ACOUT signal S1 after the relay switch 20 is turned off.

[0198] Furthermore, the logic unit 330 is configured to ignore the rising edge of the input stop detection signal SE if the input stop detection signal SE is not maintained at a high level for a predetermined mask period Tmask(>T) even after the input stop detection signal SE has risen to a high level.

[0199] With this configuration, as long as the relative high and low levels of the AC monitor signals SA1 and SA2 are periodically inverted, the zero-cross detection signal SC will not be fixed at a high level, and therefore the normal output operation of the ACOUT signal S1 will not be affected.

[0200] <Output pulse stop processing> Figure 33 is a timing chart showing an example of output pulse stop processing when the power supply is cut off. From top to bottom, it depicts the AC monitor signals SA1 (solid line) and SA2 (dashed line), the zero-crossing detection signal SC, and the input stop detection signal SE.

[0201] Before time t91, relay switch 20 is turned on. Therefore, the high-low relationship between AC monitor signals SA1 and SA2 is periodically reversed, and periodic pulses are generated in the zero-cross detection signal SC and the input stop detection signal SE, respectively. As mentioned earlier, unless the input stop detection signal SE is maintained at a high level for the mask period Tmask (>T), the zero-cross detection signal SC will not be fixed at a high level.

[0202] At time t91, when relay switch 20 is turned off, AC monitor signals SA1 and SA2 become in phase, so the input stop detection signal SE no longer falls to a low level. However, since the mask period Tmask has not elapsed at this point, the zero-crossing detection signal SC is not fixed at a high level.

[0203] Subsequently, with the input stop detection signal SE remaining at a high level, and the mask period Tmask elapsed at time t92, the zero-cross detection signal SC is fixed at a high level based on the determination that AC monitor signals SA1 and SA2 are in phase. Therefore, it becomes possible to reliably stop the pulse output of ACOUT signal S1.

[0204] Although the semiconductor integrated circuit device 300 of this embodiment is based on the fifth embodiment (Figure 22), the zero-crossing detection method is not restricted when introducing the input stop detection unit 370. For example, the zero-crossing detection unit 320 and logic unit 330 in Figure 32 can be replaced with the peak detection unit 120 and zero-crossing detection unit 130 in Figure 4. In such a case, only one of the AC monitor signals SA1 and SA2 (for example, AC monitor signal SA1) needs to be input to the peak detection unit 120.

[0205] <Package Layout (Example 3)> Figure 34 is a diagram (XZ plan view) showing a third example of the package layout in the semiconductor integrated circuit device 300. In the semiconductor integrated circuit device 300 shown in this figure, the first chip 300a and the second chip 300b are mounted on the island 300c.

[0206] First, the internal configurations of the first chip 300a and the second chip 300b will be described in detail with reference to the drawings. Figure 35 shows the internal configurations of the first chip 300a and the second chip 300b, and here an example based on the fifth embodiment (Figure 22) is shown.

[0207] The first chip 300a integrates the AC monitoring unit 310. The first chip 300a is also provided with pads P21 to P25 as means for establishing electrical connections with the outside of the chip. Inside the first chip 300a, pad P21 is connected to the first input terminal of the AC monitoring unit 310 (corresponding to the input terminal of the monitored voltage V11). Pad P22 is connected to the second input terminal of the AC monitoring unit 310 (corresponding to the input terminal of the monitored voltage V12). Pad P23 is connected to the first output terminal of the AC monitoring unit 310 (corresponding to the output terminal of the AC monitor signal SA1). Pad P24 is connected to the second output terminal of the AC monitoring unit 310 (corresponding to the output terminal of the AC monitor signal SA2). Pad P25 is connected to the ground line.

[0208] On the other hand, the second chip 300b integrates a zero-cross detection unit 320, a logic unit 330, a first output unit 340, a comparison unit 350, and a voltage reduction protection unit 360. The second chip 300b is also provided with pads P26 to P31 as means for establishing an electrical connection with the outside of the chip. Inside the second chip 300b, pad P26 is connected to the first input terminal of the zero-cross detection unit 320 (corresponding to the input terminal of the AC monitor signal SA1). Pad P27 is connected to the second input terminal of the zero-cross detection unit 320 (corresponding to the input terminal of the AC monitor signal SA2). Pad P28 is connected to the ground line. Pad P29 is connected to the input terminal (power line) of the voltage reduction protection unit 360. Pad P30 is connected to the ground line. Pad P31 is connected to the output terminal of the first output unit 340.

[0209] Furthermore, if the sixth embodiment (Figure 32) is used as the basis, the input stop detection unit 370 can also be integrated into the second chip 300b.

[0210] Returning to Figure 34, let's continue the explanation of the package layout. Pad P21 is connected to pin 7 (VHAC1 pin) via wire W21. Pad P22 is connected to pin 6 (VHAC2 pin) via wire W22. Pad P23 is connected to pad P26 via wire W23. Pad P24 is connected to pad P27 via wire W24. Pad P25 is connected to pad P28 via wire W25. Pad P29 is connected to pin 4 (VCC pin) via wire W26. Pad P30 is connected to pin 3 (GND pin) via wire W27. Pad P31 is connected to pin 1 (ACOUT pin) via wire W28.

[0211] Furthermore, focusing on the frame area inside the package, pins 1 (ACOUT pin), 4 (VCC pin), 5 (NC pin), and 7 (VHAC1 pin) are all larger than pins 2 (NC pin), 3 (GND pin), and 6 (VHAC2 pin).

[0212] In other words, focusing on the X direction (= left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) have portions that protrude more than pins 2 (NC pin) and 3 (GND pin). Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) have portions that protrude more than pin 6 (VHAC2 pin).

[0213] Furthermore, focusing on the Z direction (vertical direction of the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 300c. Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) partially overlap with island 300c.

[0214] Furthermore, support frames 300e and 300f supporting the island 300c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC1 pin), and between pin 4 (VCC pin) and pin 5 (NC pin), respectively.

[0215] The relative positions of each chip, the advantages of the two-chip configuration, and the grounding route of the first chip 300a are as described in the first example (Figure 16) and the second example (Figure 19) above, so we will omit any redundant explanations.

[0216] <Package Layout (Example 4)> Figure 36 is a diagram (XZ plan view) showing a fourth example of the package layout in the semiconductor integrated circuit device 300. In this semiconductor integrated circuit device 300, as in the third example (Figure 34), the first chip 300a and the second chip 300b are mounted on island 300c. In addition, in this semiconductor integrated circuit device 300, the number of package pins has been increased from "7" to "11" due to the incorporation of a DC monitoring unit (details will be described later).

[0217] First, the internal configurations of the first chip 300a and the second chip 300b will be described in detail with reference to the drawings. Figure 37 shows the internal configurations of the first chip 300a and the second chip 300b, and here a configuration is shown that is based on the fifth embodiment (Figure 22) with the addition of a DC monitoring unit 380 and a second output unit 390.

[0218] The internal configurations of the first chip 300a and the second chip 300b are basically the same as those shown in Figure 35. Therefore, the following explanation will focus on the changes from Figure 35.

[0219] The first chip 300a newly integrates a DC monitoring unit 380. The DC monitoring unit 380 is a high-voltage (e.g., 650V withstand voltage) circuit block that generates a DC monitor signal Sx from the rectified voltage V1 input to the 9th pin (VHDC pin), and corresponds to the DC monitoring unit 150 in the first to fourth embodiments.

[0220] Furthermore, pads P32 and P33 are added to the first chip 300a due to the integration of the DC monitoring unit 380. Inside the first chip 300a, pad P32 is connected to the input terminal of the DC monitoring unit 380. Pad P33 is connected to the output terminal of the DC monitoring unit 380.

[0221] On the other hand, the second chip 300b newly integrates a second output unit 390. The second output unit 390 is a circuit block that receives the input of a DC monitor signal Sx, generates a DCOUT signal S2, and outputs it to pin 4 (DCOUT pin), and corresponds to the second output unit 160 in the first to fourth embodiments.

[0222] Furthermore, the second chip 300b has additional pads P34 and P35 added to accommodate the integration of the second output unit 390. Inside the second chip 300b, pad P34 is connected to the input terminal of the second output unit 390. Pad P35 is connected to the output terminal of the second output unit 390.

[0223] Returning to Figure 36, let's continue the explanation of the package layout. Pad P21 is connected to pin 11 (VHAC1 pin) via wire W21. Pad P22 is connected to pin 10 (VHAC2 pin) via wire W22. Pad P23 is connected to pad P26 via wire W23. Pad P24 is connected to pad P27 via wire W24. Pad P25 is connected to pad P28 via wire W25. Pad P29 is connected to pin 7 (VCC pin) via wire W26. Pad P30 is connected to pin 5 (GND pin) via wire W27. Pad P31 is connected to pin 3 (ACOUT pin) via wire W28. Pad P32 is connected to pin 9 (VHDC pin) via wire W29. Pad P33 is connected to pad P34 via wire W30. Pad P35 is connected to pin 4 (DCOUT pin) via wire W31.

[0224] Furthermore, focusing on the frame area inside the package, both the 2-pin (NC pin) and 6-pin (NC pin) packages are larger than the 3-pin (ACOUT pin), 4-pin (DCOUT pin), and 5-pin (GND pin) packages.

[0225] In other words, focusing on the X direction (= left-right direction on the paper), pins 2 (NC pin) and 6 (NC pin) have portions that protrude more than pins 3 (ACOUT pin), 4 (DCOUT pin), and 5 (GND pin).

[0226] Furthermore, focusing on the Z direction (= vertical direction of the paper), pins 2 (NC pin) and 6 (NC pin) do not overlap with island 100c. Similarly, pins 1 (NC pin), 7 (VCC pin), 8 (NC pin), and 11 (VHAC1 pin) also do not overlap with island 100c.

[0227] Furthermore, between pin 1 (N.C. pin) and pin 11 (VHAC1 pin), and between pin 7 (VCC pin) and pin 8 (N.C. pin), support frames 300e and 300f for supporting island 300c are respectively formed.

[0228] <AC Monitoring Unit and DC Monitoring Unit> Figure 38 is a diagram showing a configuration example of the AC monitoring unit 310 and the DC monitoring unit 380 in the aforementioned Figure 37. The AC monitoring unit 310 of this configuration example includes resistors 311a to 315a and 311b to 315b, NMOSFETs 316a and 316b, PMOSFETs 317a and 317b, and fuses 318a and 318b.

[0229] Resistors 311a to 315a are connected in series in the order shown between pad P21 (VHAC1 pad) and pad P25 (GND pad). The connection node between resistor 313a and resistor 314a is connected to pad P23 (ACIN1 pad). That is, resistors 311a to 315a function as a voltage dividing circuit that divides the monitored voltage V11 (= first monitored signal) input to pad P21 to generate an AC monitor signal SA1.

[0230] On the other hand, resistors 311b to 315b are connected in series in the order shown between pad P22 (VHAC2 pad) and pad P25 (GND pad). The connection node between resistor 313b and resistor 314b is connected to pad P24 (ACIN2 pad). That is, resistors 311b to 315b function as a voltage dividing circuit that divides the monitored voltage V12 (= second monitored signal) input to pad P22 to generate an AC monitor signal SA2.

[0231] Of the resistors 311a-315a and 311b-315b, resistors 311a and 311b correspond to the first feedback resistors. Resistors 312a-315a and 312b-315b correspond to the second feedback resistors. In particular, the resistance values ​​of resistors 312a and 315a, and resistors 312b and 315b, among the second feedback resistors, can be arbitrarily adjusted by trimming using fuses 318a and 318b.

[0232] The drain of the NMOSFET316a is connected to pad P21. The source, gate, and back gate of the NMOSFET316a are connected to pad P25. The drain of the PMOSFET317a is connected to pad P25. The source, gate, and back gate of the PMOSFET317a are connected to pad P23.

[0233] The drain of the NMOSFET316b is connected to pad P22. The source, gate, and back gate of the NMOSFET316b are connected to pad P25. The drain of the PMOSFET317b is connected to pad P25. The source, gate, and back gate of the PMOSFET317b are connected to pad P22.

[0234] The NMOSFETs 316a and 316b, as well as the PMOSFETs 317a and 317b, connected in this manner, all function as electrostatic protection elements.

[0235] On the other hand, the DC monitoring unit 380 in this configuration example includes resistors 381 to 385, an NMOSFET 386, a PMOSFET 387, and a fuse 388.

[0236] Resistors 381 to 385 are connected in series between pad P32 (VHDC pad) and pad P25 (GND pad) in the order shown in the diagram. The connection node between resistors 383 and 384 is connected to pad P33 (DCIN pad). In other words, resistors 381 to 385 function as a voltage divider circuit that divides the rectified voltage V1 (= third monitored signal) input to pad P32 to generate the DC monitor signal Sx.

[0237] Of the resistors 381 to 385, resistor 381 corresponds to the first feedback resistor, and resistors 382 to 385 correspond to the second feedback resistors. In particular, the resistance values ​​of resistors 382 and 385, which are part of the second feedback resistors, can be arbitrarily adjusted by trimming using fuse 388.

[0238] The drain of the NMOSFET386 is connected to pad P32. The source, gate, and back gate of the NMOSFET386 are connected to pad P25. The drain of the PMOSFET387 is connected to pad P25. The source, gate, and back gate of the PMOSFET387 are connected to pad P33.

[0239] The NMOSFET386 and PMOSFET387 (and their associated body diodes) connected in this manner function as electrostatic protection elements.

[0240] <Chip layout (first chip)> Figure 39 shows the layout of the first chip 300a. Note that the wiring laid on the first chip 300a is omitted from the illustration to avoid complexity. Furthermore, for convenience, the positional relationships of pads and elements will be explained below by defining the top, bottom, left, and right directions of the paper as the top, bottom, left, and right directions in a plan view of the first chip 300a.

[0241] The first chip 300a is cut into a rectangular shape (more precisely, a slightly horizontally elongated rectangle) in which the ratio of the short sides (right and left sides) to the long sides (top and bottom sides) is approximately equal when viewed from above.

[0242] In a plan view of the first chip 300a, region A1 (= region corresponding to approximately the left half of the first chip 300a) has three high-voltage regions 400X to 400Z (details described later) arranged vertically on the first chip 300a. Each of the high-voltage regions 400X to 400Z has a pair of resistor 311a and pad P21 (VHAC1), a pair of resistor 311b and pad P22 (VHAC2), and a pair of resistor 381 and pad P32 (VHDC), respectively.

[0243] On the other hand, in a plan view of the first chip 300a, region A2 (= region corresponding to approximately the right half of the first chip 300a) has pads P23~P25 and P33, resistors 312a~315a, 312b~315b and 382~385, NMOSFETs 316a, 316b and 386, PMOSFETs 317a, 317b and 387, and fuses 318a, 318b and 388 formed therein.

[0244] Pads P23-P25 and P33 are formed in a plan view of the first chip 300a slightly above the vertical center of the first chip 300a (= on the extension of the boundary line of the high-voltage region 400Y and 400Z extended to the right), and are arranged in the left-right direction of the first chip 300a. The arrangement order of each pad can be, for example, arranged from left to right on the page as pads P33 (DCIN), P24 (ACIN2), P23 (ACIN1), and P25 (GND). Furthermore, the distance between pads P23 and P25 should be wider than the distance between pads P23 and P24, and between pads P24 and P33.

[0245] Resistors 312a to 315a are formed at positions closer to the lower side of the first chip 300a than pads P23 to P25 and P33 in a plan view of the first chip 300a, and at positions adjacent to the right side of the high breakdown voltage region 400X (more specifically, at positions slightly closer to the upper side than the vertical center of the high breakdown voltage region 400X). Also, when focusing on the left-right direction of the paper surface, resistors 312a to 315a are formed from a position substantially flush with the left side of pad P33 (DCIN) to a position substantially flush with the left side of pad P23 (ACIN1) in a plan view of the first chip 300a.

[0246] Resistors 312b to 315b are formed at positions closer to the lower side of the first chip 300a than pads P23 to P25 and P33 in a plan view of the first chip 300a (more specifically, at positions sandwiched between pads P23 to P25 and P33 and resistors 312a to 315a), and at positions adjacent to the right side of the high breakdown voltage region 400Y (more specifically, at positions closer to the lower side of the high breakdown voltage region 400Y). Also, when focusing on the left-right direction of the paper surface, resistors 312b to 315b are formed from a position substantially flush with the left side of pad P33 (DCIN) to a position substantially flush with the left side of pad P23 (ACIN1) in a plan view of the first chip 300a, similar to resistors 312a to 315a.

[0247] Resistors 382 to 385 are formed at positions closer to the upper side of the first chip 300a than pads P23 to P25 and P33 in a plan view of the first chip 300a, and at positions adjacent to the right side of the high breakdown voltage region 400Z (more specifically, at positions closer to the upper side of the high breakdown voltage region 400Z). Also, when focusing on the left-right direction of the paper surface, resistors 382 to 385 are formed from a position substantially flush with the left side of pad P33 (DCIN) to a position substantially flush with the left side of pad P23 (ACIN1) in a plan view of the first chip 300a, similar to resistors 312a to 315a and 312b to 315b.

[0248] Furthermore, resistors 312a and 315a, resistors 312b and 315b, and resistors 382 and 385 each contain multiple unit resistors, and their connection state (number of series or parallel connections) can be arbitrarily switched by using fuses 318a, 318b, and 388.

[0249] NMOSFETs 316a, 316b, and 386 are formed in a plan view of the first chip 300a, arranged vertically on the first chip 300a. Referring to this figure, NMOSFET 316a is located below pad P25, and NMOSFET 316b is located above pad P25. NMOSFET 386 is located even higher above NMOSFET 316b (= upper right corner of the first chip 300a).

[0250] PMOSFET 317a is located approximately midway between pad P23 and the bottom edge of the first chip 300a in a plan view of the first chip 300a. On the other hand, PMOSFET 317b is located between pad P33 and the high-voltage region 400Y in a plan view of the first chip 300a. Furthermore, PMOSFET 387 is located between pad P33 and the high-voltage region 400Z in a plan view of the first chip 300a. Note that PMOSFETs 317b and 387 are formed side by side in the vertical direction of the first chip 300a.

[0251] Fuses 318a, 318b, and 388 are formed in a plan view of the first chip 300a, arranged in the vertical direction of the first chip 300a. Referring to this figure, fuse 318a is located between PMOSFET 317a and the lower edge of the first chip 300a, fuse 318b is located between pad P23 and PMOSFET 317a, and fuse 388 is located between pad P23 and the upper edge of the first chip 300a. Fuses 318a, 318b, and 388 can each be understood as a group of fuse elements containing multiple fuse elements.

[0252] Furthermore, it is desirable to use polysilicon resistors with a voltage rating of 100V or higher (e.g., 650V) as resistors 311a, 311b, and 381 to which high voltages are applied. In particular, when integrating the above resistors, it is necessary to increase the voltage rating not only of the path through each resistor (lateral direction) but also of the path between each resistor and the semiconductor substrate (vertical direction).

[0253] Therefore, it is desirable to form three high-voltage regions 400X to 400Z, which have a higher withstand voltage in the substrate thickness direction (vertical direction) than other regions, on the first chip 300a where the AC monitoring unit 310 and the DC monitoring unit 380 are integrated, and to form resistors 311a and 311b, and resistor 381 on each of the high-voltage regions 400X to 400Z.

[0254] Furthermore, for the three high-voltage regions 400X to 400Z mentioned above, the LDMOSFET (lateral double-diffused MOSFET) region, which has a proven track record in high-voltage applications, can be utilized. The structure of the LDMOSFET region will be explained in detail below.

[0255] <High voltage range (LDMOSFET range)> Figures 40 and 41 are a longitudinal section and a top view, respectively, showing an example structure of the first chip 300a (particularly the area around the feedback resistor formation region located in the center of the high-voltage regions 400X to 400Z). The longitudinal section in Figure 40 schematically shows the α1-α2 section in Figure 41.

[0256] The first chip 300a in this figure has a p-type semiconductor substrate 410, on which an LDMOSFET region is formed that is used as a high-voltage region 400 (corresponding to the previously mentioned high-voltage regions 400X to 400Z). More specifically, in the central part of the high-voltage region 400, the p-type semiconductor substrate 410 has a low-concentration n-type semiconductor region 411 and a high-concentration p-type semiconductor region 412 surrounding it. The breakdown voltage in the substrate thickness direction in the high-voltage region 400 increases as the impurity concentration of the low-concentration n-type semiconductor region 411 decreases or its thickness increases.

[0257] A high-concentration n-type semiconductor region 413 is formed in the low-concentration n-type semiconductor region 411, and a high-concentration n-type semiconductor region 414 is formed in the high-concentration p-type semiconductor region 412. These high-concentration n-type semiconductor regions 413 and 414 correspond to the drain region (D) and source region (S) of the LDMOSFET, respectively. As shown in Figure 41, the high-voltage region 400 has multiple concentric annular drain regions (D) and source regions (S) alternately formed in its plan view.

[0258] Furthermore, a field oxide film 415 is formed on the outer surface of the low-concentration n-type semiconductor region 411, surrounding the high-concentration n-type semiconductor region 413. In addition, a gate oxide film 416 is formed on the surface of the p-type semiconductor substrate 410, extending between the high-concentration n-type semiconductor region 414 and the field oxide film 415. A gate region 417 made of polysilicon is formed on the gate oxide film 416.

[0259] Furthermore, a field plate 418 made of polysilicon is formed on the field oxide film 415 as a means to equalize the electric field distribution (= spacing of equipotential lines) and prevent breakdown due to pressure.

[0260] Furthermore, directly beneath the field oxide film 415, a low-concentration p-type semiconductor region 419 is formed as a means for forming parasitic capacitance between the field oxide film 415 and the low-concentration n-type semiconductor region 411. With this configuration, the breakdown voltage in the substrate thickness direction can be increased by the amount of the holding voltage of the parasitic capacitance.

[0261] Furthermore, a field oxide film 402 is formed on the central surface layer of the low-concentration n-type semiconductor region 411, which is surrounded by a high-concentration n-type semiconductor region 413 (corresponding to the innermost drain region (D)), and the feedback resistor 401 (= resistor 311a or 311b, or resistor 381) is formed on this field oxide film 402. Note that the feedback resistor 401 may be formed using the same polysilicon layer as the gate region 417 and the field plate 418.

[0262] Furthermore, in the example shown in this figure, both ends of the feedback resistor 401 are connected to the first metal layer 1M via vias, and the first metal layer 1M is connected to the second metal layer 2M via vias. For example, pad 403 (= pad P21 or P22, or pad P32) can be formed on the second metal layer 2M. However, the number of metal layers is not limited to this, and there may be only one layer or three or more layers.

[0263] Furthermore, the feedback resistor 401 can be formed by combining multiple unit resistors 401(1) to 401(m) (where m≧2), as shown in Figure 41. For example, if the resistance value of each unit resistor is 1MΩ, and the combined resistance of the feedback resistor 401 is to be 10MΩ, then 10 unit resistors can be connected in series.

[0264] In this way, by reusing the LDMOSFET region (for example, 600V withstand voltage) as the high-voltage region 400, it is possible to achieve a high voltage resistance between the feedback resistor 401 and the p-type semiconductor substrate 410.

[0265] <Chip layout (second chip)> Figure 42 shows the layout of the second chip 300b. For convenience, the positional relationships of pads and circuit blocks will be explained below by defining the top, bottom, left, and right directions of the paper as the top, bottom, left, and right directions in a plan view of the second chip 300b.

[0266] In addition, in this figure, in addition to the pads P26 to P31 and P34 to P35 already described in FIG. 37, pads P41 to P49 for chip testing are newly depicted. The pads P41 to P49 will be briefly described. Pads P41 (SCANIN), P42 (SCANMODE), P43 (SCANCLK), P44 (SCANRST), P45 (SCANEN), and P49 (SCANOUT) are a set of pads for scan path testing (test signal input pads, mode switching signal input pads, clock signal input pads, reset signal input pads, enable signal input pads, and test signal output pads). Pad P46 (TSD) is a temperature protection signal output pad. Pad P47 (VCLA) is a test voltage application pad for analog circuits. Pad P48 (VCLD) is a test voltage application pad for digital circuits.

[0267] In its plan view, the second chip 300b is cut out in a vertically long rectangular shape where the right and left sides are longer than the upper and lower sides.

[0268] In the plan view of the second chip 300b, in the vicinity of the left side of the second chip 300b, pads P34 (DCIN), P27 (ACIN2), P26 (ACIN1), P28 (GND), P31 (ACOUT), and P49 (SCANOUT) are formed side by side in the vertical direction in order from the upper side of the paper surface.

[0269] On the other hand, in the plan view of the second chip 300b, in the vicinity of the right side of the second chip 300b, pads P41 (SCANIN), P42 (SCANMODE), P43 (SCANCLK), P44 (SCANRST), P45 (SCANEN), P46 (TSD), P47 (VCLA), and P48 (VCLD) are formed side by side in the vertical direction in order from the upper side of the paper surface.

[0270] Furthermore, in a plan view of the second chip 300b, near the bottom edge of the second chip 300b, pads P35 (DCOUT), P30 (GND), and P29 (VCC) are formed in a horizontal direction, starting from the left side of the paper.

[0271] Pads P26 and P27 should be placed adjacent to each other. The distance between pads P27 and P34 should be wider than the distance between pads P26 and P27. Pad P28 (GND) should be placed between pad P26 (ACIN1) and pad P31 (ACOUT). Pad P30 (GND) should be placed between pad P29 (VCC) and pad P35 (DCOUT). Electrostatic discharge protection elements (28VPD or EBZ) are formed directly beneath pads P26-P28, P31, and P34-P35, respectively. TEST blocks (test circuits) are formed between pads P41 and P42, and between pads P43 and P44, respectively.

[0272] In a plan view of the second chip 300b, the vicinity of pads P26~P28, P31 and P34 (excluding the pad formation area, the area occupying approximately the left 1 / 4 and upper 3 / 4 of the second chip 300b) contains the following blocks: ACDET block (corresponding to the comparison unit 350), ACMON block (an RC filter provided before the ZERODET block, not explicitly shown in Figure 37), ZERODET block (corresponding to the zero-cross detection unit 320), ZERODET02V block (corresponding to the input stop detection unit 370), and ACOUT block (corresponding to the first output unit 340).

[0273] The ACMON block, ZERODET block, and ZERODET02V block are all formed in a vertically elongated region extending from a position adjacent to pad P26 to a position adjacent to pad P31. Furthermore, the ACMON block, ZERODET block, and ZERODET02V block are formed side by side in the left-right direction of the second chip 300b.

[0274] The ACDET block is formed in the region sandwiched between the upper edges of the ACMON block, ZERODET block, and ZERODET02V block and the upper edge of the second chip 300b. The area of ​​the ACDET block is larger than the area of ​​each of the ACMON block, ZERODET block, and ZERODET02V block.

[0275] The ACOUT block is formed in a curved region extending from the bottom edge of the ACMON block, ZERODET block, and ZERODET02V block to the left edge of the second chip 300b. In other words, a portion of the ACOUT block is formed in the region sandwiched between pads P31 and P49.

[0276] The DCOUT block is formed in the vicinity of pad P35 (DCOUT) (i.e., the horizontally elongated region enclosed by pads P35, P30, and P49). The area of ​​the DCOUT block is larger than the area of ​​the ACOUT block.

[0277] The LOGIC block (corresponding to the previously mentioned logic section 330) is formed in the upper right region of the second chip 300b (excluding the pad formation region, this region occupies approximately 3 / 4 of the right side and 4 / 7 of the upper side of the second chip 300b). The area of ​​the LOGIC block is larger than the area of ​​any other block.

[0278] In a plan view of the second chip 300b, the area where the above-mentioned blocks (ACDET, ACMON, ZERODET, ZERODET02V, ACOUT, DCOUT, and LOGIC) are not formed (= an area occupying approximately 3 / 4 of the right side and 3 / 7 of the bottom side of the second chip 300b) is formed a BGR block that generates a bandgap reference voltage, a VREFAMP block that generates an internal reference voltage from the bandgap reference voltage, a VREFDET block that monitors the internal reference voltage (= corresponding to the undervoltage protection unit 360), an IREF block that generates an internal reference current, an OSC block that supplies a clock signal to the LOGIC block, and a FUSE block that sets the operation of the LOGIC block.

[0279] <Package Layout (Example 5)> Figure 43 is a diagram (XZ plan view) showing a fifth example of the package layout in the semiconductor integrated circuit device 300. In the semiconductor integrated circuit device 300 shown in this figure, the package layout (third example) in Figure 34 is used as a base, with the first chip 300a in Figure 39 and the second chip 300b in Figure 42 mounted on the island 300c.

[0280] Specifically, in this figure, the first chip 300a from Figure 39 is mounted in the upper right region of island 300c, rotated 180° clockwise (or counterclockwise). Also, in this figure, the second chip 300b from Figure 42 is mounted in the lower left region of island 300c, rotated 90° clockwise.

[0281] Pad P21 (VHAC1) is connected to the tip of pin 7 (VHAC1) via wire W21. Pad P22 (VHAC2) is connected to pin 6 (VHAC2) via wire W22. Pad P23 (ACIN1) is connected to pad P26 (ACIN1) via wire W23. Pad P24 (ACIN2) is connected to pad P27 (ACIN2) via wire W24. Pad P25 (GND) is connected to pad P28 (GND) via wire W25. Pad P33 (DCIN) is connected to pad P34 (DCIN) via wire W30. Pad P29 (VCC) is connected to the tip of pin 4 (VCC) via wire W26. Pad P30 (GND) is connected to pin 3 (GND) via wire W27. Pad P31 (ACOUT) is connected to the tip of pin 1 (ACOUT) via wire W28.

[0282] In the semiconductor integrated circuit device 300 shown in this figure, the DC voltage monitoring function is not used, so pads P32 (VHDC) and P35 (DCOUT) are not connected to any pins. On the other hand, pads P33 (DCIN) and P34 (DCIN) are connected via wire W30. Therefore, for example, following Figure 37 above, if you connect pad P32 (VHDC) to the unused 5 pins with wire W29, and connect pad P35 (DCOUT) to the unused 2 pins with wire W30, you can use the DC voltage monitoring function.

[0283] Furthermore, the pads P23-P25 and P33 of the first chip 300a and the pads P26-P28 and P34 of the second chip 300b are arranged in a corresponding order in the left-right direction (X-axis direction) of the paper. Therefore, the wires W23-W25 and W30 between each pad can be laid at the shortest distance without crossing.

[0284] Furthermore, the pads P21-P22 and P32 of the first chip 300a are arranged in the vertical direction (Z-axis direction) of the paper in an order corresponding to the 7-pin (VHAC1 pin), the 6-pin (VHAC2 pin), and the 5-pin (the pin that becomes the VHDC pin when the DC voltage monitoring function is used), respectively. Therefore, the wires W21-W22 (and wire W29 when the DC voltage monitoring function is used) between the pins and pads can be laid over the shortest distance without crossing each other.

[0285] Similarly, pads P29-P30 and P35 of the second chip 300b are arranged in the vertical direction (Z-axis direction) of the paper in an order corresponding to 4 pins (VCC pin), 3 pins (GND pin), and 2 pins (which become DCOUT pins when the DC voltage monitoring function is used), respectively. Therefore, the pin-pad wires W26-W27 (and wire W29 when the DC voltage monitoring function is used) can be laid along the shortest distance without crossing.

[0286] Note that the chip test pads P41-P49 are not used after packaging into the semiconductor integrated circuit device 300, and therefore are not connected to any of the pins.

[0287] Furthermore, focusing on the frame area inside the package, pins 1 (ACOUT pin), 4 (VCC pin), 5 (NC pin), and 7 (VHAC1 pin) are all larger than pins 2 (NC pin), 3 (GND pin), and 6 (VHAC2 pin).

[0288] In other words, focusing on the X direction (= left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) have portions that protrude more than pins 2 (NC pin) and 3 (GND pin). Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) have portions that protrude more than pin 6 (VHAC2 pin).

[0289] Furthermore, focusing on the Z direction (vertical direction of the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 300c. Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) partially overlap with island 300c.

[0290] Furthermore, support frames 300e and 300f supporting the island 300c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC1 pin), and between pin 4 (VCC pin) and pin 5 (NC pin), respectively.

[0291] <Package Layout (Example 6)> Figure 44 is a diagram (XZ plan view) showing a sixth example of the package layout in the semiconductor integrated circuit device 300. In the semiconductor integrated circuit device 300 shown in this figure, the package layout (fourth example) in Figure 36 is used as a base, and, as in the fifth example (Figure 43), the first chip 300a in Figure 39 and the second chip 300b in Figure 42 are mounted on the island 300c.

[0292] Specifically, in this figure, the first chip 300a from Figure 39 is mounted in the upper left-right central region of island 300c (a position shifted closer to the left-right center of island 300c compared to Figure 43) after being rotated 180° clockwise (or counterclockwise). Also, in this figure, the second chip 300b from Figure 42 is mounted in the lower left region of island 300c (a position shifted closer to the top-bottom center of island 300c compared to Figure 43) after being rotated 90° clockwise.

[0293] Pad P21 (VHAC1) is connected to pin 11 (VHAC1) via wire W21. Pad P22 (VHAC2) is connected to pin 10 (VHAC2) via wire W22. Pad P32 (VHDC) is connected to pin 9 (VHDC) via wire W29. Pad P23 (ACIN1) is connected to pad P26 (ACIN1) via wire W23. Pad P24 (ACIN2) is connected to pad P27 (ACIN2) via wire W24. Pad P25 (GND) is connected to pad P28 (GND) via wire W25. Pad P33 (DCIN) is connected to pad P34 (DCIN) via wire W30. Pad P29 (VCC) is connected to the tip side of pin 7 (VCC) via wire W26. Pad P30 (GND) is connected to pin 5 (GND) via wire W27. Pad P35 (DCOUT) is connected to pin 4 (DCOUT) via wire W31. Pad P31 (ACOUT) is connected to the tip of pin 3 (ACOUT) via wire W28.

[0294] Furthermore, the pads P23-P25 and P33 of the first chip 300a and the pads P26-P28 and P34 of the second chip 300b are arranged in a corresponding order in the left-right direction (X-axis direction) of the paper. Therefore, the wires W23-W25 and W30 between each pad can be laid at the shortest distance without crossing. This is the same as in Figure 43 above.

[0295] Furthermore, the pads P21-P22 and P32 of the first chip 300a are arranged in the vertical direction (Z-axis direction) of the paper in an order corresponding to the 11 pins (VHAC1 pin), 10 pins (VHAC2 pin), and 9 pins (VHDC pin), respectively. Therefore, the wires W21-W22 and W29 between the pins and pads can be laid at the shortest distance without crossing.

[0296] Similarly, pads P29-P30 and P35 of the second chip 300b are arranged in the vertical direction (Z-axis direction) of the paper in an order corresponding to the 7-pin (VCC pin), 5-pin (GND pin), and 4-pin (DCOUT pin), respectively. Therefore, the pin-pad wires W26-W27 and W31 can be laid along the shortest distance without crossing.

[0297] Note that the chip test pads P41-P49 are not used after packaging into the semiconductor integrated circuit device 300, and therefore are not connected to any pins. This is the same as in Figure 43 above.

[0298] Furthermore, focusing on the frame area inside the package, both the 2-pin (NC pin) and 6-pin (NC pin) packages are larger than the 3-pin (ACOUT pin), 4-pin (DCOUT pin), and 5-pin (GND pin) packages.

[0299] In other words, focusing on the X direction (= left-right direction on the paper), pins 2 (NC pin) and 6 (NC pin) have portions that protrude more than pins 3 (ACOUT pin), 4 (DCOUT pin), and 5 (GND pin).

[0300] Furthermore, focusing on the Z direction (= vertical direction of the paper), pins 2 (NC pin) and 6 (NC pin) do not overlap with island 100c. Similarly, pins 1 (NC pin), 7 (VCC pin), 8 (NC pin), and 11 (VHAC1 pin) also do not overlap with island 100c.

[0301] Furthermore, support frames 300e and 300f are formed between pin 1 (NC pin) and pin 11 (VHAC1 pin), and between pin 7 (VCC pin) and pin 8 (NC pin), respectively, to support island 300c.

[0302] <Pin configuration> Figure 45 is a plan view showing the pin configuration of a semiconductor integrated circuit device 300 using a 7-pin package (Figure 43). On the left side of the package, starting from the top of the page, pins 1 (ACOUT), 2 (NC), 3 (GND), and 4 (VCC) are derived. On the right side of the package, starting from the bottom of the page, pins 5 (NC), 6 (VHAC2), and 7 (VHAC1) are derived.

[0303] Furthermore, it is desirable that the distance w11 between pin 7 (VHAC1) and pin 6 (VHAC2), to which high voltage is applied, be wider than the distance w12 between pins 1 to 4 and the distance w13 between pins 5 and 6. For example, in the example shown in this figure, the distance w11 between pins 6 and 7 is widened by removing the external terminal that would normally be provided between pins 6 and 7 (= the pin opposite pin 2).

[0304] Furthermore, the lengths of pins 1-4 derived from the left side of the package and the lengths of pins 5-7 derived from the right side of the package do not necessarily have to be the same. For example, as shown in this figure, pins 5-7 may be derived to be longer than pins 1-4.

[0305] Figure 46 is a plan view showing the pin configuration of a semiconductor integrated circuit device 300 using an 11-pin package (Figure 44). In this example, the left side of the package has pins 1 (NC), 2 (NC), 3 (ACOUT), 4 (DCOUT), 5 (GND), 6 (NC), and 7 (VCC) derived from the top of the page. On the other hand, the right side of the package has pins 8 (NC pin), 9 (VHDC), 10 (VHAC2), and 11 (VHAC1) derived from the bottom of the page.

[0306] Furthermore, it is desirable that the terminal distances w21 between pin 11 (VHAC1) and pin 10 (VHAC2), w22 between pin 10 (VHAC2) and pin 9 (VHDC), and w23 between pin 9 (VHDC) and pin 8 (NC), to which high voltage is applied, be wider than the terminal distances w24 between pins 1 to 7. For example, in the example shown in this figure, by removing the external terminals that would normally be provided between pins 8 and 9, between pins 9 and 10, and between pins 10 and 11 (= pins opposite pins 2, 4, and 6 respectively), the terminal distances w23 between pins 8 and 9, w22 between pins 9 and 10, and w21 between pins 10 and 11 are widened, respectively.

[0307] Furthermore, the lengths of pins 1 through 7 derived from the left side of the package and the lengths of pins 8 through 11 derived from the right side of the package do not necessarily have to be the same. For example, as shown in this figure, pins 8 through 11 may be derived to be shorter than pins 1 through 7.

[0308] Additionally, pins 1 through 11 should be shaped so that their bases become thinner.

[0309] <Input offset and signal delay> Next, we will examine the input offset and signal delay of the zero-cross detection unit 320 with reference to Figures 47 to 49. Figures 47 to 49 are diagrams showing the generation operation of the comparison signal SB in the zero-cross detection unit 320, and depict the AC monitor signals SA1 (solid line) and SA2 (dashed line) and the comparison signal SB in order from the top of the page.

[0310] Figures 47 to 49 show the behavior under the first condition (no input offset, no signal distortion), the second condition (no input offset, signal distortion present), and the third condition (input offset, signal distortion present), respectively.

[0311] As shown in Figure 47, in applications where distortion is unlikely to occur in the AC monitor signals SA1 and SA2 (i.e., hair dryers that drive motors with low current), chattering of the comparison signal SB is unlikely to occur even without input offset to the zero-crossing detection unit 320. Therefore, there is no signal delay in the zero-crossing detection unit 320, and the logic level of the comparison signal SB switches without delay each time the AC monitor signals SA1 and SA2 cross.

[0312] On the other hand, as shown in Figure 48, in applications where distortion is likely to occur in the AC monitor signals SA1 and SA2 (such as washing machines that drive motors with high current), if an input offset is not applied to the zero-cross detection unit 320, there is a risk of chattering occurring in the comparison signal SB near the zero-cross timing.

[0313] As shown in Figure 49, if an input offset (for example, an input offset SA1_ofs that shifts the AC monitor signal SA1 to the positive side) is applied to the zero-crossing detection unit 320, chattering of the comparison signal SB can be avoided even if distortion occurs in the AC monitor signals SA1 and SA2. However, if an input offset is applied to the zero-crossing detection unit 320, the logic switching timing of the comparison signal SB (and consequently the detection result of the zero-crossing timing) will be delayed by a delay time Td.

[0314] In particular, the delay time Td is known to be dependent on the monitored voltage V11 (and consequently the AC voltage V0) applied to the VHAC1 pin, which may interfere with the operation of the application. Below, we propose a novel embodiment to resolve this problem.

[0315] <Semiconductor integrated circuit device (7th embodiment)> Figure 50 shows a seventh embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the previously shown Figure 37 (= fifth embodiment (Figure 22) + DC monitor function + 11-pin package), but further includes a delay adjustment unit 510 and a control unit 520. Therefore, redundant explanations of previously mentioned components are omitted by using the same reference numerals as in Figure 37, and the following will focus on describing the characteristic parts of this embodiment.

[0316] The delay adjustment unit 510 is located downstream of the logic unit 330 and adjusts the delay time Td of the zero-crossing detection signal SC (hereinafter referred to as the zero-crossing delay time Td) according to the delay adjustment amount Td_adj instructed by the control unit 520.

[0317] The control unit 520 sets the delay adjustment amount Td_adj based on multiple comparison signals SD (=logic signals that reflect the peak value of the monitored voltage V11, and consequently the peak value of the AC voltage V0) output from the comparison unit 350. The control unit 520 also has a function to switch the input offset SA1_ofs of the zero-cross detection unit 320 based on the multiple comparison signals SD.

[0318] Figure 51 shows the process by which the delay adjustment unit 510 and the control unit 520 suppress fluctuations in the zero-crossing delay time Td. From the top of the page, the zero-crossing delay time Td, the delay adjustment amount Td_adj, and the input offset SA1_ofs are depicted in order.

[0319] The horizontal axis of this figure represents the peak value of the terminal voltage VHAC1 (which corresponds to the peak value of the monitored voltage V11 applied to the VHAC1 pin, and consequently, the peak value of the AC voltage V0). The threshold voltages VthH, VthM, and VthL compared to this are assumed to satisfy the condition VthH > VthM > VthL.

[0320] Furthermore, regarding the zero-crossing delay time Td, the solid line L1 shows the behavior when switching control of the delay adjustment amount Td_adj and input offset SA1_ofs is implemented. On the other hand, the dashed line L2 shows the behavior when switching control of the delay adjustment amount Td_adj and input offset SA1_ofs is not implemented (when Td_adj=0 and SA1_ofs=+OFS). The dashed line L3 shows the behavior when no input offset SA1_ofs is applied (when Td_adj=0 and SA1_ofs=0).

[0321] If switching control of the delay adjustment amount Td_adj and input offset SA1_ofs is not performed, the zero-crossing delay time Td increases as the terminal voltage VHAC1 decreases, as shown by the dashed line L2, and deviates from the predetermined target zero-crossing delay time Td_target.

[0322] In contrast, when switching control of the delay adjustment amount Td_adj and input offset SA1_ofs is implemented, the zero-crossing delay time Td is maintained at a predetermined target zero-crossing delay time Td_target (or a nearby value), as shown by the solid line L1.

[0323] Specifically described in accordance with this figure, for example, in voltage range (I) where VthH < VHAC1, Td_adj = 0 (no delay adjustment) and SA1_ofs = +OFS (with input offset) are set. In this voltage range (I), since the zero-crossing delay time Td is not adjusted, the solid line L1 shows the same behavior as the dashed line L2. That is, the zero-crossing delay time Td increases as the terminal voltage VHAC1 decreases, deviating from the target zero-crossing delay time Td_target. However, in voltage range (I), the degree of deviation from the target zero-crossing delay time Td_target is not so large, so there is no particular problem.

[0324] On the other hand, in voltage range (II) where VthM < VHAC1 < VthH, Td_adj = -ADJ1 (small delay adjustment) and SA1_ofs = +OFS (with input offset) are set. That is, the zero-crossing delay time Td (solid line L1) after delay adjustment is expressed as Td = Td0 - ADJ1 (where Td0 is the zero-crossing delay time (dashed line L2) before delay adjustment).

[0325] Also, in voltage range (III) where VthL < VHAC1 < VthM, Td_adj = -ADJ2 (large delay adjustment) and SA1_ofs = +OFS (with input offset) are set. That is, the zero-crossing delay time Td (solid line L1) after delay adjustment is expressed as Td = Td0 - ADJ2 (where ADJ2 > ADJ1).

[0326] Of course, the zero-crossing delay time Td (solid line L1) after delay adjustment also varies depending on the terminal voltage VHAC1, similar to the zero-crossing delay time Td0 (dashed line L2) before delay adjustment. However, since it is shifted to the negative side by the delay adjustment amount Td_adj, the degree of deviation from the target zero-crossing delay time Td_target is kept small.

[0327] Furthermore, in the voltage range (IV) where VHAC1 < VthL, Td_adj = 0 (no delay adjustment) and SA1_ofs = 0 (no input offset) are set. Thus, in the voltage range (IV) where the deviation from the target zero-crossing delay time Td_target cannot be suppressed within the desired range even with delay adjustment, the application of the input offset SA1_ofs itself is stopped. As a result, the signal delay in the zero-crossing detection unit 320 disappears, and the zero-crossing delay time Td no longer deviates from the target zero-crossing delay time Td_target.

[0328] In applications where the AC monitor signals SA1 and SA2 are less likely to be distorted, without depending on the peak value of the terminal voltage VHAC1, both the delay adjustment amount Td_adj and the input offset SA1_ofs are fixed to zero values, and as shown by the dashed-dotted line L3, the zero-crossing delay time Td may be maintained at the target zero-crossing delay time Td_target.

[0329] <Semiconductor Integrated Circuit Device (Eighth Embodiment)> FIG. 52 is a diagram showing an eighth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the previously described seventh embodiment (FIG. 50), and six pins are used as delay setting terminals DSET. Therefore, for the components already described, the same reference numerals as in FIG. 50 are given to omit duplicate explanations, and hereinafter, the characteristic parts of this embodiment will be mainly described.

[0330] Inside the semiconductor integrated circuit device 300, an internal resistor 531 (resistance value: R1) is connected between the application terminal of the internal reference voltage VREF and the delay setting terminal DSET. Also, outside the semiconductor integrated circuit device 300, an external resistor 532 (resistance value: R2) is connected between the delay setting terminal DSET and the ground terminal. Therefore, at the delay setting terminal DSET, a terminal voltage VDSET (= α × VREF) obtained by dividing the internal reference voltage VREF by a predetermined voltage division ratio α (= R2 / (R1 + R2)) appears.

[0331] The control unit 520 has a function of arbitrarily setting the target zero-crossing delay time Td_target according to the terminal voltage VDSET (equivalent to the delay setting signal).

[0332] FIG. 53 is a diagram showing an example of arbitrarily setting the target zero-crossing delay time Td_target. In this figure, the horizontal axis represents the terminal voltage VDSET. For the threshold voltages VH, VM, and VL to be compared with this, it is assumed that VREF > VH > VM > VL (for example, VREF = 3.0V, VH = 2.5V, VM = 1.0V, VL = 0.3V) holds.

[0333] Specifically described in accordance with this figure, in the voltage range (i) where VH < VDSET, Td_target is set to 0. In order for the terminal voltage VDSET to fall within the voltage range (i), for example, the delay setting terminal DSET may be opened (VDSET ≈ 3.0V).

[0334] Also, in the voltage range (ii) where VM < VDSET < VH, Td_target is set to -2X (for example, X = 200 [μs]). In order for the terminal voltage VDSET to fall within the voltage range (ii), for example, an external resistor 532 of 330 kΩ may be connected to the internal resistor 531 of 280 kΩ (VDSET ≈ 1.6V).

[0335] Also, in the voltage range (iii) where VL < VDSET < VM, Td_target is set to -1X. In order for the terminal voltage VDSET to fall within the voltage range (iii), for example, an external resistor 532 of 68 kΩ may be connected to the internal resistor 531 of 280 kΩ (VDSET ≈ 0.6V).

[0336] Also, in the voltage range (iv) where VDSET < VL, Td_target is set to +1X. In order for the terminal voltage VDSET to fall within the voltage range (iv), for example, the delay setting terminal DSET may be shorted to GND (VDSET ≈ 0V).

[0337] Incidentally, in the logic section 330, as described above, the crossing timing of the AC monitor signals SA1 and SA2 in the previous cycle is detected, and the timing control of the zero-crossing detection signal SC in the next cycle is performed (see FIG. 26, etc.). Therefore, it is also possible to set the target zero-crossing delay time Td_target to a negative value (<0) as described above.

[0338] Note that the arbitrary setting function of the target zero-crossing delay time Td_target (eighth embodiment) does not necessarily have to be introduced in combination with the fluctuation suppression function of the zero-crossing delay time Td (seventh embodiment), and each can be introduced independently.

[0339] Also, in this embodiment, an example in which the target zero-crossing delay time Td_target is switched in four steps according to the terminal voltage VDSET is given, but the number of switching steps is arbitrary.

[0340] <ACOUT Output Waveform> Next, consider the output waveform of the ACOUT signal S1. The output format of the ACOUT signal S1 may be a rectangular waveform (FIG. 54) in which the logic level alternates every zero-crossing timing of the AC voltage V0, or an edge type (FIG. 55) in which a trigger pulse having a predetermined pulse width tw is generated every zero-crossing timing of the AC voltage V0.

[0341] <Semiconductor Integrated Circuit Device (Ninth Embodiment)> FIG. 56 is a diagram showing a ninth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the previously shown FIG. 37 (= fifth embodiment (FIG. 22) + DC monitor function + 11-pin package), and two pins are used as output mode setting terminals MODE. Therefore, for the existing components, the same reference numerals as in FIG. 37 are given to omit the overlapping description, and hereinafter, the characteristic parts of this embodiment will be mainly described.

[0342] The logic unit 330 has a function to switch the output format of the ACOUT signal S1 between a square wave type (Figure 54) and an edge type (Figure 55) depending on the input signal to the output mode setting terminal MODE. The input signal to the output mode setting terminal MODE may be an analog signal or a digital signal.

[0343] Furthermore, while the seventh embodiment (Figure 50), the eighth embodiment (Figure 52), and the ninth embodiment (Figure 56) described above all use Figure 37 as a basis, other embodiments may also be used as a basis. For example, when adopting the seventh to ninth embodiments, the presence or absence of a DC monitor function and the number of pins in the package are not relevant at all.

[0344] <Summary> The various embodiments disclosed herein will be described in general below.

[0345] For example, the zero-cross detection circuit disclosed herein includes a peak detection unit that detects the peak of a signal to be monitored, which is input via a diode from the application terminal of an AC signal, and generates a peak detection signal, and a zero-cross detection unit that estimates the zero-cross of the AC signal from the peak detection signal and generates a zero-cross detection signal.

[0346] Furthermore, the zero-cross detection circuit having the above configuration may further include a monitoring unit that adapts the monitored signal to the input to the peak detection unit.

[0347] Furthermore, in the zero-crossing detection circuit having the above configuration, the zero-crossing detection unit may count the period of the peak detection signal and use the count value to estimate the zero-crossing of the AC signal.

[0348] Furthermore, the zero-cross detection circuit having the above configuration may further include a comparison unit that compares the monitored signal with a plurality of thresholds to generate a plurality of comparison signals, and a waveform determination unit that detects whether both a rising edge and a falling edge occurred in at least one comparison signal during one cycle of the zero-cross detection signal and generates a waveform determination signal.

[0349] Furthermore, in the zero-cross detection circuit having the above configuration, the zero-cross detection unit may stop generating or outputting the zero-cross detection signal when the waveform determination signal is at the logic level for abnormal detection.

[0350] Furthermore, in the zero-crossing detection circuit having the above configuration, the zero-crossing detection unit may ignore the logic level change if the logic level after the peak detection signal has been switched is not maintained for a predetermined period of time.

[0351] Furthermore, for example, the zero-cross detection circuit disclosed herein includes a zero-cross detection unit that generates a first comparison signal by comparing a first monitored signal and a second monitored signal input via diodes from a first node and a second node to which AC signals are applied, respectively, and a logic unit that generates a zero-cross detection signal by estimating the zero-cross of the AC signal from the first comparison signal.

[0352] Furthermore, the zero-cross detection circuit having the above configuration may further include a monitoring unit that adapts the first monitored signal and the second monitored signal to the input to the zero-cross detection unit.

[0353] Furthermore, in the zero-crossing detection circuit having the above configuration, the logic unit may count the period of the first comparison signal and use the count value to estimate the zero-crossing of the AC signal.

[0354] Furthermore, in the zero-crossing detection circuit having the above configuration, the zero-crossing detection unit further generates a second comparison signal by comparing the first monitored signal with a predetermined threshold, and the logic unit, when the first monitored signal falls below the threshold, counts the period of the second comparison signal instead of the first comparison signal, and uses the count value to estimate the zero-crossing of the AC signal.

[0355] Furthermore, in the zero-cross detection circuit having the above configuration, the logic unit may ignore the logic level change if the logic level after the switch is not maintained for a predetermined period of time after the logic level of the second comparison signal has been switched.

[0356] Furthermore, the zero-cross detection circuit having the above configuration may further include a control unit that sets a delay adjustment amount based on the peak value of the AC signal, and a delay adjustment unit that adjusts the delay time of the zero-cross detection signal according to the delay adjustment amount.

[0357] Furthermore, in the zero-crossing detection circuit having the above configuration, the control unit should increase the delay adjustment amount as the peak value of the AC signal decreases.

[0358] Furthermore, in the zero-crossing detection circuit having the above configuration, the control unit may switch the input offset of the zero-crossing detection unit based on the peak value of the AC signal.

[0359] Furthermore, in the zero-cross detection circuit having the above configuration, the control unit may set both the delay adjustment amount and the input offset to zero when the peak value of the AC signal is lower than a predetermined threshold.

[0360] Furthermore, the zero-cross detection circuit having the above configuration may further include a comparison unit that generates a plurality of comparison signals by comparing the first monitored signal or its divided voltage signal with a plurality of thresholds, and the control unit may accept input of the plurality of comparison signals having logic values ​​that reflect the peak value of the AC signal.

[0361] Furthermore, in the zero-cross detection circuit having the above configuration, the control unit may include a function to fix both the delay correction amount and the input offset to zero, regardless of the peak value of the AC signal.

[0362] Furthermore, the zero-cross detection circuit having the above configuration may further include a control unit that sets the delay time of the zero-cross detection signal according to the delay setting signal.

[0363] Furthermore, in the zero-cross detection circuit having the above configuration, the delay setting signal is an analog signal having a voltage value corresponding to the resistance value of an external resistor, and the control unit may stepwise switch the delay time according to the comparison result between the analog signal and the threshold.

[0364] Furthermore, in the zero-cross detection circuit having the above configuration, the zero-cross detection signal may be a square wave type in which the logic level alternately switches at each zero-cross timing of the AC signal, or an edge type in which a trigger pulse with a predetermined pulse width is generated at each zero-cross timing of the AC signal.

[0365] Furthermore, in the zero-cross detection circuit having the above configuration, the logic unit may switch the output format of the zero-cross detection signal between the square wave type and the edge type according to the output mode setting signal.

[0366] Furthermore, for example, the zero-cross detection circuit disclosed herein includes a logic unit that generates a zero-cross detection signal by estimating the zero-cross of the AC signal in accordance with at least one of a first monitored signal and a second monitored signal input via diodes from a first node and a second node to which an AC signal is applied between them, and an input stop detection unit that generates an input stop detection signal by adding an offset to one of the first monitored signal and the second monitored signal and comparing them with each other, wherein the logic unit fixes the logic level of the zero-cross detection signal in accordance with the input stop detection signal.

[0367] In the zero-cross detection circuit having the above configuration, the logic unit may ignore the logic level change if the logic level after the input stop detection signal has been switched is not maintained for a predetermined period of time.

[0368] Furthermore, the zero-cross detection circuit having the above configuration may further include a zero-cross detection unit that compares the first monitored signal and the second monitored signal to generate a comparison signal, and the logic unit may estimate the zero-cross of the AC signal from the comparison signal.

[0369] Furthermore, the zero-cross detection circuit having the above configuration may further include a monitoring unit that adapts the first monitored signal and the second monitored signal to the input to the zero-cross detection unit.

[0370] Furthermore, in the zero-crossing detection circuit having the above configuration, the logic unit may count the period of the comparison signal and use the count value to estimate the zero-crossing of the AC signal.

[0371] Furthermore, for example, the semiconductor integrated circuit device disclosed herein is comprised of an integrated circuit comprising at least a portion of the circuit elements that form a zero-cross detection circuit having the above configuration.

[0372] In a semiconductor integrated circuit device having the above configuration, it is desirable that the distance between the first external terminal for receiving the signal to be monitored and the adjacent second external terminal be greater than the distance between other external terminals.

[0373] Furthermore, the semiconductor integrated circuit device having the above configuration may further integrate an AC / DC converter that generates a first DC voltage from the AC voltage input as the AC signal.

[0374] Furthermore, the semiconductor integrated circuit device having the above configuration may further integrate a DC / DC converter that generates a second DC voltage from the first DC voltage.

[0375] Furthermore, the semiconductor integrated circuit device having the above configuration may be formed by encapsulating a first chip, which integrates a monitoring unit that adapts the monitored signal to the input to the peak detection unit, and a second chip, which integrates the peak detection unit and the zero-crossing detection unit, with a molding resin.

[0376] Furthermore, the electronic equipment disclosed herein includes a rectifier unit that generates a rectified voltage by normally rectifying or voltage-doubling an AC voltage, a zero-cross detection circuit that detects the zero-cross of the AC voltage, and a microcontroller that performs drive control of a load according to the detection result of the zero-cross detection circuit, wherein the zero-cross detection circuit is a zero-cross detection circuit having the above configuration, or a zero-cross detection circuit formed using a semiconductor integrated circuit device having the above configuration.

[0377] In the electronic device having the above configuration, the rectifier section includes a first capacitor and a second capacitor connected in series between the output terminal and the ground terminal of the rectified voltage, and the connection node between them is preferably connected to the second node from which the second monitored signal is drawn.

[0378] In the electronic device having the above configuration, the zero-cross detection circuit is preferably operated with reference to a ground voltage common to the microcontroller.

[0379] Furthermore, in the electronic device having the above configuration, the load may be a motor or a triac.

[0380] <Note A> A note is added regarding Figures 39 to 42 mentioned earlier. The first chip, which integrates the monitoring unit that adapts the first and second monitored signals to the input to the zero-cross detection unit, should be cut into a rectangular shape in its plan view, where the ratio of the short side to the long side is approximately equal.

[0381] Furthermore, the first chip may have a high-voltage region with a higher voltage withstand capability in the substrate thickness direction (vertical direction) than other regions, and a first pad to which the first and second monitored signals are input, and a first feedback resistor connected thereto may be formed above the high-voltage region.

[0382] Furthermore, the above-mentioned high-voltage regions may be formed in multiple locations along the first edge of the first chip in a plan view of the first chip. In addition, these multiple high-voltage regions (for example, the first high-voltage region, the second high-voltage region, and the third high-voltage region) may be concentrated and formed in the first region of the first chip (for example, half of the first chip) in a plan view of the first chip.

[0383] On the other hand, in a plan view of the first chip, a second pad for outputting a signal from the monitoring unit to the zero-cross detection unit and a second feedback resistor connected thereto, a third pad connected to the ground terminal, an electrostatic protection element for protecting each pad, and a fuse for adjusting the resistance value of the second feedback resistor may be formed in the second region of the first chip (for example, the remaining half of the first chip).

[0384] Furthermore, the second and third pads should be formed in multiple locations along the second edge of the first chip, perpendicular to the first edge, in a plan view of the first chip. In particular, the second and third pads should be formed in a plan view of the first chip, closer to the second edge than the center of the first edge, and aligned along the second edge. In addition, the distance between the second and third pads should be wider than the distance between multiple second pads.

[0385] Furthermore, the second feedback resistor is preferably formed in a position adjacent to the high-voltage region in a plan view of the first chip.

[0386] Furthermore, it is desirable to use a polysilicon resistor with a voltage rating of 100V or higher (for example, 650V) as the first feedback resistor to which a high voltage is applied.

[0387] Furthermore, it is desirable that the high-voltage region be the LDMOSFET region.

[0388] Furthermore, in the LDMOSFET region, multiple concentric annular drain regions and source regions are alternately formed in a plan view of the first chip, and the first feedback resistor is preferably formed on the field oxide film surrounded by the innermost drain region.

[0389] Furthermore, the first and second feedback resistors may each be composed of a combination of multiple unit resistors.

[0390] On the other hand, the second chip, which integrates the zero-cross detection unit, is preferably cut into a long rectangular shape in its plan view.

[0391] Furthermore, the multiple pads connected to the first chip are preferably formed in a line near the first edge of the second chip when viewed from above.

[0392] On the other hand, multiple pads that are not connected to the first chip may be formed in a plan view of the second chip, arranged near the second edge opposite the first edge of the second chip.

[0393] Furthermore, the first pad, into which the divided voltage signal of the first monitored signal is input, and the second pad, into which the divided voltage signal of the second monitored signal is input, should be provided adjacent to each other.

[0394] Furthermore, the distance between the third pad and the second pad, to which the divided signal of the third monitored signal is input, should be wider than the distance between the first pad and the second pad.

[0395] Furthermore, it is preferable to provide a fifth pad connected to ground potential between the first pad and the fourth pad that outputs the ACOUT signal.

[0396] Furthermore, it is preferable to provide an eighth pad connected to ground potential between the sixth pad, which outputs the DCOUT signal, and the seventh pad, which is connected to the power supply potential.

[0397] Furthermore, it is preferable to form an electrostatic protection element directly beneath each of the first to sixth pads.

[0398] Furthermore, the test circuit is preferably formed between the first test pad and the second test pad.

[0399] Furthermore, the comparison unit, RC filter, zero-crossing detection unit, input stop detection unit, and first output unit are preferably formed in the vicinity of the first to fifth pads in a plan view of the second chip.

[0400] Furthermore, the second output section may be formed in the vicinity of the sixth pad in a plan view of the second chip.

[0401] <Note B> Next, let's add some notes to Figures 43 and 44 mentioned earlier. The pads of the first and second chips should be connected via corresponding pins and wires.

[0402] Regardless of whether the DC voltage monitoring function is used or not, it is recommended to connect the DCIN pin of the first chip to the DCIN pin of the second chip.

[0403] Furthermore, the multiple output pads and ground pads of the first chip, and the multiple input pads and ground pads of the second chip connected to them respectively, should be arranged in a corresponding order.

[0404] <Note C> Next, we will add some notes regarding Figures 45 and 46 mentioned earlier. For the semiconductor integrated circuit device, for example, a 7-pin package or an 11-pin package may be used.

[0405] Furthermore, it is advisable to derive the pins to which high voltage is not applied from the first side of the package, and the pins to which high voltage is applied from the second side of the package.

[0406] Furthermore, it is desirable to increase the distance between pins to which high voltage is applied compared to the distance between pins to which high voltage is not applied.

[0407] Furthermore, the length of the pins derived from the first side of the package and the length of the pins derived from the second side of the package do not necessarily have to be the same. For example, the pins on the second side may be derived to be longer than the pins on the first side. Conversely, the pins on the second side may be derived to be shorter than the pins on the first side.

[0408] Additionally, each pin may be shaped so that its base tapers.

[0409] <Other variations> In the above embodiment, an example was given in which the motor drive control is performed according to the detection result of the zero-cross detection circuit. However, the application of the zero-cross detection circuit is not limited to this, and it can also be suitably used in power supply devices that detect the zero-cross of an AC voltage and control the drive of a triac.

[0410] Thus, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation.

[0411] For example, mutual substitution between bipolar transistors and MOS field-effect transistors, and logic level inversion of various signals are optional. In other words, the above embodiments should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the above embodiments. [Industrial applicability]

[0412] The zero-cross detection circuits disclosed herein can be used, for example, for drive control of motors or triacs. [Explanation of symbols]

[0413] 10 Electronic equipment 11 filters 12 Rectifier 12a~12d diodes 12e~12g Capacitor 13 AC / DC Converters 13a, 13b resistance 13c Error Amplifier 13d Comparator 13e RS Flip-Flop 13f Level Shifter 13g NMOSFET 13h coil 13i diode 14 DC / DC Converters 15 Microcontrollers 16 drivers 17 Motor 18. Zero-crossing detection circuit 19 Input reactor 20 Relay Switches 100 Semiconductor integrated circuit devices (zero-cross ICs) 100a First Chip 100b Second chip 100c Island 100d mold resin 100e, 100f support frame 110 AC monitoring section 111-115 Resistors 116 NMOSFET 117 PMOSFET 118 diodes 120 Peak detection unit 121, 122 resistors 123, 124 Capacitors 125 Comparator 130 Zero-crossing detection unit 140 First Output Section 141, 142 Inverter 143 NMOSFET 144 resistors 150 DC monitoring section 160 Second Output Section 170 Undervoltage protection section 180 Comparison Section 181-184 Comparators 190 AC waveform judgment section 200 Printed Circuit Boards 210 copper wiring 220 Handa 300 Semiconductor integrated circuit devices (zero-cross ICs) 300a First Chip 300b Second chip 300c Island 310 AC monitoring section 311-314 Resistors 311a~315a, 311b~315b resistance 316a, 316b NMOSFET 317a, 317b PMOSFET 318a, 318b fuses 320 Zero-crossing detection unit 321, 322 Comparators 330 Logic Section 340 First Output Section 350 Comparison Section 360 Undervoltage Protection Unit 370 Input Stop Detection Unit 371 Offset Power Supply 372 Comparator 380 DC monitoring section 381-385 Resistors 386 NMOSFET 387 PMOSFET 388 Fuse 390 Second Output Section 400, 400X~400Z High voltage range (LDMOSFET range) 401 Feedback resistor (polysilicon resistor) 401(1)~401(m) Unit resistance 402 Field Oxide 410 p-type semiconductor substrate 411 Low-concentration n-type semiconductor region 412 High-concentration p-type semiconductor region 413, 414 High-concentration n-type semiconductor regions 415 Field Oxide Film 416 Gate oxide film 417 Gate Region 418 Field Plate 419 Low-concentration p-type semiconductor region 510 Delay Adjustment Section 520 Control Unit 531 Internal resistance 532 External resistor A1, A2 area C1, C11 Capacitors D1, D11, D12 diodes P1-P12, P21-P35, P41-P49 pads R resistance component W1-W9, W21-W31 wires

Claims

1. A zero-cross detection unit applies an AC voltage with a constant period and phase between a first node and a second node, compares a first monitored signal and a second monitored signal input from the first node and the second node via a first diode and a second diode, respectively, and generates a first comparison signal having a first period. A monitoring unit that divides the voltage of the first monitored signal and the second monitored signal and outputs them to the zero-cross detection unit, A comparison unit compares the output signal from the monitoring unit with a predetermined threshold to generate a second comparison signal, A logic unit that counts the first period of the first comparison signal, estimates the zero-crossing of the AC voltage using the count value to generate a zero-crossing detection signal, and generates a pulse signal with a constant second period which is the zero-crossing detection signal, or fixes the pulse signal to a predetermined level, according to the detection result of the second comparison signal. It has, The first comparison signal is a signal whose logic level switches between a high level and a low level depending on the comparison result between the first monitored signal and the second monitored signal. The second comparison signal is a signal whose logic level switches between a high level and a low level depending on the comparison result between the output signal from the monitoring unit and the predetermined threshold. The first period is the time from the moment the first comparison signal switches from one logic level, high level or low level, to the other logic level, until the moment the first comparison signal switches from one logic level to the other logic level. The logic unit switches the zero-cross detection signal from one logic level (high level and low level) to the other logic level when the first comparison signal switches from one logic level to the other logic level, starts counting the waiting time corresponding to the first cycle acquired before the logic of the first comparison signal switches, and switches the zero-cross detection signal from the other logic level to the one logic level when the waiting time has elapsed. The first chip on which the monitoring unit is integrated is cut into a rectangular shape in a plan view, where the ratio of the short side to the long side is approximately equal, and is a semiconductor integrated circuit device.

2. The semiconductor integrated circuit apparatus according to claim 1, wherein the comparison unit compares the output signal from the monitoring unit with a plurality of thresholds to generate a plurality of second comparison signals.

3. The semiconductor integrated circuit apparatus according to claim 1 or 2, wherein the logic unit detects whether both a rising edge and a falling edge have occurred in at least one of the plurality of second comparison signals during one cycle of the zero-crossing detection signal and generates a waveform determination signal.

4. The semiconductor integrated circuit apparatus according to any one of claims 1 to 3, wherein the first chip has a high-voltage region that has a higher voltage withstand capability against voltage in the substrate thickness direction than other regions, and above the high-voltage region, a first voltage divider resistor is formed which is connected to a first pad to which the first monitored signal is input and for dividing the voltage of the first monitored signal, and a second voltage divider resistor is formed which is connected to a second pad to which the second monitored signal is input and for dividing the voltage of the second monitored signal.

5. The semiconductor integrated circuit apparatus according to claim 4, wherein the high-voltage regions are formed in multiple locations along the first edge of the first chip in a plan view of the first chip.

6. The semiconductor integrated circuit apparatus according to claim 5, wherein the plurality of high-voltage regions are located on the first side of the first chip in a plan view of the first chip and are concentrated in a first region which is half of the first chip.

7. In a plan view of the first chip, the second region of the first chip is A third voltage divider resistor for dividing the voltage of the first monitored signal, wherein one terminal is connected to the first voltage divider resistor and the other terminal is connected to a third pad on which a divided voltage signal of the first monitored signal is output, A fourth voltage divider resistor for dividing the first monitored signal, with one terminal connected to the second voltage divider resistor and the other terminal connected to a fourth pad on which a divided voltage signal of the second monitored signal is output, The fifth pad to which the ground potential is applied at the first chip, An electrostatic protection element for protecting the third to fifth pads from electrostatic discharge, A fuse for adjusting the resistance values ​​of the third and fourth voltage divider resistors, A semiconductor integrated circuit apparatus according to claim 6, having the following features.

8. The semiconductor integrated circuit apparatus according to claim 7, wherein the third to fifth pads are formed in plurality along a second edge perpendicular to the first edge of the first chip in a plan view of the first chip.

9. The semiconductor integrated circuit apparatus according to claim 8, wherein the third to fifth pads are formed in a plan view of the first chip, closer to the second side than the center of the first side, and arranged along the second side.

10. The semiconductor integrated circuit apparatus according to any one of claims 7 to 9, wherein the third pad and the fourth pad are adjacent to each other, and the distance between the third pad and the fifth pad and the distance between the fourth pad and the fifth pad are greater than the distance between the third pad and the fourth pad.

11. The semiconductor integrated circuit apparatus according to any one of claims 7 to 10, wherein the third voltage divider resistor and the fourth voltage divider resistor are formed in a position adjacent to the high-voltage region in a plan view of the first chip.

12. The semiconductor integrated circuit apparatus according to any one of claims 4 to 11, wherein polysilicon resistors having a voltage rating of 100V or more are used as the first voltage dividing resistor and the second voltage dividing resistor.

13. The semiconductor integrated circuit apparatus according to any one of claims 4 to 12, wherein the high-voltage region is an LDMOSFET region.

14. The semiconductor integrated circuit apparatus according to claim 13, wherein, in the LDMOSFET region, a plurality of concentric annular drain regions and source regions are alternately formed in a plan view of the first chip, and the first voltage divider resistor and the first pad are formed on a field oxide film surrounded by the innermost drain region.

15. The semiconductor integrated circuit apparatus according to any one of claims 7 to 11, wherein each of the first to fourth voltage divider resistors is made up of a combination of multiple unit resistors.

16. The semiconductor integrated circuit apparatus according to any one of claims 1 to 15, wherein the second chip on which the zero-cross detection unit is integrated is cut into a long rectangular shape in a plan view thereof.

17. The semiconductor integrated circuit apparatus according to claim 16, wherein, among the plurality of pads provided on the second chip, the plurality of pads connected to the first chip are arranged in a plan view of the second chip so as to be concentrated along the first edge of the second chip that is closest to the first chip.

18. The semiconductor integrated circuit apparatus according to claim 17, wherein among the plurality of pads provided on the second chip, the plurality of pads that are not connected to the first chip are formed so as to be arranged along the second edge of the second chip that is opposite to the first edge of the second chip in a plan view of the second chip.

19. The semiconductor integrated circuit apparatus according to any one of claims 16 to 18, referencing any one of claims 7 to 11 or 15, wherein the second chip comprises a sixth pad to which a divided voltage signal of the first monitored signal is input through a wire to the third pad, and a seventh pad to which a divided voltage signal of the second monitored signal is input through a wire to the fourth pad, and the sixth pad and the seventh pad are provided adjacent to each other.

20. The semiconductor integrated circuit apparatus according to claim 19, wherein the second chip includes an eighth pad to which a divided voltage signal of a third monitored signal is input, which is a rectified voltage generated by full-wave rectifying the AC voltage applied between the first node and the second node, and the distance between the eighth pad and the seventh pad is wider than the distance between the sixth pad and the seventh pad.

21. The semiconductor integrated circuit apparatus according to claim 20, wherein the second chip comprises a first output unit that receives the zero-crossing detection signal and generates a first detection result signal, a ninth pad that outputs the first detection result signal, and a tenth pad to which the ground potential of the second chip is applied, and the tenth pad is provided between the sixth pad and the ninth pad.

22. The semiconductor integrated circuit apparatus according to claim 21, wherein the second chip comprises a second output unit that receives a voltage division signal of the third monitored signal and generates a second detection result signal, an eleventh pad that outputs the second detection result signal, a twelfth pad to which the power supply potential is applied, and a thirteenth pad to which the ground potential of the second chip is applied, and the thirteenth pad is provided between the eleventh pad and the twelfth pad.

23. The semiconductor integrated circuit apparatus according to claim 22, wherein an electrostatic protection element is formed directly beneath each of the sixth to eleventh pads.

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