Packaging substrate and method for manufacturing the same

Abstract

To provide a packaging substrate enabling easy detection of defects that may occur in a glass substrate, and a manufacturing method thereof.SOLUTION: A packaging substrate 20 includes a glass substrate 21 having an edge region and containing a first surface and a second surface facing each other, and an upper layer 70 laminated on the first surface or a lower layer 80 laminated under the second surface. The edge region of the glass substrate includes an edge of the glass substrate and a region of the glass substrate which protrudes beyond the upper layer or the lower layer. A manufacturing method of the packaging substrate includes a step of preparing the glass substrate and forming the upper layer on the first surface, a step of removing a part of the upper layer along a cutting line which is a cutting-planned position, thereby forming a removal line, a filamentation forming step of forming a filamentation in the glass substrate along the removal line, and a step of cutting the glass substrate using the filamentation.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] This embodiment relates to a semiconductor packaging substrate and a method for manufacturing a semiconductor packaging substrate, and is a technology related to a packaging substrate including a glass substrate and a manufacturing method therefor.

Background Art

[0002] In manufacturing electronic components, the process of implementing a circuit on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer into a state where it can be used as an actual product is called the back-end process (BE), and the packaging process is included in this back-end process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has developed into various forms such as line widths in nano units below micro, more than 10 million cells, high-speed operation, and a large amount of heat dissipation. However, relatively, the technology to perfectly package this has not been supported. Therefore, the electrical performance of a semiconductor may sometimes be determined by the packaging technology and the electrical connection thereby, rather than the performance of the semiconductor technology itself.

[0004] As materials for packaging substrates, ceramics or resins are applied. Recently, research has been underway to apply silicon or glass to high-end packaging substrates. In particular, a packaging substrate having a cavity structure has been developed by applying a glass substrate.

[0005] On the other hand, within the packaging process, redistribution layer (RDL) refers to a general term for techniques that change the position of electrical terminals (e.g., Al Pads) already formed using wafer-level packaging (WLP) process technology to any desired position. Such RDL is used as a method to overcome design limitations in semiconductor manufacturing plants through packaging, that is, it is utilized in the stacking of semiconductor chips.

[0006] Relevant prior art includes U.S. Patent Publication US2022 / 0336481A1 and Korean Patent Publication No. 10-2020-0133340. [Overview of the project] [Problems that the invention aims to solve]

[0007] The objective of this embodiment is to provide a packaging substrate and a manufacturing method for the same that can easily detect defects that may occur in a glass substrate, in a glass substrate and a packaging substrate on which a large number of elements are mounted on the glass substrate.

[0008] Furthermore, the objective of this embodiment is to provide a packaging substrate and a manufacturing method therefor that can simultaneously detect defects occurring on the surface and cross-section of a glass substrate.

[0009] Furthermore, the purpose of this implementation is to reduce the time and cost involved in the inspection and quality check of glass substrates. [Means for solving the problem]

[0010] To achieve the above objective, a packaging substrate according to one embodiment includes a glass substrate having a first surface and a second surface facing each other; an upper layer laminated on the first surface, or a lower layer laminated below the second surface; wherein the glass substrate may have an edge region. The edge region includes the edge of the glass substrate and a region of the glass substrate that protrudes beyond the upper layer or the lower layer.

[0011] The upper layer may include a first insulating layer laminated on the first surface.

[0012] The edge of the first insulating layer may be positioned inward from the edge of the glass substrate, and the edge region may include the edge of the glass substrate and the edge of the first insulating layer.

[0013] In addition, the lower layer may also include a second insulating layer laminated beneath the second surface, the edge of the second insulating layer being positioned inward from the edge of the glass substrate, and the edge region may include the edge of the glass substrate and the edge of the second insulating layer.

[0014] The width from the edge of the first insulating layer to the edge of the glass substrate may be 5 μm to 200 μm.

[0015] The width from the edge of the second insulating layer to the edge of the glass substrate may be 5 μm to 200 μm.

[0016] In one embodiment, the edge region may be a curved surface.

[0017] The corners of the glass substrate in the edge region may be curved.

[0018] In other embodiments, the aforementioned edge region may be chamfered.

[0019] The corners of the glass substrate in the edge region may be chamfered.

[0020] The upper layer or the lower layer may each have a tapered shape that becomes thinner in the direction of the edge region.

[0021] The upper layer or the lower layer may each have a tapered shape that becomes thinner in the direction of the cut surface of the glass substrate.

[0022] A semiconductor element may be mounted on the top of the upper layer.

[0023] To achieve the above object, a method for manufacturing a packaging substrate according to an embodiment includes preparing a glass substrate including a first surface and a second surface facing each other, forming an upper layer on the first surface, removing a part of the upper layer along a cutting line which is a position where cutting is scheduled to form a removal line, a filamentation process step of forming filamentation on the glass substrate along the removal line, and cutting the glass substrate using the filamentation, thereby manufacturing the above-described packaging substrate.

[0024] The method for manufacturing the packaging substrate may further include, before the filamentation process step, forming a lower layer under the second surface, and removing a part of the lower layer along the cutting line to form a removal line.

[0025] The width of the removal line may be 5 μm or more, and may also be 200 μm or less.

[0026] The upper layer and / or the lower layer may each have a tapered shape that becomes thinner in the cutting surface direction of the glass substrate.

[0027] The step of cutting the glass substrate may be a step of applying a tensile stress or a rotational force to the filamentation to separate the glass substrate into two or more parts, and forming a cutting surface on the glass substrate.

[0028] The method for manufacturing the packaging substrate may further include, after the step of cutting the glass substrate, a step of grinding the cutting surface of the cut glass substrate.

[0029] The edge region includes the edge of the glass substrate and the region of the glass substrate that protrudes more than the upper layer or the lower layer.

[0030] The method for manufacturing the packaging substrate may further include the step of detecting a defect in any one selected from the group consisting of the edge region of the glass substrate, the cut surface of the glass substrate, the removal line of the upper layer, the removal line of the lower layer, and combinations thereof. [Effects of the Invention]

[0031] The embodiment allows for easy detection of defects that may occur in packaging substrates and / or glass substrates. Furthermore, the embodiment can simultaneously detect defects occurring on the surface and cross-section of glass substrates. Additionally, the embodiment can effectively and cost-effectively detect cracks, breaks, and other defects that may occur in glass substrates. [Brief explanation of the drawing]

[0032] [Figure 1] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in a real-world example. [Figure 2] This is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate related to other concrete examples. [Figure 3] (a) and (b) are conceptual diagrams illustrating a portion of a packaging substrate related to an actual example in cross-section. [Figure 4] This flowchart shows a cross-sectional view of the process of generating the core distribution layer, which is part of the manufacturing process of a packaging substrate related to a concrete example. [Figure 5] This flowchart shows a cross-sectional view of the process of generating the upper layer within the manufacturing process of a packaging substrate, as illustrated in the example. [Figure 6] (a) to (c) are diagrams illustrating the cross-section of a packaging substrate related to a specific example. [Figure 7] This diagram shows a top view of a packaging substrate related to an actual example, where Gr (glass crack) and Gh (glass chipping) indicate glass chipping. [Figure 8](a) to (c) are flowcharts illustrating the manufacturing process of a packaging substrate in a cross-sectional view, where (a) is laser ablation, (b) is laser filamentation, and (c) is separation. [Figure 9] (a) to (c) are flowcharts illustrating the manufacturing process of a packaging substrate in cross-section for other concrete examples, where (a) is laser ablation, (b) is laser filamentation, and (c) is separation. [Figure 10] (a) and (b) are photographs showing the manufacturing process of a packaging substrate related to an actual example, where the left side of (a) is a sectional view and the right side is a top view. [Figure 11] This is a photograph of a cross-section of a ground glass substrate in an example of its application. The solid line represents the cutting line (CL), and the dotted line indicates the edge of the ground glass. [Figure 12] (a) shows a glass substrate from above in relation to another example of its implementation, and (b) is a photograph of a part of it. [Best Mode for Carrying Out the Invention]

[0033] The embodiments are described below in detail with reference to the accompanying drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the embodiments belong. However, the embodiments can be realized in a variety of different forms and are not limited to the embodiments described herein. Similar parts are denoted by the same reference numerals throughout the specification.

[0034] Throughout this specification, the term “these combinations” as used in any expression in Markush form means one or more mixtures or combinations selected from the group of components described in the Markush form, and includes one or more of those components.

[0035] Throughout this specification, terms such as “First,” “Second,” or “A,” “B” are used to distinguish identical terms from one another. Furthermore, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0036] In this specification, the term "~" may mean that the compound contains a compound corresponding to "~" or a derivative of "~".

[0037] In this specification, the meaning of B being located on A means either B being in direct contact with A, or B being located on A with other layers located between them, and is not limited to B being in contact with the surface of A.

[0038] In this specification, the meaning of B being connected to A means either that A and B are directly connected, or that A and B are connected through other components between them, and is not limited to the direct connection of A and B unless otherwise specified.

[0039] In this specification, unless otherwise specified, singular expressions are interpreted to include singular or plural, as interpreted in the context.

[0040] In the process of developing a semiconductor device that is more integrated, thinner, and capable of high performance, the inventors recognized that not only the element itself but also the packaging is a crucial factor in improving performance. While researching this, they discovered that, unlike conventional methods that applied two or more core layers as a packaging substrate on a motherboard, such as interposers and organic substrates, applying a single layer of glass core and a cavity structure could make the packaging substrate even thinner and contribute to improving the electrical characteristics of the semiconductor device.

[0041] On the other hand, glass substrates are susceptible to cracks and chipping during the manufacturing process due to internal stress and / or external impacts. Detecting these defects requires costly cross-sectional analysis. For example, detecting cracks and chipping may require microscopic inspection of all cross-sections of the glass substrate, which can be time-consuming and costly. We have confirmed that inspecting the core substrate can be easily performed by making the glass substrate protrude in the cross-sectional direction from the layers stacked above or below it. In other words, by exposing a portion of the glass substrate, it is possible to quickly detect defects on the surface and cross-section of the glass substrate without the need for instruments such as microscopes, thus completing the invention.

[0042] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in an example; Figure 2 shows a conceptual diagram illustrating the cross-sectional structure of a packaging substrate in another example; and Figures 3(a) and 3(b) are conceptual diagrams illustrating a cross-sectional portion of a packaging substrate in an example, respectively.

[0043] To achieve the above objective, the semiconductor device 100 according to the embodiment includes a semiconductor element section 30 on which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to the semiconductor elements 32, 34, and 36 and connects them to each other.

[0044] A packaging substrate 20 according to one example includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be positioned.

[0045] The semiconductor element portion 30 refers to an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connecting electrodes or the like. Specifically, the semiconductor element portion 30 may be, for example, a computing element such as a CPU or GPU (first element: 32, second element: 34), a memory element such as a memory chip (third element: 36), etc., but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0046] The motherboard 10 may be a printed circuit board, a printed wiring board, or the like.

[0047] The packaging substrate 20 may further include a lower layer (not shown) selectively located below the core layer.

[0048] The core layer 22 may include a glass substrate 21 having a first region 221 with a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 which is thinner than the first region; a number of core vias 23 penetrating the glass substrate 21 in the thickness direction; and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23, which electrically connects a first surface 213 of the glass substrate 21 and a second surface 214 facing the first surface via the core vias 23. That is, the core layer 22 can refer to a glass structure consisting of a glass substrate 21 having a first surface 213 and a second surface 214 facing each other, a core via 23, a cavity 28, or all of these.

[0049] The second region 222 of the core layer 22 can function as a cavity structure.

[0050] Within the same area, the glass substrate 21 has a first surface 213 and a second surface 214 that face each other, and since these two surfaces are generally parallel to each other, the glass substrate 21 has a constant thickness throughout.

[0051] The internal space 281 formed by the difference in thickness between the first area 221 and the second area 222 serves to accommodate part or all of the cavity element 40.

[0052] The glass substrate 21 may include core vias 23 that penetrate the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first region 221 and the second region 222 and may be formed with an intended pitch and pattern.

[0053] Conventionally, packaging substrates for semiconductor devices have been applied in a form where silicon substrates and organic substrates are stacked. In the case of silicon substrates, due to their semiconductor properties, there is a risk of parasitic elements occurring when applied to high-speed circuits, which is a disadvantage as it results in relatively large power losses. In the case of organic substrates, a large area is required to form even more complex distribution patterns, which does not fit with the trend towards manufacturing ultra-miniaturized electronic devices. In order to form complex distribution patterns within a given size, it is practically necessary to miniaturize the pattern, but due to the properties of materials such as polymers used in organic substrates, there are practical limitations to the miniaturization of the pattern.

[0054] In this concrete example, a glass substrate 21 is used as a support for the core layer 22 to solve these problems. Furthermore, by applying core vias 23 formed through the glass substrate 21 together with the glass substrate 21, the length of the electrical current is further shortened, resulting in a more compact packaging substrate 20 with faster response and lower loss characteristics.

[0055] The glass substrate 21 is preferably a glass substrate used for semiconductors, and may, but is not limited to, a borosilicate glass substrate or an alkali-free glass substrate.

[0056] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined area of ​​the glass substrate 21, specifically by etching a plate-shaped glass by physical and / or chemical methods.

[0057] Specifically, the formation of the core via 23 may involve a method such as forming defects (scratches) on the surface of the glass substrate using a laser, followed by chemical etching, or laser etching, but is not limited to these methods.

[0058] The core vias 23 may be positioned in a number of 100 to 3,000, 100 to 2,500, or 225 to 1,024 locations per unit area (1 cm × 1 cm) of the glass substrate 21. When these pitch conditions are met, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0059] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate via through vias, and a core insulating layer 223 surrounding the core distribution pattern. The core layer 22, having an electrically conductive layer formed inside it via core vias, acts as an electrical passage across the glass substrate 21, and by connecting the upper and lower parts of the glass substrate over a relatively short distance, it can have faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0060] The cavity portion 28 is not limited in shape, and can be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, or any other shape.

[0061] The cavity element 40 may have a shape that is generally cylindrical, rectangular, or polygonal.

[0062] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0063] On the other hand, the cavity portion according to other embodiments may be implemented in a form that penetrates the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by the same process as the core via 23 formation process, and the area and shape that penetrate the glass substrate 21 may differ from those of the core via 23.

[0064] In such an embodiment, an insulating layer may be generated after the cavity elements 40 are arranged in the cavity. That is, an insulating layer may be generated in the cavity through the process by which the core insulating layer 223 described above is generated.

[0065] The core distribution pattern 241 may be formed in such a way that it can be electrically connected to the cavity element 40.

[0066] The cavity element 40 may include an active element such as a transistor, or a power transfer element such as a multilayer ceramic capacitor (MLCC), i.e., a passive element.

[0067] When a transistor or similar element is used as the cavity element 40, which plays a role in converting electrical signals between the motherboard and the semiconductor element to an appropriate level, the transistor or similar element is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0068] Furthermore, power transfer elements such as multilayer ceramic capacitors (MLCCs) play a crucial role in the performance of semiconductor devices. These passive power transfer elements are typically applied in quantities of at least 200 to a semiconductor device, and their performance is influenced by the characteristics of the electrical conductive layer surrounding the element. In one example, non-circular core vias can be applied where a low-resistance electrical conductive layer is required, such as in these power transfer elements.

[0069] On the other hand, the cavity element 40 may be applied by individually inserting passive elements such as capacitors, or a group of elements containing numerous passive elements embedded between insulating layers (cavity element insulating layers) may be formed so that the electrodes are exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate can be further streamlined and it is even more advantageous to ensure that the insulating layer is positioned sufficiently and with high reliability in the complex spaces between elements.

[0070] The glass substrate 21 plays an intermediate or mediating role in connecting the semiconductor element section 30 and the motherboard 10 to its upper and lower parts, respectively, and the core via 23 acts as a passage for transmitting these electrical signals, thereby ensuring smooth signal transmission. For the purpose of distinguishing it from the core via of the second area 222 described later, the core via located in the first area 221 is referred to as the first area core via 231.

[0071] The upper layer 26 is located on the first surface 213.

[0072] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the uppermost surface of the upper layer 26 may be protected by a cover layer 60 having openings formed therein that allow the connection electrodes of the semiconductor element to make direct contact.

[0073] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface and an upper distribution pattern 251 embedded in the upper insulating layer 253, which is an electrically conductive layer having a predetermined pattern and to which the core distribution layer 24 and at least a portion thereof are electrically connected. The upper distribution layers 25, which are arranged vertically relative to each other, may be connected to each other via blind vias 252.

[0074] The upper insulating layer 253 can be any material that is applied as an insulating layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler may be used, but it is not limited to this.

[0075] The insulating layer may be formed by forming a coating layer and curing it, or by laminating an in-cured or semi-cured insulating film onto the core layer 22 and curing it. In this case, if a vacuum lamination method or the like is applied, the insulating material can be embedded into the space inside the core via 23, enabling efficient process execution.

[0076] In one embodiment, even when multiple insulating layers are laminated and applied, it may be difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case their boundary is not substantially distinguished. Alternatively, in other embodiments, the boundary between the insulating layers can be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0077] The upper distribution pattern 251 refers to an electrically conductive layer located within the upper insulating layer 253 in a predetermined configuration, and may be formed, for example, by a build-up layer method. Specifically, by forming an insulating layer, removing unnecessary portions of the insulating layer, forming an electrically conductive layer by a method such as copper plating, selectively removing unnecessary portions of the electrically conductive layer, forming another insulating layer on this electrically conductive layer, removing unnecessary portions again, and then forming another electrically conductive layer by a method such as plating, an upper distribution pattern 251 can be formed in which electrically conductive layers are formed vertically or horizontally in the desired pattern.

[0078] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, it is formed to include a fine pattern in at least a part of it so that electrical signals can be transmitted smoothly with the semiconductor element portion 30 and the intended complex pattern can be adequately accommodated. In this case, the fine pattern may have a width and spacing of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm, respectively (the description of the fine pattern is the same hereafter).

[0079] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253, to which the upper distribution pattern 251 and at least a portion thereof are electrically connected, and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a portion thereof may be embedded while being exposed on the upper insulating layer. For example, if the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating, and if the upper connection pattern is embedded while a portion thereof is exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or electrically conductive layer may be removed by methods such as surface polishing or surface etching.

[0080] The top connection pattern 272, like the top distribution pattern 251 described above, can include a fine pattern in at least part of its structure. A top connection pattern 272 including such a fine pattern allows even more elements to be electrically connected in a small area, making the connection of electrical signals between elements or to the outside smoother and enabling more integrated packaging.

[0081] The upper connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or it may be connected via an element connection portion 51 such as a solder ball.

[0082] The cavity portion 28 is located above and / or below the second region 222 and includes an internal space 281 in which a cavity distribution layer 282 and a cavity element 40 are located, which are electrically connected to the core distribution pattern 241. The cavity distribution layer 282 may be formed via a second region core via 232.

[0083] Specifically, the glass substrate 21 in the second region 222 is even thinner than that in the first region 221, and the cavity element 40 can be located in the internal space 281 formed by this difference in thickness. In addition, the core vias 23 and core distribution layer 24 formed on the glass substrate 21 serve as electrical connection structures that connect the cavity element 40 to external elements.

[0084] Furthermore, as described above, a cavity portion may be generated not in the second region 222, but in the first region 221, that is, a cavity portion that penetrates the first surface 213 and the second surface 214 of the glass substrate 1, and cavity elements 40 may be arranged in the cavity portion.

[0085] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the terminals of the motherboard 10 by the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or it may be electrically connected via a board connection part 52 such as a solder ball. Alternatively, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located below the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as the connection part 50.

[0086] For example, the packaging substrate 20 located between the semiconductor element section 30 and the motherboard 10 may not have any substantially additional substrates applied other than the glass substrate 21.

[0087] Conventionally, when connecting elements to a motherboard, an interposer and an organic substrate were stacked together between them. This multi-layered configuration was applied for at least two reasons: firstly, there were scaling issues in directly bonding the fine patterns of the elements to the motherboard; and secondly, there was a risk of wiring damage due to differences in thermal expansion coefficients during the bonding process or the operation of the semiconductor device. In this concrete example, these problems were solved by using a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element, and by forming a fine pattern with a scale small enough to mount the element on the first surface and the upper layer of the glass substrate.

[0088] The following describes a method for manufacturing a packaging substrate according to an embodiment of the present invention.

[0089] Figures 4 and 5 are flowcharts illustrating the manufacturing process of a packaging substrate in a cross-sectional view, based on an actual example.

[0090] First, a glass substrate 21a having a flat first surface and a flat second surface is prepared as shown in Figure 4(a), and defects (grooves) 21b are formed on the glass surface at predetermined positions for the formation of core vias. The glass substrate may be a glass substrate used for electronic devices, and may, for example, an alkali-free glass substrate, but is not limited to this. Commercial products manufactured by companies such as Corning, Schott, and AGC may be used. Methods such as mechanical etching and laser irradiation may be used to form the defects (grooves).

[0091] As shown in Figure 4(b), the glass substrate 21a on which the defect (groove) 21b is formed undergoes an etching step to form core vias 23 through a physical or chemical etching process. During the etching process, vias are formed in the defective area of ​​the glass substrate, and at the same time, the surface of the glass substrate 21a may also be etched. To prevent such etching of the glass surface, a masking film can be applied, but considering the hassle of applying and removing the masking film, the defective glass substrate itself can be etched, in which case the thickness of the glass substrate with core vias may be slightly thinner than the thickness of the original glass substrate.

[0092] Subsequently, as shown in Figures 4(c) and 4(d), the core layer manufacturing step can be carried out by forming an electrically conductive layer 21d on the glass substrate. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited to this.

[0093] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface is inferior due to their differing properties. In practical applications, the adhesion between the glass surface and the metal can be improved using two methods: a dry method and a wet method.

[0094] The dry method is a method that applies sputtering, that is, a method that forms a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper, etc. In such cases, the adhesion between the glass and the metal can be improved by an anchoring effect caused by the interaction between the surface morphology of the glass and the metal particles.

[0095] The wet method is a method of priming, in which a primer layer 21c is formed by pretreatment with a compound having a functional group such as an amine. Depending on the desired degree of adhesion, pretreatment with a silane coupling agent can be performed, followed by priming with a compound or particles having an amine functional group. As mentioned above, the support substrate in the embodiment needs to be high-performance enough to form a fine pattern, and this must be maintained even after priming. Therefore, when such a primer contains nanoparticles, it is preferable to use nanoparticles having an average diameter of 150 nm or less, and for example, it is preferable to use nanoparticles for particles having an amine group. The primer layer may, as an example, be formed by applying an adhesion improver manufactured by MEC's ​​CZ series or the like.

[0096] The seed layer / primer layer 21c can selectively form a metal layer with or without removing portions where the formation of an electrical conductive layer is unnecessary. Furthermore, the seed layer / primer layer 21c can be treated in a state where the formation of an electrical conductive layer is necessary or unnecessary, either by activating or deactivating it with metal plating, before proceeding to subsequent steps. For example, the activation or deactivation treatment may include light irradiation treatment such as a laser of a certain wavelength, or chemical treatment. For the formation of the metal layer, copper plating methods used in the manufacture of semiconductor devices may be used, but are not limited to these.

[0097] As shown in Figure 4(e), if a portion of the core distribution layer is unnecessary, it may be removed, or after a portion of the seed layer is removed or deactivated, a metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming the etching layer 21e of the core distribution layer.

[0098] Figure 5 illustrates the manufacturing steps for forming the insulating layer and the upper distribution pattern using an example.

[0099] As shown in Figure 5(a), the core via can undergo an insulating layer formation step in which the void space is filled with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. At this time, the insulating layer to be applied may be one manufactured in the form of a film, for example, by laminating an insulating layer in the form of a film under reduced pressure. By performing lamination under reduced pressure in this way, the insulating layer is sufficiently embedded into the void space inside the core via, thereby forming a core insulating layer without void formation.

[0100] Figures 5(b) to (e) illustrate the upper layer manufacturing steps.

[0101] The upper layer manufacturing step involves forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating with a resin composition that forms the insulating layer 23a, or by laminating an insulating film, and the method of laminating an insulating film is preferred for simplicity. The lamination of the insulating film can be carried out by a process of laminating and curing the insulating film, and in this case, if a reduced-pressure lamination method is applied, the insulating resin can be sufficiently embedded even in layers where an electrically conductive layer has not been formed inside the core vias. The upper insulating layer also comes into direct contact with the glass substrate at least in part, and therefore, one with sufficient adhesion is used. Specifically, it is preferable that the glass substrate and the upper insulating layer have characteristics that satisfy an adhesion test value of 4B or higher according to ASTM D3359.

[0102] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching away unnecessary parts to form an etched layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with the insulating layer in between, the pattern can be formed by forming blind vias 23b in the insulating layer and then performing a plating process. Blind vias can be formed using dry etching methods such as laser etching or plasma etching, or wet etching methods using a masking layer and etching solution.

[0103] Subsequently, although not shown in the diagram, an upper connecting layer and a cover layer may be formed.

[0104] The top connection pattern and top connection electrodes can also be formed by a process similar to that of the top distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, then forming an electrically conductive layer thereon, and then forming an etching layer of the electrically conductive layer. Alternatively, a method may be applied that selectively forms only the electrically conductive layer without applying the etching method. The cover layer may be formed so that openings (not shown) are formed at positions corresponding to the top connection electrodes, exposing the top connection electrodes and allowing direct connection to the element connection portion or the terminals of the element.

[0105] Once the upper layer is generated, the process of forming the lower connecting layer and cover layer to generate the lower layer can be carried out. The lower distribution layer and / or lower connecting layer, and selectively a cover layer (not shown) can be formed in a manner similar to the upper connecting layer and cover layer formation steps described above.

[0106] In concrete examples, one or more semiconductor elements may be mounted on the packaging substrate 20. In the manufacturing process of the packaging substrate, many packaging substrates may be manufactured simultaneously on a large-area substrate, and the packaging substrate 20 may be cut into predetermined units, i.e., individual packaging substrates called units. Exemplary examples include strip substrates in which multiple individual products are arranged with dummy areas in between, quad substrates in which dummy areas are placed between multiple strip substrates, and panel substrates in which dummy areas are placed between multiple quad substrates, and in the manufacturing of these, a glass substrate may be used as the core. The glass substrate (core substrate or core layer) may be cut during or after the placement of the upper and / or lower layers to have a pattern of a certain size and to have individual semiconductor chips or chip units mounted, or to be in a state where they can be mounted. Such cutting, separation, and division processes of a substrate may be called dicing or singulation. In the following, "packaging substrate" refers to both a pre-singulation packaging substrate on which individual packaging substrates are arranged, or a substrate in a singulated state within a single product, depending on the context.

[0107] In this specification, dicing or singulation may mean dividing a packaging substrate, which includes a glass substrate as a core layer, into multiple units. Furthermore, a substrate in which a glass substrate is used as a core layer may be referred to in various ways, such as core substrate, glass substrate, or packaging substrate.

[0108] Figures 6(a) to 6(c) are diagrams illustrating the cross-sections of packaging substrates related to specific examples.

[0109] As explained with reference to Figures 1 to 5, core vias and cavity portions may be formed on the glass substrate 21. A core distribution layer and a cover layer may be formed on the upper layer. The lower layer may also have a multilayer structure including an insulating layer and a metal distribution pattern. In the following drawings, for the sake of explanation, the packaging substrate 20, which includes the glass substrate 21, the upper layer 70 formed on the first surface of the glass substrate 21, and the lower layer 80 formed on the second surface, will be described in a simplified manner, and a detailed explanation of the remaining detailed components will be omitted.

[0110] Referring to Figure 6, the upper layer 70 is placed on the first surface of the glass substrate 21. Selectively, the lower layer 80 may be placed on the second surface of the glass substrate 21.

[0111] The upper layer 70 may include an upper distribution layer 71 consisting of a multilayer laminated structure including an upper metal pattern (upper distribution pattern) and an upper insulating layer, and a first cover layer 72 formed on top of the upper distribution layer 71 to protect the substrate. The specific arrangement of the upper distribution pattern and the upper insulating layer within the upper distribution layer is omitted from the drawing.

[0112] The lower layer 80 may also include a lower distribution layer 81 consisting of a multilayer structure including a lower metal pattern (lower distribution pattern) and a lower insulating layer, and a second cover layer 82 formed on top of the lower distribution layer 81 to ultimately planarize and protect the substrate. The arrangement of the lower distribution pattern and lower insulating layer within the lower distribution layer is omitted in the drawings.

[0113] The first cover layer 72 and / or the second cover layer 82 may be embodied in a solder resist to protect the surface circuit from the external environment. Alternatively, as in some embodiments, the first cover layer 72 and / or the second cover layer 82 may be embodied in a polyimide film (PI), which is a heat-resistant insulating film having high thermal stability and high mechanical strength.

[0114] Core vias, cavity portions, and metal pattern layers are formed on the glass substrate 21, and semiconductor elements (not shown) are mounted on the upper layer 70, or before mounting, the packaging substrate can be cut into specific units.

[0115] The packaging substrate can be cut along the cutting lines. The cutting lines are predetermined positions where cutting is intended.

[0116] In the actual example, a portion of the upper layer 70 and / or a portion of the lower layer 80 corresponding to the cutting line may not have a metal pattern layer. That is, only an insulating layer or a protective layer may be placed on the portion of the upper layer 70 and / or a portion of the lower layer 80 that is to be cut and removed.

[0117] The cut packaging substrate 20 generally has a cross-section like that shown in Figure 6(a). That is, the cut surface and the first surface, or the cut surface and the second surface of the packaging substrate 20, are generally angular in shape, and the corners are relatively sharp.

[0118] In a structure like that shown in Figure 6(a), cracks and damage can easily occur originating from the edges or cut surfaces of the glass substrate 21. Therefore, a packaging substrate like that shown in Figure 6(b) or (c) is proposed based on an embodiment of the present invention.

[0119] In the embodiment shown in Figure 6(b), the cross-section of the glass substrate 21 can have a shape that protrudes beyond the upper layer 70 and / or the lower layer 80. That is, the glass substrate 21 can have an edge region 213a, which is an edge that protrudes beyond the upper layer 70 and / or the lower layer 80. The edge region of the first surface and / or the edge region 213a of the second surface adjacent to the cross-section of the glass substrate 21 can be exposed to the outside by removing the upper layer 70 and / or the lower layer 80.

[0120] In the embodiment shown in Figure 6(b), the cross-section of the glass substrate 21 may have a shape that protrudes beyond the upper distribution layer 71 and / or the lower distribution layer 81. That is, the glass substrate 21 may have an edge region 213a that protrudes beyond the upper distribution layer 71 and / or the lower distribution layer 81. The edge region of the first surface and / or the edge region 213a of the second surface adjacent to the cross-section of the glass substrate 21 may have the upper distribution layer 71 and / or the lower distribution layer 81 removed, exposing the first surface and / or the second surface of the glass substrate 21 to the outside. The upper distribution layer 71 and / or the lower distribution layer 81 may each have two or more layers, three or more layers, four or more layers, or five or more layers arranged in the upper layer 70 and the lower layer 80, respectively. Alternatively, they may have 10 or fewer layers, 8 or fewer layers, or 6 or fewer layers.

[0121] In the embodiment, the upper layer 70 may further include an insulating layer, such as a first cover layer 72 laminated on the first surface, the edge of the insulating layer being positioned inward from the edge of the glass substrate 21, and the edge region 213a may include the region from the edge of the glass substrate 21 to the edge of the insulating layer.

[0122] Furthermore, the lower layer 80 may further include an insulating layer, such as a second cover layer 82 laminated on the second surface, the edge of the insulating layer being positioned inward from the edge of the glass substrate 21, and the edge region 213a may include the region from the edge of the glass substrate 21 to the edge of the insulating layer.

[0123] The cutting process may also be a process in which the panel substrate is cut into quad substrates.

[0124] The cutting process may also be a process in which the quad substrate is cut into strip substrates.

[0125] The cutting process may be a process in which the strip substrate is cut into individual packaging substrates.

[0126] This process is collectively referred to as the process of cutting into unit units.

[0127] In the cutting process of the packaging substrate 20, that is, the process of cutting it into unit units, the upper layer 70 or the lower layer 80 may be removed, and through such a process, after the cutting process, the side surface of the glass substrate 21 may protrude in the cutting direction more than the layer laminated on the upper or lower surface. The removal may be carried out by methods such as laser irradiation, but is not limited thereto.

[0128] The width of the edge region 213a where the upper layer 70 or lower layer 80 is removed and the glass substrate 21 is exposed may be such that the width from the edge of the insulating layer to the edge of the glass substrate 21 is, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more, by removing a portion of the upper or lower layer. Alternatively, the width of the edge region 213a may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less, by removing a portion of the upper or lower layer. In other words, the width of the removed portion (removed line) may be twice or more, or 2.2 times or more, the width of the removed portion (removed line) may also be four times or less, or three times or less.

[0129] As shown in Figure 6(b), the glass substrate 21 protrudes in the direction of the cut surface, so that the cross-section of the packaging substrate has a thickness that decreases from the upper layer 70 or the lower layer 80 toward the glass substrate 21, and the overall shape can be a horizontal "U" shape with opposing tapered shapes.

[0130] The edge region 213a of the protruding glass substrate 21 may have its corners rounded and ground, as shown in Figure 6(c). In other words, the edge region 213a located at the corner of the glass substrate 21 may be curved.

[0131] Alternatively, as in one example, the edge region 213a located at the corner of the glass substrate 21 may be chamfered.

[0132] For example, the upper layer 70 or the lower layer 80 may also be removed or ground to form a tapered shape that becomes thinner in the direction of the cross-section.

[0133] As shown in Figure 6, when the upper layer is removed from the edge region 213a of the glass substrate 21, the glass substrate 21 is exposed to the extent of the removed upper layer.

[0134] The width from the edge of the insulating layer to the edge of the glass substrate 21 may, for example, be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more. The width of the edge region 213a may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0135] Figure 7 shows a top view of a packaging substrate related to an actual implementation example.

[0136] As shown in the figure, when viewing the packaged substrate cut into units from above, a first cover layer 72 is formed on the first surface of the glass substrate 21, and the upper layer including the first cover layer 72 is removed at the edge region 213a. When the glass substrate 21 is rectangular in shape, the upper layer can be removed along the four sides of the glass substrate 21. In other words, the edge of the first cover layer 72 is located inward from the edge of the glass substrate 21, and the edge region 213a can mean the region from the edge of the glass substrate 21 to the edge of the first cover layer 72.

[0137] In the exposed edge region 213a of the glass substrate 21, cracks or chipping of the glass can be observed relatively easily, as in some cases.

[0138] As mentioned above, when glass substrates are used as the core structure of packaging substrates, there is a high possibility that the substrate may crack or break due to internal stress and external impact during the manufacturing process. To detect this, analysis of all cross-sections of the cut packaging substrate is necessary. Cross-sectional analysis requires inspection of the cut surface of the packaging substrate using a microscope, but this is a time-consuming and costly process.

[0139] According to this embodiment, as shown in Figure 7, defects such as cracks and chipping can be detected quickly and accurately by inspecting only the exposed region 213a of the glass substrate 21. In other words, by detecting defects in the edge region 213a of the glass substrate 21 from which the upper or lower layer has been removed, and in the cut surface of the glass substrate, it is possible to perform surface inspection and cross-sectional inspection of the glass substrate simultaneously without expensive equipment.

[0140] Figure 8 is a flowchart illustrating the manufacturing process of a packaging substrate in a cross-sectional view, based on an actual example.

[0141] According to the example shown in Figure 8, an upper layer 70 is formed on the first surface of the glass substrate 21, and a semiconductor element (not shown) can be stacked on top of the upper layer 70.

[0142] First, as shown in Figure 8(a), a laser can be used to remove the upper layer 70 along the cutting line by a predetermined width to form a removal line (Laser Ablation).

[0143] Using a green laser or ultraviolet laser, the laminated upper layer 70, specifically an insulating layer such as ABF, can be removed along cutting lines such as dicing streets.

[0144] In this case, the width of the upper layer 70 to be removed, i.e., the width of the removal line, may be approximately 10 μm to 600 μm. The width may be 10 μm or more, 14 μm or more, 20 μm or more, 30 μm or more, 40 μm or more, 50 μm or more, 60 μm or more, or 70 μm or more. The width may be 600 μm or less, 550 μm or less, 500 μm or less, 450 μm or less, 400 μm or less, 380 μm or less, 360 μm or less, 340 μm or less, 320 μm or less, 300 μm or less, 280 μm or less, 260 μm or less, 240 μm or less, 220 μm or less, 200 μm or less, or 180 μm or less. The width of the upper layer 70 to be removed can be set to approximately twice or more the width of the edge region of the glass substrate 21 that you want to protrude.

[0145] On the other hand, as shown in the figure, when the upper layer 70 is removed using a laser, virtually no defects (damage) are formed in the glass substrate 21.

[0146] Subsequently, as shown in Figure 8(b), a filamentation process may be performed on the glass substrate 21 from which the upper layer has been removed, to form filaments along the cutting line (Laser Filamentation).

[0147] The method of cutting a substrate using a laser beam such as an infrared laser (IR laser) involves focusing a very short wave laser beam into the interior of the glass substrate 21 and irradiating it along a desired cutting path. This induces phenomena such as internal filamentation, causing a cutting groove of a certain depth to be formed inside the glass substrate 21. By forming filamentation, defects can be created inside the glass substrate 21 along the cut surface.

[0148] As the ultrashort wave laser beam passes through the glass substrate 21, some of it is absorbed and energy is transferred to the constituent molecules. However, due to the high energy density of the ultrashort wave laser pulse, the absorbed energy density is also high, causing plasma to form instantaneously inside the glass substrate 21. Such plasma can affect the optical properties of subsequent pulses when continuous pulses are applied. The plasma thus generated disappears after a certain lifetime, which can cause deformation into a structure different from the surrounding material. Depending on the cutting processing conditions, a narrow and long empty space in the thickness direction may be formed in the area irradiated by the ultrashort wave laser beam; this is called "filamentation".

[0149] Filamentation is distinct from gaps or cracks caused by thermal expansion. Because the pulse width is shorter than the reaction time of molecular bonding structures, it does not affect surrounding molecules with thermal or vibrational energy. Instead, it is a narrow gap that is instantaneously formed when energy is concentrated in the irradiated area of ​​an ultrashort wave laser beam.

[0150] Once filamentation is formed, the glass substrate 21 can be cut using the filamentation, that is, separated into units (separation), as shown in Figure 8(c).

[0151] As shown in the figure, the glass substrate 21 can be separated into two or more units by applying tensile stress or rotational force (rotational torque) to the filamentation in order to cut the glass substrate 21.

[0152] In other embodiments, the glass substrate 21 may be separated using a laser or a dicing saw.

[0153] As shown in Figure 8(c), when the glass substrate 21 is separated into predetermined units, the insulating layer of the upper layer 70 has a tapered shape, becoming thinner in the direction of the cut surface of the glass substrate 21, and the glass substrate 21 has a shape in which the upper layer 70 is exposed and protrudes in the direction of the cut surface.

[0154] Depending on the specific example, if a green laser is used to remove the upper layer 70, the laser speed used to irradiate the upper layer 70 may be 20 mm / s to 40 mm / s. The laser speed used for filamentation irradiation may be 50 mm / s to 150 mm / s, or 80 mm / s to 120 mm / s.

[0155] Figure 9 is a flowchart illustrating the manufacturing process of a packaging substrate in another concrete example, shown in cross-section.

[0156] As shown in Figure 9(a), an upper layer 70 is formed on the first surface of the glass substrate 21, and a lower layer 80 is formed on the second surface. In other words, in the glass substrate 21 of Figure 8, the upper layer 70 is formed only on the first surface of the two surfaces, so only the upper layer 70 was removed. However, in the case of Figure 9, since the lower layer 80, including an insulating layer, is also formed on the second surface of the glass substrate 21, the insulating layer can be removed on both sides.

[0157] The width of the upper layer 70 and the lower layer 80 to be removed may be within the same range. Specifically, the width of the lower layer 80 to be removed may be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more, based on the width from the edge of the insulating layer to the edge of the glass substrate in the unit glass substrate. Alternatively, the width may be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0158] The widths of the upper layer 70 and the lower layer 80 to be removed may vary depending on the design of the semiconductor element or motherboard to be mounted. The removal width of the lower layer 80 may be greater than that of the upper layer 70. Specifically, the difference between the removal width of the upper layer and the removal width of the lower layer may be 1 μm or more, 3 μm or more, 5 μm or more, or 10 μm or more. The difference may also be 20 μm or less.

[0159] The laser irradiation intensity used to remove the insulating layer is not greater than the irradiation intensity used to form filamentation, and even if lasers are used on both surfaces, no damage or defects can be formed on the glass substrate 21.

[0160] The insulating layer can be removed by simultaneously or sequentially irradiating both surfaces on which the upper layer 70 and the lower layer 80 are formed with a laser. On the other hand, while the laser for removing the upper layer 70 and the lower layer 80 can act on either of the two surfaces, as shown in Figure 9(b), the laser for generating filamentation can be irradiated on only one of the first and second surfaces (on single side).

[0161] The separation of the glass substrate 21 after the filamentation process can be performed based on tension or rotational torque induced by an external force, as shown in Figure 9(c).

[0162] Figures 10(a) and (b) are photographs showing the manufacturing process of a packaging substrate in a concrete example.

[0163] Figure 10(a) is a sectional view and top view photograph of the glass substrate 21 (before being separated into units) with the upper layer 70 removed, as shown in Figure 8(a) or Figure 9(a). In other words, it is a photograph corresponding to an enlarged view of the dotted rectangular area in Figure 9(a), which is part of the substrate.

[0164] As shown in the sectional view of Figure 10(a), the upper layer 70 is removed by a predetermined width w, and it can be confirmed in the top view that the glass substrate 21 is exposed by the removed width w. Furthermore, as can be observed in the sectional view, no defects are formed in the glass substrate 21 even when the upper layer 70 is removed. In addition, the removed upper layer 70 may have a tapered shape that becomes thinner in the direction of the cut surface.

[0165] Figure 10(b) is a photograph showing the cut edges after the glass substrate 21 has been cut into units according to Figures 8(a) and 9(a). The glass substrate 21 is separated in a nearly straight line, with the upper layer 70 and lower layer 80 positioned on both sides of the glass substrate, each at a certain distance inward from the edge of the glass substrate.

[0166] As shown in the figure, the glass substrate 21 can be separated by filamentation formed along a predetermined cutting line. Such separation reduces the likelihood of defects occurring or being inherent in the glass, and even if defects do occur, they can be identified quickly and in a relatively simple manner, thus further improving the efficiency of the semiconductor packaging substrate manufacturing process, including the unitization process of the glass substrate.

[0167] On the other hand, in one embodiment, the edge regions located at the corners of the glass substrate 21 can be processed to become curved. That is, the edge regions of the glass substrate 21 can be ground. In other words, the corners of the glass substrate 21 can be rounded from a cut, sharp state (see the illustrative photograph in Figure 11).

[0168] Figure 11 is a photograph of a cross-section of a ground glass substrate in an example of its application.

[0169] As shown in the figure, the cross-section of the glass substrate 21 protruding from the upper or lower layer (indicated as "CL" in Figure 11) can be rounded in cross-sectional view by grinding. The edges of the glass substrate removed through the grinding process may be approximately 10 μm or more, 20 μm or more, 30 μm or more, or 50 μm or more, and may be approximately 100 μm or less.

[0170] Through grinding, the corners of the cut surface may take on a curved shape as shown in Figure 11, and may be further modified to a chamfered shape in the form of a C-shape (curved shape) or R-shape (round shape) as shown in other embodiments.

[0171] A packaging substrate 20 having a cross-section may have its side surface, corresponding to its thickness, ground when viewed from the side (or cross-section). For example, the shape of the ground side surface may be a flat edge (a shape where the corner where the side surface and top surface of the packaging substrate meet is chamfered), or a pencil edge (a shape where the side surface connecting the top and bottom surfaces is ground in a rounded shape so that the central part of the side surface protrudes).

[0172] The side (edge) of the packaging substrate 20 may be a straight line or have a partially broken glass shape immediately after the cut surface is formed, and can be manufactured into a shape with a certain radius of curvature by grinding. In this case, the radius of curvature is called the side radius of curvature.

[0173] The radius of curvature of the side surface of the packaging substrate 20 may be 0.05 mm or more, 0.1 mm or more, 0.15 mm or more, or 0.2 mm or more. The radius of curvature of the side surface may be 2.0 mm or less, 1.8 mm or less, 1.6 mm or less, 1.2 mm or less, 1 mm or less, 0.8 mm or less, or 0.6 mm or less. In this case, workability can be improved, such as minimizing the occurrence of cracks in the packaging substrate or glass substrate during manufacturing and transportation processes.

[0174] For example, when grinding with a blade design angle of 90°±1° and a cutting amount of 0.08~0.14mm, it is possible to manufacture a packaging substrate with an edge curvature radius of 0.241mm.

[0175] Furthermore, as an example, when grinding is performed with the blade design angle set to 120°±1° and the cutting amount set to 0.05~0.12mm, it is possible to manufacture a packaging substrate with an edge curvature radius of 0.522mm.

[0176] Figure 12 shows a top view of a glass substrate relating to another embodiment, and a photograph of a part thereof. The glass substrate may have rounded edges not only in its cross-section, but also in the corners of the rectangle when viewed from above. Figure 12(a) shows a top view of a unit glass substrate, and the first surface 213 and the second surface 214 may also be rounded to give them a rounded shape, as shown in the figure.

[0177] A rectangular packaging substrate, when viewed from above, has four corners, and each corner is rounded to have a predetermined curvature, thereby removing sharp edges. This radius of curvature is called the substrate radius of curvature. The substrate radius of curvature may be 0.5 mm or more, 1 mm or more, 1.2 mm or more, or 1.5 mm or more. The substrate radius of curvature may also be 8 mm or less, 7 mm or less, 6 mm or less, or 5 mm or less. In such cases, the occurrence of cracks at the corners can be minimized, while at the same time, the area where the electrical conductive layers of the upper and / or lower layers are placed can be stably secured.

[0178] On the other hand, depending on the specific example, the vertices of the rectangular glass substrate 21 may also be curved through grinding. When the vertices are ground, the risk of damage or breakage can be reduced when moving the glass substrate 21 or transporting it on a tray or the like. The curvature of the ground vertices can be determined by setting a diameter that minimizes the deviation from a predetermined target value.

[0179] The cut edges of unprocessed glass substrates have uneven right-angle deviations, and hackle can occur at the cut corners, potentially leading to further damage such as cracks or chipping. Through grinding, glass substrates with curved edges or chamfered cut edges can have their risk of such further damage significantly reduced. Furthermore, external impacts can be properly dispersed during transport of glass substrates or packaging substrates in trays for movement or additional processes, minimizing defects caused by cracks or chipping.

[0180] As demonstrated in other examples, grinding may be applied not only to the protruding glass substrate 21 but also to the upper or lower layers.

[0181] The packaging substrate and its manufacturing method according to the embodiments described above are effective for inspecting defects that may occur in packaging substrates including glass structures, and can effectively protect the glass substrate from external impacts.

[0182] The present invention described above has been explained with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person with ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present invention is not limited to the embodiments described above, and various modifications and improvements made by persons skilled in the art using the basic concepts of the embodiments as defined in the attached claims also fall within the scope of the embodiments. Therefore, the true technical scope of protection of the present invention must be determined by the technical idea of ​​the attached claims. [Explanation of Symbols]

[0183] 100 Semiconductor Equipment 10 Motherboards 30 Semiconductor element section 32 First Semiconductor Element 34. Second Semiconductor Element 36 Third Semiconductor Device 20 Packaging substrates 21,21a Glass substrate 22 core layers 223 Core insulating layer 213 Page 1 214 2nd page 213a Border region 23 Corevia 24-core distribution layer 241 Core Distribution Pattern 26,70 Upper layer 25,71 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connecting layer 271 Top connecting electrode 272 Top connection pattern 28 Cavity section 281 Interior space 282 Cavity Distribution Layer 40 Cavity elements 60 Cover layer 72. First Cover Layer 80 Lower layer 81 Lower distribution layer 82 Second Cover Layer

Claims

1. A method for manufacturing a packaging substrate, The steps include preparing a glass substrate including a first surface and a second surface facing each other, and forming an upper layer on the first surface, A step of removing a portion of the upper layer along the cutting line, which is the position where cutting is planned, by laser ablation using a green laser or ultraviolet laser to form a removal line, A filamentation step of forming filaments on the glass substrate along the removal line using an infrared laser, The steps include cutting the glass substrate using the filamentation described above, The steps include grinding the cut surface of the cut glass substrate, Includes, The aforementioned packaging substrate is A glass substrate including a first surface and a second surface facing each other, It includes an upper layer laminated on the first surface, or a lower layer laminated below the second surface, The glass substrate has an edge region, The aforementioned edge region is The edge of the glass substrate, Including the region of the glass substrate that protrudes from the upper layer or the lower layer, A method for manufacturing a packaging substrate, further comprising the step of detecting a defect in any one selected from the group consisting of the edge region of the glass substrate, the cut surface of the glass substrate, the removal line of the upper layer, the removal line of the lower layer, and combinations thereof.

2. Before the aforementioned filamentation step, The steps include forming a lower layer below the second surface, The method for manufacturing a packaging substrate according to claim 1, further comprising the step of removing a portion of the lower layer along the cutting line to form a removal line.

3. The method for manufacturing a packaging substrate according to claim 1 or 2, wherein the width of the removal line is 5 μm or more.

4. The method for manufacturing a packaging substrate according to claim 1 or 2, wherein the upper layer or the lower layer each has a tapered shape that becomes thinner in the direction of the cut surface of the glass substrate.

5. The step of cutting the glass substrate is: The method for manufacturing a packaging substrate according to claim 1, comprising the step of applying tensile stress or rotational force to the filamentation to separate the glass substrate into two or more parts and forming a cut surface on the glass substrate.

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