Perform a host-initiated link reset in a storage area network.

Abstract

A computer-implemented method for performing a host-initiated link reset in a storage area network (SAN) includes identifying, by a host in communication with the SAN, each link in the SAN, where each link is defined by a pair of ports; obtaining, by the host, a buffer credit for each port in the SAN; and, based on a determination that the buffer credit of a port in the SAN is below a threshold, causing a reset of the link associated with the port by sending a link reset record from the host to a control device for the link.

Description

Technical Field

[0001] The present invention generally relates to a storage area network (SAN), and more specifically to performing a link reset initiated by a host in a SAN.

Background Art

[0002] During normal operation of a SAN, fiber channel frames including acknowledgements can be damaged in transmission. Such damage can be caused by optics failing, bad cables, loose connections, out-of-range optical budgets, intermittent hardware malfunctions, and the like.

[0003] When the receiving side of a fiber channel connection cannot recognize the start of frame (SOF) in the header of an incoming frame, it does not respond with an appropriate acknowledgement. In one example, the transmitting side decrements the available buffer credit by 1 as soon as it sends a frame, but does not receive the corresponding acknowledgement. As a result, from the perspective of buffer credits, the synchronization between the transmitting side and the receiving side is distorted. When this condition occurs, it tends to continue, gradually reducing the number of buffer credits recognized as available until it affects performance, or even causing the link transmission to completely stop.

[0004] Currently, the buffer credit recovery mechanism provided in the fiber channel standard attempts to prevent errors in the synchronization of buffer credits between the transmitting side and the receiving side. The standard supports two modes of buffer credit recovery: 1) link reset and 2) calculations that simply result in replenishment of credits. However, both modes of buffer credit recovery are performed exclusively by network devices such as switches and only for switch ports.

Summary of the Invention

[0005] One aspect of the present invention relates to a computer-implemented method for performing a host-initiated link reset in a storage area network (SAN). A non-limiting example of the computer-implemented method includes a host communicating with the SAN identifying each link within the SAN, each link being defined by a pair of ports. The method also includes the host obtaining buffer credits for each port in the SAN and, based on the determination that the buffer credits for a port in the SAN are below a threshold, causing a link reset associated with the port by sending a link reset record from the host to a link control device.

[0006] Other embodiments include storage area networks (SANs). Non-limiting examples of SANs include one or more network devices and a plurality of terminal devices, each coupled to at least one of the one or more network devices. One of the plurality of terminal devices is a host device configured to identify each link in the SAN, each link defined by a pair of ports. The host device is also configured to acquire buffer credits for each port in the SAN and to cause a reset of the link associated with a port by sending a link reset record from the host to a link control device based on a determination that the buffer credits for a port in the SAN are below a threshold.

[0007] Another aspect of the present invention relates to a computer program product for performing a host-initiated link reset in a storage area network (SAN), the computer program product comprising a computer-readable storage medium in which program instructions are embodied. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes a host communicating with the SAN identifying each link in the SAN, each link defined by a pair of ports. The method also includes the host obtaining buffer credits for each port in the SAN and causing a link reset associated with a port by sending a link reset record from the host to a link control device based on the determination that the buffer credits for a port in the SAN are below a threshold.

[0008] Further technical features and advantages are realized through the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered to be part of the subject matter claimed. For a better understanding, please refer to the detailed description and drawings.

[0009] Details of the exclusive rights described herein are specifically pointed out and expressly claimed in the patent claims at the conclusion of this specification. The above and other features and advantages of embodiments of the present invention will become apparent when the following detailed description is read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram of a computer system according to an embodiment of the present invention. [Figure 2] This is a schematic diagram of a storage area network according to an embodiment of the present invention. [Figure 3] This is a flowchart illustrating a method for performing a host-initiated link reset in a storage area network according to an embodiment of the present invention. [Figure 4]This is a flowchart illustrating a method for performing a host-initiated link reset in a storage area network, according to another embodiment of the present invention. [Figure 5] This is a block diagram of a link reset command according to another embodiment of the present invention. [Figure 6] This is a block diagram of a link reset record according to another embodiment of the present invention. [Modes for carrying out the invention]

[0011] The figures shown herein are for illustrative purposes only. Many variations are possible in the figures or the actions described therein without departing from the spirit of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term “combined” and its variations describe having a communication path between two elements, and do not imply a direct connection between elements where there is no intervening element / connection between them. All of these variations are considered part of this specification.

[0012] Exemplary embodiments include methods, systems, and computer program products for performing host-initiated link resets in a Storage Area Network (SAN). In the exemplary embodiments, a host device connected to the SAN is configured to monitor buffer credits reported as available on all ports in the SAN, including channel ports and switch ports. The host device is further configured to cause a link reset in the SAN as soon as it determines that the buffer credits on a port associated with a link have fallen below a threshold. The link reset forces the buffer credit counters for both ports of the link to return to their maximum default values.

[0013] Referring next to Figure 1, an embodiment of computer system 100 is shown in its entirety. Computer system 100 can be an electronic computer framework comprising, using, or both comprising, any number and combination of computing devices and networks utilizing various communication technologies, as described herein. Computer system 100 can be easily scalable, extensible, and modular with the ability to change to different services independently of others or to reconfigure some functions. Computer system 100 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer system 100 can be a cloud computing node. Computer system 100 can be described in general terms of computer system executable instructions, such as program modules, which are executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform a specific task or implement a specific abstract data type. The computer system 100 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may be located on both local and remote computer system storage media, including memory storage devices.

[0014] As shown in Figure 1, the computer system 100 has one or more central processing units (CPUs) 101a, 101b, 101c, etc. (collectively referred to as processors 101). Processors 101 can be single-core processors, multi-core processors, computing clusters, or any number of other configurations. Processors 101, also called processing circuits, are coupled to system memory 103 and various other components via a system bus 102. System memory 103 may include read-only memory (ROM) 104 and random-access memory (RAM) 105. ROM 104 may include a basic input / output system (BIOS) coupled to the system bus 102, which controls some basic functions of the computer system 100. RAM is read-write memory coupled to the system bus 102 for use by processors 101. System memory 103 provides memory space for the operation of the instructions during their operation. System memory 103 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0015] The computer system 100 comprises an input / output (I / O) adapter 106 and a communication adapter 107 coupled to a system bus 102. The I / O adapter 106 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 108 or any other similar component, or both. The I / O adapter 106 and the hard disk 108 are collectively referred to as the mass storage device 110 in this specification.

[0016] Software 111 for execution on computer system 100 may be stored in mass storage device 110. Mass storage device 110 is an example of a tangible storage medium readable by processor 101, and the software 111 is stored as instructions for execution by processor 101 to operate computer system 100, such as those described herein below with respect to various figures. Examples of computer program products and the execution of such instructions will be discussed in more detail herein. A communication adapter 107 interconnects system bus 102 to a network 112 which can be an external network, enabling computer system 100 to communicate with other such systems. In one embodiment, a portion of system memory 103 and mass storage device 110 jointly store an operating system, which can be any suitable operating system, such as the z / OS(R) or AIX(R) operating system from IBM Corporation, for coordinating the functions of the various components shown in Figure 1.

[0017] Additional input / output devices are shown connected to the system bus 102 via display adapter 115 and interface adapter 116. In one embodiment, adapters 106, 107, 115, and 116 may be connected to one or more I / O buses connected to the system bus 102 via an intermediate bus bridge (not shown). A display 119 (e.g., a screen or display monitor) is connected to the system bus 102 by display adapter 115, which may include a graphics controller and a video controller to improve performance for graphics-intensive applications. A keyboard 121, mouse 122, speaker 123, etc., may be interconnected to the system bus 102 via interface adapter 116, which may include, for example, a super I / O chip integrating multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Accordingly, as configured in Figure 1, the computer system 100 includes processing capabilities in the form of a processor 101, storage capabilities including system memory 103 and mass storage device 110, input means such as a keyboard 121 and mouse 122, and output capabilities including a speaker 123 and display 119.

[0018] In some embodiments, the communication adapter 107 can transmit data using any suitable interface or protocol, among others, such as the Internet Small Computer System Interface. The network 112 can be a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet. An external computing device can connect to the computer system 100 through the network 112. In some examples, the external computing device can be an external web server or a cloud computing node.

[0019] It should be understood that the block diagram in Figure 1 is not intended to show that computer system 100 includes all the components shown in Figure 1. Rather, computer system 100 may include any suitable fewer or additional components not shown in Figure 1 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, embodiments described herein with respect to computer system 100 can be implemented using any suitable logic, which in various embodiments may include any suitable hardware (e.g., among other things, a processor, an embedded controller, or an application-specific integrated circuit), software (e.g., among other things, an application), firmware, or any suitable combination of hardware, software, and firmware.

[0020] Figure 2 is a diagram of a storage area network (SAN) 200 according to an embodiment. The SAN 200 includes a plurality of terminal devices 210, 220, each connected to one or more network devices 230, such as switches. The network devices 230 include memory circuits and processing circuits (including, for example, monitoring circuits and limiting circuits). The network topology of the SAN 200 can be a switched fabric, where the network devices 230 are switches. In some embodiments, a particular switch 230 may be configured in switch mode or N-port ID virtualization (NPIV) mode. In an exemplary embodiment, at least one of the terminal devices 210, 220 within the SAN device 210 is configured as a host device 210. In one embodiment, the host device 210 is embodied in a computer system, such as the one shown in Figure 1.

[0021] In an exemplary embodiment, each network device 230 includes a plurality of ports that connect the network device 230 to various terminal devices 210, 220 via a link 225. In addition, each terminal device 210, 220 includes one or more ports that connect the terminal device to one or more network devices 230 or other terminal devices 220. In an exemplary embodiment, each link 225 is defined by two ports connected to the link 225. The ports of the terminal devices 220, 210 are called channel ports, and the ports of the network device 230 are called switch ports.

[0022] In an exemplary embodiment, network device 230 supports Fibre Channel (FC) or Fibre Channel over Ethernet (R) (FCoE) protocol or both. For example, certain fixed port network devices may support FC protocol or FCoE protocol or both. As another example, if a particular network device includes multiple line cards, at least some of them may support FC protocol, or at least some of them may support FCoE protocol, or both. It is noted that a particular port on a particular network device 230 may support FC protocol or FCoE protocol by default or as configured (e.g., if the particular port is a universal port). Optionally, network device 230 supports one or more other protocols, such as Simple Network Management Protocol (SNMP) for collecting information, for example, for output on management device 210.

[0023] Next, referring to FIG. 3, a flow diagram of a method 300 for performing a link reset initiated by a host in a storage area network according to an embodiment of the present invention is shown. As shown in block 302, method 300 includes identifying each link in the SAN by a host communicating with the SAN. In an exemplary embodiment, each link in the SAN is defined by a pair of ports, which can be one of a channel port and a switch port, or two switch ports in the case of an inter-switch link. Method 300 also includes, as shown in block 304, obtaining buffer credits for each port in the SAN by the host. Next, as shown in block 306, method 300 includes determining whether the buffer credit for a port in the SAN has dropped below a threshold value. If the buffer credit for a link port in the SAN has dropped below the threshold value, method 300 proceeds to block 308 and causes a link reset by transmitting a link reset record from the host to the control device of the port. Otherwise, method 300 returns to block 304.

[0024] In an exemplary embodiment, the threshold value has a default value of 1 and can be set to any other positive integer value by the user of the host device. In other embodiments, the threshold value can be set based on link characteristics such as the bit rate of the link or the distance of the link or both. In an exemplary embodiment, obtaining buffer credits for each port in the SAN is performed on a periodic basis. For example, in one embodiment, the host device is configured to obtain buffer credits for each port in the SAN every 15 minutes or at other predetermined intervals set by the user of the host device.

[0025] In exemplary embodiments, after it is determined that a link needs to be reset, the action taken to reset the link depends on the type of ports defining the link. In one embodiment, based on the determination that at least one of the port pair for the link is a channel port, the host device causes the link to be reset by issuing a command to the channel port to reset the link. In another embodiment, based on the determination that neither of the port pair is a channel port, the host device causes the link to be reset by instructing the network device in the SAN associated with the link to perform a link reset. In one embodiment, the instruction is sent to the network device using a control unit port (CUP).

[0026] In an exemplary embodiment, a SAN utilizes Fibre Channel for communication between nodes. Fibre Channel is configured to transmit packets of data called frames, which include frame delimiters that define the start-of-frame (SOF) or end-of-frame (EOF) boundaries. Primitive signals representing events on a transmitting port include acknowledgment signals (R_RDY) and inter-buffer state change (BB_SC) signals. The BB_RDY_N variable is typically used to hold a count of received R_RDY primitives, and BB_FRM_N holds a count of received frames. The inter-buffer state change (BB_SC_N) reflects a value specifying the number of frames between BB_SCs primitives and the number of R_RDYs between BB_SCr primitives. The inter-buffer state change R_RDY (BB_SCr) signal is transmitted periodically to allow an attached port to determine whether any R_RDYs have been lost. The inter-buffer state change SOF(BB_SCs) signal is sent to allow the attached port to determine whether any frames have been lost.

[0027] In an exemplary embodiment, BB_SC_N (number of buffer-to-buffer state changes) is used to track the agreed-upon maximum buffer credit for the link between two ports. For example, when two ports are connected, during login (FLOGI or PLOGI), the ports perform Exchange Link Parameters (ELP) and send each other Internal Link Service (ILS) frames carrying those values. If the two ports have different values, the larger of the two values ​​is used by both ports. Typically, BB_SC_N is in the range of 1 to 15. In an exemplary embodiment, the variable F is used to specify the number of frames to be sent between BB_SCs and the number of R_RDYs sent between BB_SCr fundamental signals. In one embodiment, F is 2 BB_SC_N It is defined as follows. In other words, to establish a checkpoint, the BB_SCs signal is sent every F frames and BB_SCr is sent every F R_RDYs. In one example, BB_SC_N=3 and therefore F=8. In this example, each port will send BB_SCs every 8 frames to receive inter-buffer flow control, and each port will send BB_SCr every 8 R_RDYs.

[0028] In an exemplary embodiment, each port maintains a count of the number of frames received between the completion of login and the reception of the first BB_SCs, e.g., BB_FRM_N. In addition, each port also maintains a count of consecutive occurrences of BB_SCs. When the frame count reaches F, it wraps back to zero and starts again from the beginning. However, if the counter is not zero when BB_SCs arrive, this means that one or more frames have been lost.

[0029] In an exemplary embodiment, each port maintains a count of the number of R_RDYs received between the completion of the login and the reception of the first BB_SCr, e.g., BB_RDY_N. Each port also maintains a count of consecutive occurrences of BB_SCr. When the count of R_RDYs reaches a calculated value F, it wraps back to zero and starts again. However, if the count of received R_RDYs is not zero when BB_SCr is received, one or more R_RDYs have been lost.

[0030] Next, referring to Figure 4, a flowchart of method 400 for performing a host-initiated link reset in a storage area network according to another embodiment of the present invention is shown. As shown in block 402, BB_SCr or BB_SCs reach the port. Next, as shown in determination block 404, it is determined whether BB_RDY_N or BB_FRM_N is equal to zero. If BB_RDY_N or BB_FRM_N is equal to zero, method 400 proceeds to block 406 and continues normal operation of the SAN. However, if one of BB_RDY_N and BB_FRM_N is not equal to zero, it is determined that one or more frames or R_RDYs have been lost, and method 400 proceeds to determination block 408.

[0031] As those skilled in the art will understand, BB_RDY_N and BB_FRM_N are different embodiments of the counting / tracking implementations permitted in the Fibre Channel standard. In exemplary embodiments, it is normal for these counters to have zero values ​​and no action is required. However, when these counters have non-zero values, this indicates that the R_RDY base element is lost or missing, and therefore the number of buffer credits available on the receiving end of the link is no longer their full or expected configured value. In exemplary embodiments, a threshold is used to trigger the decision of when to perform buffer credit recovery. In different embodiments, the threshold trigger can be a user-configurable value based on the percentage of the port's logged-in BB_Credit value, 0 remaining buffer credits, buffer credits less than a specified value (e.g., less than 5), or the number of frame pacing delay instances reported through the RMF (Resource Measurement Function) 74-7 (FICON Director Activity Report) during a configured RMF interval.

[0032] Continuing with Figure 4, in decision block 408, it is determined whether the threshold for buffer credit loss has been triggered. If so, method 400 proceeds to decision block 410. Otherwise, method 400 proceeds to block 406 and continues the normal operation of the SAN. In decision block 410, it is determined whether one or more of the link's ports are channel ports or directly attached control unit (CU) ports. If one or more of the link's ports are channel ports or directly attached CU ports, method proceeds to block 412, where the host device issues a command to the channel port to perform a link reset (LR). Otherwise, method proceeds to block 414, where the host device issues a command (via FICON CUP or SMI-S) to perform a link reset. In an exemplary embodiment, the host device sends a link reset command to the control device for the identified link. The link reset command includes a link reset record created by the host. The link reset record includes, among other things, the identification of the source and destination ports that define the link to be reset. Method 400 is completed in block 416 when the buffer credit on the link is recovered. In an exemplary embodiment, during the LR, frames are not discarded, but are held in the buffer until the LR is completed and all involved counters are reset to their initial values, effectively "replenishing" the "lost" buffer credit.

[0033] Referring to Figure 5, a link reset command 500 according to another embodiment of the present invention is shown. In an exemplary embodiment, a host device is configured to generate a link reset command 500 and send the link reset command 500 to a control device. In an exemplary embodiment, the control device is a network device in the SAN associated with the link to be reset. The link reset command 500 is sent by a link reset log, which causes the control device to reset the link.

[0034] Referring next to Figure 6, a link reset record 600 according to another embodiment of the present invention is shown. As shown, the link reset record 600 includes a director type field 602, a C field 604, an R field 606, a source port address identifier field 608, a destination port address identifier field 610, a director domain ID field 612, a transmit frame pacing time field 614, a receive frame pacing time field 616, a host identifier field 618, and a threshold field 620. In one embodiment, the director type field 602 is a 4-bit field used to identify the type of director that created the link reset record 600. The director type is used to identify the type of director listed in the director ID field 612. The director type is one of a source director, an intermediate director, and a destination director. The Source Director type indicates that the Director ID 612 field identifies the source port address of the link to be reset. The Intermediate Director type indicates that the Director ID 612 field identifies a director located between the source director and the destination director, and does not contain either a source or destination port address. The Destination Director type indicates that the Director ID 612 field identifies the destination port address of the link to be reset. The C field 604 is used to specify whether the link reset threshold used is the transmit frame pacing time or the receive frame pacing time. The R field 606 is a reserved field that defaults to containing all zeros. The Source Port Address Identifier field 608 contains the 24-bit Fibre Channel source port address identifier of the link to be reset. The Destination Port Address Identifier field 610 contains the 24-bit Fibre Channel destination port address identifier of the link to be reset.The transmit frame pacing time field 614 and the receive frame pacing time field 616 include a count of the number of frame transmission units that were prevented from being transmitted or received. The host identifier field 618 includes the identification of the host that created the link reset record 600. The threshold field 620 includes a user-defined value for a threshold for frame pacing time used to generate the link reset record 600.

[0035] In an exemplary embodiment, as soon as the host detects that the buffer credits for a link in the storage area network are below a threshold, the host device creates a link reset record, such as the one shown in Figure 6. The host then creates a link reset command, such as the one shown in Figure 5. The link reset command, along with the link reset record, is then sent from the host to the control device for the identified link. The link reset command includes the link reset record created by the host.

[0036] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments of the present invention can be devised without departing from the scope of the present invention. Various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described in the following description and in the drawings. These connections or positional relationships, or both, can be direct or indirect unless otherwise specified, and the present invention is not limited in this respect. Thus, the joining of entities can refer to direct or indirect joining, and the positional relationships between entities can be direct or indirect positional relationships. Furthermore, various tasks and processing steps described herein can be incorporated into more comprehensive procedures or processes having additional steps or functions not described herein in detail.

[0037] The following definitions and abbreviations are for use in the claims and interpretation of this specification. As used herein, the terms “comprises, comprising,” “includes, including,” “has, having,” “contains or containing,” or any other variation thereof, encompass non-exclusive inclusion. For example, a composition, mixture, process, method, product, or apparatus comprising a list of elements is not necessarily limited to those elements and may include other elements not expressly enumerated or specific to such composition, mixture, process, method, product, or apparatus.

[0038] In addition, the term “exemplary” as used herein means “serving as an example, case, or illustration.” Embodiments or designs described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” may be understood to include any integer one or more, i.e., 1, 2, 3, 4, etc. The term “a plurality” may be understood to include any integer two or more, i.e., 2, 3, 4, 5, etc. The term “connection” may include both indirect and direct “connections.”

[0039] The terms “about,” “substantially,” and “approximately,” and their variations, are intended to include the degree of error associated with the measurement of a particular quantity, based on the equipment available at the time of filing this application. For example, “about” could include ±8%, 5%, or 2% of a given value.

[0040] For simplicity, prior art relating to the creation and use of embodiments of the present invention may or may not be described in detail herein. Specifically, various embodiments of computing systems and particular computer programs for implementing the various technical features described herein are well known. Therefore, for simplicity, details of many conventional implementations are described only briefly herein, or are omitted entirely without showing details of well known systems or processes or both.

[0041] The present invention may be a system, method, or computer program product or combination thereof at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0042] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium may be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disks (DVDs), memory sticks, floppy disks, mechanical encoding devices such as punch cards or grooved structures with instructions recorded on them, and any suitable combination thereof. As used herein, computer-readable storage media are not interpreted as being transient signals in themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through electric wires.

[0043] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0044] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk(R) and C++, and procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may be executed as a standalone software package exclusively on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or exclusively on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute a computer-readable program instruction by personalizing the electronic circuit using state information of the computer-readable program instruction in order to perform an aspect of the present invention.

[0045] Aspects of the present invention are described herein by reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and combinations of blocks in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0046] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a dedicated computer, or another programmable data processing device to generate a machine that produces means for instructions to be executed by the processor of a computer or other programmable data processing device to perform functions / operations specified in one or more blocks of a flowchart or block diagram, or both. These computer-readable program instructions can also be stored in a computer-readable storage medium on which the instructions are stored, which can instruct a computer, a programmable data processing device, or other device or combination thereof to function in a particular way to provide a product containing instructions that perform the modes of functions / operations specified in one or more blocks of a flowchart or block diagram, or both.

[0047] Computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other device so that the instructions executed on the computer, other programmable device, or other device perform a function / operation specified in one or more blocks of a flowchart or block diagram, or both, and so that a series of action steps are performed on the computer, other programmable device, or other device to produce a process executed by the computer.

[0048] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this context, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction comprising one or more executable instructions for performing a specified logical function. In some alternative implementations, the functions described within a block may occur in a different order than those shown in the figure. For example, two consecutively shown blocks may actually be executed substantially in parallel, or blocks may sometimes be executed in reverse order depending on the functionality involved. It should also be noted that each block in a block diagram or flowchart, or both, and combinations of blocks in a block diagram or flowchart, or both, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or executes a combination of dedicated hardware and computer instructions.

[0049] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not exhaustive or limited to the embodiments disclosed. Those skilled in the art will see many variations and modifications without departing from the scope and spirit of the embodiments described. The terminology used herein has been chosen to best describe the principles of the embodiments, practical applications, or technical improvements to the art available on the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A computer-based method for performing a host-initiated link reset in a storage area network (SAN), The identification of each link within the SAN by a host communicating with the SAN, wherein each link is defined by a pair of ports, The host obtains buffer credits for each port within the SAN, Based on the determination that the buffer credits of a port within the SAN are less than the link reset threshold buffer credits, the host sends a link reset record to the link control device, thereby causing a reset of the link associated with the port. Includes, The link reset record includes a source port address and a destination port address that identify the link. method.

2. The method, performed by a computer according to claim 1, wherein the acquisition of the buffer credits for each port within the SAN is performed on a periodic basis.

3. The method performed by the computer according to claim 2, wherein the frequency of the periodic base is configurable by the user of the host.

4. The computer-based method according to claim 1, wherein the threshold is a predetermined number provided by the user.

5. The computer-based method according to claim 1, wherein the threshold is a predetermined number having a default value of zero.

6. A Storage Area Network (SAN), One or more network devices and Each comprises a plurality of terminal devices coupled to at least one of the one or more network devices, and one of the plurality of terminal devices is Identifying each link within the SAN, where each link is defined by a pair of ports, and the identification of each link. To obtain buffer credits for each port within the aforementioned SAN, Based on the determination that the buffer credits of a port within the SAN are less than the link reset threshold buffer credits, the host sends a link reset record to the link control device, thereby causing a reset of the link associated with the port. A host device configured to perform the following: The link reset record includes a source port address and a destination port address that identify the link. Storage Area Network (SAN).

7. The SAN according to claim 6, wherein the acquisition of the buffer credits for each port within the SAN is performed on a periodic basis.

8. The SAN according to claim 7, wherein the frequency of the periodic base is configurable by the user of the host.

9. The SAN according to claim 6, wherein the threshold is a predetermined number provided by the user.

10. The SAN according to claim 6, wherein the threshold is a predetermined number having a default value of zero.

11. A computer program that causes a computer to perform the method described in any one of claims 1 to 5.

Images