Display panels and display devices

Abstract

To provide a display panel and a display device.SOLUTION: A display panel includes: a first display region; a second display region located on at least one side of the first display region, density of pixel units in the first display region is less than density of pixel units in the second display region; a plurality of pixel units including a pixel circuit; and a first power line configured to provide a first voltage signal to the pixel circuit, where the first power line includes a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of third conductive lines, the first conductive lines extend from the second display region to the first display region, the plurality of second conductive lines are located in the first display region and are located between adjacent first conductive lines, the second conductive lines extend along a first direction, the third conductive lines extend along a second direction, the first direction crosses the second direction, the third conductive lines extend from the second display region to the first display region, and adjacent second conductive lines are spaced apart from each other along the first direction, and the second conductive lines are connected to the first conductive lines through the third conductive lines.SELECTED DRAWING: Figure 6A

Description

Cross-reference to related applications

[0001] For all purposes, this patent application claims the priority of Chinese Patent Application No. 202010498518.8 filed on June 4, 2020, and the entire content disclosed in the above Chinese patent application is incorporated herein by reference as part of this application.

Technical Field

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device.

Background Art

[0003] Based on the design of an under-screen camera, the display panel usually includes a high pixel density (Pixels Per Inch, PPI) region and a low PPI region. However, in a general display panel, the light transmittance of the low PPI region is low, which is disadvantageous for improving the display effect in the imaging region of the camera.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure includes a first display area, a second display area located at least to one side of the first display area, and a plurality of pixel units located in the first and second display areas, wherein the density of pixel units in the first display area is less than the density of pixel units in the second display area, the pixel units comprising a plurality of pixel units including a pixel circuit, and a first power line configured to provide a first voltage signal to the pixel circuit, wherein the first power line comprises a plurality of first conductors, a plurality of second conductors, and a plurality of third conductors. The present invention provides a display panel in which one conductor extends from the second display area to the first display area, the plurality of second conductors are located in the first display area and between adjacent first conductors, the second conductors extend along a first direction, the third conductor extends along a second direction, the first direction intersects with the second direction, the third conductor extends from the second display area to the first display area, adjacent second conductors are spaced apart from each other along the first direction, and the second conductors are connected to the first conductors via the third conductors.

[0006] According to some embodiments of the present disclosure, the plurality of second conductors are arranged sequentially along the first direction.

[0007] According to some embodiments of the present disclosure, the adjacent second conductors are not directly connected.

[0008] According to some embodiments of the present disclosure, the length of the portion of the first conductor located in the first display area in the first direction is greater than the length of the second conductor in the first direction.

[0009] According to some embodiments of the present disclosure, the first conductor includes portions located in different layers, and these portions are connected via vias that penetrate the insulating layer.

[0010] According to some embodiments of the present disclosure, the first power line further includes a fourth conductor extending in the second direction, the second conductor being connected to the first conductor via the fourth conductor, and the length of the fourth conductor in the second direction being less than or equal to the length of the third conductor in the second direction.

[0011] According to some embodiments of the present disclosure, a display panel includes a plurality of fourth conductors located between adjacent third conductors, wherein the plurality of fourth conductors are arranged sequentially along the second direction, and adjacent fourth conductors are spaced apart from each other in the second direction.

[0012] According to some embodiments of the present disclosure, a portion of the first conductor and the third conductor are located on the same layer, and the fourth conductor and the third conductor are located on the same layer.

[0013] According to some embodiments of the present disclosure, the display panel is configured such that the pixel unit located in the first display area constitutes a plurality of pixel islands, each pixel island includes two pixel units located in at least two adjacent rows, and the first and second wires each overlap with the two pixel units located in the two adjacent rows.

[0014] According to some embodiments of the present disclosure, a display panel comprises a pixel unit further comprising a light-emitting element, the pixel circuit comprising a first transistor and a second transistor, the first transistor being connected to the second transistor, the second transistor being connected to the light-emitting element, the first transistor comprising a first channel and a second channel, the first channel and the second channel being connected via a conductive portion, the second conductor further comprising a connecting arm, the connecting arm being spaced apart from and partially overlapping the conductive portion of one pixel unit superimposed on the second conductor in the pixel island in the third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

[0015] According to some embodiments of the present disclosure, the shape of the connecting arm includes a C-shape.

[0016] According to some embodiments of the present disclosure, the first conductor has a branch, the branch is spaced apart from the conductive portion of one pixel unit superimposed on the first conductor in the pixel island in the third direction, and partially overlaps with the third direction.

[0017] According to some embodiments of the present disclosure, the first direction is perpendicular to the second direction.

[0018] According to some embodiments of the present disclosure, the first power line further includes a fifth conductor, the fifth conductor extending along the first direction, located in the second display area, between adjacent first conductors, and spaced apart from a second conductor adjacent to the fifth conductor along the first direction.

[0019] According to some embodiments of the present disclosure, the display panel further includes initialization signal lines configured to provide initialization signals to the pixel circuit, wherein the second conductor is surrounded by a portion of the initialization signal lines.

[0020] According to some embodiments of the present disclosure, the first conductor includes a first portion and a second portion, the first portion of the first conductor is located on the same layer as the second conductor, the second portion of the first conductor is not located on the same layer as the second conductor, and the first portion of the first conductor is surrounded by a portion of the initialization signal line.

[0021] According to some embodiments of the present disclosure, the first portion of the first conductor has a first sub-part extending in a first direction and a second sub-part extending in a second direction, the second sub-part having a branch extending in the first direction.

[0022] According to some embodiments of the present disclosure, the length of the branch in the first direction is less than the length of the first sub-part in the first direction.

[0023] According to the display panel according to some embodiments of the present disclosure, the pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected via a conductive portion, the branch is spaced apart from the conductive portion of one pixel unit that overlaps the first conductor in the pixel island in the third direction and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0024] According to the display panel according to some embodiments of the present disclosure, the second conductor further includes a connection arm, the connection arm is spaced apart from the conductive portion of one pixel unit that overlaps the second conductor in the pixel island in the third direction and partially overlaps in the third direction.

[0025] According to the display panel according to some embodiments of the present disclosure, the display panel further includes a base substrate and a data line configured to provide a data signal to the pixel circuit, the data line includes a first data line, the first data line extends from the first display area to the second display area, and the first data line partially overlaps with the orthographic projection of the third conductor on the base substrate.

[0026] According to the display panel according to some embodiments of the present disclosure, the first data line includes a first portion and a second portion, the first portion of the first data line partially overlaps with the third conductor, the second portion of the first data line does not overlap with the third conductor, and the first portion of the first data line and the second portion of the first data line are located in different layers.

[0027] According to the display panel according to some embodiments of the present disclosure, there is a light transmission area between adjacent pixel islands, and the first portion of the first data line is located between adjacent pixel islands.

[0028] According to the display panel according to some embodiments of the present disclosure, two first data lines are provided, and the two first data lines are respectively connected to two adjacent columns of pixel units, and the two first data lines are partially overlapped with the orthographic projection of the same third conductor on the base substrate.

[0029] According to the display panel according to some embodiments of the present disclosure, the display panel further includes a gate line configured to provide a scanning signal to one row of pixel units, and the gate line includes a first gate line extending from the second display area to the first display area, and the light transmission area is surrounded by two adjacent first gate lines and two adjacent first data lines.

[0030] Some embodiments of the present disclosure further provide a display device including any of the above display panels.

[0031] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings described below are only related to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

[0032] [Figure 1A] FIG. 1A is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1B] FIG. 1B is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 1C] FIG. 1C is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of the second display area of a display panel according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram of the first display area of a display panel according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic diagram of a pixel unit and a signal line for providing a signal to the pixel unit in a display panel according to an embodiment of the present disclosure. [Figure 5] Figure 5 is a schematic diagram of the display panel. [Figure 6A] Figure 6A is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 6B] Figure 6B is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 6C] Figure 6C is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 6D] Figure 6D is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 6E] Figure 6E is a schematic diagram of a display panel according to some embodiments of the present disclosure. [Figure 7A] Figure 7A is a schematic diagram of a display panel according to one embodiment of the present disclosure. [Figure 7B] Figure 7B is a schematic diagram of a display panel according to one embodiment of the present disclosure. [Figure 8] Figure 8 is a schematic diagram of the pixel circuit of a display panel according to one embodiment of the present disclosure. [Figure 9] Figure 9 is a plan view of a semiconductor pattern in a display panel according to one embodiment of the present disclosure. [Figure 10] Figure 10 is a plan view of the first conductive pattern layer in a display panel according to one embodiment of the present disclosure. [Figure 11] Figure 11 is a plan view of the second conductive pattern layer in a display panel according to one embodiment of the present disclosure. [Figure 12] Figure 12 is a plan view of the first insulating layer in a display panel according to one embodiment of the present disclosure. [Figure 13] Figure 13 is a plan view of the third conductive pattern layer in a display panel according to one embodiment of the present disclosure. [Figure 14] Figure 14 is a plan view of the second insulating layer in a display panel according to one embodiment of the present disclosure. [Figure 15] Figure 15 is a plan view of the pixel electrode layer in a display panel according to one embodiment of the present disclosure. [Figure 16]Figure 16 is a plan view of the pixel definition layer in a display panel according to one embodiment of the present disclosure. [Figure 17] Figure 17 is a schematic diagram of the active layer forming a thin-film transistor in a display panel according to one embodiment of the present disclosure. [Figure 18] Figure 18 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the second conductive pattern layer and the first insulating layer have been formed. [Figure 19] Figure 19 is a schematic plan view of a display panel according to one embodiment of the present disclosure after a third conductive pattern layer has been formed. [Figure 20] Figure 20 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the second insulating layer has been formed. [Figure 21] Figure 21 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the pixel electrode layer has been formed. [Figure 22] Figure 22 is a schematic plan view of a display panel according to one embodiment of the present disclosure after pixel definitions have been formed. [Figure 23] Figure 23 is a schematic plan view of adjacent pixel islands in the second direction in the first display area of ​​a display panel according to one embodiment of the present disclosure. [Figure 24] Figure 24 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 25] Figure 25 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0033] To further clarify the purpose, technical proposal and advantages of the embodiments of this disclosure, the technical proposal of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. As is obvious, the embodiments described are a part of, but not all, of, the embodiments of this disclosure. All other embodiments that a person skilled in the art could obtain without creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0034] Unless otherwise defined, technical or scientific terms used in this disclosure should have a general meaning that is understandable to those skilled in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but merely distinguish different components. Similarly, similar terms such as “includes” or “equip” mean that the element or component listed before the term includes the elements or components listed after the term, and their equivalents, but do not exclude other elements or components. Similar terms such as “connected” or “linked” are not limited to physical or mechanical connections, but may also include electrical connections, whether directly or indirectly connected. “Up,” “down,” “left,” “right,” etc., are used only to indicate relative positions, and such relative positions may change as the absolute position of the subject changes.

[0035] In typical display panels, the first power lines use a mesh structure regardless of whether they are in the high-PPI or low-PPI region. To improve light transmittance in the low-PPI region and enhance the display effect in the camera's imaging region, the display panel according to the embodiment of the present disclosure achieves higher transmittance by optimizing the signal lines in the low-PPI region. For example, the embodiment of the present disclosure optimizes the arrangement of the wires in the mesh first power lines, both vertically and horizontally.

[0036] Figures 1A to 1C are schematic diagrams of display panels according to some embodiments of the present disclosure. As shown in Figures 1A to 1C, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is a high-pixel density (Pixels Per Inch, PPI) area, and the second display area R2 is a low-PPI area. The second display area R2 is a partially light-transmitting area. As shown in Figures 1A to 1C, the second display area R2 is located on at least one side of the first display area R1. The display panels shown in Figures 1A and 1B further include a third area R3. For example, a sensor such as a camera may be installed in the first display area R1 (see Figure 1C), or in the first display area R1 and the third area R3 (see Figures 1A and 1B). The third area R3 shown in Figures 1A and 1B may be a drilled area, i.e., a through hole is formed by removing material at the location corresponding to the third area R3. The sensor can receive ambient light. Taking a camera as an example, an underscreen camera can be implemented. When the screen is used normally, the first display area corresponding to the sensor can display the screen normally, while when the camera is taking pictures, the first display area can transmit ambient light to support normal use. For example, the sensor is installed on the non-display side of the display panel. The sensor may also be called an underscreen device.

[0037] Figure 1A further shows a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 include a first gate line GL1, and the plurality of data lines 313 include a first data line DL1. The first gate line GL1 extends from the second display area R2 to the first display area R1. The first data line DL1 extends from the first display area R1 to the second display area R2. In embodiments of this disclosure, when a certain element extends from the first display area R1 to the second display area R2, it may be understood that the element is located in both the first and second display areas R1 and R2, or it may be said that a certain element extends from the second display area R2 to the first display area R1. For clarity of illustration, Figure 1A shows some gate lines 113 and some data lines 313 as examples, and the number of gate lines 113 and data lines 313 can be determined as needed. The plurality of gate lines 113 and the plurality of data lines 313 intersect with each other and are insulated from each other.

[0038] Figure 2 is a schematic diagram of the second display area of ​​a display panel according to one embodiment of the present disclosure. Figure 3 is a schematic diagram of the first display area of ​​a display panel according to one embodiment of the present disclosure. As shown in Figures 2 and 3, the display panel includes a plurality of pixel units P0, the plurality of pixel units P0 include a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104. One first pixel unit 101, one second pixel unit 102, one third pixel unit 103, and one fourth pixel unit 104 constitute a pixel group P1. For example, one pixel group P1 includes two pixels, in which one first pixel unit 101 and one second pixel unit 102 constitute one pixel, and one third pixel unit 103 and one fourth pixel unit 104 constitute one pixel. One pixel group P1 improves the display effect by forming two virtual pixels. For example, one pixel group P1 is a repeating unit and is arranged in an array in the second display area R2. As shown in Figure 3, in the first display area R1, one pixel group P1 is called one pixel island A1. The first display area R1 includes multiple light-transmitting areas R0, which are located between adjacent pixel islands A1. The light-transmitting areas R0 can transmit ambient light. For example, the light-transmitting areas R0 may include a base substrate and a transparent insulating layer located on the base substrate, and the light-transmitting areas R0 do not have a light-shielding structure such as metal wiring. For example, the light-transmitting areas R0 are located within an area surrounded by four adjacent pixel islands A1, but are not limited to this. For example, as shown in Figure 3, adjacent pixel islands A1 may be spaced apart.

[0039] In the embodiments of this disclosure, the first pixel unit 101 is a red pixel unit, the second pixel unit 102 is a green pixel unit, the third pixel unit 103 is a blue pixel unit, and the fourth pixel unit 104 is a green pixel unit. However, in other embodiments, the pixel group may consist of pixel units of other colors. Of course, in other embodiments, the arrangement of the multiple pixel units P0 in the display panel is not limited to those shown in Figures 2 and 3.

[0040] As shown in Figures 2 and 3, multiple pixel units P0 are located in the first display area R1 and the second display area R2, and the density of pixel units in the first display area R1 is less than the density of pixel units in the second display area R2. Or, the pixel density in the first display area R1 is less than the pixel density in the second display area R2. The density of pixel units in the first display area R1 shown in Figure 3 is 1 / 4 of the density of pixel units in the second display area R2. That is, the pixel density in the first display area R1 shown in Figure 3 is 1 / 4 of the density of pixels in the second display area R2. The arrangement of light transmission areas R0 and pixel units in the first display area R1 is not limited to that shown in Figure 3 and can be set as needed. For example, in other embodiments, the density of pixel units in the first display area R1 is a value other than 1 / 4, such as 1 / 2, 1 / 3, 1 / 6, or 1 / 8 of the density of pixel units in the second display area R2.

[0041] For example, as shown in Figures 1A and 3, the display panel further includes gate lines 113 and data lines 313. The gate lines 113 and data lines 313 are isolated from each other. Each gate line 113 is connected to a row of pixel units, and each data line 313 is connected to a column of pixel units. For example, the gate lines 113 are configured to provide a scan signal to a row of pixel units.

[0042] For example, as shown in Figures 1A and 3, data line 313 includes a first data line DL1. The first data line DL1 is located at least in the first display area R1. For example, the first data line DL1 extends from the first display area R1 to the second display area R2.

[0043] For example, as shown in Figures 1A and 3, the gate line includes a first gate line GL1, and the first gate line GL1 extends from the second display area R2 to the first display area R1. As shown in Figure 3, the light transmission area R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited to this.

[0044] Figure 4 is a schematic diagram of a pixel unit and signal lines that provide signals to a pixel unit in a display panel according to one embodiment of the present disclosure. As shown in Figure 4, the display panel includes a plurality of pixel units P0, each pixel unit P0 including a light-emitting element EMC and a pixel circuit 10 that supplies a drive current to the light-emitting element EMC. The light-emitting element EMC may be an electroluminescent element, for example, an organic electroluminescent element, or for example, an organic light-emitting diode (OLED).

[0045] As shown in Figure 4, the display panel further includes an initialization signal line 210, an illumination control signal line 110, a data line 313, a first power line 311, and a second power line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The illumination control signal line 110 is configured to provide an illumination control signal EM to the pixel unit P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the second power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, where the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited to this; for example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit 10 is controlled by signals such as the scan signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM to output a drive current and drive the light-emitting element EMC to emit light. As shown in Figure 4, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.

[0046] Figure 5 is a schematic diagram of the display panel. As shown in Figure 5, regardless of whether it is the first display area R1 or the second display area R2, the first power line 3110 uses a mesh structure, and the horizontal portion of the first power line 3110 is directly connected, and the vertical portion of the first power line 3110 is directly connected. However, this wiring method of the first power line with a mesh structure results in low light transmittance in the first display area R1.

[0047] Figures 6A to 6E are schematic diagrams of display panels according to some embodiments of the present disclosure. As shown in Figures 6A to 6E, the first power line 311 includes a plurality of first conductors L1, a plurality of second conductors L2, and a plurality of third conductors L3, where the first conductor L1 extends from the second display area R2 to the first display area R1, the plurality of second conductors L2 are located in the first display area R1 and between adjacent first conductors L1, each second conductor L2 extends along the first direction D1, and the third conductor L3 is located in at least the first display area R1, for example, the third conductor L3 extends from the second display area R2 to the first display area R1, the third conductor L3 extends along the second direction D2, the first direction D1 intersects with the second direction D2, and adjacent second conductors L2 are spaced apart from each other along the first direction D1, and the second conductors L2 are connected to the first conductor L1 via the third conductor L3. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first conductor L1 extends along the first direction D1. For example, in embodiments of the present disclosure, the second conductor L2 is located only in the first display area R1. In embodiments of the present disclosure, an element extending along a certain direction is not necessarily a straight line, but may have curved or broken portions, for example, the extension direction of an element is a general tendency of the element to extend, and for example, each portion of the element does not necessarily extend along that direction.

[0048] The display panel according to the embodiment of this disclosure adjusts the structure of the first power lines in the first display area, which is equivalent to removing a portion of the first power lines that are installed along the second direction in a typical display panel, thereby simplifying the first power lines in the first display area and improving the light transmittance of the first display area.

[0049] For example, as shown in Figures 6A to 6E, the first wire L1 and the second wire L2 are connected to two adjacent rows of pixel units in one pixel island A1, but are not limited to this, and in other embodiments, the pixel island A1 may include two or more rows of pixel units. For example, as shown in Figures 6A to 6E, the pixel island A1 includes two pixel units located in at least two adjacent rows, and the first wire L1 and the second wire L2 overlap with two pixel units located in two adjacent rows. For example, as shown in Figures 6A to 6E, the first wire L1 overlaps with the first pixel unit 101, and the second wire L2 overlaps with the third pixel unit 103. For example, as shown in Figures 6A to 6E, the first wire L1 further overlaps with the second pixel unit 102, and the second wire L2 further overlaps with the fourth pixel unit 104.

[0050] For example, as shown in Figures 6A to 6E, multiple second conductors L2 are arranged sequentially along the first direction D1. For example, as shown in Figures 6A to 6E, adjacent second conductors L2 are not directly connected, and multiple second conductors L2 that are not directly connected are formed by removing a portion of the first power line installed along the first direction.

[0051] For example, as shown in Figures 6A to 6E, in order to improve the light transmittance of the first display area, the length of the portion of the first conductor L1 located in the first display area R1 in the first direction D1 is greater than the length of the second conductor L2 in the first direction D1.

[0052] For example, as shown in Figures 6A to 6E, the first power line 311 further includes a fourth conductor L4, which extends along a second direction D2, and the second conductor L2 is connected to the first conductor L1 via the fourth conductor L4, with the length of the fourth conductor L4 in the second direction D2 being less than or equal to the length of the third conductor L3 in the second direction D2. In the display panels shown in Figures 6A, 6B, and 6E, the length of the fourth conductor L4 in the second direction D2 is less than the length of the third conductor L3 in the second direction D2. In the display panel shown in Figure 6C, the length of the fourth conductor L4 in the second direction D2 is equal to the length of the third conductor L3 in the second direction D2.

[0053] For example, as shown in Figures 6A to 6E, to further improve the light transmittance of the first display area, multiple fourth conductors L4 are provided, which are arranged sequentially along the second direction D2, with adjacent fourth conductors L4 spaced apart from each other in the second direction D2. For example, as shown in Figure 6A, multiple fourth conductors L41 are located between third conductors L31 and L32, and third conductors L31 and L32 are adjacent third conductors L3. Although Figure 6A shows three fourth conductors L41, the number of fourth conductors L4 located between adjacent third conductors L3 is not limited to those shown and can be determined as needed. Spacing multiple fourth conductors L4 apart in the second direction D2 is equivalent to eliminating some of the first power lines installed along the second direction in a typical display panel, thereby reducing wiring, optimizing wiring space, and improving light transmittance.

[0054] For example, as shown in Figures 6A to 6E, the first power line 311 further includes a fifth conductor L5, which extends along the first direction D1, is located in the second display area R2, is located between adjacent first conductors L1, and the fifth conductor L5 and its adjacent second conductor L2 are spaced apart from each other along the first direction D1. This reduces wiring at the boundary between the first and second display areas and improves light transmittance.

[0055] In the display panel shown in Figure 6E, each pixel island contains a 2x3 pixel unit arrangement. The embodiments of this disclosure do not limit the number of pixel units included in each pixel island or the arrangement of the pixel units, and the first power line arrangement method according to the embodiments of this disclosure can be used as long as the number of pixel units included in each pixel island is two or more.

[0056] As shown in Figures 6A and 6B, in the display panel, the first power line 311 further includes a plurality of sixth conductors L6, which are located in the second display area R2 and extend along the second direction D2. In the second display area R2, the plurality of fifth conductors L5 and the plurality of sixth conductors L6 are installed intersecting each other. In the embodiments of this disclosure, both the fifth conductors L5 and the sixth conductors L6 are located only in the second display area R2.

[0057] Figure 7A is a schematic diagram of a display panel according to one embodiment of the present disclosure. As shown in Figure 7A, the same gate line 113 connects pixel units located in the second display areas on both sides of the first display area R1 with pixel units located within the first display area R1 to form a row of pixel units. In the embodiments of the present disclosure, the form of the first conductor is not limited, and it is sufficient that it can extend from the second display area R2 to the first display area R1. The first power line in Figure 7A may be replaced with the first power line in other embodiments of the present disclosure. Furthermore, the method of extending the gate line 113 is not limited to that shown in Figure 7A, and the arrangement method of the gate line 113 is sufficient that it can connect pixels in the second display area R2 with pixels in the first display area R1.

[0058] Figure 7B is a schematic diagram of a display panel according to one embodiment of the present disclosure. Compared to the display panel shown in Figure 7A, the display panel shown in Figure 7B has an adjusted installation position for some of the gate lines located in the first display area. Specifically, in the display panel shown in Figure 7B, one gate line is installed above and below each pixel island. On the other hand, in the display panel shown in Figure 7A, two gate lines are installed below each pixel island.

[0059] Figures 6A to 6E, 7A, and 7B illustrate an example where the second conductor is connected to one of two adjacent first conductors but not directly to the other. In the display panels shown in Figures 6A to 6E, 7A, and 7B, the fourth conductor is in contact with one of the two adjacent first conductors, for example, via a via penetrating the insulating layer.

[0060] For example, in the embodiments of this disclosure, a row of pixel units is connected to the same gate line 113, while a column of pixel units is connected to the same data line 313. In the embodiments of this disclosure, the first conductor L1, the second conductor L2, and the fifth conductor L5 all extend along the row direction, and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 extend along the column direction, but this is not limited to this. In other embodiments, the first conductor L1, the second conductor L2, and the fifth conductor L5 all extend along the column direction, and the third conductor L3, the fourth conductor L4, and the sixth conductor L6 extend along the row direction, and the second direction D2 and the first direction D1 can be interchanged accordingly.

[0061] Figures 6A to 6E illustrate an example where the pixel island contains two rows of pixel units, but in other embodiments, the pixel island may contain three or more rows of pixel units, in which case the plurality of second wires can be understood as second wires connected to pixel units in the same row. When the first wire L1, the second wire L2, and the fifth wire L5 all extend along the column direction, and the third wire L3, the fourth wire L4, and the sixth wire L6 extend along the row direction, the plurality of second wires can be understood as second wires connected to pixel units in the same column.

[0062] Hereinafter, several embodiments of this disclosure will be described with reference to Figures 8 to 25. Figures 8 to 24 illustrate the pixel circuit of the 7T1C as an example.

[0063] Figure 8 is a schematic diagram of the pixel circuit of a display panel according to one embodiment of the present disclosure. Figure 9 is a plan view of the semiconductor pattern in a display panel according to one embodiment of the present disclosure. Figure 10 is a plan view of the first conductive pattern layer in a display panel according to one embodiment of the present disclosure. Figure 11 is a plan view of the second conductive pattern layer in a display panel according to one embodiment of the present disclosure. Figure 12 is a plan view of the first insulating layer in a display panel according to one embodiment of the present disclosure. Figure 13 is a plan view of the third conductive pattern layer in a display panel according to one embodiment of the present disclosure. Figure 14 is a plan view of the second insulating layer in a display panel according to one embodiment of the present disclosure. Figure 15 is a plan view of the pixel electrode layer in a display panel according to one embodiment of the present disclosure. Figure 16 is a plan view of the pixel definition layer in a display panel according to one embodiment of the present disclosure. Figure 17 is a schematic diagram of the active layer forming a thin-film transistor in a display panel according to one embodiment of the present disclosure. Figure 18 is a schematic plan view of the display panel according to one embodiment of the present disclosure after the second conductive pattern layer and the first insulating layer have been formed. Figure 19 is a schematic plan view of the display panel according to one embodiment of the present disclosure after the third conductive pattern layer has been formed. Figure 20 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the second insulating layer has been formed. Figure 21 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the pixel electrode layer has been formed. Figure 22 is a schematic plan view of a display panel according to one embodiment of the present disclosure after the pixel definition has been formed. Figure 23 is a schematic plan view of adjacent pixel islands in the second direction in the first display area of ​​a display panel according to one embodiment of the present disclosure. Figure 24 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. Figure 25 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. In the embodiments of the present disclosure, for clarity of illustration, the insulating layer is shown in the form of vias in the plan views, and the insulating layer itself is made transparent.

[0064] For example, as shown in Figure 8, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light emission control line 110 is configured to provide a light emission control signal EM to the pixel unit P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, and the second power line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, where the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude may be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited to this, and may be, for example, less than or equal to the second voltage signal ELVSS. For example, the pixel circuit is controlled by signals such as the scanning signal SCAN, data signal DATA, initialization signal Vint, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM to output a drive current and drive the light-emitting element 20 to emit light. The light-emitting element 20 is driven by the corresponding pixel circuit 10 to emit red light, green light, blue light, or white light, etc.

[0065] As shown in Figure 8, the pixel circuit 10 includes a drive transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The drive transistor T1 is electrically connected to the light-emitting element 20 and outputs a drive current controlled by signals such as a scanning signal SCAN, a data signal DATA, a first voltage signal ELVDD, and a second voltage signal ELVSS to drive the light-emitting element 20 to emit light.

[0066] For example, a display panel according to an embodiment of the present disclosure further includes a data drive circuit and a scan drive circuit. The data drive circuit is configured to provide a data signal DATA to a pixel unit P0 based on instructions from the control circuit, and the scan drive circuit is configured to provide signals such as an illumination control signal EM, a scan signal SCAN, and a reset control signal RESET to the pixel unit P0 based on instructions from the control circuit. For example, the control circuit includes, but is not limited to, an external integrated circuit (IC). For example, the scan drive circuit is a Gate driver on array (GOA) structure mounted on the display panel, or a drive chip (IC) structure bonded to the display panel. For example, different drive circuits may be used to provide the illumination control signal EM and the scan signal SCAN, respectively. For example, the display panel further includes a power supply (not shown) to provide the above voltage signals, which may be a voltage source or a current source as needed, and the power supply is configured to provide a first voltage signal ELVDD, a second power supply voltage ELVSS, and an initialization signal Vint, etc., to the pixel unit P0 via a first power line 311, a second power line 312, and an initialization signal line 210, respectively.

[0067] As shown in Figure 8, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first pole T21 and second pole T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first pole T11 of the drive transistor T1, respectively. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the drive transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the drive transistor T1.

[0068] For example, as shown in Figure 8, both the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are connected to the light emission control signal line 110.

[0069] For example, as shown in Figure 8, the first pole T41 and second pole T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the drive transistor T1, respectively. The first pole T51 and second pole T52 of the second light-emitting control transistor T5 are electrically connected to the second pole T12 of the drive transistor T1 and the pixel electrode E1 of the light-emitting element 20 (which may be the anode of the OLED), respectively. The common electrode E2 of the light-emitting element 20 (which may be the common electrode of the OLED, for example, the cathode) is electrically connected to the second power line 312.

[0070] For example, as shown in Figure 8, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the drive transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0071] Figure 9 shows the semiconductor pattern SCP, and Figure 10 shows the first conductive pattern layer LY1, with a first gate insulating layer placed between the first conductive pattern layer LY1 and the semiconductor pattern SCP. By doping the semiconductor pattern SCP with the first conductive pattern layer LY1 as a mask, the regions of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retain semiconductor properties and form the channel of the thin-film transistor, while the regions of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 become conductors and form the source or drain of the thin-film transistor. Figure 17 shows the active layer ALT formed after the semiconductor pattern SCP has been partially made conductors.

[0072] As shown in Figure 10, the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and the first pole C11 of a storage capacitor C1. Figure 10 further shows the first portion DL11 (conductor 114) of the first data line DL1. Figure 10 further shows the gate line GL0, which is a portion of the gate line extending from the second display area to the first display area. For example, as shown in Figure 19, in an embodiment of the present disclosure, the first reset control signal line 111 and the second reset control signal line 112 are connected.

[0073] Figure 11 shows the second conductive pattern layer LY2, with a second gate insulating layer installed between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes stopper blocks BK0 and BK1, an initialization signal line 210, and the second pole C12 of the storage capacitor C1. The second pole C12 of the storage capacitor C1 has an opening OPN. The initialization signal line 210 includes the first initialization signal line 211 and the second initialization signal line 212. As shown in Figure 11, the second conductive pattern layer LY2 includes the first portion L11 and the third portion L13 of the first conductor L1. As shown in Figure 11, the stopper block BK0 extends from the first conductor L1. Figure 12 shows the pattern of the first insulating layer ISL1, where the dots are vias in the first insulating layer ISL1, and the first insulating layer ISL1 includes at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. The first gate insulating layer, the second gate insulating layer and interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2 and the third conductive pattern layer LY3 can be seen in Figures 24 and 25. Figure 18 is a schematic plan view after the formation of the first insulating layer ISL1.

[0074] Figure 13 shows the third conductive pattern layer LY3, which includes the third conductor L3 (part of the first power line 311), the second data line DL12 (part of the data line 313), the first connecting electrode 31a, the second connecting electrode 31b, the third connecting electrode 31c, and the fourth connecting electrode 31d. As shown in Figure 13, the third conductive pattern layer LY3 further includes the second portion L12 of the first conductor L1. The first portion L11 and the third portion L13 of the first conductor L1 are connected via the second portion L12.

[0075] As shown in Figures 13, 17, 18, and 19, the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 via via V4, the first power line 311 is electrically connected to the first pole T41 of the first light emission control transistor T4 via via V3, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 via via V6, and the first power line 311 is electrically connected to the conductive block BK1 via via V5. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 via via V11, and the other end of the first connection electrode 31a is connected to the first pole T61 of the first reset transistor T6 via via V12, and further the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211. One end of the second connecting electrode 31b is electrically connected to the second pole T62 of the first reset transistor T6 via via V21, and the other end of the second connecting electrode 31b is electrically connected to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1) via via V22, thereby electrically connecting the second pole T62 of the first reset transistor T6 to the gate T10 of the drive transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connecting electrode 31c is electrically connected to the second initialization signal line 212 via via V31, and the other end of the third connecting electrode 31c is connected to the first pole T71 of the second reset transistor T7 via via V32, thereby electrically connecting the first pole T71 of the second reset transistor T7 to the first initialization signal line 211. The fourth connecting electrode 31d is electrically connected to the second pole T52 of the second light emission control transistor T5 via via V1. The fourth connecting electrode 31d is electrically connected to the pixel electrode E1 (see Figure 8) of the subsequently formed light-emitting element 20.

[0076] Figure 14 shows the second insulating layer ISL2, where the dots are vias V1 in the second insulating layer ISL2. As shown in Figure 14, via V1 includes vias V10, V20, V30, and V40. Figure 20 is a plan view after the second insulating layer has been formed.

[0077] Figure 15 shows the electrode layer ETL. The electrode layer ETL includes multiple pixel electrodes E1. The electrode layer ETL includes the pixel electrode E11 of the first pixel unit 101, the pixel electrode E12 of the second pixel unit 102, the pixel electrode E13 of the third pixel unit 103, and the pixel electrode E14 of the fourth pixel unit 104. The pixel electrode E11 of the first pixel unit 101 is connected to the corresponding fourth connection electrode 31d via via V10, the pixel electrode E12 of the second pixel unit 102 is connected to the corresponding fourth connection electrode 31d via via V20, the pixel electrode E13 of the third pixel unit 103 is connected to the corresponding fourth connection electrode 31d via via V30, and the pixel electrode E14 of the fourth pixel unit 104 is connected to the corresponding fourth connection electrode 31d via via V40. Figure 21 is a plan view of the display panel after the electrode layer has been formed.

[0078] As shown in Figures 15 and 22, the pixel electrode E14 of the fourth pixel unit 104 includes a supplementary section E0, and the orthographic projection of the supplementary section E0 on the base substrate can cover the orthographic projection of the shared electrodes of the data writing transistor T2 and the first light emission control transistor T4 (the second electrode T22 of the data writing transistor T2 and the second electrode T42 of the first light emission control transistor T4) on the base substrate, thereby improving the stability and lifespan of the data writing transistor T2 and the first light emission control transistor T4, and thereby improving the long-term light emission stability and lifespan of the display panel.

[0079] Figure 16 shows a plan view of the pixel definition layer. As shown in Figure 16, the pixel definition layer PDL includes multiple apertures, which include apertures OPN1, OPN2, OPN3, and OPN4. Figure 22 shows a schematic diagram of the display panel after the pixel definition layer has been formed. As shown in Figure 22, aperture OPN1 exposes a portion of the pixel electrode E11, aperture OPN2 exposes a portion of the pixel electrode E12, aperture OPN3 exposes a portion of the pixel electrode E13, and aperture OPN4 exposes a portion of the pixel electrode E14. In subsequent processes, an emissive functional layer and a common electrode are formed, and then the light-emitting element EMC is formed.

[0080] The transistors used in any embodiment of this disclosure may be thin-film transistors, field-effect transistors, or other switching devices having the same characteristics. Since the source and drain of the transistors used here may be structurally symmetrical, the source and drain may not have a structural distinction. In any embodiment of this disclosure, the two poles of a transistor, excluding the gate, are directly described as one being the first pole and the other the second pole, so in any embodiment of this disclosure, the first and second poles of all or some transistors are interchangeable as needed. For example, the first pole of a transistor described in an embodiment of this disclosure may be the source and the second pole may be the drain, or the first pole of a transistor may be the drain and the second pole may be the source.

[0081] Furthermore, transistors may be classified into N-type and P-type transistors depending on their characteristics. The embodiments of this disclosure are described as examples in which all transistors are P-type transistors. Based on the description and teaching of the embodiments of this disclosure, a person skilled in the art can easily conceive of embodiments in which at least some of the transistors in the pixel circuits of the embodiments of this disclosure are N-type transistors, that is, embodiments using N-type transistors or a combination of N-type and P-type transistors, and therefore these embodiments also fall within the scope of protection of this disclosure.

[0082] Figures 8 to 25 illustrate a 7T1C pixel circuit as an example, and the embodiments of this disclosure include, but are not limited to, this. Furthermore, the embodiments of this disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display substrate panel may include, for example, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure with a different number of transistors, but the embodiments of this disclosure are not limited thereto.

[0083] Figure 25 is a schematic cross-sectional view of a display panel according to one embodiment of the present disclosure. For example, as shown in Figure 25, the display panel includes a thin-film transistor 50 and a storage capacitor C1. The thin-film transistor 50 includes an active layer ATL1 located on a base substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL1 away from the base substrate BS, and a gate GE located on the side of the first gate insulating layer GI1 away from the base substrate BS. The display panel further includes a second gate insulating layer GI2 located on the side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the base substrate BS, and a connecting electrode CNE1 located on the side of the interlayer insulating layer ILD away from the base substrate BS. The active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 located on opposite sides of the channel CN11, respectively, and the connecting electrode CNE1 is connected to the second electrode ET2 via vias penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first electrode C11 and a second electrode C12, where the first electrode C11 and the gate GE are located in the same layer and are both located in the first conductive pattern layer LY1, and the second electrode C12 is located between the second gate insulating layer GI2 and the interlayer insulating layer ILD and is located in the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is the source and the other is the drain. The connecting electrode CNE1 is located in the third conductive pattern layer LY3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the connecting electrode CNE1 may be the fourth connecting electrode 31d, and the thin-film transistor 50 may be the second light emission control transistor T5.

[0084] As shown in Figure 25, the display panel further includes a light-emitting element EMC, which includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2, and the pixel electrode E1 is connected to a connecting electrode CNE1 via vias that penetrate the passivation layer PVX and the planarization layer PLN. The display panel further includes a package layer CPS, which includes a first package layer CPS1, a second package layer CPS2, and a third package layer CPS3. For example, the first package layer CPS1 and the third package layer CPS3 are inorganic material layers, and the second package layer CPS2 is an organic material layer. For example, the pixel electrode E1 is the anode and the common electrode E2 is the cathode, but is not limited to this.

[0085] For example, the light-emitting element EMC includes an organic light-emitting diode. The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer EML includes at least a light-emitting layer and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0086] As shown in Figure 25, the display panel further includes a pixel definition layer (PDL) and spacers (PS). The pixel definition layer (PDL) has an aperture configured to limit the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the spacers (PS) are configured to support a fine metal mask when forming the light-emitting functional layer (EML). Figure 25 shows, but is not limited to, spacers (PS) being placed on opposite sides of the light-emitting element.

[0087] For example, a data line is configured to input a data signal to the pixel unit, and a first power supply signal line is configured to input a first power supply voltage to the drive transistor. A second power supply signal line is configured to input a second power supply voltage to the pixel unit. The first power supply voltage is a constant voltage, and the second power supply voltage is a constant voltage, for example, the first power supply voltage is a positive voltage and the second power supply voltage is a negative voltage, but is not limited to this. For example, in some embodiments, the first power supply voltage is a positive voltage and the second power supply signal line is grounded.

[0088] As shown in Figure 25, in the embodiments of this disclosure, the first insulating layer ISL1 includes at least one of the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0089] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS are all made of insulating material. For example, the material of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX includes, but is not limited to, at least one of SiOx and SiNx. For example, the planarization layer PLN, the pixel definition layer PDL, and the spacer PS may be made of, but is not limited to, an organic insulating material such as resin.

[0090] As shown in Figure 17, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, which are connected via a conductive part CP. As shown in Figure 18, the second wire L2 further includes a connecting arm L21. The threshold compensation transistor T3 is a dual-gate transistor, and when the threshold compensation transistor T3 is off, the conductive part CP is in a floating state and is susceptible to jumps due to the influence of the surrounding line voltage. Voltage jumps in the conductive part CP adversely affect the leakage current of the threshold compensation transistor T3 and further adversely affect the luminescence brightness of the pixel unit. Therefore, it is necessary to stabilize the voltage of the conductive part CP, and a stop block may be designed to form a capacitor with the conductive part CP. The stop block may have a constant voltage signal, thereby stabilizing the voltage of the conductive part CP in the floating state. The stop block BK0, stop block BK, and connecting arm L21 mentioned in the embodiments of this disclosure all exert the effect of stabilizing the voltage of the conductive part CP.

[0091] As shown in Figure 24, the connecting arm L21 partially overlaps with the conductive part CP of the threshold compensation transistor T3 to form a capacitor C0, and the first gate insulating layer GI1 and the second gate insulating layer GI2 are placed between the connecting arm L21 and the conductive part CP. Figure 24 further shows the second channel CN2. Capacitor C0 may also be called a stabilizing capacitor, and the connecting arm L21 and the conductive part CP are the two plates of capacitor C0. As shown in Figure 24, the gate GE2 and the second channel CN2 overlap in a direction perpendicular to the base substrate BS. Gate GE2 is one of the gates of the threshold compensation transistor T3. As shown in Figure 24, the second connecting electrode 31b is connected to the second electrode T32 of the threshold compensation transistor T3.

[0092] As shown in Figure 19, the second conductor L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive part CP are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3 (see Figure 24). For example, the shape of the connecting arm L21 includes a C shape. The connecting arm L21 may be approximately C-shaped, and of course, other shapes may be used for the connecting arm L21 as long as it can perform the function of stabilizing the threshold compensation transistor T3.

[0093] For example, the third direction D3 is perpendicular to the first direction D1 and the second direction D2, and the third direction D3 is perpendicular to the base substrate BS, with the first gate insulating layer GI1 and the second gate insulating layer GI2 installed between the connecting arm L21 and the conductive part CP. For example, the first direction D1 and the second direction D2 are parallel to the main surface of the base substrate BS, and the third direction D3 is perpendicular to the main surface of the base substrate BS. Various elements are fabricated on the main surface of the base substrate BS.

[0094] As shown in Figures 11, 19, and 24, the first portion L11 includes a first sub-part La extending along a first direction D1 and a second sub-part Lb extending along a second direction, the second sub-part Lb having a branch extending along the first direction D1, and the retaining block BK0 is the branch of the second sub-part Lb. As shown in Figures 17, 19, and 24, the branch of the second sub-part Lb (retaining block BK0) is spaced apart from the conductive part of one pixel unit superimposed on the first conductor L1 in the pixel island in the third direction D3, and partially overlaps with the third direction D3. As shown in Figures 17, 19, and 24, the branch (stopper block BK0) of the second sub-part Lb is spaced apart from the conductive part CP of one pixel unit (the upper left pixel unit in Figure 24) that overlaps with the first conductor L1 in the pixel island, and partially overlaps with it in the third direction D3. For example, the length of the branch (stopper block BK0) in the first direction D1 is less than the length of the first sub-part La in the first direction D1.

[0095] For example, as shown in Figures 8, 17, 19, and 24, the pixel circuit 10 includes a first transistor and a second transistor, the first transistor being connected to the second transistor, and the second transistor being connected to the light-emitting element. The first transistor includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 being connected via a conductive part CP. The second conductor L2 further includes a connecting arm L21, the connecting arm L21 is spaced apart from the conductive part CP of one pixel unit (the lower left pixel unit in Figure 19) that overlaps with the second conductor L2 in the pixel island, in the third direction D3, and partially overlaps in the third direction D3. For example, the first transistor and the second transistor are a threshold compensation transistor T3 and a light-emitting control transistor connected to the light-emitting element, respectively, in the pixel circuit 10. For example, the light-emitting control transistor connected to the light-emitting element is the second light-emitting control transistor T5. Of course, in other embodiments of this disclosure, the stop block or connecting arm that forms a capacitor together with the conductive portion CP of the first transistor in the pixel island may be of other forms, but is not limited thereto.

[0096] For example, as shown in Figure 19, in the embodiment of this disclosure, both the stopper block BK0 (branch of the second sub-part Lb) and the connecting arm L21 are connected to the third conductor L3 of the pixel unit in this row, but the stopper block BK is connected to the third conductor of the row adjacent to the pixel unit row where the conductive part shielded by it is located. That is, as shown in Figure 19, the stopper block BK0 (branch of the second sub-part Lb), the connecting arm L21, and the stopper block BK are all connected to the same third conductor L3.

[0097] For example, as shown in Figure 11, the initialization signal line 210 includes multiple hollow regions HP, and the second conductor L2 is located within one hollow region HP and surrounded by the portion of the initialization signal line surrounding the hollow region HP, and the second conductor L2 does not overlap with the portion of the initialization signal line surrounding the hollow region HP. That is, the second conductor L2 is completely surrounded by the portion of the initialization signal line surrounding the hollow region HP. In the embodiments of this disclosure, the hollow region HP is a location corresponding to a thin film portion that was removed when the initialization signal line 210 was fabricated.

[0098] For example, as shown in Figures 11, 13, and 19, the first conductor L1 includes a first portion L11 and a second portion L12, the first portion L11 of the first conductor L1 is located on the same layer as the second conductor L2, the second portion L12 of the first conductor L1 is not located on the same layer as the second conductor L2, and the second portion L12 of the first conductor L1 overlaps at least partially with the initialization signal line 210. As shown in Figures 11, 13, and 19, both the first portion L11 of the first conductor L1 and the second conductor L2 are located on the second conductive pattern layer LY2, and the second portion L12 of the first conductor L1 is located on the third conductive pattern layer LY3.

[0099] For example, as shown in Figures 11, 13, and 19, the second conductor L2 is surrounded by a portion of the initialization signal line 210, and the first portion L11 of the first conductor L1 is surrounded by a portion of the initialization signal line 210. As shown in Figures 11, 13, and 19, the second conductor L2 is surrounded by a portion 210a located below the initialization signal line 210, and the first portion L11 of the first conductor L1 is surrounded by a portion 210b located above the initialization signal line 210.

[0100] For example, as shown in Figures 3 and 19, the data line 313 includes a first data line DL1, which extends from the first display area R1 to the second display area R2, and the first data line DL1 partially overlaps with the orthographic projection of the third conductor L3 on the base substrate BS. This installation configuration is advantageous in reducing the wiring area and improving light transmittance.

[0101] For example, as shown in Figures 13, 18, and 19, the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps with the third conductor L3, the second portion DL12 of the first data line DL1 does not overlap with the third conductor L4, and the first portion DL11 and the second portion DL12 of the first data line DL1 are located in different layers. For example, in Figure 19, the first portion DL11 (conductor 214) of the left first data line DL1 is located in the second conductive pattern layer, the second portion DL12 of the left first data line DL1 is located in the third conductive pattern layer, the first portion DL11 (conductor 114) of the right first data line DL1 is located in the first conductive pattern layer, and the second portion DL12 of the right first data line DL1 is located in the third conductive pattern layer. For example, as shown in Figures 3, 19, and 23, the first portion DL11 of the first data line DL1 is located between adjacent pixel islands A1.

[0102] For example, as shown in Figures 13 and 19, two first data lines DL1 are provided, each connected to two adjacent rows of pixel units, and the two first data lines DL1 partially overlap the orthographic projection of the same third conductor L3 on the base substrate BS. This configuration allows the data lines located between pixel islands in two adjacent rows of pixel units to be hidden beneath the third conductor, thereby reducing the wiring area and improving light transmittance.

[0103] For example, the first conductor L1 includes portions located in different layers, and these portions are connected via vias that penetrate the insulating layer. As shown in Figure 19, the first conductor L1 includes a first portion L11, a second portion L12, and a third portion L13. The first portion L11 and the third portion L13 are located in the second conductive pattern layer LY2, and the second portion L12 is located in the third conductive pattern layer LY3. The first portion L11 and the second portion L12 are connected via a via V41 that penetrates the insulating layer, and the third portion L13 and the second portion L12 are connected via a via V42 that penetrates the insulating layer. As shown in Figures 24 and 25, an interlayer dielectric layer ILD is installed between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, i.e., via V41 penetrates the interlayer dielectric layer ILD, and via V42 penetrates the interlayer dielectric layer ILD.

[0104] For example, as shown in Figure 19, a portion of the first conductor L1 (second portion L12) and the third conductor L3 are located on the same layer, both in the third conductive pattern layer LY3. The fourth conductor L4 and the third conductor L3 are located on the same layer, both in the third conductive pattern layer LY3.

[0105] At least one embodiment of the present disclosure further provides a display device including any of the above-described display panels. For example, the display device may be a display device such as an organic light-emitting diode (OLED) display, and any product or component having a display function, such as a television, digital camera, mobile phone, wristwatch, tablet PC, laptop, or navigator, that includes such display devices.

[0106] For example, in the embodiments of this disclosure, the first conductor L1 may include a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer, the second conductor L2 consists only of a portion located in the second conductive pattern layer, the third conductor L3 consists only of a portion located in the third conductive pattern layer, the fourth conductor L43 consists only of a portion located in the third conductive pattern layer, and the fifth conductor L5 includes a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer, but is not limited thereto and can be configured as needed.

[0107] For example, as shown in Figures 11 and 19, in the embodiments of this disclosure, the second pole C12 of the storage capacitor C1 of the pixel unit P0 is part of the second conductor L2 or part of the first conductor L1.

[0108] Furthermore, the following points need to be explained.

[0109] (1) Unless otherwise defined, the same reference numerals in the embodiments and drawings of this disclosure shall have the same meaning.

[0110] (2) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures should refer to conventional designs.

[0111] (3) For clarity, in the drawings illustrating embodiments of the present disclosure, the thickness of layers or regions is magnified. To make it understandable, when an element such as a layer, film, region or substrate is described as being located "above" or "below" another element, the element may be located "directly" above or below the other element, or an intermediate element may be present.

[0112] (4) Features of the same and different embodiments of the present disclosure can be combined with each other, as long as they do not contradict each other.

[0113] While specific embodiments of this disclosure have been described above, the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art could easily conceive of within the technical scope disclosed herein should also be included within the scope of protection of this disclosure. Accordingly, the scope of protection of this disclosure should be the same as the scope of protection of the claims.

Claims

1. It is a display panel, A base substrate including a first display area and a second display area located at least on one side of the first display area, A plurality of pixel units located in the first display area and the second display area, wherein the density of pixel units in the first display area is less than the density of pixel units in the second display area, each pixel unit includes a pixel circuit, each pixel unit located in the first display area constitutes a plurality of pixel islands, each having a light-transmitting region between adjacent pixel islands, and each pixel island includes at least two pixel units, and A plurality of first power lines configured to provide a first voltage signal to the pixel circuit, Includes, The first power line includes a first conductor extending along a first direction and extending from the second display area to the first display area, a second conductor located in the first display area and extending along the first direction, and a third conductor located in at least the first display area and extending along a second direction intersecting the first direction, and The adjacent second conductors are spaced apart from each other along the first direction, the second conductors are connected to the third conductor, and the orthographic projection of the second conductors on the base substrate and the orthographic projection of at least two pixel units within the pixel island on the base substrate are superimposed. The present invention further includes data lines arranged to provide data signals to the pixel circuits, the data lines comprising a plurality of first data lines, the plurality of first data lines extending from the second display area to the first display area, passing through the plurality of pixel islands, and being electrically connected to the pixel circuits of the plurality of pixel islands, the plurality of first data lines having a first portion located between adjacent pixel islands, a gap between the first portions of two adjacent first data lines, the orthographic projection of the third conductor on the base substrate covering the orthographic projection of the gap on the base substrate, the data lines extending along the second direction, the first data lines extending along the second direction, and the first portion of the first data lines extending along the second direction. A display panel in which the orthographic projection of the third conductor on the base substrate and the orthographic projection of the first portion of the first data line on the base substrate are superimposed.

2. The display panel according to claim 1, wherein the plurality of second conductors are arranged sequentially along the first direction, and adjacent second conductors are not directly connected.

3. The display panel according to claim 1, wherein the first conductor includes portions located in different layers, and the portions located in different layers are connected via vias penetrating an insulating layer.

4. The display panel according to claim 1, wherein a portion of the first conductor is located on the same layer as the third conductor.

5. The display panel according to claim 1, wherein the pixel unit further includes a light-emitting element, the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected via a conductive portion, the second conductor further includes a connecting arm, the connecting arm is spaced apart from the conductive portion of one pixel unit superimposed on the second conductor in the pixel island in a third direction and partially overlaps with the third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

6. The display panel according to claim 5, wherein the first conductor has a branch, the branch is spaced apart from the conductive portion of one pixel unit superimposed on the first conductor in the pixel island in the third direction, and partially overlaps with the third direction.

7. The display panel according to claim 1, wherein the orthographic projection of the third conductor on the base substrate at least partially covers the orthographic projection of the first portion of the first data line on the base substrate.

8. The display panel according to claim 1, wherein the length of the third conductor along the second direction is greater than the length of the first portion of the two corresponding first data lines along the second direction.

9. The display panel according to any one of claims 1 to 8, wherein the first data line includes a second portion, the second portion of the first data line does not overlap with the third conductor, the first portion of the first data line and the second portion of the first data line are located in different layers, and the second portion of the first data line extends along the second direction.

10. The display panel according to any one of claims 1 to 8, wherein two of the plurality of first data lines are connected to two adjacent pixel units of the same pixel island, and the two first data lines partially overlap with the orthographic projection of the same third conductor on the base substrate.

11. The display panel according to any one of claims 1 to 8, wherein the first power line further includes a fifth conductor located in the second display area, the fifth conductor being located between adjacent first conductors, the fifth conductor and the adjacent second conductor being spaced apart from each other along the first direction, and the fifth conductor extending along the first direction.

12. The display panel according to any one of claims 1 to 5 and 7 to 8, wherein the first conductor includes a first portion and a second portion, the first portion having a first sub-part extending in a first direction and a second sub-part extending in a second direction, and the second portion having a branch extending in a first direction.

13. A display panel according to any one of claims 1 to 8, further comprising gate lines configured to provide a scanning signal to a row of pixel units, wherein the gate lines extend along a first direction, and the gate lines include a first gate line extending from a second display area to the first display area, and the light-transmitting area is surrounded by two adjacent first gate lines and two adjacent first data lines.

14. A display device comprising a display panel and a sensor according to any one of claims 1 to 8, wherein the sensor is located in the first display area.

15. The display device according to claim 14, wherein the sensor is a camera.

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