Substrate-insulated strain-gate all-around field-effect transistor

Abstract

The present invention provides a gate-all-around transistor device and a method for manufacturing a gate-all-around transistor device. The semiconductor device includes a substrate. The substrate includes a plurality of insulating regions formed therein, the plurality of insulating regions include an insulating material. The substrate further includes buffer regions formed therein, the buffer regions separating adjacent insulating regions. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding insulating region of the plurality of insulating regions. Each fin includes a buffer layer in contact with the insulating material and a plurality of silicon layers and a plurality of silicon-germanium layers arranged alternately in a plurality of stacked pairs on the buffer layer.

Description

Technical Field

[0001] The present disclosure relates to transistor devices and methods for manufacturing transistor devices. More particularly, the present disclosure relates to gate-all-around (GAA) transistor devices and methods for manufacturing GAA transistor devices.

Background Art

[0002] The electronics industry is facing an ever-growing demand for smaller and faster electronic devices, while being able to support a larger number of increasingly complex and sophisticated functions. Thus, the semiconductor industry has been trending towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimum feature size), thereby improving production efficiency and reducing associated costs. However, such miniaturization has brought greater complexity to the semiconductor manufacturing process. Therefore, similar progress in semiconductor manufacturing processes and technologies is required to realize continuous progress in semiconductor ICs and semiconductor devices.

[0003] Recently, multi-gate devices have been introduced to improve gate control by enhancing gate-channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). One such multi-gate device that has been introduced is the gate-all-around transistor (GAA). In a GAA device, all sides of the channel region are surrounded by gate electrodes, which results in more complete depletion in the channel region, and as a result, the short-channel effect is reduced due to a steeper subthreshold current swing and a smaller drain induced barrier lowering (DIBL).

[0004] As transistor dimensions are scaled down to smaller technology nodes, further improvements in GAA design and manufacturing will be required. [Overview of the project]

[0005] This disclosure relates to transistor devices and methods for manufacturing transistor devices. More specifically, this disclosure relates to GAA transistor devices and methods for manufacturing GAA transistor devices.

[0006] In at least one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate. The substrate includes a plurality of insulating regions formed therein, the plurality of insulating regions include an insulating material. The substrate further includes buffer regions formed therein, the buffer regions separating adjacent insulating regions. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding insulating region of the plurality of insulating regions. Each fin includes a buffer layer in contact with the insulating material and a plurality of silicon layers and a plurality of silicon-germanium layers arranged alternately in a plurality of stacked pairs on the buffer layer.

[0007] The implementation configuration may include one or more of the following: The buffer region comprises a relaxed Si(1-x)Ge(x) material, where x represents the germanium concentration. The buffer layer comprises a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material comprises silicon germanium, which has a substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region. The semiconductor device further comprises a source / drain region formed in a source / drain recess defined by adjacent fins. The semiconductor device further comprises a dielectric insulating layer separating the source / drain region from the upper surface of the buffer region. The insulating region has a thickness greater than the thickness of the buffer region.

[0008] In another embodiment, a method for forming a semiconductor device is provided. The method comprises forming a plurality of insulating regions in a silicon substrate. The insulating regions comprise an insulating material. The method further comprises removing portions of the silicon substrate to form recesses between adjacent insulating regions. The method further comprises filling the recesses with buffer material to form buffer regions. The method further comprises growing a buffer layer on the silicon substrate, insulating material, and buffer material. The method further comprises forming a superlattice structure on the buffer layer. The superlattice structure comprises a plurality of silicon layers and a plurality of silicon germanium layers arranged alternately in a plurality of stacked pairs. The method further comprises patterning and etching the superlattice structure and the buffer layer to form fins from the superlattice structure and the buffer layer. The fins are aligned with the insulating regions and the fins define source / drain recesses. The method further comprises filling the source / drain recesses with epitaxial material to form source / drain regions.

[0009] The implementation configuration may include one or more of the following. The method further includes forming a dielectric insulating layer in the source / drain recess before filling the source / drain recess with the epitaxial material. Filling the recess with the buffer material to form a buffer region includes epitaxially growing a Si(1-x)Ge(x) material, where x represents the germanium concentration. Growing a buffer layer on a silicon substrate, insulating material, and buffer material includes epitaxially growing a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material includes silicon germanium, which has a substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region. The crystalline material grows selectively vertically from the buffer region, and then laterally on top of the insulating region.

[0010] In another embodiment, a method for forming a semiconductor device is provided. The method comprises forming a plurality of insulating regions in a silicon substrate. The insulating regions comprise an insulating material. The method further comprises removing portions of the silicon substrate to form recesses between adjacent insulating regions. The method further comprises epitaxially growing buffer material in the recesses to form buffer regions. The method further comprises epitaxially growing a buffer layer on top of the buffer regions and insulating regions, the buffer layer growing epitaxially from the buffer regions. The method further comprises forming a superlattice structure on the buffer layer. The superlattice structure comprises a plurality of silicon layers and a plurality of silicon-germanium layers arranged alternately in a plurality of stacked pairs. The method further comprises patterning and etching the superlattice structure and the buffer layer to form fins from the superlattice structure and the buffer layer. The fins are aligned with the insulating regions and the fins define source / drain recesses. The method further comprises forming spacers on the outer surface of the silicon-germanium layer. The method further includes filling the source / drain recess with an epitaxial material to form a source / drain region.

[0011] The implementation configuration may include one or more of the following: Epitaxial growth of the buffer material in the recess includes epitaxial growth of Si(1-x)Ge(x) material, where x represents the germanium concentration. Epitaxial growth of the buffer layer on top of the buffer region and insulating region includes epitaxial growth of a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material contains silicon germanium, which has a substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region.

[0012] In another embodiment, a non-temporary computer-readable medium stores instructions thereon, when executed by a processor, causing a process to perform the operation and / or method of the above-mentioned device.

[0013] To allow for a more detailed understanding of the features described above, a more specific description of the embodiments, which is briefly summarized above, can be obtained by referring to the implementations shown in the accompanying drawings, some of which are examples of the features described above. However, it should be noted that the accompanying drawings only illustrate general implementations of the disclosure and should not be considered to limit the scope of the disclosure, as the disclosure may recognize other equally valid implementations. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows a schematic cross-sectional view of a GAA structure according to one or more implementations of the present disclosure. [Figure 2] This figure shows a schematic cross-sectional view of another GAA structure according to one or more implementations of the present disclosure. [Figure 3] This figure shows an illustrative flowchart of a method for forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4A-4C] This figure shows cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4D-4F] This figure shows cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4G-4H] This figure shows cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4I-4J] This figure shows cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4K] This figure shows cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. [Figure 4L-4M]A diagram showing cross-sectional views of various stages of forming a GAA structure according to one or more implementations of the present disclosure. [Figure 5] A diagram showing a plan view of a cluster tool according to one or more embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0015] For ease of understanding, equivalent reference numbers are used as much as possible to designate equivalent elements common to the figures. It is contemplated that elements and features of one implementation may be advantageously incorporated into other implementations without further elaboration.

[0016] The scaling down of silicon metal oxide semiconductor (MOS) devices has become a major issue in the semiconductor industry. One problem associated with scaling of conventional planar devices is the short-channel effect that begins to affect device performance. One solution to this problem involves the introduction of multi-gate devices with 3D architectures, such as fin-based semiconductor devices or FINFETs and GAA devices. The 3D architecture of multi-gate devices, where gates are either wrapped around thin semiconductor fins for FINFETs or surround all sides of the channel region for GAA, allows for improved gate control over the channel (and thus less short-channel effect) by using multiple gates. State-of-the-art GAA is formed on a bulk silicon substrate with a drive current proportional to the bulk silicon mobility. Therefore, the drive current is limited by the mobility of bulk silicon.

[0017] Superlattice structures can be utilized in the fabrication of devices with 3D architectures. These superlattice structures incorporate stacks of films, such as alternating silicon (Si) layers and silicon germanium (SiGe) layers, with varying properties depending on the specific application in which the films are deposited.

[0018] The various embodiments described utilize relaxed SiGe buffers and epitaxial lateral overgrowth techniques to create localized templates for strained GAA channel superlattice structures, thereby enabling increased mobility, as well as n-FETs and p-FETs within the same biaxially strained silicon channel. In at least one implementation form, the structure further incorporates bottom dielectric insulation beneath the channel to reduce substrate leakage current. The usefulness of the GAA structure for multiple technology nodes is extended by the ability to adjust the level of strain and thus the improvement in mobility within the channel. Techniques for localized substrate insulation are provided without using a full silicon-on-insulator (SOI) substrate. Compared to SOI, costs are reduced, and substrate insulation is possible only where needed, instead of across the entire wafer as in the case of SOI. Substrate insulation is possible by forming the GAA channel region on a dielectric region, e.g., an STI region, thereby reducing substrate leakage current (a pseudo-SOI structure is created). Furthermore, the formation of strained Si / Si(1-x)Ge(x) superlattices for GAA channels is possible by creating a single-crystal material on top of the dielectric region.

[0019] FIG. 1 shows a schematic cross-sectional view of a gate-all-around (GAA) structure 100 according to one or more implementations of the present disclosure. The GAA structure 100 includes a multi-material layer 130 disposed on a substrate 110. The substrate 110 has a front surface 110f (also referred to as a front surface) and a back surface 110b opposite the front surface 110f. The substrate 110 can be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 110 can have various dimensions such as 200 mm, 300 mm, 450 mm, or other diameters, and can be a rectangular or square panel. Unless otherwise specified, the examples described are performed on substrates with a diameter of 200 mm, 300 mm, or 450 mm.

[0020] The GAA structure 100 further includes insulating regions 112a-c formed in the substrate 110. The insulating regions 112a-c are formed in the corresponding trenches 114a-c. In at least one mounting configuration, the insulating regions 112a-c are shallow trench insulation (STI). The trenches 114a-c extend from the front surface 110f of the substrate 110 into the substrate 110. Thus, the top surface 113t of the insulating regions 112a-c is coplane or substantially coplane with the front surface 110f of the substrate 110. The insulating regions 112a-c include a bottom surface 113b, a top surface 113t, and at least one side wall 113s. The insulating regions 112a-c are formed by filling the trenches 114a-c with an insulating material. In at least one mounting configuration, the insulating material is a dielectric material. For example, insulating materials include, consist of, or essentially consist of, low-k dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), and carbon-doped oxides; ultra-low-k dielectrics such as porous carbon-doped silicon dioxide; polymers such as polyimide; and combinations thereof. In a particular implementation, the insulating material includes, consists of, or essentially consists of silicon oxide.

[0021] The GAA structure 100 further includes buffer regions 118a-b formed in the substrate 110. The buffer regions 118a-b are formed in corresponding recesses 120a-b. In at least one implementation configuration, the buffer regions 118a-b are relaxed Si(1-x)Ge(x) buffer regions. The growth of the relaxed SiGe buffer material in the buffer regions 118a-b between the insulating regions 112a-c allows dislocations to terminate on the sidewalls of the insulating regions 112a-c, thereby reducing the dislocation density on the front surface 110f of the substrate 110. Furthermore, the buffer regions enable epitaxial lateral overgrowth so that a single-crystal epitaxial layer is formed on the front surface 110f of the substrate 110. The recesses 120a-b extend from the front surface 110f of the substrate 110 into the substrate 110. Therefore, the top surface 119t of buffer regions 118a-b is coplane or substantially coplane with the front surface 110f of the substrate 110. Each buffer region 118a-b includes a bottom surface 119b, a top surface 119t, and at least one side wall 119s. In at least one mounting configuration, each buffer region 118a-b extends from one side wall of an insulating region to the side wall of an adjacent insulating region. For example, as shown in Figure 1, each buffer region 118a extends from the side wall 113s of insulating region 112a to the side wall 113s of insulating region 112b. In at least one mounting configuration, the bottom surface 119b of each buffer region 118a-b is offset from the bottom surface 113b of each insulating region 112a-b. In one example, as shown in Figure 1, the bottom surface 119b of buffer regions 118a-b defines a plane located above the plane defined by the bottom surface 113b of insulating regions 112a-b. In another example, the bottom surface 119b of buffer regions 118a-b extends below the bottom surface 113b of insulating regions 112a-b. In yet another example, the bottom surface 119b of buffer regions 118a-b is coplane with or substantially coplane with the bottom surface 113b of insulating regions 112a-b. Buffer regions 118a-b are formed by filling recesses 120a-b with SRB. In at least one implementation configuration, the strain-relaxing buffer material has at least one component, for example, a stepped concentration of germanium. In at least one implementation configuration, the SRB material comprises a group IV material, such as silicon and germanium.For example, the SRB material is Si. 1-x Ge x This includes x, where x is the germanium concentration. The germanium concentration (atomic percentage) in buffer regions 118a-b may be stepwise.

[0022] The GAA structure 100 further comprises a multi-material layer 130. The multi-material layer 130 comprises a buffer layer 134, a superlattice structure 141 disposed on the buffer layer 134, and optionally oxide layers 150a-c disposed on the superlattice structure 141. The oxide layers 150a-c may be gate oxide layers or dummy gate oxide layers. In at least one implementation, the buffer layer 134 is a single-crystal epitaxial layer. In at least one implementation, the buffer layer 134 comprises, consists of, or essentially consists of a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. In one example, the buffer layer 134 is a single-crystal silicon layer. In another example, the buffer layer 134 is a relaxed epitaxial Si(1-x)Ge(x) buffer material, where the germanium concentration "x" is either stepwise, uniform, or substantially uniform throughout the buffer layer 134. In at least one implementation, the thickness of the buffer layer 134 is in the range of approximately 20 Å to approximately 200 Å, such as approximately 50 Å.

[0023] The superlattice structure 141 includes at least one pair of layers, each pair containing a first material layer 142 and a second material layer 144. The example shown in Figure 1 shows three pairs, each containing a first material layer 142 and a second material layer 144 (these are alternating pairs, each containing a first material layer 142 and a second material layer 144). The number of pairs may vary based on different process needs, such as requiring extra first material layers 142 or second material layers 144, or not requiring extra first material layers 142 or second material layers 144. In one implementation configuration, the thickness of each single first material layer 142 can be between approximately 20 Å and approximately 200 Å, such as approximately 50 Å, and the thickness of each single second material layer 144 can be between approximately 20 Å and approximately 200 Å, such as approximately 50 Å. The superlattice structure 141 may have a total thickness between approximately 10 Å and approximately 5000 Å, such as between approximately 40 Å and approximately 4000 Å.

[0024] The first material layer 142 is an amorphous material layer. In at least one configuration, the first material layer 142 is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layer. Alternatively, the first material layer 142 is a doped silicon layer, including a p-doped silicon layer or an n-doped layer. In yet another configuration, the first material layer 142 is a Group III-V material, such as a GaAs layer. In yet another configuration, the second material layer 144 is a silicon layer, and the first material layer 142 is a metallic material having a high-k material coating on its outer surface. Suitable examples of high-k materials include, in particular, hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO4), hafnium aluminum oxide (HfAlO), zirconium silicate oxide (ZrSiO4), tantalum dioxide (TaO2), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT). In a particular packaging configuration, the coating layer is a hafnium dioxide (HfO2) layer.

[0025] Spacer 146 is formed adjacent to the edge of the first material layer 142 and can be considered a portion of the first material layer 142. Spacer 146 is a dielectric spacer, an air gap, or a combination of a dielectric spacer and an air gap. Spacer 146 can be formed by etching and removing each portion of the first material layer 142 using an etching precursor to form a recess at each edge of the first material layer 142. Spacer 146 is formed in the recess adjacent to each of the first material layer 142. Furthermore, a liner layer (not shown) may be deposited in the recess before the deposition of spacer 146. Spacer 146 is formed from a dielectric material and separates each of the nanowires or nanosheets formed as the second material layer 144. In at least one implementation configuration, spacer 146 is selected to be a silicon-containing material, such as a low-k material, that can reduce parasitic capacitance between the gate and source / drain structure in the GAA nanowire structure. The silicon-containing material or low-k material may be other suitable materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbide nitride, doped silicon layer, or Black Diamond® material available from Applied Materials. In one example, spacer 146 is a low-k material (e.g., with a dielectric constant less than 4) or a silicon oxide / silicon nitride / silicon carbide-containing material. In another example, spacer 146 is an air gap.

[0026] Each of the second material layers 144 is a crystalline layer, such as a single crystal, polycrystalline, or single-crystal silicon layer. The second material layer 144 is formed using an epitaxial deposition process. Alternatively, the second material layer 144 is a doped silicon layer, including a p-doped silicon layer or an n-doped layer. Suitable p-dopants include B dopant, Al dopant, Ga dopant, In dopant, etc. Suitable n-dopants include N dopant, P dopant, As dopant, Sb dopant, etc. Another alternative is that the second material layer 144 is a Group III-V material, such as a GaAs layer.

[0027] The multilayer material layer 130 further includes oxide layers 150a to 150c disposed on the superlattice structure 141.

[0028] As shown in Figure 1, the multilayer material 130 is patterned to form fins, such as a first fin 140a, a second fin 140b, and a third fin 140c. Each fin 140a-c is positioned on and aligned with the corresponding insulating regions 112a-c. For example, the first fin 140a is positioned on insulating region 112a, the second fin 140b is positioned on insulating region 112b, and the third fin 140c is positioned on insulating region 112c. The formation and alignment of the fins 140a-c on the insulating regions 112a-c respectively allows for the insulation of the substrate 110 from the fins 140a-c by creating a pseudo-SOI structure that reduces substrate leakage current. As shown in Figure 1, the fin comprises a buffer layer 134, a first material layer 142, a second material layer 144, and an oxide layer 150. Although three fins 140a-c are shown in Figure 1, it should be understood that any suitable number and type of fins may be used.

[0029] The GAA structure 100 further includes source / drain regions 160a-b. The source / drain regions 160a-b are formed in recesses defined by adjacent fins 140a-c. For example, as shown in Figure 1, the source / drain region 160a is formed in a recess defined between a first fin 140a and a second fin 140b, and the source / drain region 160b is formed in a recess defined between a second fin 140b and a third fin 140c. In at least one implementation configuration, the source / drain regions 160a-b are formed from doped silicon containing p-type doped silicon and n-type doped silicon. In an implementation configuration where the GAA structure 100 is an n-channel metal oxide semiconductor (NMOS), the source / drain regions 160a-b are formed from silicon doped with an n-type dopant. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, or combinations thereof. In a configuration where the GAA structure 100 is a p-channel metal oxide semiconductor (PMOS), the source / drain regions 160a-b are formed from silicon doped with p-type dopants. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, or combinations thereof.

[0030] As shown in Figure 1, the source / drain regions 160a-b include a bottom surface 161b, a top surface 161t, and at least one sidewall 161s. In at least one implementation configuration shown in Figure 1, the source / drain regions 160a-b extend from the sidewall of a fin, e.g., a first fin 140a, to the sidewall of an adjacent fin, e.g., a second fin 140b. The bottom surface 161b is defined by the top surface 119t of the buffer regions 118a-b. At least one sidewall 161s is defined by a buffer layer 134 and a superlattice structure 141, e.g., a spacer 146 and a second material layer 144.

[0031] In at least one implementation, the upper surface 161t of the source / drain regions 160a-b is offset from the upper surfaces of the fins 140a-c. In one example, as shown in Figure 1, the upper surface 161t of the source / drain regions 160a-b defines a plane located above the plane defined by the upper surfaces of the fins 140a-c.

[0032] Figure 2 shows a schematic cross-sectional view of another GAA structure 200 according to one or more implementations of the present disclosure. The GAA structure 200 is similar to the GAA structure 100 shown in Figure 1. However, the GAA structure 200 shown in Figure 2 further includes bottom dielectric insulating layers 210a-b. The bottom dielectric insulating layers 210a-b are formed at the bottom of recesses defined by adjacent fins. For example, the bottom dielectric insulating layer 210a is formed at the bottom of a recess defined by the sidewall of the first fin 140a and the sidewall of the second fin 140b. The bottom dielectric insulating layers 210a-b insulate the buffer regions 118a-b from the source / drain regions 160a-b and the buffer layer 134. The bottom dielectric insulating layers 210a to 210b are in contact with the upper surface 119t of the buffer regions 118a to 210b, the side wall of the buffer layer 134, and the bottom surface 161b of the source / drain regions 160a to 210b.

[0033] Figure 3 shows an exemplary flowchart of Method 300 for forming a GAA structure according to one or more implementations of the present disclosure. Figures 4A to 4M show cross-sectional views of various stages in forming a GAA structure according to one or more implementations of the present disclosure. Referring to Figures 4A to 4M, cross-sectional views of several implementations of the GAA structure at various stages of manufacturing are given to illustrate the method of Figure 3. While Figures 4A to 4M are used to describe Method 300, it should be understood that the structures disclosed in Figures 4A to 4M are not limited to Method 300 and can instead be independent structures unrelated to Method 300. Similarly, while Figures 4A to 4M are used to describe Method 300, it should be understood that Method 300 is not limited to the structures disclosed in Figures 4A to 4M and can instead be independent structures unrelated to Figures 4A to 4M.

[0034] Figure 4A shows cross-sectional views of parts of the GAA structure 100 during the intermediate manufacturing stage corresponding to operation 310, in several implementation configurations. During operation 310, a substrate, for example, the substrate 110 shown in Figure 4A, is given.

[0035] Figures 4B-4C show cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 320, in several implementation configurations. During operation 320, insulating regions are formed, for example, as shown in Figures 4B-4C, insulating regions 112a-c are formed in the substrate 110. Referring to Figure 4B, trenches 114a-c are formed in the substrate 110. Trenches 114a-c extend from the front surface 110f of the substrate 110 into the substrate 110. Trenches 114a-c may be formed by a patterning and etching process. The patterning and etching process may include forming a mask layer on the front surface 110f of the substrate 110. The mask layer may be patterned using photolithography techniques. Generally, a photoresist material (not shown) is deposited on the mask layer. The photoresist material is irradiated (exposed to light) with radiation, e.g., light, through a patterned reticle to induce a reaction in the portion of the photoresist material that is exposed to energy. The photoresist material is developed to remove portions of the photoresist material, and the remaining photoresist material protects the material beneath the substrate 110 from subsequent processing operations such as etching.

[0036] Referring to Figure 4C, insulating material is deposited in trenches 114a-c to form corresponding insulating regions 112a-c in the substrate 110. In at least one mounting configuration, the insulating material is deposited using a process such as chemical vapor deposition (CVD), flowable CVD (FCVD), or a spin-on glass process, but any acceptable process may be used. Subsequently, the insulating regions 112a-c may undergo one or more mask removal and planarization processes, such as an etching process or a chemical mechanical polishing (CMP) process, to remove the portion of the insulating regions 112a-c that extends over the front surface 110f of the substrate 110. The planarization process may be performed so that the upper surface 113t of the insulating regions 112a-c is coplane or substantially coplane with the front surface 110f of the substrate 110.

[0037] Figure 4D shows cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 330, in several mounting configurations. During operation 330, recesses, for example, recesses 120a-b, are formed in the substrate 110. Recesses 120a-b may be formed by patterning and etching processes. Recesses 120a-b extend from the front surface 110f of the substrate 110 into the substrate 110. Recesses 120a-b are defined by the sidewalls 113s of insulating regions 112a-c. For example, as shown in Figure 4D, recess 120a is defined by the sidewalls 113s of insulating region 112a and the sidewalls 113s of insulating region 112b, and recess 120b is defined by the sidewalls 113s of insulating region 112b and the sidewalls 113s of insulating region 112c. Recesses 120a-b may be formed by patterning and etching processes. The etching process may be a selective etching process that selectively removes the material of the substrate 110 (e.g., silicon) from the material (e.g., an oxide such as silicon oxide) of the insulating regions 112a to c in order to form recesses 120a to b.

[0038] Figure 4E shows cross-sectional views of a portion of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 340, according to several implementation configurations. During operation 340, recesses 120a-b are filled with strain-relieving buffer (SRB) material to form buffer regions 118a-b. Buffer regions 118a-b are formed by filling recesses 120a-b with SRB material. Buffer regions 118a-b include an upper surface 119t and a lower surface 119b. In at least one implementation configuration, the strain-relieving buffer material has at least one component, for example, a stepped concentration of germanium. In at least one implementation configuration, the SRB material includes a group IV material such as silicon and germanium. In one example, the SRB material is Si 1-x Ge x The material contains x, where x is the germanium concentration. The germanium concentration (atomic percentage) in buffer regions 118a-b may be stepwise. In at least one implementation, the SRB material is deposited in recesses 120a-b via an epitaxial chemical vapor deposition process. The epitaxial deposition process allows for precise control of the germanium content in each of the buffer regions 118a-b and in the later-formed buffer layer 134, thereby providing favorable control of lattice matching with the substrate 110, the later-deposited superlattice structure 141, or both the substrate 110 and the later-deposited superlattice structure 141. In one example, a relaxed epitaxial Si(1-x)Ge(x) buffer material is grown in recesses 120a-b such that dislocations vanish on the sidewalls 113s of insulating regions 112a-c.

[0039] In at least one implementation, buffer regions 118a-b have Si with stepwise germanium concentrations. 1-x Ge xThe material contains such that the germanium concentration at the interface between the bottom surface 119b of the buffer region 118a-b and the substrate 110 is similar to the germanium concentration of the substrate 110 (e.g., 0 at%), the germanium concentration at the interface between the top surface 119t of the buffer region 118a-b and the backside surface 134b of the buffer layer 134' (e.g., 10-15 at%) is similar to the uniform or substantially uniform germanium concentration of the buffer layer 134' (e.g., 10-15 at%), and the uniform or substantially uniform germanium concentration of the buffer layer 134' is similar to the germanium concentration of the adjacent SiGe layer in the superlattice structure (e.g., 10-15 at%).

[0040] Figure 4F shows cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 350, according to several implementation configurations. During operation 350, a buffer layer 134' is formed. The buffer layer 134' is formed on the front surface 110f of the substrate 110. The buffer layer 134' has a back surface 134b and a front side surface 134f (also called the front surface) opposite the back surface 134b (also called the back surface). The back surface 134b is in contact with the front surface 110f of the substrate 110, the upper surfaces 113t of the insulating regions 112a-c, and the upper surfaces 119t of the buffer regions 118a-b. In at least one implementation configuration, the buffer layer 134' is formed via an epitaxial chemical vapor deposition process. In at least one implementation configuration, the buffer layer 134' is formed via the same epitaxial deposition process used to form the buffer regions 118a-b. In an alternative implementation, the buffer layer 134' is formed via a different epitaxial deposition process.

[0041] The epitaxial deposition process allows for precise control of the germanium content in each of the buffer regions 118a-b and in the buffer layer 134, thereby providing favorable control of lattice matching between the substrate 110, the later deposited superlattice structure 141, or both the substrate 110 and the later deposited superlattice structure 141.

[0042] In at least one implementation configuration, the buffer layer 134' comprises a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. In at least one implementation configuration, the buffer layer 134' has a germanium concentration gradient. The germanium concentration gradient may increase from the back surface 134b of the buffer layer 134' to the front surface 134f of the buffer layer 134'. The buffer layer 134' may be a SiGe spacer layer.

[0043] In at least one implementation configuration, the germanium concentration in the buffer layer 134' may increase so that it is lowest near the interface with the front surface 110f of the substrate 110 (for example, near the back surface 134b of the buffer layer 134') and highest near the interface with the superlattice structure 141. In another implementation configuration, the germanium concentration in the buffer layer 134' may decrease so that it is highest near the interface with the front surface 110f of the substrate 110 (for example, near the back surface 134b of the buffer layer 134) and lowest near the interface with the superlattice structure 141.

[0044] In at least one implementation, the buffer layer 134' contains silicon germanium, which has a uniform or substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the upper surface 119t of the buffer regions 118a~b.

[0045] In at least one implementation, buffer regions 118a-b have Si with stepwise germanium concentrations. 1-x Ge x The germanium concentration at the interface between the bottom surface 119b of the buffer region 118a-b and the substrate 110 is similar to the germanium concentration of the substrate 110 (e.g., 0 at%), the germanium concentration at the interface between the top surface 119t of the buffer region 118a-b is similar to the germanium concentration of the back surface 134b of the buffer layer 134', and the front surface 134f of the buffer layer 134' (e.g., 10-15 at%) is similar to the uniform or substantially uniform germanium concentration of the superlattice structure 141 that will be deposited later.

[0046] In at least one implementation, the stepwise germanium concentration of the buffer layer 134' has a germanium content that increases in the range of approximately 0% to approximately 20%, approximately 0% to approximately 15%, approximately 0.1% to approximately 15%, approximately 0.5% to approximately 15%, approximately 1% to approximately 15%, or approximately 1% to approximately 10%. The silicon content of the buffer layer 134' may be in the range of approximately 80% to approximately 100%, approximately 85% to approximately 100%, approximately 85% to approximately 99.9%, approximately 85% to approximately 99.5%, or approximately 90% to approximately 99%. The buffer layer 134' may have a maximum germanium content of 10% or less, 15% or less, or 20% or less.

[0047] The buffer layer 134' may be subjected to a planarization process. In at least one implementation configuration, the front surface 134f of the buffer layer 134' has high surface roughness. This high surface roughness of the front surface 134f of the buffer layer 134' makes it difficult to use the buffer layer 134' as a template for subsequent growth of the superlattice structure 141 on the buffer layer 134'. The planarization process removes the portion of the front surface 134f of the buffer layer 134' to form a smoothed surface. Any preferred planarization process may be used. The planarization process may be a chemical mechanical polishing (CMP) process or an etch-back process.

[0048] Figure 4G shows cross-sectional views of a portion of the gate-all-around structure 100 during an intermediate stage of manufacturing corresponding to operation 360, in several implementation configurations. During operation 360, a superlattice structure, e.g., superlattice structure 141, is formed on the substrate 110, e.g., on a buffer layer 134'. The superlattice structure 141 includes at least one pair of layers, each pair including a first material layer 142' and a second material layer 144'. The example shown in Figure 4G shows three pairs, each including a first material layer 142' and a second material layer 144' (these are alternating pairs, each including a first material layer 142' and a second material layer 144'). The number of pairs may vary based on different process needs, such as whether extra first material layers 142 or second material layers 144 are required or not.

[0049] The first material layer 142' is an amorphous material layer. In at least one implementation configuration, the first material layer 142' is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layer. Alternatively, the first material layer 142' is a doped silicon layer containing a p-type doped silicon layer or an n-type doped layer. In yet another implementation configuration, the first material layer 142' is a Group III-V material, such as a GaAs layer. The first material layer 142' is formed using an epitaxial deposition process performed in an epitaxial deposition chamber.

[0050] The second material layer 144' is a crystalline material layer, such as a single crystal, polycrystalline, or single-crystal silicon layer. The second material layer 144' is formed using an epitaxial deposition process performed in an epitaxial deposition chamber. Alternatively, the second material layer 144' is a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. Suitable p-type dopants include B dopant, Al dopant, Ga dopant, In dopant, etc. Suitable n-type dopants include N dopant, P dopant, As dopant, Sb dopant, etc. Another alternative is that the second material layer 144' is a Group III-V material, such as a GaAs layer.

[0051] Figure 4H shows a cross-sectional view of a portion of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 365, according to several implementation configurations. Optionally, in operation 365, an oxide layer 150' is formed. The oxide layer 150' may be formed on the superlattice structure 141. In at least one implementation configuration, the oxide layer 150' may be formed by a deposition process, e.g., thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming a dummy gate oxide layer. In at least one implementation configuration, the oxide layer 150' may be formed from the same material as the insulating regions 112a-c. In at least another implementation configuration, the oxide layer 150' may be manufactured from one or more suitable dielectric materials, such as low-k dielectrics like silicon oxide, silicon nitride, carbon-doped oxide, ultra-low-k dielectrics like porous carbon-doped silicon dioxide, polymers like polyimide, or combinations thereof. In another implementation, the oxide layer 150' includes a dielectric material having a high dielectric constant (k value), for example, greater than 3.9. The material may include silicon nitride, oxynitride, metal oxides such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, combinations thereof, or multiple layers thereof.

[0052] Figure 4I shows cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 370, for several implementation configurations. In operation 370, patterning and etching processes are performed to form source / drain recesses 412a-b in a multi-material layer 130 including a buffer layer 134', a superlattice structure 141, and optionally, an oxide layer 150 (if present). In at least one implementation configuration, as shown in Figure 4I, the source / drain recesses 412a-b are defined by sidewalls 413s and a bottom surface 413b. The sidewalls 413s are defined by the buffer layer 134, the superlattice structure 141, and the oxide layers 150a-c (if present) of the fins 140a-c. The bottom surface 413b is defined by the top surface 119t of the buffer regions 118a-b. The patterning and etching process of operation 370 may include forming a hard mask layer on the upper surface of the superlattice structure 141 or (if present) on the upper surface of the oxide layer 150'. In at least one implementation, a photolithography technique is used to pattern the hard mask layer. Generally, a photoresist material (not shown) is deposited on top of the hard mask layer. The photoresist material is irradiated (exposed to light) with radiation, e.g., light, through a patterned reticle to induce a reaction in the portion of the photoresist material that is exposed to energy. The photoresist material is developed to remove the portion of the photoresist material, and the remaining photoresist material protects the underlying material from subsequent processing operations, such as etching. In at least one implementation, the etching process is such as a reactive ion etching (RIE) process. In one example, the RIE process is performed using chlorine, bromine, or fluorine-based chemistry to anisotropically etch the superlattice structure.

[0053] As shown in Figure 4I, after the etching process is performed on the superlattice structure 141, the remaining areas of the superlattice structure 141 and the underlying substrate 110 form fins, such as the first fin 140a, the second fin 140b, and the third fin 140c. As can be seen in Figure 4I, the fins 140a-c include portions of the buffer layer 134, portions of the superlattice structure 141 (e.g., portions of the first material layer 142' (e.g., the silicon layer) and portions of the second material layer 144' (e.g., the SiGe layer)), and portions of the oxide layers 150a-c. Although three fins 140a-c are shown in Figure 4I, it should be understood that any preferred number and type of fins may be utilized.

[0054] Figure 4J shows cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 380, in several implementation configurations. In operation 380, an inner spacer, for example, spacer 146, is formed. As shown in Figure 4J, spacer 146 is formed adjacent to the edge of the first material layer 142 and can be considered a portion of the first material layer 142. Spacer 146 is a dielectric spacer, an air gap, or both a dielectric spacer and an air gap. Spacer 146 can be formed by etching and removing each portion of the first material layer 142 using an etching precursor to form a recess at each edge of the first material layer 142. Spacer 146 is formed in the recess adjacent to each of the first material layer 142. Furthermore, a liner layer (not shown) may be deposited in the recess before the deposition of spacer 146. Spacer 146 is formed from a dielectric material and separates each of the nanowires or nanosheets formed as the second material layer 144. In at least one implementation configuration, the spacer 146 is selected to be a silicon-containing material capable of reducing parasitic capacitance between the gate and source / drain structures in the GAA nanowire structure, such as a low-k material. The silicon-containing material or low-k material may be other suitable materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbide nitride, doped silicon layer, or Black Diamond® material available from Applied Materials. In one example, the spacer 146 is a low-k material (e.g., with a dielectric constant less than 4) or a silicon oxide / silicon nitride / silicon carbide-containing material. In another example, the spacer 146 is an air gap.

[0055] Figure 4K shows cross-sectional views of portions of the GAA structure 100 during an intermediate stage of manufacturing corresponding to operation 395, according to several implementation configurations. In operation 395, source / drain regions 160a-b are formed within source / drain recesses 412a-b. Source / drain region 160a fills the source / drain recess 412a between the first fin 140a and the second fin 140b, and source / drain region 160b fills the source / drain recess 412b between the second fin 140b and the third fin 140c. In at least one implementation configuration, as shown in Figure 4L, the source / drain regions 160a-b are in contact with the side walls of the fins 140a-c and the upper surfaces 119t of the buffer regions 118a-b.

[0056] The source / drain regions 160a-b can be formed via an epitaxial deposition process. The use of epitaxially grown material within the source / drain regions 160a-b allows stress to be applied to the channel region. The material used for the source / drain regions 160a-b may vary for n-type and p-type FinFETs, such that one type of material is used to apply tensile stress to the channel region for n-type FinFETs, and another type of material is used to apply compressive stress for p-type FinFETs. For example, SiP or SiC may be used to form an n-type FinFET, and SiGe or Ge may be used to form a p-type FinFET. However, any suitable material may be used. The epitaxial source / drain regions 160a-b can be doped either by an injection process to inject a suitable dopant, or by in-doping during material growth. In at least one implementation configuration, the first source / drain region 160a is formed from phosphorus (P)-doped SiC or SiP to form an n-type FinFET device, and the second source / drain region 160b is formed from boron (B)-doped SiGe or Ge to form a p-type FinFET device.

[0057] Figure 4L shows a cross-sectional view of a portion of the GAA structure 200 during an intermediate stage of manufacturing corresponding to optional operation 390, in several implementation configurations. The GAA structure 200 shown in Figure 4L is similar to the GAA structure 100 shown in Figure 4K, except that the gate-all-around structure 200, formed before source / drain deposition in operation 395, includes bottom dielectric insulating layers 210a-b. In optional operation 390, the bottom dielectric insulating layers 210a-b are formed. The bottom dielectric insulating layers 210a-b are formed at the bottom of the source / drain recesses 412a-b. The bottom dielectric insulating layers 210a-b insulate the source / drain regions 160a-b, which are deposited later, from the buffer regions 118a-b, the buffer layer 134, and the substrate 110. In at least one implementation configuration, the bottom dielectric insulating layers 210a-b contain dielectric material. For example, the dielectric material may include, consist of, or be essentially composed of, low-k dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), and carbon-doped oxides; ultra-low-k dielectrics such as porous carbon-doped silicon dioxide; polymers such as polyimide; and combinations thereof. In a particular packaging configuration, the insulating material may include, consist of, or be essentially composed of silicon oxide. In at least one packaging configuration, the dielectric material of the bottom dielectric insulating layers 210a-b is formed by a process such as CVD, fluid CVD (FCVD), or a spin-on glass process, but any preferred process may be used. The dielectric material of the bottom dielectric insulating layers 210a-b may include, consist of, or be essentially composed of the same material as the insulating regions 112a-c.

[0058] Figure 4M shows cross-sectional views of portions of the gate-all-around structure 200 during an intermediate stage of manufacturing corresponding to operation 395, according to several implementation configurations. In operation 395, source / drain regions 160a-b are formed within source / drain recesses 412a-b. Source / drain region 160a fills the source / drain recess 412a between the first fin 140a and the second fin 140b, and source / drain region 160b fills the source / drain recess 412b between the second fin 140b and the third fin 140c. In at least one implementation configuration, as shown in Figure 4L, the source / drain regions 160a-b are in contact with the sidewalls of the fins 140a-c and the bottom dielectric insulating layers 210a-b.

[0059] Figure 5 is a plan view of the cluster tool 500 according to another embodiment described. The cluster tool 500 features at least one epitaxial deposition chamber. An example of the cluster tool 500 is the CENTURA® EPI system, available from Applied Materials, Inc. in Santa Clara, California. Cluster tools manufactured by other companies may also be used. Any convenient type of transfer robot 504 is positioned in the transfer chamber 502 of the cluster tool 500. A load lock 506 with two load lock chambers 506A, 506B is coupled to the transfer chamber 502. Multiple processing chambers 508, 510, 512, 514, and 516 are also coupled to the transfer chamber 502. In at least one embodiment, the multiple processing chambers 508, 510, 512, 514, and 516 include at least one of a pre-clean chamber, a material deposition chamber such as an epitaxial deposition chamber, and a heat treatment chamber such as an annealing, degassing, or oxidation chamber.

[0060] Processing chamber 508 may be a pre-clean chamber configured to clean the substrate before epitaxial deposition of a material, such as a buffer material, a strain-relaxing buffer material, or a superlattice structure. The pre-clean chamber may be configured to perform the Applied Materials SICONI® pre-clean process. Processing chambers 510 and / or 514 may be material deposition chambers, such as epitaxial deposition chambers, on which an epitaxial growth process can be performed. Processing chambers 512 and / or 516 may be additional material deposition chambers or heat treatment chambers on which a heat treatment process can be performed.

[0061] The system controller 557 communicates with the transport robot 504 and the multiple processing chambers 508, 510, 512, 514, and 516. The system controller 557 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 557 may be a computer including a central processing unit (CPU) 592, memory 594, input / output 596, suitable circuitry 598, and storage.

[0062] The process can generally be stored in the memory of the system controller 557 as a software routine that, when executed by the processor, causes the process chamber to execute the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Thus, the process can be implemented in software and executed using a computer system, implemented in hardware, for example as an application-specific integrated circuit or other type of hardware embodiment, or implemented as a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a purpose-specific computer (controller) that controls the chamber operation so that the process can be executed.

[0063] In at least one implementation, the system controller 557 has a configuration for controlling the epitaxial growth chamber to grow an epitaxial material, for example, at least one of the buffer regions 118a-b, buffer layer 134', superlattice structure 141, and source / drain regions 160a-b.

[0064] A cluster tool 500 may be used to perform at least a portion of the method 300 described above. During processing, a substrate to be processed may arrive at the cluster tool 500 in a pod (not shown). The substrate is transferred from the pod to vacuum-enabled load-lock chambers 506A, 506B by a factory interface robot (not shown). The substrate is then picked up by a transfer robot 504 in a transfer chamber 502, which is generally kept under vacuum. The transfer robot 504 then loads the substrate into a processing chamber 508 for cleaning. The transfer robot 504 then picks up the substrate from the processing chamber 508 and loads the substrate into either the processing chamber 510 or 514, whichever is available, for epitaxial deposition. The epitaxial material described may be grown on the cleaned substrate in the processing chamber 510 or 514. The transfer robot 504 then picks up the substrate from the processing chamber 510 or 514 and transfers the substrate into either the processing chamber 512 or 516, which is a heat treatment chamber. The epitaxial material may then be subjected to a rapid heating / cooling process. The transfer robot 504 then picks up the substrate from the processing chamber 512 or 516 and transfers the substrate to the processing chamber 514 to deposit additional material on top of the epitaxial material.

[0065] The summary of the invention, the modes for carrying out the invention, the claims, and the accompanying drawings refer to specific features (including method operations) of the disclosure. It should be understood that the disclosure herein includes all possible combinations of such specific features. For example, where a particular feature is disclosed in the context of a particular aspect, implementation, or example of the disclosure, or in the context of a particular claim, that feature may be used to the extent possible in combination with other particular aspects and implementations of the disclosure, and / or in the context of other particular aspects and implementations of the disclosure, as well as in general within the disclosure.

[0066] The term “comprises” and its grammatical equivalents are used to mean that other components, materials, actions, etc., may optionally be present. For example, an article “comprising” (or “which comprises”) components A, B, and C may consist of (i.e., contain only) components A, B, and C, or it may contain not only components A, B, and C, but also one or more other components. Furthermore, whenever the transitional phrase “comprising” or its grammatical equivalent precedes a composition, element, or group of elements, it is intended that the same composition or group of elements may be preceded by the transitional phrase “consisting essentially of,” “consisting of,” “selected from the group consisting of,” or “is,” and vice versa.

[0067] If a method is referenced that includes two or more defined actions, the defined actions may be performed in any order or concurrently (unless the context excludes that possibility), and the method may include one or more other actions that are performed before any of the defined actions, between two of the defined actions, or after all of the defined actions (unless the context excludes that possibility).

[0068] When introducing elements of this disclosure or its exemplary aspects or embodiments, the articles “a,” “an,” “the,” and “said” are intended to mean that one or more of the elements exist.

[0069] The foregoing applies to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. It is a substrate, A plurality of insulating regions formed in the substrate, comprising a plurality of insulating regions including an insulating material, A buffer region formed in the substrate, wherein the buffer region separates adjacent insulating regions of the plurality of insulating regions. A substrate including, A plurality of fins, each fin is formed on a corresponding insulating region of the plurality of insulating regions, and each fin is A buffer layer in contact with the insulating material, Multiple silicon layers and multiple silicon germanium layers are alternately arranged in multiple stacked pairs on the buffer layer. Multiple fins, including Semiconductor devices, including those mentioned above.

2. The semiconductor device according to claim 1, wherein the buffer region comprises a relaxed Si(1-x)Ge(x) material, where x represents the concentration of germanium.

3. The semiconductor device according to claim 2, wherein the buffer layer comprises a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

4. The semiconductor device according to claim 3, wherein the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

5. The semiconductor device according to claim 4, wherein the crystalline material contains silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region.

6. The semiconductor device according to claim 1, further comprising a source / drain region formed in a source / drain recess defined by adjacent fins.

7. The semiconductor device according to claim 6, further comprising a dielectric insulating layer that separates the source / drain region from the upper surface of the buffer region.

8. The semiconductor device according to claim 1, wherein the insulating region has a thickness greater than the thickness of the buffer region.

9. A method for forming a semiconductor device, The process involves forming multiple insulating regions in a silicon substrate, wherein each insulating region contains an insulating material. To form a recess between adjacent insulating regions of the plurality of insulating regions, the portion of the silicon substrate is removed. To form a buffer region, the recess is filled with buffer material, Growing a buffer layer on the silicon substrate, the insulating material, and the buffer material, The method involves forming a superlattice structure on the buffer layer, wherein the superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers arranged alternately in a plurality of stacked pairs. Patterning and etching the superlattice structure and the buffer layer to form fins from the superlattice structure and the buffer layer, wherein the fins are aligned with the insulating region and the fins define source / drain recesses. Filling the source / drain recess with epitaxial material to form the source / drain region Methods that include...

10. The method according to claim 9, further comprising forming a dielectric insulating layer in the source / drain recess before filling the source / drain recess with the epitaxial material.

11. The method according to claim 9, wherein filling the recess with the buffer material to form the buffer region comprises epitaxially growing a relaxed Si(1-x)Ge(x) material, where x represents the concentration of germanium.

12. The method according to claim 11, wherein growing the buffer layer on the silicon substrate, the insulating material, and the buffer material includes epitaxial growth of a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

13. The method according to claim 12, wherein the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

14. The method according to claim 13, wherein the crystalline material contains silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region.

15. The method according to claim 12, wherein the crystalline material is selectively grown vertically from the buffer region and then grown laterally on the insulating region.

16. A method for forming a semiconductor device, The process involves forming multiple insulating regions in a silicon substrate, wherein each insulating region contains an insulating material. To form a recess between adjacent insulating regions of the plurality of insulating regions, the portion of the silicon substrate is removed. To form a buffer region, the buffer material is epitaxially grown in the recess, The method involves epitaxially growing a buffer layer on the buffer region and the insulating region, wherein the buffer layer grows epitaxially from the buffer region, The method involves forming a superlattice structure on the buffer layer, wherein the superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers arranged alternately in a plurality of stacked pairs. Patterning and etching the superlattice structure and the buffer layer to form fins from the superlattice structure and the buffer layer, wherein the fins are aligned with the insulating region and the fins define source / drain recesses. Forming a spacer on the outer surface of the silicon germanium layer, Filling the source / drain recess with epitaxial material to form the source / drain region Methods that include...

17. The method according to claim 16, wherein epitaxial growth of the buffer material in the recess comprises epitaxial growth of a relaxed Si(1-x)Ge(x) material, where x represents the concentration of germanium.

18. The method according to claim 17, wherein epitaxial growth of the buffer layer on the buffer region and the insulating region comprises epitaxial growth of a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

19. The method according to claim 18, wherein the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

20. The method according to claim 19, wherein the crystalline material comprises the silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the concentration "x" of germanium in the relaxed Si(1-x)Ge(x) material on the upper surface of the buffer region.

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