Method for manufacturing non-volatile switching elements
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NANOBRIDGE SEMICON INC
- Filing Date
- 2022-10-12
- Publication Date
- 2026-08-05
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a non-volatile switching element.
Background Art
[0002] For example, Patent Document 1 discloses a thin film transistor substrate using an oxide semiconductor and a method for manufacturing the same. Sputtering film formation is used when manufacturing the thin film transistor. In sputtering film formation, it is said that when film formation is performed under conditions where the influence of scattering by argon (Ar) ions is small, less argon is incorporated into the film, and a high-quality film can be obtained. The ratio of the distance TS between the target and the substrate to the mean free path λ of argon, that is, TS / λ, means the average number of collisions during the movement of argon from the substrate to the target, and can be used as an index of argon scattering during sputtering. In order to reduce the influence of argon scattering, it is common to reduce TS / λ, that is, to lower the pressure of argon and increase λ.
[0003] Particularly, in a sputtering apparatus in which the material target is smaller than the film formation substrate and is offset, material particles with high straightness that are not scattered are obliquely incident on the rotating substrate. In this case, by setting TS / λ to 1 or less, a high-quality thin film with excellent uniformity can be formed on a flat substrate even though a small-diameter target is used.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] In conventional manufacturing of non-volatile switching elements, buffer layer material was deposited under the conditions described above. However, the surface on which the buffer layer material is deposited has a concave step structure. As a result, the side walls of the step structure act as an obstacle, and due to the so-called shadowing effect, the thickness of the buffer material layer deposited on the lower electrode becomes uneven. Consequently, a certain number of the manufactured non-volatile switching elements exhibit degraded retention characteristics.
[0006] This disclosure has been made in view of the above points, and aims to provide a method for manufacturing a non-volatile switching element with excellent retention characteristics by eliminating uneven deposition of the buffer layer material that is sputtered onto the lower electrode. [Means for solving the problem]
[0007] According to one aspect of this disclosure, a method for manufacturing a non-volatile switching element is provided, comprising the steps of: forming a first interlayer insulating film on a substrate; embedding a lower electrode in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film; forming an opening in the first interlayer insulating film and the second interlayer insulating film in which a part of the lower electrode is exposed; sputtering a buffer layer into the opening; forming a solid electrolyte layer on the buffer layer; and forming an upper electrode on the solid electrolyte layer, wherein in the step of sputtering a buffer layer into the opening, the ratio of the mean free path of argon at the pressure of argon during film formation to the distance between the cathode and the opening is set to between 2 and 3.5 when sputtering.
[0008] The film-forming surface on which the buffer layer is formed may have a concave step pattern.
[0009] The thickness of the buffer layer may be 0.5 nm to 5 nm.
[0010] The buffer layer material of the buffer layer may be a metal or metal oxide mainly composed of titanium, aluminum, tantalum, zirconium, or hafnium.
[0011] The buffer layer material is a metal, and the process of forming a film of the buffer layer material having a thickness of 0.25 nm to 1.0 nm and the process of oxidizing the buffer layer material may be repeated until the buffer layer reaches a desired thickness.
[0012] The oxidation step may be a step of oxidizing the buffer layer material by exposing its surface to an oxidizing gas.
[0013] The shape of the film-forming surface on which the buffer layer is formed may be a concave pattern in which the aspect ratio, which is the ratio of the thickness of the second interlayer insulating film to the width of the exposed surface of the lower electrode, is 0.4 to 1, in terms of the coverage of the buffer layer material of the buffer layer.
[0014] The shape of the film-forming surface on which the buffer layer is formed may be such that one or more copper electrodes or copper wiring are partially exposed at the bottom of the opening, the side wall height of the opening is 10 to 30 nm, the diameter of the opening is 200 nm or less, and the size of the portion where the copper electrodes or copper wiring are partially exposed may be 20 to 50 nm.
[0015] The buffer layer may be formed using a sputtering apparatus in which the diameter of the sputtering target for the buffer layer is 60% or less of the diameter of the substrate on which the film is to be deposited, and the central axes of each target are offset. [Effects of the Invention]
[0016] According to this disclosure, it is possible to eliminate uneven deposition of the buffer layer material deposited by sputtering on the lower electrode and provide a method for manufacturing a non-volatile switching element with excellent retention characteristics. [Brief explanation of the drawing]
[0017] [Figure 1] This figure shows a cross-section of a non-volatile switching element according to an embodiment of the disclosed technology. [Figure 2A]It is a diagram for explaining the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 2B] It is a diagram for explaining the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 2C] It is a diagram for explaining the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 3A] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 3B] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 3C] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element according to the embodiment. [Figure 3D] It is a diagram showing the film thickness distribution of the buffer layer material formed on a flat wafer under the conditions of the embodiment. [Figure 4A] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element of the prior art. [Figure 4B] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element of the prior art. [Figure 4C] It is a diagram showing a cross-sectional SEM image of a stepped structure simulating the non-volatile switching element manufactured by the manufacturing process of the non-volatile switching element of the prior art. [Figure 4D] It is a diagram showing the film thickness distribution of the buffer layer material formed on a flat wafer under the conditions of the prior art. [Figure 5A] It is a diagram for explaining the film formation of the buffer layer. [Figure 5B] It is a diagram for explaining the film formation of the buffer layer. [Figure 6A] It is a diagram showing the result of measuring the dependence of the relative value of the data defect rate on the baking time. [Figure 6B]This figure shows the results of measuring the relative data retention failure rate and the probability of occurrence per chip. [Figure 7] This figure shows a cross-section of a non-volatile switching element according to an embodiment of the disclosed technology. [Modes for carrying out the invention]
[0018] Hereinafter, an example of an embodiment of this disclosure will be described with reference to the drawings. In each drawing, identical or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios.
[0019] Figure 1 is a diagram showing a cross-section of a non-volatile switching element according to this embodiment. The non-volatile switching element 100 comprises a first interlayer insulating film 101 formed on a substrate 110, a second interlayer insulating film 102 formed on the first interlayer insulating film 101, a lower electrode 103 embedded in the first interlayer insulating film 101, a barrier metal 104 protecting the lower electrode 103, a buffer layer 105 in contact with the lower electrode 103 at an opening 109 formed in the first interlayer insulating film 101 and the second interlayer insulating film 102, a solid electrolyte layer 106 formed on the buffer layer 105, and a first upper electrode 107 and a second upper electrode 108 formed on the solid electrolyte layer 106.
[0020] The first interlayer insulating film 101 and the second interlayer insulating film 102 can be, for example, a silicon oxide film, or a low dielectric constant film with a lower relative permittivity than a silicon oxide film (for example, an SiOCH film). Alternatively, the first interlayer insulating film 101 and the second interlayer insulating film 102 may be a laminated film formed by laminating a silicon oxide film, or a low dielectric constant film with a lower relative permittivity than a silicon oxide film.
[0021] The lower electrode 103 may be mainly composed of copper, for example, and may contain additives such as titanium (Ti), aluminum (Al), manganese (Mn), tungsten (W), and magnesium (Mg). The barrier metal 104 prevents the metal of the lower electrode 103 from diffusing into the first interlayer insulating film 101. As the barrier metal 104, tantalum (Ta) or tantalum nitride, and multilayer films thereof can be used. Multilayer copper wiring provided in the semiconductor integrated circuit of the semiconductor device can be used for the lower electrode 103 and the barrier metal 104.
[0022] The buffer layer 105 and the solid electrolyte layer 106 function as a resistive switching film of the non-volatile switching element 100. The material of the buffer layer 105 can be a metal or metal oxide mainly composed of titanium, aluminum, tantalum, zirconium, or hafnium. The lower electrode 103 functions as an active electrode that supplies copper ions to the resistive switching film.
[0023] The first upper electrode 107 is made of a material that is inert to copper ions. The second upper electrode 108 also serves as a protective layer to protect the first upper electrode 107 during etching and other processes when manufacturing the non-volatile switching element 100, and can be made of, for example, titanium nitride (TiN).
[0024] The second interlayer insulating film 102 has an opening 109. A portion of the upper surface of the lower electrode 103 is exposed to the opening 109, and the lower electrode 103 is in contact with the buffer layer 105 in the region where the opening 109 is formed. The buffer layer 105 covers the opening 109 and is in contact with a portion of the upper surface of the lower electrode 103.
[0025] The manufacturing process for the non-volatile switching element 100 is described below. Figures 2A to 2C illustrate the manufacturing process for the non-volatile switching element 100.
[0026] In the manufacturing of the non-volatile switching element 100, as shown in Figure 2A, an opening 109 is provided with a concave step pattern in the lower electrode 103 embedded in the first interlayer insulating film 101 and the second interlayer insulating film 102, thereby exposing the upper surface of the end of the lower electrode 103. The size of the opening 109 is typically 100 to 150 nm. The thickness of the second interlayer insulating film 102 is typically 10 to 30 nm. The thickness of the second interlayer insulating film 102 becomes the height of the side wall when forming the buffer layer 105. The size of the portion of the upper surface of the lower electrode 103 exposed to the opening 109 is typically 20 to 50 nm. The height of the lower electrode 103 in the portion exposed to the opening 109 (the amount of recess in the first interlayer insulating film 101) is also typically 20 to 50 nm.
[0027] As shown in Figure 2A, a concave stepped pattern is formed on the first interlayer insulating film 101 and the second interlayer insulating film 102, and as shown in Figure 2B, a material metal film for the buffer layer 105 is deposited by sputtering. In this embodiment, the argon (Ar) pressure p during film deposition is 4.9E. -2 The p value was set to Pa, and the target-substrate distance (TS) was set to 340 mm. Here, in this embodiment, the target-substrate distance TS refers to the distance between the cathode of the sputtering apparatus and the aperture 109. Assuming the van der Waals radius r of argon is 0.188 nm, p = 4.9E -2 At Pa, the mean free path λ of argon at T=300K can be calculated as 134.5 mm from the following formula (1).
[0028]
number
[0029] Therefore, in this embodiment, the buffer layer deposition condition is set to TS / λ = 2.53.
[0030] As described above, when the thickness H of a typical second interlayer insulating film 102 is 10 to 30 nm, and the size of the upper surface W of the exposed lower electrode 103 is 20 to 50 nm, uniformly depositing the material metal film of the buffer layer 105 requires the ability to embed into concave step patterns with an aspect ratio H / W of about 1 to 0.4.
[0031] The film deposition state when a buffer layer material was formed on a concave step pattern (i.e., aspect ratio 1) with an aperture 109 of approximately 120 nm in size and height of approximately 120 nm, with a TS / λ = 2.53 setting, was observed using a cross-sectional SEM image. Figures 3A to 3C show cross-sectional SEM images of a step structure simulating a non-volatile switching element 100 fabricated under the above conditions.
[0032] Figure 3A is a cross-sectional SEM image of the left side of the wafer. On the left side of the wafer, the film thickness is approximately 4% thicker on the right side of the step bottom, i.e., the portion closer to the center of the wafer, than on the left side of the step bottom, i.e., the portion closer to the outer edge of the wafer. Figure 3B is a cross-sectional SEM image of the center of the wafer. In the center of the wafer, the buffer film thickness on the left and right sides of the step bottom was the same. Figure 3C is a cross-sectional SEM image of the right side of the wafer. On the right side of the wafer, it can be seen that the film thickness is approximately 4% thicker on the left side of the step bottom, i.e., the portion closer to the center of the wafer, than on the left side of the step bottom, i.e., the portion closer to the outer edge of the wafer.
[0033] Figure 3D shows the film thickness distribution of the buffer layer material deposited on a flat wafer under the conditions of the embodiment described above. When deposited on a flat surface, the center of the wafer is thicker, with a film thickness distribution of 9.63%. Table 1 shows the thickness of the buffer layer deposited at the bottom of the concave pattern, with the film thickness on the flat surface set to 100. The film thickness measurement points at the bottom of the concave stepped pattern correspond to the locations indicated by arrows in Figures 3A to 3C, respectively. On the flat surface, a film thickness distribution of 9.63% occurred as shown in Figure 3D, but at the bottom of the stepped pattern, a buffer layer of almost the same thickness was deposited regardless of its location on the wafer.
[0034] [Table 1]
[0035] In the manufacturing method of non-volatile switching elements shown in Table 1, the buffer layer material metal is, for example, when the Ar pressure (p) during film formation is 2.1E -2 The film was deposited at Pa with a target-substrate distance (TS) of 250 mm. Assuming the van der Waals radius r of argon is 0.188 nm, the mean free path λ of argon at T=300 K can be calculated from equation (1) as 313.9 mm, and TS / λ is 0.80.
[0036] Using the conventional technology condition of TS / λ = 0.80, a buffer layer metal material was deposited on a 300 mm wafer using a 164 mm target. Figures 4A to 4C show cross-sectional SEM images of a stepped structure simulating a conventional non-volatile switching element fabricated under the above conditions.
[0037] Figure 4D shows the film thickness distribution of a buffer layer material deposited on a flat wafer under the conditions of the prior art. When deposited on a flat surface, the film thickness distribution is 3.36%, which is superior to the uniformity of the manufacturing method of this embodiment. However, under these conventional conditions, when a buffer layer is formed on a concave step pattern with an opening size of approximately 120 nm and a height of approximately 120 nm, the film thickness of the buffer material deposited at the bottom of the step becomes uneven.
[0038] Figure 4B is a cross-sectional SEM image of the center of the wafer. In the center of the wafer, the buffer film thickness on the left and right sides of the step bottom was the same. Figure 4A is a cross-sectional SEM image of the center of the wafer. On the left side of the wafer, the deposited film thickness on the right side of the step bottom, i.e., the part closer to the center of the wafer, was approximately 60% thicker than on the left side, i.e., the part closer to the outer edge of the wafer. Figure 4C is a cross-sectional SEM image of the right side of the wafer. Furthermore, on the right side of the wafer, it can be seen that the deposition on the left side of the step bottom, i.e., the part closer to the center of the wafer, was approximately 43% thicker than on the left side, i.e., the part closer to the outer edge of the wafer.
[0039] The buffer layer deposition conditions of the conventional technology, fabricated under the conditions described above, show excellent uniformity with a film thickness distribution of 3.36% on flat surfaces, but at the bottom of steps, there is a significant bias in the deposition thickness depending on the location. The thickness of the buffer layer deposited at the bottom of the concave pattern, when the film thickness on a flat surface using the conventional technology is set to 100, is summarized in Table 1, as in this embodiment. The film thickness measurement points at the bottom of the concave pattern correspond to the locations indicated by the arrows in Figures 4A to 4C. As shown in Table 1, it can be seen that in this embodiment, almost the same deposition film thickness is obtained regardless of the location on the wafer or at the bottom of the step. In contrast, it can be seen that in the conventional technology, the deposition film thickness changes significantly depending on the location on the wafer and at the bottom of the step.
[0040] The unevenness in deposition thickness at the bottom of the step can be explained as follows. Figures 5A and 5B illustrate the deposition of the buffer layer. As shown in Figure 5A, a target 201 with a smaller diameter than the substrate 202 is positioned offset at a certain angle from the substrate 202, and concave step patterns 203, 204, and 205 are positioned on the substrate 202.
[0041] When highly directional material particles are incident at an oblique angle from target 201, the right-side wall of each pattern acts as an obstruction, causing the material particles to accumulate in the left-side region 206 in the central step pattern 204 and in the left-side region 207 in the right-side step pattern 205. In the left-side step pattern 203, which is outside the beam of material particles from target 201, almost no material particles accumulate.
[0042] The substrate 202 is rotating, and at a certain time, it takes on the configuration shown in Figure 5B. When it is in the configuration shown in Figure 5B, material particles accumulate in the left region 208 of the central step pattern 204, and in the left region 209 of the right step pattern 203. In the left step pattern 205, it is outside the beam of material particles from the target 201, and almost no material particles accumulate there.
[0043] When the process shown in Figures 5A and 5B is repeated, material particles are deposited evenly on both sides of the bottom of the concave step pattern 204 in the center of the substrate, but in the concave step patterns 204 located on the outside, material particles are preferentially deposited on the bottom of the step on the side closer to the center of the substrate. As a result, an unevenness in the deposited film thickness is observed by SEM. It is obvious that this unevenness in the deposited film thickness increases from the center of the substrate outwards.
[0044] An example of a method for depositing buffer layer 105 is shown. First, a buffer material metal is deposited at a thickness of 0.5 nm, and then, for example, a mixed gas of oxygen and argon is introduced into the chamber and oxidized. Suitable buffer material metals include titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), and hafnium (Hf).
[0045] In film deposition with a thickness of 0.5 nm, 1 to 2 atomic layers of metallic material are deposited. Therefore, even with a natural oxidation method with weak oxidizing power, an oxide with sufficiently strong oxygen bonding can be obtained. The metal film deposition process and the oxidation process may then be repeated until the buffer layer 105 reaches the desired thickness.
[0046] For buffer films of non-volatile switching elements, a suitable total thickness of the metal film is in the range of 0.5 nm to 5 nm. More typically, the characteristics of the non-volatile switching element are superior when the total thickness of the metal film is in the range of 1.0 nm to 2.0 nm. Furthermore, a suitable thickness for a single metal film deposition is 0.25 nm to 1 nm. This corresponds to a film thickness of 1 to 3 atomic layers.
[0047] By considering the main constituent elements of the buffer layer, the deposition conditions, and the oxidation method and conditions, it is possible to determine the appropriate thickness of the metallic material to be applied to the buffer layer 105. When using strong oxidizing methods such as plasma oxidation or thermal oxidation, it is possible to continuously deposit buffer material metals with a thickness of 1 nm or more. Furthermore, an oxide buffer layer may be directly deposited using reactive sputtering. When depositing oxides, it is desirable to deposit a thickness approximately twice that of the buffer material metal. In addition to the conventional DC sputtering method, RF sputtering and pulsed DC sputtering may also be used as deposition methods.
[0048] In the manufacturing of the non-volatile switching element 100, after depositing the buffer layer 105, a solid electrolyte layer 106 is deposited on top of the buffer layer 105. The material for the solid electrolyte layer 106 can be oxides, sulfides, or organic materials. For example, oxides containing aluminum (Al), titanium (Ti), tantalum (Ta), silicon (Si), hafnium (Hf), Zr, etc., chalcogenide compounds containing Ge, As, Te, S, etc., or organic polymer films containing carbon, oxygen, and silicon can be used. After depositing the solid electrolyte layer 106, as shown in Figure 2C, a first upper electrode 107 and a second upper electrode 108 are sequentially deposited on top of the solid electrolyte layer 106. The first upper electrode 107 in contact with the solid electrolyte layer 106 may be made of noble metals such as ruthenium (Ru) or platinum (Pt), or a material mainly composed of these, with Ta, Ti, W, etc. also included. Furthermore, the second upper electrode 107 may be made of Ta or the like. The buffer layer 105, solid electrolyte layer 106, first upper electrode 107, and second upper electrode 108 are processed into a desired shape, for example, as shown in Figure 1, using a so-called semiconductor process. In addition, the non-volatile switching element 100 is embedded in the interlayer insulating film and electrically connected to the upper wiring via vias or the like.
[0049] The manufacturing process for the non-volatile switching element 100 formed as shown in Figure 1 further includes the steps of depositing a protective insulating layer, laminating at least one insulating layer on top of the protective insulating layer, embedding wiring and vias inside the insulating layer, and covering the top surface with a barrier insulating layer. For such steps, the processes disclosed in, for example, International Publication No. 2017 / 170149, International Publication No. 2018 / 123678, International Publication No. 2020 / 145253, etc., can be used.
[0050] In the manufacturing method of the non-volatile switching element according to this embodiment, TS / λ is set to a larger value, and the material particles are scattered by argon to create a distribution in the incident direction (angle) of the material beam. As a result, the unevenness of the deposited film thickness at the bottom of the concave step pattern can be reduced. To accurately depict the movement of material particles in the concave step pattern, it is desirable to know the dispersion of the incident angle (direction) of the material beam scattered by argon accurately. However, for use as an indicator in comparison with experiments, it is quite practical to use TS / λ, which is the ratio of the mean free path of argon (λ) to the distance between the target and the substrate, as it is easier to calculate.
[0051] Using TS / λ as an indicator, we investigated the deposition film thickness at the bottom of a concave step pattern and confirmed that setting TS / λ between 2 and 3.5 sufficiently reduced the unevenness of the deposition film thickness. As shown in Table 2, particularly excellent results were obtained when TS / λ was in the range of 2.4 to 2.7. It was found that when TS / λ exceeds 3.5, the buffer material grows like an overhang at the top of the step, narrowing the opening, which reduces the deposition film thickness at the bottom of the step and makes it unsuitable for the manufacture of non-volatile switching elements.
[0052] [Table 2]
[0053] The data retention performance of a non-volatile switching element manufactured by the manufacturing method of this embodiment was compared with that of a non-volatile switching element manufactured using the conventional technology. Figure 6A shows the results of measuring the bake time dependence of the relative data failure rate when the data "1" was written to a large number of non-volatile switching elements and baked at 150°C. According to this embodiment, the data retention failure rate was about half that of elements manufactured using the conventional technology.
[0054] Figure 6B shows the results of measuring the relative data retention failure rate and occurrence probability per chip when data "1" is written to multiple chips equipped with many non-volatile switching elements and baked at 260°C for 1 hour. The non-volatile switching elements manufactured by the manufacturing method of non-volatile switching elements according to this embodiment have a lower data retention failure rate per chip than conventional technology. Furthermore, it was shown that the chip yield of non-volatile switching elements manufactured by the manufacturing method of non-volatile switching elements according to this embodiment improves when a certain data retention failure rate is set as the threshold for good chips.
[0055] (modified version) Although the above embodiment shows an example of a non-volatile switching element having only one lower electrode, the non-volatile switching elements of the present disclosure are not limited to this example. Two lower electrodes may be exposed by an opening, and a buffer layer may be sputter-deposited thereon. Figure 7 shows a cross-sectional example of a non-volatile switching element according to a modified embodiment of the present disclosure. As shown in Figure 7, the non-volatile switching element 10 may have two lower electrodes 103 embedded in the first interlayer insulating film 101.
[0056] While embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to these examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical idea set forth in the claims, and these modifications or alterations are also understood to fall within the technical scope of the present disclosure.
[0057] Furthermore, the effects described in the above embodiments are descriptive or illustrative, and are not limited to those described in the above embodiments. In other words, the technology relating to this disclosure may produce other effects that would be obvious to a person of ordinary skill in the art of this disclosure from the descriptions in the above embodiments, in addition to or in lieu of the effects described in the above embodiments. [Explanation of Symbols]
[0058] 100 Non-volatile switching elements 101 First interlayer insulating film 102 Second Interlayer Insulating Film 103 Lower electrode 104 Barrier Metal 105 Buffer Layer 106 Solid electrolyte layer 107 1st upper electrode 108 2nd upper electrode 109 Opening 110 circuit boards
Claims
1. A step of forming a first interlayer insulating film on a substrate, A step of embedding the lower electrode in the first interlayer insulating film, A step of forming a second interlayer insulating film on the first interlayer insulating film, A step of forming an opening in the first interlayer insulating film and the second interlayer insulating film in which a part of the lower electrode is exposed, A step of sputtering a buffer layer onto the aforementioned opening, The step of forming a solid electrolyte layer on the buffer layer, The steps include forming an upper electrode on the solid electrolyte layer, It has, In the process of sputtering a buffer layer into the aforementioned opening, the ratio of the mean free path of argon at the argon pressure during film formation to the distance between the cathode and the aforementioned opening is set to between 2 and 3.5 when sputtering is performed. The shape of the film-forming surface on which the buffer layer is formed is a concave pattern in which the aspect ratio, which is the ratio of the thickness of the second interlayer insulating film to the width of the exposed surface of the lower electrode, is 0.4 to 1, in terms of the coverage of the buffer layer material of the buffer layer. A method for manufacturing non-volatile switching elements.
2. The shape of the film-forming surface on which the buffer layer is formed is, One or more copper electrodes or copper wiring are partially exposed on the bottom surface of the opening. The height of the side wall of the aforementioned opening is 10 to 30 nm. The diameter of the aforementioned opening is 200 nm or less. The method for manufacturing a non-volatile switching element according to claim 1, wherein the size of the portion in which the copper electrode or copper wiring is partially exposed is 20 to 50 nm.
3. The diameter of the sputtering target for the buffer layer is 60% or less of the diameter of the substrate on which the film is to be deposited. A method for manufacturing a non-volatile switching element according to claim 1, wherein the buffer layer is formed using a sputtering apparatus in which the respective central axes are offset.