CMOS inverter manufacturing method
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KOREA ADVANCED INST OF SCI & TECH
- Filing Date
- 2024-12-17
- Publication Date
- 2026-08-05
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Abstract
Description
Technical Field
[0001] The present invention relates to a CMOS inverter and a method for manufacturing the same, and more particularly, to a CMOS inverter including a complementary metal-oxide-semiconductor (CMOS) transistor having a vertical channel structure and a method for manufacturing the same.
Background Art
[0002] A CMOS inverter is a core component of modern electronic devices and is responsible for inverting the logical state of a signal using two complementary transistors (NMOS and PMOS). CMOS inverters are essential components for various digital circuits. With the development of semiconductor devices, various technologies for miniaturization and high integration of CMOS inverters have been proposed.
[0003] However, the miniaturization of planar transistors faces limitations. Furthermore, the short-channel effect may occur as a side effect of excessive miniaturization. Therefore, there is a need to develop a technology for realizing a CMOS inverter capable of achieving miniaturization and high integration.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The present invention is for solving the above-described conventional problems, and an object thereof is to provide a CMOS inverter and a method for manufacturing the same, which can achieve high integration by applying a structure in which two transistors (NMOS and PMOS) stand upright in the vertical direction.
[0005] Another object of the present invention is to provide a CMOS inverter and a method for manufacturing the same, which can achieve miniaturization by sharing one gate electrode between two transistors (NMOS and PMOS).
Means for Solving the Problems
[0006] A CMOS inverter according to one embodiment of the present invention may include a base substrate, a p-type semiconductor layer, an n-type semiconductor layer, and a first gate electrode.
[0007] The base substrate is parallel to the plane defined by the first direction and the second direction intersecting the first direction.
[0008] The p-type semiconductor layer may be disposed on a base substrate. The p-type semiconductor layer may include a first hole doping region, a second hole doping region, and a first channel region.
[0009] The n-type semiconductor layer may be placed on a base substrate. The n-type semiconductor layer is separated from the p-type semiconductor layer. The n-type semiconductor layer may include a first electron doping region, a second electron doping region, and a second channel region.
[0010] The first gate electrode may be located on a base substrate. The first gate electrode may have a shape that surrounds the first channel region and the second channel region.
[0011] The first hole doping region may be positioned adjacent to the base substrate.
[0012] The first channel region may be positioned adjacent to the first hole doping region in a third direction orthogonal to the first and second directions.
[0013] The second hole doping region may be positioned adjacent to the first channel region in a third direction.
[0014] The first electron doping region may be positioned adjacent to the base substrate.
[0015] The second channel region may be arranged adjacent to the first electron doping region in a third direction.
[0016] The second electron doping region may be positioned adjacent to the second channel region in the third direction.
[0017] In one embodiment of the present invention, the CMOS inverter may further include a connecting metal. The connecting metal may contact the first hole doping region and the first electron doping region.
[0018] In one embodiment of the present invention, the CMOS inverter may further include an insulating layer, a plurality of terminals, and a plurality of connecting wirings.
[0019] The insulating layer may be disposed on the base substrate. The insulating layer may cover the p-type semiconductor layer, the n-type semiconductor layer, the connecting metal, and the first gate electrode.
[0020] The plurality of terminals may be disposed on the insulating layer. The plurality of terminals may include a first input terminal, a power supply terminal, an output terminal, and a ground terminal.
[0021] The plurality of connecting wirings may be disposed on the base substrate. The plurality of connecting wirings may include first to fourth connecting wirings.
[0022] The first connecting wiring may contact the first input terminal and the first gate electrode.
[0023] The second connecting wiring may contact the power supply terminal and the second hole doping region.
[0024] The third connecting wiring may contact the output terminal and the connecting metal.
[0025] The fourth connecting wiring may contact the ground terminal and the second electron doping region.
[0026] In one embodiment of the present invention, the cross-sectional area of the p-type semiconductor layer may be larger than the cross-sectional area of the n-type semiconductor layer.
[0027] In one embodiment of the present invention, the CMOS inverter may further include a second gate electrode. The second gate electrode may be disposed on the base substrate. The second gate electrode may be separated from the third connecting wiring.
[0028] The third connection wiring may be disposed between the first channel region and the second channel region.
[0029] The second gate electrode may have a shape surrounding the third connection wiring.
[0030] In one embodiment of the present invention, the plurality of terminals may further include a second input terminal.
[0031] The plurality of connection wirings may further include a fifth connection wiring.
[0032] The fifth connection wiring may contact the second input terminal and the second gate electrode.
[0033] In one embodiment of the present invention, the first gate electrode may contact the second gate electrode.
[0034] In one embodiment of the present invention, the CMOS inverter may further include a connection metal. The connection metal may contact the second p-type doping region and the second n-type doping region.
[0035] In one embodiment of the present invention, the CMOS inverter may further include an insulating layer, a plurality of terminals, and a plurality of connection wirings.
[0036] The insulating layer may be disposed on the base substrate. The insulating layer may cover the p-type semiconductor layer, the n-type semiconductor layer, the connection metal, and the first gate electrode.
[0037] The plurality of terminals may be disposed on the insulating layer. The plurality of terminals may include a first input terminal, a power supply terminal, an output terminal, and a ground terminal.
[0038] The plurality of connection wirings may be disposed on the base substrate. The plurality of connection wirings may include the first to fourth connection wirings.
[0039] The first connection wiring may contact the first input terminal and the first gate electrode.
[0040] The second connection wiring may be in contact with the power terminal and the first hole doping area.
[0041] The third connection wire may be in contact with the output terminal and the connecting metal.
[0042] The fourth connection wiring may be in contact with the grounding terminal and the first electronic doping area.
[0043] A CMOS inverter manufacturing method according to one embodiment of the present invention may include a vertical semiconductor layer formation step of forming a first vertical semiconductor layer and a second vertical semiconductor layer on a base substrate; an ion doping step of doping the first vertical semiconductor layer and the second vertical semiconductor layer with ions; a gate formation step of forming a gate electrode on a base substrate; a connecting metal formation step of forming a connecting metal that contacts the first vertical semiconductor layer and the second vertical semiconductor layer on a base substrate; an insulating layer formation step of forming an insulating layer that covers the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connecting metal; and a wiring connection step of connecting the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connecting metal to each of a plurality of terminals arranged on the insulating layer.
[0044] The vertical semiconductor layer formation step may include a sacrificial vertical pillar formation step in which sacrificial vertical pillars are formed on a base substrate; a spacer formation step in which spacers are formed to cover the sides of the sacrificial vertical pillars and the top surface of the base substrate; a spacer hard mask formation step in which a part of the spacer is etched and a spacer hard mask surrounding the sides of the sacrificial vertical pillars is formed; a cutting step in which the spacer hard mask and the sacrificial vertical pillars are cut in a direction perpendicular to the base substrate; a vertical layer formation step in which a part of the base substrate and the sacrificial vertical pillars are removed and a first vertical semiconductor layer and a second vertical semiconductor layer are formed; and a spacer hard mask removal step in which the spacer hard mask is removed.
[0045] In one embodiment of the present invention, the ion doping step may include a first hole doping region formation step in which a first ion having a first energy in a direction perpendicular to the base substrate is doped to form a first hole doping region; a second hole doping region formation step in which a second ion having a second energy different from the first energy in a direction perpendicular to the base substrate is doped to form a second hole doping region; a first electron doping region formation step in which a third ion having a third energy in a direction perpendicular to the base substrate is doped to form a first electron doping region; and a second electron doping region formation step in which a fourth ion having a fourth energy different from the third energy in a direction perpendicular to the base substrate is doped to form a second electron doping region.
[0046] The first and second ions may contain boron (B).
[0047] The third and fourth ions may contain arsenic (AS) or phosphine (P).
[0048] In one embodiment of the present invention, the gate formation step may include a masking step in which the upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer are covered with a mask; a first insulating step in which an insulating layer is formed to cover the sides of the first hole doping region and the first electron doping region; a gate electrode placement step in which a gate electrode having a shape surrounding the first vertical semiconductor layer and the second vertical semiconductor layer is placed on the insulating layer; and an etching step in which the portion overlapping the gate electrode with the second hole doping region or the second electron doping region is etched.
[0049] In one embodiment of the present invention, the connecting metal formation step may include a masking removal step in which a mask covering the upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer is removed, and a connecting metal contact step in which a connecting metal that comes into contact with the first hole doping region and the first electron doping region is formed. [Brief explanation of the drawing]
[0050] [Figure 1] This is a perspective view showing an example of a CMOS inverter in one embodiment of the present invention. [Figure 2a] Figure 1 is an illustrative diagram showing a cross-section of a CMOS inverter cut along line I-I' in one embodiment of the present invention. [Figure 2b] Figure 1 is an illustrative diagram showing a cross-section of a CMOS inverter cut along line II-II' in one embodiment of the present invention. [Figure 3] Figure 1 is an illustrative diagram showing a CMOS inverter in one embodiment of the present invention. [Figure 4] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 5a] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 5b] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 6a] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 6b] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 6c] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 7a] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 7b] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 7c] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 8] This is an illustrative diagram showing a cross-section of a CMOS inverter in one embodiment of the present invention. [Figure 9] This flowchart shows an example of a CMOS inverter manufacturing method according to one embodiment of the present invention. [Figure 10] This is an illustrative diagram showing the vertical semiconductor layer formation step in a CMOS inverter manufacturing method according to one embodiment of the present invention. [Modes for carrying out the invention]
[0051] Preferred embodiments of the present invention will be described in more detail below with reference to the attached drawings. In the drawings, the proportions and dimensions of the components may be exaggerated to effectively illustrate the technical content.
[0052] Terms such as “including” are intended to indicate the presence of features, figures, stages, operations, components, parts, or combinations thereof as described in the specification, and should not be understood to preemptively exclude the possibility of the presence or addition of one or more other features, figures, stages, operations, components, parts, or combinations thereof.
[0053] Furthermore, when the term "above" is used to describe a component, it means either above or below that component, and does not necessarily mean that it is located on the upper side relative to the direction of gravity.
[0054] Furthermore, when it is stated that one component is “connected” or “joined” with another component, this may include not only cases where the component is directly connected or joined to the other component, but also cases where the component is indirectly connected or joined through the other component.
[0055] Furthermore, while terms such as "first," "second," etc., may be used to describe a particular component, these terms are merely for distinguishing it from other components, and should not limit the essence, order, or sequence of the components.
[0056] Preferred embodiments of the present invention will be described in more detail below with reference to the attached drawings. In the drawings, the proportions and dimensions of the components may be exaggerated to effectively illustrate the technical content.
[0057] Figure 1 is a perspective view showing an example of a CMOS inverter (CVT) according to one embodiment of the present invention. Figure 2a is an illustrative diagram showing a cross-section of the CMOS inverter (CVT) according to one embodiment of the present invention of Figure 1, cut along line I-I'. Figure 2b is an illustrative diagram showing a cross-section of the CMOS inverter (CVT) according to one embodiment of the present invention of Figure 1, cut along line II-II'.
[0058] Referring to Figures 1, 2a, and 2b, a CMOS inverter (CVT) according to one embodiment of the present invention may include a base substrate (BS), a p-type semiconductor layer (PSC), an n-type semiconductor layer (NSC), and a first gate electrode (GT1).
[0059] The base substrate (BS) is parallel to the plane defined by a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The base substrate (BS) may contain at least one of silicon, germanium, tensile silicon, tensile silicon germanium, or silicon carbide.
[0060] The p-type semiconductor layer (PSC) may be disposed on a base substrate (BS). The p-type semiconductor layer (PSC) may include a first hole doping region (HD1), a second hole doping region (HD2), and a first channel region (CH1). The p-type semiconductor layer (PSC) may be electrically connected to a first gate electrode (GT1) and operate as a PMOS transistor.
[0061] The first hole doping region (HD1) may be positioned adjacent to the base substrate (BS). The first hole doping region (HD1) may be defined as the drain region of the PMOS transistor.
[0062] The first channel region (CH1) may be positioned adjacent to the first hole doping region (HD1) in a third direction (DR3) that is orthogonal to the first direction (DR1) and the second direction (DR2).
[0063] The second hole doping region (HD2) may be positioned adjacent to the first channel region (CH1) in the third direction (DR3). The second hole doping region (HD2) may be defined as the source region of the PMOS transistor.
[0064] The n-type semiconductor layer (NSC) may be placed on a base substrate (BS). The n-type semiconductor layer (NSC) may be separated from the p-type semiconductor layer (PSC). The n-type semiconductor layer (NSC) may include a first electron doping region (LD1), a second electron doping region (LD2), and a second channel region (CH2). The n-type semiconductor layer (NSC) may be electrically connected to a first gate electrode (GT1) and operate as an NMOS transistor.
[0065] The first electron doping region (LD1) may be positioned adjacent to the base substrate (BS). The first electron doping region (LD1) may be defined as the drain region of the NMOS transistor.
[0066] The second channel region (CH2) may be positioned adjacent to the first electron doping region (LD1) in the third direction (DR3).
[0067] The second electron doping region (LD2) may be positioned adjacent to the second channel region (CH2) in the third direction (DR3). The second electron doping region (LD2) may be defined as the source region of the NMOS transistor.
[0068] Each of the first channel region (CH1) and the second channel region (CH2) may contain at least one of the following: silicon, silicon germanium, tensile silicon, tensile silicon germanium, insulating layer embedded silicon, silicon carbide, or group 3-5 compound semiconductors.
[0069] The first gate electrode (GT1) may be located on a base substrate (BS). The first gate electrode (GT1) may have a shape that surrounds the first channel region (CH1) and the second channel region (CH2). The first gate electrode (GT1) may be electrically connected to the first channel region (CH1) and the second channel region (CH2). The first gate electrode (GT1) may contain at least one of n-type polysilicon, p-type polysilicon, aluminum, molybdenum, chromium, palladium, platinum, nickel, titanium, tantalum, tungsten, silver, titanium nitride, or tantalum nitride.
[0070] By utilizing the present invention, the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) can be positioned vertically, enabling high integration density. The p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) may not each have a gate electrode and may share a first gate electrode (GT1). This makes it possible to reduce the area of the CMOS inverter and enable miniaturization.
[0071] A CMOS inverter (CVT) according to one embodiment of the present invention may further include a gate insulating film. The gate insulating film may be disposed on a base substrate (BS). The gate insulating film may be disposed between a first gate electrode (GT1) and a first channel region (CH1). The gate insulating film may be formed after ion doping of the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC), respectively. The gate insulating film may be disposed between a first gate electrode (GT1) and a second channel region (CH2). The gate insulating film may include at least one of an oxide film, a nitride film, an oxynitride film, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, a polymer insulating film, lanthanum-doped hafnia, or hafnium zirconium oxide, or may be formed in an air-filled state.
[0072] A CMOS inverter (CVT) according to one embodiment of the present invention may further include a connecting metal (CM). The connecting metal (CM) may be in contact with a first hole doping region (HD1) and a first electron doping region (LD1). The first hole doping region (HD1) and the first electron doping region (LD1) may be electrically connected via the connecting metal (CM).
[0073] A CMOS inverter (CVT) according to one embodiment of the present invention may further include an insulating layer (DL), a plurality of terminals (PNS), and a plurality of connection wirings (CWS).
[0074] The insulating layer (DL) may be placed on the base substrate (BS). The insulating layer (DL) may cover the p-type semiconductor layer (PSC), the n-type semiconductor layer (NSC), the connecting metal (CM), and the first gate electrode (GT1).
[0075] Multiple terminals (PNS) may be arranged on an insulating layer (DL). Multiple terminals (PNS) may include a first input terminal (VIN1), a power terminal (VDD), an output terminal (VOUT), and a ground terminal (GND).
[0076] Multiple connection lines (CWS) may be arranged on the base board (BS). Multiple connection lines (CWS) may include the first to fourth connection lines (CW1 to CW4).
[0077] The first connecting wire (CW1) may be in contact with the first input terminal (VIN1) and the first gate electrode (GT1). The first input terminal (VIN1) and the first gate electrode (GT1) may be electrically connected via the first connecting wire (CW1). The CMOS inverter (CVT) may receive an input signal via the first input terminal (VIN1).
[0078] The second connection wiring (CW2) may be in contact with the power terminal (VDD) and the second hole doping area (HD2). The power terminal (VDD) and the second hole doping area (HD2) may be electrically connected via the second connection wiring (CW2). The CMOS inverter (CVT) may receive power supply via the power terminal (VDD).
[0079] The third connecting wire (CW3) may be in contact with the output terminal (VOUT) and the connecting metal (CM). The output terminal (VOUT) and the connecting metal (CM) may be electrically connected via the third connecting wire (CW3). The CMOS inverter (CVT) may output a signal via the output terminal (VOUT).
[0080] The fourth connecting wire (CW4) may be in contact with the ground terminal (GND) and the second electronic doping area (LD2). The ground terminal (GND) and the second electronic doping area (LD2) may be electrically connected via the fourth connecting wire (CW4). The CMOS inverter (CVT) may be grounded by receiving the circuit's reference potential or 0V via the ground terminal (GND).
[0081] Figure 3 is an illustrative diagram showing the circuit diagram of a CMOS inverter (CVT) in one embodiment of the present invention shown in Figure 1.
[0082] Referring to Figure 3, a PMOS transistor connected to the power terminal (VDD) and an NMOS transistor connected to the ground terminal (GND) may be connected in series. A voltage is applied to the gate of each transistor from the first input terminal (VIN1). The CMOS inverter (CVT) of the present invention may be realized as shown in the circuit in Figure 3 and may operate as an inverter.
[0083] Figure 4 is an illustrative diagram showing a cross-sectional view of a CMOS inverter (CVT) in one embodiment of the present invention.
[0084] Referring to Figures 2a and 4, the first gate electrode (GT1) may have a shape that surrounds the first channel region (CH1) and the second channel region (CH2). As shown in Figure 2a, the first gate electrode (GT1) may have a circular shape that surrounds the first channel region (CH1) and the second channel region (CH2), and as shown in Figure 4, it may have a rectangular shape that surrounds the first channel region (CH1) and the second channel region (CH2). The shape of the first gate electrode (GT1) surrounding the first channel region (CH1) and the second channel region (CH2) is not limited to a circle or a rectangle. The first gate electrode (GT1) may have a circular, semicircular, square, rectangular, or polygonal shape.
[0085] Figures 5a and 5b are illustrative diagrams showing cross-sectional views of a CMOS inverter (CVT) in one embodiment of the present invention.
[0086] Referring to Figures 5a and 5b, the cross-sectional area of the p-type semiconductor layer (PSC) may be larger than that of the n-type semiconductor layer (NSC). The main carriers of the p-type semiconductor layer (PSC) may be holes, and the main carriers of the n-type semiconductor layer (NSC) may be electrons. Electron mobility is higher than that of holes. As a result, the cross-sectional area of the p-type semiconductor layer (PSC) may be made larger than that of the n-type semiconductor layer (NSC), and the driving currents for the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) may be made the same. By making the driving currents for the p-type semiconductor layer (PSC) and the n-type semiconductor layer (NSC) the same, improvements in power efficiency, performance, heat generation, signal integrity, and a uniform electric field distribution can be achieved.
[0087] Figures 6a, 6b, and 6c are illustrative diagrams showing cross-sectional views of a CMOS inverter (CVT) in one embodiment of the present invention.
[0088] Referring to Figures 6a, 6b, and 6c, the CMOS inverter (CVT) may further include a second gate electrode (GT2). The second gate electrode (GT2) may be located on a base substrate (BS). The second gate electrode (GT2) may be separated from a third connection line (CW3). The third connection line (CW3) may be located between a first channel region (CH1) and a second channel region (CH2). The second gate electrode (GT2) may have a shape that surrounds the third connection line (CW3).
[0089] Multiple terminals (PNS) may further include a second input terminal (VIN2). Multiple connection lines (CWS) may further include a fifth connection line (CW5). The fifth connection line (CW5) may contact the second input terminal (VIN2) and the second gate electrode (GT2). The second input terminal (VIN2) and the second gate electrode (GT2) may be electrically connected via the fifth connection line (CW5). The first gate electrode (GT1) and the second gate electrode (GT2) may operate independently. The first gate electrode (GT1) may operate as the main gate. The second gate electrode (GT2) may operate as the secondary gate. As a secondary gate, the second gate electrode (GT2) may perform additional functions such as regulating the transistor's dynamic threshold voltage.
[0090] Figures 7a, 7b, and 7c are illustrative diagrams showing cross-sectional views of a CMOS inverter in one embodiment of the present invention.
[0091] Referring to Figures 7a, 7b, and 7c, the first gate electrode (GT1) may be in contact with the second gate electrode (GT2). The first gate electrode (GT1) and the second gate electrode (GT2) may act as a single gate. By acting as a single gate in a configuration that completely encloses the channel, short-channel effects can be effectively suppressed.
[0092] Figure 8 is an illustrative diagram showing a cross-sectional view of a CMOS inverter in one embodiment of the present invention.
[0093] Referring to Figure 8, the second connection wiring (CW2) may be in contact with the power terminal (VDD) and the first hole doping region (HD1). The power terminal (VDD) and the first hole doping region (HD1) may be electrically connected via the second connection wiring (CW2). The first hole doping region (HD1) may be defined as the source region of the PMOS transistor.
[0094] The connecting metal (CM) may be in contact with the second hole doping region (HD2) and the second electron doping region (LD2). The second hole doping region (HD2) and the second electron doping region (LD2) may be electrically connected via the connecting metal (CM). The second hole doping region (HD2) may be defined as the drain region of a PMOS transistor. The second electron doping region (LD2) may be defined as the drain region of an NMOS transistor.
[0095] The fourth connection wire (CW4) may be in contact with the ground terminal (GND) and the first electron doping region (LD1). The ground terminal (GND) and the first electron doping region (LD1) may be electrically connected via the fourth connection wire (CW4). The first electron doping region (LD1) may be defined as the source region of the NMOS transistor.
[0096] Figure 8 shows the second connection wire (CW2) and the fourth connection wire (CW4) positioned outside the first gate electrode (GT1) that surrounds the first channel region (CH1) and the second channel region (CH2), respectively. However, the positions of the second connection wire (CW2) and the fourth connection wire (CW4) are not limited to this. The second connection wire (CW2) and the fourth connection wire (CW4) may be positioned between the first gate electrode (GT1) and the third connection wire (CW3). The second connection wire (CW2) and the fourth connection wire (CW4) may be positioned so as not to overlap with the first channel region (CH1) and the second channel region (CH2).
[0097] Figure 9 is a flowchart showing an example of a CMOS inverter manufacturing method (S10) in one embodiment of the present invention. Figure 10 is a diagram showing an example of the vertical semiconductor layer formation step (S100) in the CMOS inverter manufacturing method (S10) in one embodiment of the present invention.
[0098] Referring to Figures 9 and 10, the CMOS inverter (CVT) manufacturing method (S10) according to one embodiment of the present invention comprises: a vertical semiconductor layer formation step (S100) in which a first vertical semiconductor layer (VSL1) and a second vertical semiconductor layer (VSL2) are formed on a base substrate (BS); an ion doping step (S200) in which ions are doped into the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2), respectively; a gate formation step (S300) in which a gate electrode is formed on the base substrate (BS); and the first vertical semiconductor layer (VSL1 The process may include a connecting metal formation step (S400) in which a connecting metal (CM) that contacts the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the connecting metal (CM) are formed, an insulating layer formation step (S500) in which an insulating layer (DL) that covers the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the connecting metal (CM) are formed, and a wiring connection step (S600) in which each of the first vertical semiconductor layer (VSL1), the second vertical semiconductor layer (VSL2), the gate electrode, and the connecting metal (CM) is connected to each of the multiple terminals (PNS) arranged on the insulating layer (DL).
[0099] The vertical semiconductor layer formation step (S100) may include a sacrificial vertical column formation step (S101) in which a sacrificial vertical column (SVP) is formed on a base substrate (BS), a spacer formation step (S102) in which a spacer (SPC) is formed that covers the sides of the sacrificial vertical column (SVP) and the top surface of the base substrate (BS), a spacer hard mask formation step (S103) in which a part of the spacer (SPC) is etched and a spacer hard mask (SHM) surrounding the sides of the sacrificial vertical column (SVP) is formed, a cutting step (S104) in which the spacer hard mask (SHM) and the sacrificial vertical column (SVP) are cut in a direction perpendicular to the base substrate (BS), a vertical layer formation step (S105) in which a part of the base substrate (BS) and the sacrificial vertical column (SVP) are removed and a first vertical semiconductor layer (VSL1) and a second vertical semiconductor layer (VSL2) are formed, and a spacer hard mask removal step (S106) in which the spacer hard mask (SHM) is removed.
[0100] In one embodiment of the present invention, the ion doping step (S200) may include a first hole doping region formation step in which a first ion having a first energy perpendicular to the base substrate (BS) is doped to form a first hole doping region (HD1); a second hole doping region formation step in which a second ion having a second energy different from the first energy perpendicular to the base substrate (BS) is doped to form a second hole doping region (HD2); a first electron doping region formation step in which a third ion having a third energy perpendicular to the base substrate (BS) is doped to form a first electron doping region (LD1); and a second electron doping region formation step in which a fourth ion having a fourth energy different from the third energy perpendicular to the base substrate (BS) is doped to form a second electron doping region (LD2).
[0101] Ion doping may be performed using at least one of the following methods: diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat treatment. After ion doping, the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) may be oxidized to form a gate insulating film on the outermost edges of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2). The gate insulating film may include at least one of the following: oxide film, nitride film, oxynitride film, aluminum oxide, hafnium oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, polymer insulating film, lanthanum-doped hafnia, hafnium zirconium oxide, or an air-filled state.
[0102] The first and second ions may contain boron (B). The first vertical semiconductor layer (VSL1) may have P-type semiconductor properties.
[0103] The third and fourth ions may contain arsenic (AS) or phosphine (P). The second vertical semiconductor layer (VSL2) may have N-type semiconductor properties.
[0104] In one embodiment of the present invention, the gate formation step (S300) may include a masking step in which the upper surfaces of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) are covered with a mask; a first insulating step in which an insulating layer (DL) is formed to cover the sides of the first hole doping region (HD1) and the first electron doping region (LD1); a gate electrode placement step in which a gate electrode having a shape that surrounds the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) is placed on the insulating layer (DL); and an etching step in which the portion overlapping the gate electrode with the second hole doping region (HD2) or the second electron doping region (LD2) is etched.
[0105] The gate electrode may contain at least one of the following: n-type polysilicon, p-type polysilicon, aluminum, molybdenum, chromium, palladium, platinum, nickel, titanium, tantalum, tungsten, silver, titanium nitride, or tantalum nitride.
[0106] In one embodiment of the present invention, the connecting metal formation step (S400) may include a masking removal step in which a mask covering the upper surfaces of the first vertical semiconductor layer (VSL1) and the second vertical semiconductor layer (VSL2) is removed, and a connecting metal contact step in which a connecting metal (CM) that contacts the first hole doping region (HD1) and the first electron doping region (LD1) is formed.
[0107] As described above with reference to embodiments, those skilled in the art will understand that the present invention can be modified and altered in various ways without departing from the spirit and scope of the invention as described in the attached claims. Furthermore, the embodiments disclosed herein are not intended to limit the technical spirit of the invention, and all technical spirit within the attached claims and equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]
[0108] CVT: CMOS inverter BS: Base board HD1: Hole Doping Zone 1 HD2: Second Hole Doping Zone CH1: First channel region LD1: First Electron Doping Domain LD2: Second Electron Doping Area CH2: Second channel region GT1: First Gate PSC: n-type semiconductor layer NSC: n-type semiconductor layer
Claims
1. Vertical semiconductor layer formation step in which a first vertical semiconductor layer and a second vertical semiconductor layer are formed on a base substrate. An ion doping step in which ions are doped into the first vertical semiconductor layer and the second vertical semiconductor layer, In the gate formation step, a first gate electrode is formed on the base substrate. A connecting metal formation step is performed on the base substrate in which a connecting metal that contacts the first vertical semiconductor layer and the second vertical semiconductor layer is formed. An insulating layer formation step in which an insulating layer covering the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connecting metal is formed, and The process includes a wiring connection step in which each of the first vertical semiconductor layer, the second vertical semiconductor layer, the first gate electrode, and the connecting metal is connected to each of the plurality of terminals arranged on the insulating layer, The aforementioned vertical semiconductor layer formation step is, Sacrificial vertical column formation step, in which a sacrificial vertical column is formed on the base substrate, Spacer forming step in which spacers covering the side surface of the sacrificial vertical column and the upper surface of the base substrate are formed. In the spacer hard mask formation step, a portion of the spacer is etched, and a spacer hard mask surrounding the side surface of the sacrificial vertical column is formed. A cutting step in which the spacer hard mask and the sacrificial vertical column are cut in a direction perpendicular to the base substrate, A vertical layer formation step in which a part of the base substrate and the sacrificial vertical column are removed and a first vertical semiconductor layer and a second vertical semiconductor layer are formed, and Spacer hard mask removal step in which the spacer hard mask is removed. A method for manufacturing a CMOS inverter, including the above.
2. The aforementioned ion doping step is, A first hole doping region formation step is performed in which a first ion having a first energy is doped in a direction perpendicular to the base substrate to form a first hole doping region. In the second hole doping region formation step, a second ion having a second energy different from the first energy is doped in a direction perpendicular to the base substrate to form a second hole doping region. A first electron doping region formation step in which a third ion having a third energy is doped in a direction perpendicular to the base substrate to form a first electron doping region, and The process includes a second electron doping region formation step in which a fourth ion having a fourth energy different from the third energy is doped in a direction perpendicular to the base substrate to form a second electron doping region. The first ion and the second ion contain boron (B), The third and fourth ions include arsenic (AS) or phosphine (P). The method for manufacturing a CMOS inverter according to claim 1.
3. The gate formation step is, In the masking step, the upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer are covered with a mask. In the first insulation step, an insulating layer is formed that covers the sides of the first hole doping region and the first electron doping region. A gate electrode arrangement step in which a gate electrode having a shape surrounding the first vertical semiconductor layer and the second vertical semiconductor layer is arranged on the insulating layer, and Etching step in which the portion overlapping the gate electrode and the second hole doping region or the second electron doping region is etched. A method for manufacturing a CMOS inverter according to claim 2, including the method described in claim 2.
4. The aforementioned connecting metal formation step is A masking removal step in which the mask covering the upper surfaces of the first vertical semiconductor layer and the second vertical semiconductor layer is removed, and Connecting metal contact step in which a connecting metal that contacts the first hole doping region and the first electron doping region is formed. A method for manufacturing a CMOS inverter according to claim 3, including the method described in claim 3.