Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which a damage at bonding can be reduced, and a manufacturing method for the same.SOLUTION: A semiconductor device includes a semiconductor chip and a metal wire. The semiconductor chip includes a semiconductor part, an electrode provided on the semiconductor part, and a control electrode provided between the semiconductor part and the electrode. The control electrode extends in a first direction along a surface of the semiconductor part that faces the electrode. The metal wire includes a bonding part that is bonded on the electrode of the semiconductor chip and exists over the control electrode through the electrode. The bonding part is in contact with the electrode and the length thereof in the first direction is longer than the width thereof in a second direction that is orthogonal to the first direction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor device for power control, a semiconductor chip is electrically connected to an external circuit via a metal wire capable of passing a large current. However, when bonding such a metal wire to an electrode of the semiconductor chip, damage may be caused to the semiconductor chip.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device and a method for manufacturing the same that can reduce damage during bonding.

Means for Solving the Problems

[0005] A semiconductor device according to an embodiment includes a semiconductor chip and a metal wire. The semiconductor chip has a semiconductor portion, an electrode provided on the semiconductor portion, and a control electrode provided between the semiconductor portion and the electrode. The control electrode extends in a first direction along a surface of the semiconductor portion facing the electrode. The metal wire is bonded onto the electrode of the semiconductor chip and has a bonding portion located on the control electrode via the electrode. The bonding portion is in contact with the electrode, and a length in the first direction is longer than a width in a second direction orthogonal to the first direction.

Brief Description of the Drawings

[0006] [Figure 1]This is a schematic diagram showing a semiconductor chip according to an embodiment. [Figure 2] This is a schematic plan view showing a semiconductor device according to an embodiment. [Figure 3] This is a schematic cross-sectional view showing a semiconductor device according to an embodiment. [Figure 4] This is a schematic diagram showing a semiconductor device related to a comparative example. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. Identical parts in the drawings will be numbered the same, and detailed explanations of those parts will be omitted as appropriate, while different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of sizes between parts, etc., are not necessarily the same as in reality. Furthermore, even when representing the same part, the dimensions and ratios may be depicted differently in different drawings.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are mutually orthogonal and represent the X, Y, and Z directions, respectively. In some cases, the Z direction is described as upward and the opposite direction as downward.

[0009] Figures 1(a) and (b) are schematic diagrams showing a semiconductor chip 1 according to an embodiment. Figure 1(a) is a cross-sectional view of the semiconductor chip 1 along the XZ plane. Figure 1(b) is a perspective view. The semiconductor chip 1 is, for example, a MOS transistor.

[0010] As shown in Figure 1(a), the semiconductor chip 1 comprises a semiconductor portion 10, a source electrode 20, a drain electrode 30, and a gate electrode 40. The semiconductor portion 10 is, for example, silicon carbide (SiC). Alternatively, the semiconductor portion 10 may be silicon, gallium nitride (GaN), or the like.

[0011] The semiconductor portion 10 is provided between the source electrode 20 and the drain electrode 30. The source electrode 20 is provided on the surface 10F side of the semiconductor portion 10. The drain electrode 30 is provided on the back surface 10B of the semiconductor portion 10.

[0012] The gate electrode 40 is provided between the semiconductor portion 10 and the source electrode 20. The gate electrode 40 faces the semiconductor portion 10 via a gate insulating film 43. The gate electrode 40 is also electrically insulated from the source electrode 20 by an interlayer insulating film 45. The gate electrode 40 constitutes a so-called planar MOS gate structure. The gate insulating film 43 and the interlayer insulating film 45 are, for example, silicon oxide films. The gate insulating film 43 is provided between the semiconductor portion 10 and the gate electrode 40. The interlayer insulating film 45 is provided between the source electrode 20 and the gate electrode 40.

[0013] The semiconductor section 10 includes, for example, an n-type drift layer 11, a p-type body layer 13, an n-type source layer 15, a p-type contact layer 17, and an n-type drain layer 19. The n-type drift layer 11 extends between the source electrode 20 and the drain electrode 30.

[0014] The p-type body layer 13 is partially provided on the n-type drift layer 11 between the n-type drift layer 11 and the source electrode 20. The gate electrode 40 faces the n-type drift layer 11 and the p-type body layer 13 via the gate insulating film 43.

[0015] The n-type source layer 15 is partially provided on the p-type body layer 13 between the p-type body layer 13 and the source electrode 20. The n-type source layer 15 contains n-type impurities at a higher concentration than the n-type impurity concentration of the n-type drift layer 11 and is in partial contact with the gate insulating film 43. The n-type drift layer 11, the p-type body layer, and the n-type source layer 15 are exposed on the surface 10F of the semiconductor portion 10, and the gate electrode 40 faces the p-type body layer 13 between the n-type drift layer 11 and the n-type source layer 15 via the gate insulating film 43.

[0016] The p-type contact layer 17 is partially provided on the p-type body layer 13 between the p-type body layer 13 and the source electrode 20. The p-type contact layer 17 contains p-type impurities with a higher concentration than the p-type impurity concentration of the p-type body layer 13. The source electrode 20 is electrically connected to the p-type body layer 13 through the p-type contact layer 17.

[0017] The n-type drain layer 19 is provided between the n-type drift layer 11 and the drain electrode 30. The n-type drain layer 19 contains n-type impurities with a higher concentration than the n-type impurity concentration of the n-type drift layer 11. The drain electrode 30 is electrically connected to the n-type drift layer 11 through the n-type drain layer 19.

[0018] The source electrode 20 includes, for example, a first metal layer 23 and a second metal layer 25. The first metal layer 23 is provided between the semiconductor part 10 and the second metal layer 25. The second metal layer 25 is provided on the first metal layer 23.

[0019] The first metal layer 23 includes a contact part 20cp that contacts the n-type source layer 15 and the p-type contact layer 17. Also, the first metal layer 23 covers the gate electrode 40 through the interlayer insulating film 45.

[0020] The semiconductor chip 1 further includes a Schottky diode (SBD). That is, the semiconductor chip 1 has a structure in which a MOS transistor and an SBD are integrated. The SBD is provided on the surface 10F of the semiconductor part 10 at a portion where the first metal layer 23 of the source electrode 20 contacts the n-type drift layer 11.

[0021] The first metal layer 23 is Schottky-connected to the n-type drift layer 11. Also, the first metal layer 23 is ohmic-connected to the n-type source layer 15 and the p-type contact layer 17. In other words, the first metal layer 23 of the source electrode 20 contacts, for example, n-type SiC through a Schottky barrier and includes a metal that makes ohmic contact with n-type SiC and p-type SiC containing a high concentration of n-type impurities. The first metal layer 23 is, for example, aluminum or an aluminum alloy. The first metal layer 23 is formed, for example, using a vapor deposition method or a sputtering method.

[0022] The second metal layer 25 includes, for example, a material having a hardness greater than that of the material of the first metal layer 23. The second metal layer 25 includes, for example, copper (Cu), nickel (Ni), etc., which have a hardness greater than that of aluminum. The second metal layer may be, for example, a Cu layer or a Ni layer, or may have a structure in which a Ni layer and a Cu layer are laminated. The second metal layer 25 is formed, for example, on the first metal layer 23 using a plating method.

[0023] FIG. 1(b) is a perspective view showing the surface side of the semiconductor chip 1. FIG. 1(b) represents the surface excluding the source electrode 20.

[0024] As shown in FIG. 1(b), a contact trench CT and a Schottky contact portion SCP are provided on the surface side of the semiconductor portion 10. The contact trench CT and the Schottky contact portion SCP are provided by selectively removing the interlayer insulating film 45, exposing the surface 10F of the semiconductor portion 10.

[0025] The first metal layer 23 of the source electrode 20 has a contact portion 20cp that contacts the n-type source layer 15 and the p-type contact layer 17. The contact portion 20cp extends inside the contact trench CT. Also, the first metal layer 23 extends inside the Schottky contact portion SCP and is provided so as to contact the n-type drift layer 11.

[0026] The contact trench CT and Schottky contact portion SCP extend, for example, in the Y direction. The gate electrode 40 extends in the Y direction between adjacent contact trench CTs.

[0027] Figure 2 is a schematic plan view showing a semiconductor device 2 according to an embodiment. The semiconductor device 2 comprises a semiconductor chip 1 and metal wires 50. For example, multiple metal wires 50 are connected to the source electrode 20 of the semiconductor chip 1.

[0028] The metal wire 50 may, for example, contain copper (Cu) as its main component. The metal wire 50 may also contain copper alloys, aluminum (Al), aluminum alloys, silver (Ag), or gold (Au). Furthermore, the metal wire 50 may have a structure in which a copper-containing core is coated with Ag, Au, or Al.

[0029] The semiconductor chip 1 further comprises a gate pad 60. The gate pad 60 is electrically connected to the gate electrode 40 via gate wiring (not shown). The gate electrode 40 extends in the Y direction below the source electrode 20 (see Figure 1(b)). The metal wire 50 is connected to the source electrode 20, for example, using an ultrasonic bonder. In a plan view, the metal wire 50 is positioned to extend in the direction in which the gate electrode 40 extends, i.e., in the Y direction.

[0030] One end of the metal wire 50 is connected to the source electrode 20. The other end of the metal wire 50 (not shown) is connected to, for example, a source terminal (not shown) that is connected to an external circuit.

[0031] As shown in Figure 2, the metal wire 50 includes a joint 50C that is in contact with the source electrode 20. The joint 50C has a length Lcy in the Y direction and a width Wcx in the X direction. The length Lcy in the Y direction is longer than the width Wcx in the X direction.

[0032] Figure 3 is a schematic cross-sectional view showing a semiconductor device 2 according to an embodiment. Figure 3 is a partial cross-sectional view showing the joint portion 50C of the metal wire 50.

[0033] The joint 50C has thicknesses T1 and T2 in the Z direction at its two ends CE1 and CE2, which are aligned in the Y direction. The joint 50C also has a thickness T3 in the Z direction at the midpoint between the two ends CE1 and CE2. The thickness T3 at the midpoint is thinner than the thicknesses T1 and T2 at the two ends CE1 and CE2. In other words, the metal wire 50 has protrusions P1 and P2 at its two ends CE1 and CE2 of the joint 50C that project into the second metal layer 25 of the source electrode 20. These protrusions P1 and P2 are formed by ultrasonic vibrations (see Figure 4) when the metal wire 50 is connected to the second metal layer 25. That is, the stress applied by the ultrasonic vibrations concentrates at the two ends CE1 and CE2 of the joint 50C, deforming the metal wire 50 and causing the protrusions to form.

[0034] Furthermore, the second metal layer 25 is also deformed by the stress concentration caused by ultrasonic vibrations, and has protrusions UP1 and UP2 that protrude into the first metal layer 23. The protrusions UP1 and UP2 are located below the two ends CE1 and CE2 of the joint 50C. Moreover, the first metal layer 23, which is more easily deformed than the second metal layer 25, is pushed away by the protrusions UP1 and UP2. That is, the thickness of the first metal layer 23 in the Z direction becomes thinner below the two ends CE1 and CE2 of the joint 50C than the thickness below the midpoint between the two ends CE1 and CE2.

[0035] Figure 4(a) is a schematic diagram showing a semiconductor device 3 according to a comparative example. Figure 4(a) is a plan view showing the surface side of the semiconductor chip 1. Figure 4(b) is a partial cross-sectional view showing the joint portion 50C of the metal wire 50.

[0036] As shown in Figure 4(a), the metal wire 50 is positioned planarly so as to extend in the X direction relative to the source electrode 20 of the semiconductor chip 1. That is, the metal wire 50 extends perpendicular to the Y direction, which is the direction in which the gate electrode 40 extends. The metal wire 50 is connected to the source electrode 20 by so-called wedge bonding.

[0037] As shown in Figure 4(b), the metal wire 50 is pressed onto the source electrode 20 at one end by the bonding tool BT. Furthermore, the metal wire 50 is connected to the source electrode 20 by applying ultrasonic vibration to the bonding tool BT. The length of the bonding tool BT in the direction of extension of the metal wire 50 is longer than the diameter (or width) of the metal wire. Therefore, the length of the joint portion 50C in the direction of extension of the metal wire 50 is longer than the width in the direction intersecting the extension direction.

[0038] The bonding tool BT vibrates in the direction of extension of the metal wire 50, in this case the X direction, and the stress due to the ultrasonic vibration is concentrated at the two ends CE1 and CE2 aligned in the X direction of the joint 50C. As a result, protrusions P1 and P2 are formed at the two ends CE1 and CE2, projecting into the second metal layer 25 of the source electrode 20. Furthermore, the second metal layer 25 is also deformed to have protrusions UP1 and UP2 below the two ends CE1 and CE2.

[0039] The first metal layer 23 of the source electrode 20 is pushed away by the protrusions UP1 and UP2 of the second metal layer 25, and the thickness of the first metal layer 23 in the Z direction becomes thinner below the two ends CE1 and CE2 of the joint 50C. At this time, if the extending direction of the metal wire 50 intersects with the extending direction of the gate electrode 40, a stress VS from ultrasonic vibration is applied toward the corner where the upper surface and side surface of the gate electrode 40 connect. As a result, damage such as cracks may occur in the interlayer insulating film 45 covering the corner of the gate electrode 40.

[0040] In the semiconductor device 2 according to this embodiment, the metal wire 50 is arranged to extend in the same direction as the extending direction of the gate electrode 40 in a plan view (see Figure 2). This reduces the stress VS applied toward the corner of the gate electrode 40. Therefore, it is possible to suppress damage to the semiconductor chip 1 during wire bonding and improve the reliability of the semiconductor device 2.

[0041] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0042] (Note 1) A semiconductor chip comprising a semiconductor portion, an electrode provided on the semiconductor portion, and a control electrode provided between the semiconductor portion and the electrode, wherein the control electrode extends in a first direction along the surface of the semiconductor portion facing the electrode, A metal wire bonded onto the electrode of the semiconductor chip, having a joint portion located on the control electrode via the electrode and in contact with the electrode, wherein the length of the joint portion in the first direction is longer than the width in the second direction perpendicular to the first direction, A semiconductor device equipped with the following features. (Note 2) The electrode includes a first metal layer and a second metal layer. The first metal layer is provided between the semiconductor portion and the second metal layer. The second metal layer has a hardness greater than the hardness of the first metal layer. The aforementioned metal wire is bonded onto the second metal layer in the semiconductor device described in Appendix 1. (Note 3) The joint portion of the metal wire has a first end and a second end aligned in the first direction, The semiconductor device according to Appendix 1 or 2, wherein in a third direction perpendicular to the surface of the semiconductor portion, the junction has a first thickness at the first end and a second thickness at the second end, and has a third thickness at an intermediate point between the first end and the second end that is thinner than the first and second thicknesses. (Note 4) The semiconductor device according to Appendix 3, wherein the first metal layer has a fourth thickness and a fifth thickness in the third direction below the first end and below the second end at the joint of the metal wire, respectively, and a sixth thickness in the third direction below the midpoint of the joint, the sixth thickness being thicker than the fourth and fifth thicknesses. (Note 5) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 4, A manufacturing method comprising pressing the joint portion of the metal wire with a bonding tool and bringing it into contact with the electrode of the semiconductor chip, while applying ultrasonic waves to vibrate the bonding tool in a first direction. (Note 6) A method for manufacturing a semiconductor device as described in Appendix 2, The second metal layer of the electrode of the semiconductor chip is formed on the first metal layer using a plating method. A method for manufacturing the metal wire being connected to the second metal layer. [Explanation of Symbols]

[0043] 1…Semiconductor chip, 2, 3…Semiconductor device, 10…Semiconductor part, 10B…Back side, 10F…Front side, 11…n-type drift layer, 13…p-type body layer, 15…n-type source layer, 17…p-type contact layer, 19…n-type drain layer, 20…Source electrode, 20cp…Contact part, 23…First metal layer, 25…Second metal layer, 30…Drain electrode, 40…Gate electrode, 43…Gate insulating film, 45…Interlayer insulating film, 50…Metal wire, 50C…Bond, 60…Gate pad, BT…Bonding tool, CE1, CE2…End, CT…Contact trench, P1, P2, UP1, UP2…Protrusion, SBD…Schottky diode, SCP…Schottky contact part, VS…Stress

Claims

1. A semiconductor chip comprising a semiconductor portion, an electrode provided on the semiconductor portion, and a control electrode provided between the semiconductor portion and the electrode, wherein the control electrode extends in a first direction along the surface of the semiconductor portion facing the electrode, and the semiconductor chip A metal wire bonded onto the electrode of the semiconductor chip, having a joint portion located on the control electrode via the electrode and in contact with the electrode, wherein the length of the joint portion in the first direction is longer than the width in the second direction perpendicular to the first direction, Equipped with, The electrode includes a first metal layer and a second metal layer. The first metal layer is provided between the semiconductor portion and the second metal layer. The second metal layer has a hardness greater than the hardness of the first metal layer. The aforementioned metal wire is bonded onto the second metal layer. The first metal layer contains Al, The second metal layer contains Cu, and the semiconductor device.

2. A semiconductor chip having a semiconductor portion, an electrode provided on the semiconductor portion, and a control electrode provided between the semiconductor portion and the electrode, wherein the control electrode extends in a first direction along the surface of the semiconductor portion facing the electrode, A metal wire bonded onto the electrode of the semiconductor chip, having a joint portion located on the control electrode via the electrode and in contact with the electrode, wherein the length of the joint portion in the first direction is longer than the width in the second direction perpendicular to the first direction, Equipped with, The joint portion of the metal wire has a first end and a second end aligned in the first direction, A semiconductor device wherein, in a third direction perpendicular to the surface of the semiconductor portion, the junction has a first thickness at the first end and a second thickness at the second end, and has a third thickness at an intermediate point between the first end and the second end that is thinner than the first and second thicknesses.

3. The semiconductor device according to claim 2, wherein the first metal layer has a fourth thickness and a fifth thickness in the third direction below the first end and below the second end at the joint of the metal wire, respectively, and a sixth thickness in the third direction below the midpoint of the joint, the sixth thickness being thicker than the fourth and fifth thicknesses.

4. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, A manufacturing method comprising pressing the joint portion of the metal wire with a bonding tool and bringing it into contact with the electrode of the semiconductor chip, while applying ultrasonic waves to vibrate the bonding tool in a first direction.

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