Semiconductor drive devices and semiconductor modules
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2022-12-08
- Publication Date
- 2026-08-05
Smart Images
Figure 0007901010000016 
Figure 0007901010000017 
Figure 0007901010000018
Abstract
Description
[Technical Field]
[0001] Embodiments of the present invention relate to semiconductor drive devices and semiconductor modules. [Background technology]
[0002] Insulated Gate Bipolar Transistors (IGBTs) are widely used as power semiconductor devices that control high voltage and high current. For IGBTs used as switching elements, low on-voltage and low switching losses during turn-on and turn-off are desirable. One method to reduce turn-off losses while maintaining a low on-voltage is a double-gate structure, where the gate electrode is formed in two separate systems, with one gate electrode being turned off first. However, increasing the channel density reduces short-circuit withstand capability, making it difficult to reduce turn-on losses. Therefore, an IGBT has been proposed that divides the gate electrode into three systems, driving the third gate electrode only during turn-on, thereby enabling a reduction in turn-on losses. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141304 [Overview of the project] [Problems that the invention aims to solve]
[0004] The embodiments of the present invention aim to provide a semiconductor drive device and a semiconductor module that can prevent false firing of semiconductor elements. [Means for solving the problem]
[0005] According to an embodiment of the present invention, the semiconductor driving device is a semiconductor driving device for driving a first semiconductor element and a second semiconductor element, each having a collector electrode, an emitter electrode, a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode, the second gate electrode, and the third gate electrode are controlled independently of each other, and during the period from turning on to turning off the first gate electrode, the on period of the second gate electrode is shorter than the on period of the first gate electrode, and the on period of the third gate electrode is shorter than the on period of the second gate electrode, and a third turn-off gate resistor is provided, which is electrically connected to the third gate electrode of each of the first and second semiconductor elements and inserted into a third turn-off wiring that provides a potential to turn off the third gate electrode, and in each of the first and second semiconductor elements, the threshold voltage of the third gate electrode is set to Vth3, and the resistance value of the third turn-off gate resistor is set to R CGsoff The minimum value in the voltage-dependent characteristic of the capacitance between the third gate electrode and the collector electrode is min(C). CGsgc ), if we let dv / dt be the time displacement of the voltage at turn-on,
number
[0006] [Figure 1] This is a circuit diagram of a semiconductor module according to an embodiment. [Figure 2] This is a circuit diagram of a semiconductor module according to an embodiment. [Figure 3] This is a cross-sectional perspective view of the semiconductor device according to the embodiment. [Figure 4] (a) to (c) are timing charts showing an example of a control method for semiconductor elements in the embodiment. [Modes for carrying out the invention]
[0007] The embodiments will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the respective parts, the size ratios between the parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, there are cases where their dimensions and ratios are represented differently in the drawings. Also, the same or similar elements are denoted by the same reference numerals.
[0008] As shown in FIG. 1, the semiconductor module of the embodiment includes a first semiconductor element 101, a second semiconductor element 102, and a semiconductor driving device 500 that drives the first semiconductor element 101 and the second semiconductor element 102. In FIG. 1, the semiconductor driving device 500 mainly shows the parts connected to the respective gate electrodes of the first semiconductor element 101 and the second semiconductor element 102.
[0009] The first semiconductor element 101 and the second semiconductor element 102 are, for example, IGBTs and have the same configuration. In this specification, the first semiconductor element 101 and the second semiconductor element 102 may be simply referred to as the semiconductor element 100 without distinction.
[0010] Each of the first semiconductor element 101 and the second semiconductor element 102 has a collector electrode 22, an emitter electrode 21, a first gate electrode MG, a second gate electrode CGp, and a third gate electrode CGs. The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs are electrically independent of each other. <0000A first freewheeling diode 401 is connected in parallel with the first semiconductor element 101 between the voltage source 200 and the neutral point 300. The first freewheeling diode 401 has its forward direction in the direction from the neutral point 300 towards the voltage source 200. A second freewheeling diode 402 is connected in parallel with the second semiconductor element 102 between the neutral point 300 and ground. The second freewheeling diode 402 has its forward direction in the direction from ground towards the neutral point 300. The first freewheeling diode 401 and the second freewheeling diode 402 are, for example, Schottky barrier diodes.
[0013] The semiconductor drive device 500 includes a first turn-on wiring 51a that provides a potential to turn on each first gate electrode MG, a first turn-off wiring 51b that provides a potential to turn off each first gate electrode MG, a second turn-on wiring 52a that provides a potential to turn on each second gate electrode CGp, a second turn-off wiring 52b that provides a potential to turn off each second gate electrode CGp, a third turn-on wiring 53a that provides a potential to turn on each third gate electrode CGs, and a third turn-off wiring 53b that provides a potential to turn off each third gate electrode CGs.
[0014] Furthermore, the semiconductor drive device 500 includes a first turn-on gate resistor 61a electrically connected to each first gate electrode MG and inserted into each first turn-on wiring 51a, a first turn-off gate resistor 61b electrically connected to each first gate electrode MG and inserted into each first turn-off wiring 51b, a second turn-on gate resistor 62a electrically connected to each second gate electrode CGp and inserted into each second turn-on wiring 52a, a second turn-off gate resistor 62b electrically connected to each second gate electrode CGp and inserted into each second turn-off wiring 52b, a third turn-on gate resistor 63a electrically connected to each third gate electrode CGs and inserted into each third turn-on wiring 53a, and a third turn-off gate resistor 63b electrically connected to each third gate electrode CGs and inserted into each third turn-off wiring 53b. The turn-on gate resistors and turn-off gate resistors are resistive elements or wiring resistors.
[0015] Furthermore, the semiconductor driver 500 includes turn-on diodes 71a, 72a, and 73a inserted into each turn-on wiring 51a, 52a, and 53a and connected in series with each turn-on gate resistor 61a, 62a, and 63a, and turn-off diodes 71b, 72b, and 73b inserted into each turn-off wiring 51b, 52b, and 53b and connected in series with each turn-off gate resistor 61b, 62b, and 63b. The cathodes of each turn-on diode 71a, 72a, and 73a are connected to each gate electrode MG, CGp, and CGs via each turn-on gate resistor 61a, 62a, and 63a. The anodes of each turn-off diode 71b, 72b, and 73b are connected to each gate electrode MG, CGp, and CGs via each turn-off gate resistor 61b, 62b, and 63b. Each turn-on gate resistor 61a, 62a, 63a may be connected to each gate electrode MG, CGp, CGs via each turn-on diode 71a, 72a, 73a. Each turn-off gate resistor 61b, 62b, 63b may be connected to each gate electrode MG, CGp, CGs via each turn-off diode 71b, 72b, 73b. The turn-on and turn-off diodes are diode elements and their types are not limited.
[0016] Separate current paths are provided for turning on each gate electrode MG, CGp, and CGs, and for turning off each gate electrode MG, CGp, and CGs. The current path for turning on each gate electrode MG, CGp, and CGs includes turn-on wiring 51a, 52a, and 53a, turn-on gate resistors 61a, 62a, and 63a, and turn-on diodes 71a, 72a, and 73a. The current path for turning off each gate electrode MG, CGp, and CGs includes turn-off wiring 51b, 52b, and 53b, turn-off gate resistors 61b, 62b, and 63b, and turn-off diodes 71b, 72b, and 73b.
[0017] Furthermore, the semiconductor drive unit 500 includes a first photocoupler 81, a second photocoupler 82, a third photocoupler 83, and a DC-DC converter 90, as shown in Figure 2. In Figure 1, the first photocoupler 81, the second photocoupler 82, the third photocoupler 83, and the DC-DC converter 90 are omitted.
[0018] The DC-DC converter 90 outputs a high-level potential of, for example, +15V, a low-level potential of, for example, -15V, and 0V. The potential or voltage is expressed relative to the emitter potential.
[0019] The first photocoupler 81 receives the input of the first control signal and switches between a state in which the first gate electrode MG is short-circuited with the high-level potential (+15V) of the DC-DC converter 90 and a state in which the first gate electrode MG is short-circuited with the low-level potential (-15V) of the DC-DC converter 90.
[0020] The second photocoupler 82 receives the input of the second control signal and switches between a state in which the second gate electrode CGp is short-circuited to the high-level potential (+15V) of the DC-DC converter 90, and a state in which the second gate electrode CGp is short-circuited to the low-level potential (-15V) of the DC-DC converter 90.
[0021] The third photocoupler 83 receives the input of the third control signal and switches between a state in which the third gate electrodes CGs are short-circuited to the high-level potential (+15V) of the DC-DC converter 90, and a state in which the third gate electrodes CGs are short-circuited to 0V of the DC-DC converter 90.
[0022] The first control signal, the second control signal, and the third control signal are, for example, pulse signals.
[0023] Next, an example of the structure of the semiconductor element 100 (first semiconductor element 101 and second semiconductor element 102) will be explained with reference to Figure 3.
[0024] The semiconductor device 100 has, for example, a trench gate structure. The semiconductor device 100 comprises an emitter electrode 21, a collector electrode 22, a semiconductor portion 10, a first gate electrode MG, a second gate electrode CGp, a third gate electrode CGs, a first insulating film 41, a second insulating film 42, and a third insulating film 43. In Figure 3, the emitter electrode 21 is represented by a dashed line to clearly show the surface of the semiconductor portion 10 covered by the emitter electrode 21.
[0025] The emitter electrode 21 and the collector electrode 22 are located apart in the first direction Z. In Figure 3, the two directions orthogonal to the first direction Z are denoted as the second direction X and the third direction Y. The second direction X and the third direction Y are orthogonal to each other.
[0026] The semiconductor portion 10 is provided between the emitter electrode 21 and the collector electrode 22 in the first direction Z. The material of the semiconductor portion 10 is, for example, silicon. Other materials such as silicon carbide and gallium nitride can also be used as the material of the semiconductor portion 10.
[0027] The semiconductor section 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 of a second conductivity type, a third semiconductor layer 13 of a first conductivity type, and a fourth semiconductor layer 14 of a second conductivity type. In this embodiment, for example, the first conductivity type is n-type and the second conductivity type is p-type.
[0028] The semiconductor portion 10 has a plurality of mesa portions 30 that are spaced apart from each other in a second direction X. Each mesa portion 30 extends in a third direction Y. Each mesa portion 30 includes a part of the first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13.
[0029] The first semiconductor layer 11 is, for example, an n-type drift layer in an IGBT. The second semiconductor layer 12 is, for example, a p-type base layer in an IGBT. The second semiconductor layer 12 is provided between the first semiconductor layer 11 and the third semiconductor layer 13 in the first direction Z.
[0030] The third semiconductor layer 13 is, for example, an n-type emitter layer in an IGBT. The n-type impurity concentration of the third semiconductor layer 13 is higher than that of the first semiconductor layer 11. The third semiconductor layer 13 is provided between the second semiconductor layer 12 and the emitter electrode 21 in the first direction Z and is electrically connected to the emitter electrode 21.
[0031] The fourth semiconductor layer 14 is, for example, a p-type collector layer in an IGBT. The p-type impurity concentration of the fourth semiconductor layer 14 is higher than that of the second semiconductor layer 12. The fourth semiconductor layer 14 is provided between the collector electrode 22 and the first semiconductor layer 11 in the first direction Z and is electrically connected to the collector electrode 22.
[0032] The semiconductor portion 10 may further include a fifth semiconductor layer 15 of the second conductivity type and a sixth semiconductor layer 16 of the first conductivity type.
[0033] The fifth semiconductor layer 15 is, for example, a p-type base contact layer in an IGBT. The p-type impurity concentration of the fifth semiconductor layer 15 is higher than that of the second semiconductor layer 12. The fifth semiconductor layer 15 is provided between the second semiconductor layer 12 and the emitter electrode 21 and is electrically connected to the emitter electrode 21. The fifth semiconductor layer 15 is included in the mesa portion 30. For example, on the second semiconductor layer 12 of the mesa portion 30, the third semiconductor layer 13 and the fifth semiconductor layer 15 are arranged alternately in the third direction Y.
[0034] The sixth semiconductor layer 16 is, for example, an n-type buffer layer in an IGBT. The n-type impurity concentration of the sixth semiconductor layer 16 is higher than that of the first semiconductor layer 11. The sixth semiconductor layer 16 is provided between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the first direction Z.
[0035] The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs are provided between the semiconductor portion 10 and the emitter electrode 21 in the first direction Z. The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs are electrically isolated from each other. For example, polycrystalline silicon can be used as the material for the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs.
[0036] The structure shown in Figure 3 is repeated multiple times in the second direction X. That is, multiple first gate electrodes MG, multiple second gate electrodes CGp, and multiple third gate electrodes CGs are arranged apart from each other in the second direction X. The first gate electrodes MG, second gate electrodes CGp, and third gate electrodes CGs extend in the third direction Y. The multiple first gate electrodes MG, multiple second gate electrodes CGp, and multiple third gate electrodes CGs are electrically connected to gate electrodes of the same type, for example, at their ends in the third direction Y. The third gate electrodes CGs are arranged, for example, between adjacent first gate electrodes MG and second gate electrodes CGp in the second direction X.
[0037] The first insulating film 41 is provided between the first gate electrode MG and the semiconductor portion 10. In the second direction X, the first gate electrode MG is adjacent to the mesa portion 30 via the first insulating film 41. The side surface of the first gate electrode MG in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the first insulating film 41. The first insulating film 41 is also provided between the upper end of the first gate electrode MG and the emitter electrode 21.
[0038] The second insulating film 42 is provided between the second gate electrode CGp and the semiconductor portion 10. In the second direction X, the second gate electrode CGp is adjacent to the mesa portion 30 via the second insulating film 42. The side surface of the second gate electrode CGp in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the second insulating film 42. The second insulating film 42 is also provided between the upper end of the second gate electrode CGp and the emitter electrode 21.
[0039] The third insulating film 43 is provided between the third gate electrodes CGs and the semiconductor portion 10. In the second direction X, the third gate electrodes CGs are adjacent to the mesa portion 30 via the third insulating film 43. The sides of the third gate electrodes CGs in the second direction X face the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the third insulating film 43. The third insulating film 43 is also provided between the upper end of the third gate electrodes CGs and the emitter electrode 21.
[0040] The first insulating film 41, the second insulating film 42, and the third insulating film 43 are, for example, a silicon oxide film and a silicon nitride film.
[0041] The first semiconductor element 101 and the second semiconductor element 102 are alternately switched on and off by the semiconductor drive device 500. When the first semiconductor element 101 is on, the second semiconductor element 102 is off, and when the second semiconductor element 102 is on, the first semiconductor element 101 is off. In addition, a dead time is set during which both the first semiconductor element 101 and the second semiconductor element 102 are off, in order to prevent through-current from the voltage source 200 from flowing to ground through the first semiconductor element 101 and the second semiconductor element 102.
[0042] Figures 4(a) to 4(c) are timing charts showing an example of a control method for the semiconductor device 100. Figure 4(a) shows the first gate potential V applied to the first gate electrode MG. MG This represents the second gate potential V applied to the second gate electrode CGp. Figure 4(b) shows the second gate potential V. CGpThis represents the third gate potential V applied to the third gate electrode CGs. Figure 3(c) shows the third gate potential V applied to the third gate electrode CGs. CGs This represents the output signals at the first to third gate electrode connection points of the semiconductor drive device 500.
[0043] The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs are controlled independently of each other. During the period from when the first gate electrode MG is turned on until when it is turned off (from the first time point t1 to the sixth time point t6), the on period of the second gate electrode CGp (from the second time point t2 to the fifth time point t5) is shorter than the on period of the first gate electrode MG, and the on period of the third gate electrode CGs (from the third time point t3 to the fourth time point t4) is shorter than the on period of the second gate electrode CGp.
[0044] The semiconductor element 100 is switched on and off by the first gate electrode MG. That is, the semiconductor element 100 is turned on at the first time point t1 and turned off at the sixth time point t6. The second gate electrode CGp is turned off before the first gate electrode MG when the semiconductor element 100 is turned off. The third gate electrode CGs is turned on for a short time when the semiconductor element 100 is turned on.
[0045] At the first time point t1, the first gate potential V is applied to the first gate electrode MG. MG However, this voltage is set higher than the first threshold voltage of the first gate electrode MG. This induces a first channel (n-type inversion layer) in the region of the second semiconductor layer 12 facing the first gate electrode MG. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the first channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 via the sixth semiconductor layer 16. This state is called turning on the first gate electrode MG.
[0046] At the second time point t2, the second gate potential V is applied to the second gate electrode CGp. CGpHowever, this voltage is set higher than the second equilibrium voltage of the second gate electrode CGp. This induces a second channel (n-type inversion layer) in the region of the second semiconductor layer 12 facing the second gate electrode CGp. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the second channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 via the sixth semiconductor layer 16. This state is called turning on the second gate electrode CGp.
[0047] At the third time point t3, the third gate potential V is applied to the third gate electrode CGs. CGs However, this voltage is set higher than the third threshold voltage of the third gate electrode CGs. This induces a third channel (n-type inversion layer) in the region of the second semiconductor layer 12 facing the third gate electrode CGs. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 via the third semiconductor layer 13 and the third channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 via the sixth semiconductor layer 16. This state is called turning on the third gate electrode CGs.
[0048] For example, the first time point t1 and the second time point t2 are simultaneous, and the third time point t3 is later than the first time point t1 and the second time point t2. The first time point t1, the second time point t2, and the third time point t3 may be set to the same timing or to different timings. When the semiconductor element 100 is turned on, the amount of electrons injected into the first semiconductor layer 11 can be increased in a short time by turning on the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs, thereby reducing turn-on losses. By setting the third time point t3 later than the first time point t1 and the second time point t2, the turn-on time difference due to the off-potential difference between the first gate electrode MG and the second gate electrode CGp and the third gate electrode CGs can be adjusted. During on periods other than when the semiconductor element 100 is turned on, the third gate electrode CGs can be turned off (the third channel can be eliminated), which allows the saturation current to be kept low and short-circuit withstand capability to be ensured.
[0049] At a fourth time point t4 after the first time point t1, the second time point t2, and the third time point t3, a third gate potential V CGs is made lower than a third threshold voltage. As a result, a third channel in a region of the second semiconductor layer 12 facing the third gate electrode CGs disappears. This state is referred to as the turn-off of the third gate electrode CGs.
[0050] At a fifth time point t5 after the fourth time point t4, a second gate potential V CGp is made lower than a second threshold voltage. As a result, a second channel in a region of the second semiconductor layer 12 facing the second gate electrode CGp disappears. This state is referred to as the turn-off of the second gate electrode CGp. By turning off the second gate electrode CGp before the first gate electrode MG, the amount of electron injection into the first semiconductor layer 11 can be restricted, and the turn-off loss can be reduced.
[0051] At a sixth time point t6 after the fifth time point t5, a first gate potential V MG is made lower than a first threshold voltage. As a result, a first channel in a region of the second semiconductor layer 12 facing the first gate electrode MG disappears. This state is referred to as the turn-off of the first gate electrode MG.
[0052] The period between the fourth time point t4 and the fifth time point t5 is longer than the period between the fifth time point t5 and the sixth time point t6.
[0053] For example, the first threshold voltage Vth1 of the first gate electrode MG, the second threshold voltage Vth2 of the second gate electrode CGp, and the third threshold voltage Vth3 of the third gate electrode CGs can be the same.
[0054] The third gate electrode CGs is controlled at two levels of potential. When the third gate potential V CGs is 0V, the third gate electrode CGs is turned off.
[0055] When a first semiconductor element, which is a high-side element, and a second semiconductor element, which is a low-side element, are switched alternately, a problem of misfiring of the semiconductor element can generally occur when the gate potential is 0V.
[0056] From the dead time when both the first semiconductor element 101 and the second semiconductor element 102 are off, at the timing when the first semiconductor element 101 turns on, the potential of the voltage source 200 (for example, 600V) is applied to the neutral point 300, and the potential change (dv / dt) of the neutral point 300 becomes steep. At this time, a current i, represented by the parasitic capacitance C between the gate electrode and collector electrode of the second semiconductor element 102 × the above (dv / dt), flows through the gate electrode of the second semiconductor element 102, and a voltage V, represented by the gate resistance R × the above current i, is applied to the gate electrode of the second semiconductor element 102. If this voltage V becomes greater than the threshold voltage of the gate electrode of the second semiconductor element 102, the second semiconductor element 102 may misfire.
[0057] Conversely, from the dead time when both the first semiconductor element 101 and the second semiconductor element 102 are off, at the timing when the second semiconductor element 102 turns on, the potential of the neutral point 300 changes sharply from the potential of the voltage source 200 (for example, 600V) to 0V. At this time, a current i, represented by the parasitic capacitance C between the gate electrode and collector electrode of the first semiconductor element 101 multiplied by the change in the potential of the neutral point 300 (dv / dt), flows through the gate electrode of the first semiconductor element 101, and a voltage V, represented by the gate resistance R multiplied by the current i, is applied to the gate electrode of the first semiconductor element 101. If this voltage V becomes greater than the threshold voltage of the gate electrode of the first semiconductor element 101, the first semiconductor element 101 may misfire.
[0058] To prevent the aforementioned false firing, it is conceivable to control the gate potential to a negative potential during the dead time period. However, controlling the gate electrode at three potential levels (e.g., +15V, 0V, -15V) increases the number of components in the drive unit, leading to increased costs. Furthermore, it would require the user to create complex control pulses, resulting in reduced usability.
[0059] Furthermore, reducing the gate resistance can be considered to prevent misfiring. However, reducing the gate resistance may cause electrons to be expelled rapidly during turn-off, and the holes remaining near the bottom of the trench gate may generate a high potential, raising concerns about avalanche formation.
[0060] The inventors have focused on the fact that in the semiconductor element 100 with the triple-gate IGBT structure described above, the turn-off characteristics of the semiconductor element 100 are governed by the falling speed of the first gate electrode MG, that is, the resistance value of the first turn-off gate resistor 61b connected to the first gate electrode MG, and that the resistance value of the third turn-off gate resistor 63b connected to the third gate electrode CGs is unrelated to the turn-off characteristics of the semiconductor element 100. If the resistance value of the first turn-off gate resistor 61b is reduced, there is a concern about avalanche as described above, but no matter how quickly the third gate electrode CGs, which do not affect the switching behavior, are brought down, that is, even if the resistance value of the third turn-off gate resistor 63b is reduced, avalanche is unlikely to occur.
[0061] Therefore, according to this embodiment, in each of the first semiconductor element 101 and the second semiconductor element 102, the current i that flows through the parasitic capacitance between the third gate electrode CGs and the collector electrode 22 of the other semiconductor element when one semiconductor element is turned on, and the resistance value R of the third turn-off gate resistor 63b of the other semiconductor element are considered. CGsoff The product of (R CGsoff The resistance value R of the third turn-off gate resistor 63b is set such that the voltage represented by ×i (the voltage applied to the third gate electrode CGs of the other semiconductor element) is less than or equal to the third threshold voltage Vth3 of the third gate electrode CGs. CGsoff Make it smaller.
[0062] Specifically, in the first semiconductor element 101 and the second semiconductor element 102, the threshold voltage of the third gate electrode CGs is set to Vth3, and the resistance value of the third turn-off gate resistor 63b is set to R CGsoffThe minimum value in the voltage-dependent characteristic of the capacitance between the third gate electrode CGs and the collector electrode 22 is min(C). CGsgc ), if the time displacement of the voltage at turn-on is dv / dt, then the system is designed to satisfy equation (1).
[0063]
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[0064] dv / dt represents the time displacement of the voltage at the neutral point 300 when one of the first semiconductor element 101 and the second semiconductor element 102 is turned on. The turn-on speed is faster when the current is small than when the current is large. Therefore, the time displacement (dv / dt) represents, for example, the peak value of (dv / dt) at a current of 1 / 10 of the rated current.
[0065] Capacitance C between the third gate electrode CGs and the collector electrode 22 CGsgc This depends on the collector voltage. min(C) CGsgc ) is a capacitance C that depends on the collector voltage. CGsgc This represents the minimum value within the rated voltage and is the capacitance value between the third gate electrode CGs and the collector electrode 22 at the rated voltage.
[0066] The resistance value R of the third turn-off gate resistor 63b is set to satisfy equation (1). CGsoff By reducing R, it is possible to prevent the false firing of the other semiconductor element at the timing when one semiconductor element turns on, after the dead time when both the first semiconductor element 101 and the second semiconductor element 102 are off. CGsoff For example, it is 100Ω or less.
[0067] R CGsoff The lower limit can be expressed, for example, by equation (7).
[0068]
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[0069] In equation (7), Vge represents the voltage between the third gate electrode CGs and the emitter electrode 21 of the semiconductor device 100. Rated current represents the rated current (peak rating in pulses) of the drive unit for the third gate electrode CGs (for example, the photocoupler 83 and DC-DC converter 90 shown in Figure 2).
[0070] Furthermore, the maximum value in the voltage-dependent characteristic of the capacitance between the third gate electrode and the collector electrode is max(C). CGsgc If we assume that, then equation (2) can be further satisfied.
[0071]
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[0072] set(C CGsgc ) is a capacitance C that depends on the collector voltage. CGsgc This represents the maximum value within the rated voltage and is the capacitance value between the third gate electrode CGs and the collector electrode 22 at 0V. R that satisfies equation (2) CGsoff For example, it is 50Ω or less.
[0073] Furthermore, equation (3) can also be satisfied.
[0074]
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[0075] R that satisfies equation (3) CGsoff For example, it is 10Ω or less.
[0076] Furthermore, in each of the first semiconductor element 101 and the second semiconductor element 102, the capacitance between the third gate electrode CGs and the collector electrode 22 is set to C CGsgc The resistance value of the first turn-off gate resistor 61b is R MGoff The capacitance between the first gate electrode MG and the collector electrode 22 is C MGgc If so, then equation (4) can be further satisfied.
[0077]
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[0078] Furthermore, in each of the first and second semiconductor devices, the first threshold voltage of the first gate electrode MG is set to Vth1, and the resistance value of the first turn-off gate resistor 61b is set to R MGoff The maximum value in the voltage-dependent characteristic of the capacitance between the first gate electrode MG and the collector electrode 22 is max(C). MGgc If we assume that, then equation (5) can be further satisfied.
[0079]
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[0080] set(C MGgc ) is the capacitance C between the first gate electrode MG and the collector electrode 22, which depends on the collector voltage. MGgc This represents the maximum value within the rated voltage and is the capacitance value between the first gate electrode MG and the collector electrode 22 at 0V.
[0081] Furthermore, equation (6) can also be satisfied.
[0082]
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[0083] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]
[0084] 21…Emitter electrode, 22…Collector electrode, 51a…First turn-on wiring, 51b…First turn-off wiring, 52a…Second turn-on wiring, 52b…Second turn-off wiring, 53a…Third turn-on wiring, 53b…Third turn-off wiring, 61a…First turn-on gate resistor, 61b…First turn-off gate resistor, 62a…Second turn-on gate resistor, 62b…Second turn-off gate resistor, 63a…Third turn-on gate resistor, 63b…Third turn-off gate resistor, 81…First photocoupler, 82…Second photocoupler, 83…Third photocoupler, 90…DC-DC converter, 100…Semiconductor element, 101…First semiconductor element, 102…Second semiconductor element, 500…Semiconductor drive circuit, MG…First gate electrode, CGp…Second gate electrode, CGs…Third gate electrode
Claims
1. A semiconductor driving device for driving a first semiconductor element and a second semiconductor element, each having a collector electrode, an emitter electrode, a first gate electrode, a second gate electrode, and a third gate electrode, respectively. The first gate electrode, the second gate electrode, and the third gate electrode are controlled independently of each other. During the period from when the first gate electrode is turned on until it is turned off, the on-period of the second gate electrode is shorter than the on-period of the first gate electrode, and the on-period of the third gate electrode is shorter than the on-period of the second gate electrode. The device comprises a third turn-off gate resistor inserted into a third turn-off wiring that is electrically connected to the third gate electrodes of the first and second semiconductor elements and provides a potential to turn off the third gate electrodes, In each of the first and second semiconductor elements, the threshold voltage of the third gate electrode is set to Vth3, and the resistance value of the third turn-off gate resistor is set to R. ＣＧｓｏｆｆ The minimum value in the voltage-dependent characteristic of the capacitance between the third gate electrode and the collector electrode is min(C). ＣＧｓｇｃ ), if we let dv / dt be the time displacement of the voltage at turn-on, [Math 1] A semiconductor drive device that satisfies the requirements.
2. The maximum value in the voltage-dependent characteristic of the capacitance between the third gate electrode and the collector electrode is max(C). ＣＧｓｇｃ ) If so, [Math 2] A semiconductor drive device according to claim 1, further satisfying the above. 【Request Item 3】 【Number 3】 The semiconductor drive device according to claim 2, further satisfying the above.
4. The first semiconductor element and the second semiconductor element are electrically connected to the first gate electrodes of each of them, and the first turn-off gate resistor is inserted into a first turn-off wiring that provides a potential to turn off the first gate electrodes, In each of the first and second semiconductor elements, the capacitance between the third gate electrode and the collector electrode is set to C. ＣＧｓｇｃ The resistance value of the first turn-off gate resistor is R MＧｏｆｆ The capacitance between the first gate electrode and the collector electrode is C MＧｇｃ Therefore, [Math 4] A semiconductor drive device according to any one of claims 1 to 3, further satisfying the above conditions.
5. The first semiconductor element and the second semiconductor element are electrically connected to the first gate electrodes of each of them, and the first turn-off gate resistor is inserted into a first turn-off wiring that provides a potential to turn off the first gate electrodes, In each of the first and second semiconductor elements, the threshold voltage of the first gate electrode is set to Vth1, and the resistance value of the first turn-off gate resistor is set to R. ＭＧｏｆｆ The maximum value in the voltage-dependent characteristic of the capacitance between the first gate electrode and the collector electrode is max(C). ＭＧｇｃ ) If so, [Math 5] The semiconductor drive device according to claim 3, further satisfying the above.
6. The first semiconductor element and the second semiconductor element are electrically connected to the first gate electrodes of each of them, and the first turn-off gate resistor is inserted into a first turn-off wiring that provides a potential to turn off the first gate electrodes, In each of the first semiconductor element and the second semiconductor element, the threshold voltage of the first gate electrode is Vth1, the resistance value of the first turn-off gate resistance is R ＭＧｏｆｆ , the maximum value in the voltage dependence characteristic of the capacitance between the first gate electrode and the collector electrode is max(C ＭＧｇｃ ), the minimum value in the voltage dependence characteristic of the capacitance between the first gate electrode and the collector electrode is min(C ＭＧｇｃ ), and the voltage between the first gate electrode and the emitter electrode is V －ＧＥ . Then, [Math 6] The semiconductor drive device according to claim 3, further satisfying the above.
7. A first semiconductor element and a second semiconductor element, each having a collector electrode, an emitter electrode, a first gate electrode, a second gate electrode, and a third gate electrode, wherein the first gate electrode, the second gate electrode, and the third gate electrode are controlled independently of each other, and during the period from when the first gate electrode is turned on until it is turned off, the on-period of the second gate electrode is shorter than the on-period of the first gate electrode, and the on-period of the third gate electrode is shorter than the on-period of the second gate electrode, A semiconductor drive device for driving the first semiconductor element and the second semiconductor element, Equipped with, The semiconductor drive device has a third turn-off gate resistor inserted into a third turn-off wiring that is electrically connected to the third gate electrodes of the first semiconductor element and the second semiconductor element, and provides a potential to turn off the third gate electrodes. In each of the first and second semiconductor elements, the threshold voltage of the third gate electrode is set to Vth3, and the resistance value of the third turn-off gate resistor is set to R. ＣＧｓｏｆｆ The minimum value in the voltage-dependent characteristic of the capacitance between the third gate electrode and the collector electrode is min(C). ＣＧｓｇｃ ), if we let dv / dt be the time displacement of the voltage at turn-on, [Math 1] A semiconductor module that satisfies the following conditions.
8. The semiconductor drive device according to claim 3, The first semiconductor element and, The aforementioned second semiconductor element, A semiconductor module equipped with the following features.