Residue removal
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2023-06-15
- Publication Date
- 2026-08-05
Smart Images
Figure 0007901049000001 
Figure 0007901049000002 
Figure 0007901049000003
Abstract
Description
Technical Field
[0001]
[0001] Embodiments generally relate to a method of removing defects from a substrate at a certain location on the semiconductor substrate. More specifically, embodiments relate to a method for selectively forming a desired material on a substrate having different materials at different locations of the substrate by a selective deposition process using local passivation deposition.
Background Art
[0002] Description of Related Art
[0002] Reliably generating features of sub-half micron or less is one of the important technical issues for next-generation very large scale integration (VLSI) and ultra-large scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed up and the dimensions are reduced in VLSI and ULSI technologies, further requirements are being imposed on the processing power. In order to succeed in VLSI and ULSI and in the continuous efforts to improve the circuit density and quality of individual substrates and dies, it is important to form reliable gate structures on the substrate.
[0003]
[0003] The geometric and dimensional limits of structures used to form semiconductor devices are in competition with technical limits, making it increasingly difficult to meet the need to accurately form structures with desired materials in order to manufacture structures with small limit dimensions and high aspect ratios, and structures with various materials. Conventional methods for selective deposition may be performed to locally form a material layer only at specific locations on a flat surface on a substrate made of a material different from the substrate material. However, because the geometric limits of structures continue to be imposed, selective deposition processes may not efficiently and exclusively form on specified small dimensions on the substrate, which can result in the formation of undesirable material at undesirable locations on the substrate. Furthermore, if the selectivity of the deposition process is not sufficiently high, some residual material is often formed at undesirable locations. Such residual material remains at undesirable locations, contaminating the device structure on the substrate, degrading the electrical performance of the device, and ultimately potentially leading to device failure.
[0004]
[0004] Therefore, there is a need for improved methods for removing residues after selective deposition processes suitable for the advanced production of semiconductor chips or other semiconductor devices. [Overview of the project]
[0005]
[0005] Embodiments of the present disclosure provide a method for removing residue from undesirable locations on a substrate in semiconductor applications. In one embodiment, the method includes performing a selective deposition process to form a metal-containing dielectric material at a first location on the substrate, and performing a residue removal process to remove residue from a second location on the substrate.
[0006]
[0006] In another embodiment, a method for removing residue from a substrate includes performing a selective deposition process to form a metal-containing dielectric material, which is a high dielectric constant material having a dielectric constant greater than 12, on a metal material on a substrate, leaving residue on the dielectric material on the substrate, and performing a residue removal process to remove the residue from the substrate.
[0007]
[0007] In yet another embodiment, a method for removing residue from a substrate includes performing a selective deposition process by atomic layer deposition to form a metal-containing dielectric material on a metal material on a substrate, leaving residue on the dielectric material on the substrate, and performing a residue removal process to remove residue having a diameter of less than 30 nm but greater than 2 nm from the substrate.
[0008]
[0008] A more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments of the disclosure shown in the accompanying drawings, so that the above-described features of the disclosure may be realized and understood in detail. [Brief explanation of the drawing]
[0009] [Figure 1] This is a schematic cross-sectional view of a processing chamber configured to perform an etching process according to one or more embodiments of the present disclosure. [Figure 2] This is a schematic cross-sectional view of a polishing system configured to perform chemical mechanical polishing (CMP) treatment. [Figure 3] This is a flowchart of a method for performing a residue removal process according to one or more embodiments of the present disclosure. [Figure 4A] Figure 3 shows a cross-sectional view of the substrate during the patterning process. [Figure 4B] Figure 3 shows a cross-sectional view of the substrate during the patterning process. [Figure 4C] Figure 3 shows a cross-sectional view of the substrate during the patterning process. [Figure 5] Figure 3 shows a cross-sectional view of the substrate during the patterning process. [Modes for carrying out the invention]
[0010]
[0014] For ease of understanding, the same reference numerals were used to indicate identical elements common to the figures where possible. It is assumed that elements and features of one embodiment can be usefully incorporated into other embodiments without further description.
[0011]
[0015] However, since this disclosure may also permit other equally valid embodiments, it should be noted that the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be considered to limit the scope of this disclosure.
[0012]
[0016] A method for removing residue from a substrate is provided. This method utilizes a chemical mechanical polishing process after a selective deposition process to remove the residue from the selective deposition process. Alternatively, this method utilizes an etching process that can selectively remove residue from undesirable locations on the substrate without damaging or removing the material formed at the desired locations. After the residue has been removed, additional chemical mechanical polishing can be optionally performed to remove any remaining residue from the substrate as needed.
[0013]
[0017] As used herein, the term “substrate” refers to a layer of material containing the surface to be cleaned, which forms the basis of subsequent processing operations. For example, a substrate may include one or more materials, including silicon-containing materials, Si, polysilicon, amorphous silicon, Ge, SiGe, GaAs, InP, InAs, GaAs, GaP, InGaAs, InGaAsP, InGaAsP, GaSb, InSb, or combinations thereof, containing Group IV or Group III-V compounds. Furthermore, a substrate may also include dielectric materials such as silicon dioxide, organosilicates, and carbon-doped silicon oxide. A substrate may also include one or more conductive metals, such as nickel, titanium, platinum, molybdenum, rhenium, osmium, chromium, iron, aluminum, copper, tungsten, or combinations thereof. Furthermore, depending on the application, a substrate may include any other materials, such as metal nitrides, metal oxides, and metal alloys. In one or more embodiments, the substrate can form a contact structure, a metallic silicon compound layer, or a gate structure including a gate dielectric layer and a gate electrode layer, thereby facilitating connection to interconnect features such as plugs, vias, contacts, lines, and wires, or other suitable structures used in semiconductor devices, which may subsequently be formed thereon.
[0014]
[0018] Furthermore, the substrate is not limited to a specific size or shape. The substrate may be a circular wafer with a diameter of 200 mm, 300 mm, 450 mm, or other diameters. The substrate may also be any polygonal, square, rectangular, curved, or non-circular workpiece, such as polygonal glass or plastic substrates used in the manufacture of flat panel displays.
[0015]
[0019] Figure 1 is a simplified cross-sectional view of an exemplary processing chamber 100 suitable for etching substrate residues within the processing chamber 100. The exemplary processing chamber 100 is suitable for performing patterning processes. One embodiment of a processing chamber 100 that may be adapted to benefit from this disclosure is the CENTRIS® Sym3® etching processing chamber, available from Applied Materials, Inc. in Santa Clara, California. Note that other processing chambers, including those available from other manufacturers, may also be adapted to carry out embodiments of this disclosure.
[0016]
[0020] The plasma processing chamber 100 includes a chamber body 105 having a defined chamber space 101 inside. The chamber body 105 has side walls 112 and a bottom 118, which are connected to ground 126. The side walls 112 have liners 115 to protect the side walls 112 and to extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limiting and generally increase in proportion to the size of the substrate 210 to be processed. Examples of substrate sizes include, among others, those with diameters of 200 mm, 250 mm, 300 mm, and 450 mm.
[0017]
[0021] The chamber body 105 supports the chamber lid assembly 110 surrounding the chamber space 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 is formed through the side wall 112 of the chamber body 105, facilitating the transfer of the substrate 210 into and out of the plasma processing chamber 100. The access port 113 may be connected to a transfer chamber and / or other chambers of a substrate processing system (not shown).
[0018]
[0022] A pumping port 145 is formed through the side wall 112 of the chamber body 105 and is connected to the chamber space 101. A pumping device (not shown) is connected to the chamber space 101 via the pumping port 145 for evacuating the interior and controlling the pressure. The pumping device may include one or more pumps and throttle valves.
[0019]
[0023] The gas panel 160 is connected to the chamber body 105 by a gas line 167 for supplying a processing gas into the chamber space 101. The gas panel 160 includes one or more processing gas sources 161, 162, 163, 164 and may additionally include an inert gas, a non-reactive gas, and a reactive gas if desired. Examples of processing gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbons-containing gases including methane (CH4), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), hydrogen bromide (HBr), argon gas (Ar), chlorine (Cl2), nitrogen (N2), and oxygen gas (O2). In addition, the processing gas may include gases containing chlorine, fluorine, oxygen and hydrogen, such as BCl3, C2F4, C4F8, C4F6, CHF3, CH²F², CH³F, NF3, CO2, SO2, CO and H2.
[0020]
[0024] The valve 166 controls the flow of the processing gas from the sources 161, 162, 163, 164 of the gas panel 160 and is managed by the controller 165. The gas flow supplied from the gas panel 160 to the chamber body 105 may include a combination of gases.
[0021]
[0025] The lid assembly 110 may include a nozzle 114. The nozzle 114 has one or more ports for introducing the processing gas from sources 161, 162, 164, and 163 of the gas panel 160 into the chamber space 101. After the processing gas is introduced into the plasma processing chamber 100, the gas is energized to form a plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 may supply power to the antenna 148 via a matching circuit 141 that inductively couples energy (such as RF energy) to the processing gas, thereby maintaining the plasma formed from the processing gas within the chamber space 101 of the plasma processing chamber 100. Instead of, or in addition to, the antenna power supply 142, processing electrodes below the substrate 210 and / or above the substrate 221001 may be used to capacitively couple RF power to the processing gas to maintain the plasma within the chamber space 101. The operation of the power supply 142 may be controlled by a controller (e.g., controller 165) that also controls the operation of other components within the plasma processing chamber 100.
[0022]
[0026] The substrate support pedestal 135 is disposed within the chamber space 101 and supports the substrate 210 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 301 during processing. The electrostatic chuck (ESC) 122 utilizes electrostatic attraction to hold the substrate 210 to the substrate support assembly 135. The ESC 122 is powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 includes electrodes 121 embedded within a dielectric. The electrodes 121 are connected to the RF power supply 125 and provide a bias that attracts plasma ions formed by the process gas within the chamber space 101 to the ESC 122 and the substrate 210 disposed thereon. The RF power supply 125 may repeat on and off and emit pulses during the processing of the substrate 210. The ESC 122 has an insulating portion 128 to make it difficult for plasma to be attracted to the sidewalls of the ESC 122 in order to extend the maintenance life of the ESC 122. In addition, the substrate support pedestal 135 may have a cathode liner 136 that protects the sidewalls of the substrate support pedestal 135 from the plasma gas and extends the maintenance interval of the plasma processing chamber 100.
[0023]
[0027] Further, the electrodes 121 are connected to a power supply 150. The power supply 150 supplies a chucking voltage of about 200 volts to about 2000 volts to the electrodes 121. The power supply 150 may also include a system controller for controlling the operation of the electrodes 121 by directing a DC current for chucking and de-chucking the substrate 210 to the electrodes 121.
[0024]
[0028] The ESC 122 may include a heater disposed therein and connected to a power supply (not shown) for heating the substrate. On the other hand, the cooling base 129 supporting the ESC 122 may include a conduit for circulating a heat transfer fluid for maintaining the temperature of the ESC 122 and the substrate 210 disposed thereon. The ESC 122 is configured to operate within the temperature range required by the heat balance of the devices manufactured on the substrate 210. For example, in one embodiment, the ESC 122 may be configured to maintain the substrate 210 at a temperature from about -25°C to about 500°C.
[0025]
[0029] A cooling base 129 is provided to assist in temperature control of the substrate 210. To mitigate processing drift and time, the temperature of the substrate 210 can be kept nearly constant by the cooling base 129 while the substrate 210 is in the cleaning chamber. In one embodiment, the temperature of the substrate 210 is maintained at approximately 30°C to 120°C throughout the subsequent cleaning process.
[0026]
[0030] The covering 130 is positioned on the ESC 122 and along the periphery of the substrate support pedestal 135. The covering 130 is configured to contain etching gas in a desired portion of the exposed upper surface of the substrate 210, while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins (not shown) are selectively moved through the substrate support pedestal 135 to lift the substrate 210 above the substrate support pedestal 135 to facilitate access to the substrate 210 by a transfer robot (not shown) or other suitable transfer mechanism.
[0027]
[0031] Controller 165 is available to control the processing sequence and adjust the gas flow from the gas panel 160 to the plasma processing chamber 100 and other processing parameters. When executed by the CPU, the software routines translate the CPU into a purpose-specific computer (controller) that controls the plasma processing chamber 100 so that processing is performed in accordance with this disclosure. The software routines may also be stored and / or executed by a second controller (not shown) located with the plasma processing chamber 100.
[0028]
[0032] Figure 2 is a schematic cross-sectional view of an exemplary polishing system 200. Typically, the polishing pad 205 is fixed to the platen 202 of the polishing system 200 using an adhesive, such as a pressure-sensitive adhesive, placed between the polishing pad 205 and the platen 202. A substrate carrier 208, facing the platen 202 and the polishing pad 205 mounted thereon, includes a flexible diaphragm 211 configured to apply different pressures to different areas of the substrate 210, while biasing the substrate 210 to be polished against the polishing surface of the polishing pad 205. The substrate carrier 208 includes a carrier ring 209 surrounding the substrate 210. During polishing, a downward force on the carrier ring 209 presses the carrier ring 209 against the polishing pad 205, thereby preventing the substrate 210 from slipping away from the substrate carrier 208. The substrate carrier 208 rotates around the carrier axis 214, while the flexible diaphragm 211 biases the polishing surface of the substrate 210 against the polishing surface of the polishing pad 205. The platen 202 rotates around the platen axis 204 in a direction opposite to the rotation direction of the substrate carrier 208, while the substrate carrier 208 sweeps back and forth from the central region of the platen 202 to the outer diameter of the platen 202, thereby reducing uneven wear of the polishing pad 205 to some extent. In this specification, the platen 202 and the polishing pad 205 have a surface area larger than the polished surface area of the substrate 210, however, in some polishing systems, the polishing pad 205 has a surface area smaller than the polished surface area of the substrate 210. The endpoint detection (EPD) system 230 directs light towards the substrate 210 through the platen aperture 222 and then through the optically transparent window feature 206 of the polishing pad 205 positioned above the platen aperture 222.
[0029]
[0033] During polishing, the fluid 216 is introduced to the polishing pad 205 through a fluid dispenser 218 positioned on the platen 202. Typically, the fluid 216 is a polishing fluid (containing water as part of the polishing fluid or polishing material), a polishing slurry, a cleaning fluid, or a combination thereof. In some embodiments, the fluid 216 is a polishing fluid containing chemically active components such as pH adjusters and / or oxidizing agents to enable chemi-mechanical polishing of the material surface of the substrate 210 together with the abrasive of the polishing pad 205.
[0030]
[0034] Figure 3 is a flowchart of one embodiment of method 300 for removing residue from a substrate. Method 300 begins in operation 302 by performing the formation of a wiring structure 450 on top of the substrate, as shown in Figure 4A. In one embodiment, the wiring structure 450 can be used as a back-end structure or a front-end structure for forming a semiconductor device. In the embodiment shown in Figure 4A, the wiring structure 450 may include an insulating material 402 and an adhesive material 405 and a capping layer 406 formed within an interface layer 404. Note that the wiring structure 450 may be any structure, including a front-end structure or a gate structure used to form a semiconductor device.
[0031]
[0035] In one embodiment, the substrate 401 is made of crystalline silicon (e.g., Si <100> or Si <111> Materials may include silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafer silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and the like. The substrate 401 may have various dimensions (e.g., 200 mm, 300 mm, 450 mm, or other diameters) and may be rectangular or square panels. Unless otherwise specified, the embodiments and examples described herein are performed on substrates of 200 mm, 300 mm, or 450 mm in diameter. In embodiments where an SOI structure is utilized in the substrate 401, the substrate 401 may include an embedded dielectric layer disposed on a crystalline silicon substrate. In embodiments described herein, the substrate 401 may be a crystalline silicon substrate. Moreover, the substrate 401 is not limited to a specific size or shape. The substrate 401 may be a circular substrate having a diameter of 200 mm, 300 mm, or other diameters, particularly 450 mm. The substrate 401 may also be any polygonal, square, rectangular, curved, or non-circular workpiece, such as polygonal glass substrates used in the manufacture of flat panel displays.
[0032]
[0036] The embodiment shown in Figure 4A illustrates that the wiring structure 450 is formed on the substrate 401, but it should be noted that, if necessary, further structures may be formed between the wiring structure 450 and the substrate 401. In one embodiment, a front-end structure such as a gate structure and / or a contact structure may be formed between the wiring structure 450 and the substrate 401 to enable the function of the semiconductor device.
[0033]
[0037] In one embodiment, the insulating material 402 included in the wiring structure 450 may be a low dielectric constant material such as a silicon oxide material, a silicon-containing material, a doped silicon material, or a carbon-containing material. Suitable carbon-containing materials include amorphous carbon, SiC, SiOC, a doped carbon material, or any suitable material. Suitable examples of low dielectric constant insulating dielectric materials include SiO-containing materials, SiN-containing materials, SiOC-containing materials, SiC-containing materials, SiOCN-containing materials, carbon-based materials, or other suitable materials. In one embodiment, the insulating material 402 is a SiN layer.
[0034]
[0038] The insulating material 402 may be formed as needed by plasma chemical vapor deposition (CVD), fluid chemical vapor deposition (CVD), high-density plasma (HDP) chemical vapor deposition (CVD), atomic layer deposition (ALD), periodic layer deposition (CLD), physical vapor deposition (PVD), etc.
[0035]
[0039] The interface layer 404 is placed on an insulating material 402 adjacent to the capping layer 406, with the adhesive 405 surrounding the cap layer 406. The interface layer 404 is also an insulating material, such as a dielectric material such as a silicon-containing material. Preferred examples of the interface layer 404 include SiN, SiON, SiO2, SiOC, SiOCN, SiCN, and the like. In one embodiment, the interface layer 404 is an SiON layer.
[0036]
[0040] The adhesive 405 extending perpendicularly within the insulating material 402 to the interface layer 404 can be formed from a metal-containing material such as TiN, TaN, or WN. The capping layer 406 is a metallic material such as tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), aluminum (Al), hafnium (Hf), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum (Pt), alloys thereof, and combinations thereof. In a particular embodiment, the capping layer 406 is a ruthenium (Ru), cobalt (Co), or tungsten (W) layer. In one specific embodiment, the capping layer 406 is a ruthenium (Ru) layer.
[0037]
[0041] The capping layer 406 and the interface layer 404 are exposed and ready to receive another material formed on top of them.
[0038]
[0042] In operation 304, a selective deposition process is performed on the substrate 401. The selective deposition process in operation 304 is performed to form a metal-containing dielectric material 407 on the capping layer 406, as shown in Figure 4B. The selective deposition process is performed to selectively form the metal-containing dielectric material 407 on the capping layer 406, as shown in Figure 4B. The selective deposition process performed is primarily to form a metal-containing dielectric material 407 with suitable film quality and properties on the material from the capping layer 406, but not on the interface layer 404 on the insulating material 402. As a result, the metal-containing dielectric material 407 is formed selectively and preferentially on the capping layer 406, rather than on the interface layer 404, or, in some cases, across the entire substrate 401, including some surfaces of the insulating material elsewhere.
[0039]
[0043] The metal-containing dielectric material 407 may be a high dielectric contact material having a dielectric constant greater than 10. Preferred examples of the metal-containing dielectric material 407 include metal dielectric materials such as hafnium-containing oxide (HfOx), AlN, WSiO2, WSi, AlON, TiN, TaN, TiON, TaON, zirconium oxide (ZrOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), iron oxide (FeOx), yttrium oxide (YOx), and aluminum oxide (AlOx). In a particular embodiment, the metal-containing dielectric material 407 is hafnium-containing oxide (HfOx) or Al2O3.
[0040]
[0044] In one embodiment, the selective deposition process may be ALD, CVD, or any suitable deposition process. In one embodiment shown herein, the selective deposition process is atomic layer deposition (ALD).
[0041]
[0045] In some examples, some residues 408 and / or residues of the metal-containing dielectric material 407 may continue to adversely affect undesirable locations, such as on the surface 409 of the interface layer 404. Such residues 408 can contaminate the substrate surface and ultimately lead to device failure. Therefore, in most situations, the metal-containing dielectric material 407 and the residues 408 are similar or the same material. In one embodiment, the residues 408 are also a high dielectric contact material having a dielectric constant greater than 10. Preferred embodiments of the metal-containing dielectric material 407 include metal dielectric materials such as hafnium oxide (HfOx), AlN, WSiO2, WSi, AlON, TiN, TaN, TiON, TaON, zirconium oxide (ZrOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), iron oxide (FeOx), yttrium oxide (YOx), and aluminum oxide (AlOx). In one particular embodiment, both the metal-containing dielectric material 407 and the residue 408 are hafnium-containing oxide (HfOx) or Al2O3.
[0042]
[0046] In the optional operation 306, as shown in Figure 4C, a CMP (Chemical Polishing) treatment can be performed to remove the residue 408 from the surface 409 of the interface layer 404. A CMP treatment as performed can remove the residue 408 from the surface 409 of the interface layer 404 without adversely affecting or excessively polishing the nearby metal-containing dielectric material 407. The residue 408 remaining on the substrate 401 has a relatively loose bonding structure to the surface 409 of the interface layer 404 compared to the bonding structure within the metal-containing dielectric material 407. Therefore, by using a relatively small polishing downforce, the residue 408 on the substrate 401 can be removed from the metal containing the dielectric material 407 without damaging or polishing the material.
[0043]
[0047] In one embodiment, the residue 408 is removed by a CMP apparatus such as the polishing system 200 shown in Figure 2. The polishing system 200 can perform chemical mechanical processing at a relatively reduced / gentle removal rate so as to prevent excessive metal removal from the metal-containing dielectric material 407 and thus selectively remove the residue 408 from the substrate 401.
[0044]
[0048] Chemical mechanical polishing can remove or polish residue 408 from the substrate 401 by using a specific fluid supplied during the polishing process, or by using deionized water. Relatively soft polishing pads, such as pads with more than 90% elasticity, can be used during chemical mechanical polishing. Since the selected polishing pad has a relatively soft surface during polishing, slurry or other chemical fluids may be removed as needed. In one embodiment, deionized water can be used during chemical mechanical polishing. Following chemical mechanical polishing, a washing process is performed as needed to increase the cleanliness of the substrate surface.
[0045]
[0049] In operation 308, an etching process is performed to remove residue 408 from the substrate 401, as shown in Figure 4C, with or without the optional CMP process performed in operation 306. The etching process is performed to selectively remove residue 408 from the substrate 401 without damaging the metal-containing dielectric material 407. The etching process is performed in a processing chamber such as the processing chamber 100 in Figure 1 to preferentially and selectively remove residue 408.
[0046]
[0050] The etching process in operation 308 is carried out by supplying an etching mixture gas to the substrate 401 in the processing chamber 100 to preferentially and selectively remove the residue 408 without damaging the metal-containing dielectric material 407. In one embodiment, the etching mixture gas contains at least a halogen-containing gas. Preferred examples of halogen-containing gases include BCl3, Cl2, NF3, CF4, HCl, HBr, Br2, and combinations thereof. Inert gases such as He and Ar may also be supplied to the etching mixture gas. In some embodiments, carrier gases such as N2, O2, CO2, N2O, and NO2 may also be supplied to the etching mixture gas. In one particular embodiment, the etching mixture gas contains BCl3, Cl2, and Ar, or BCl3, NF3, and Ar.
[0047]
[0051] The different geometric configurations between the residue 408 and the metal containing the metal-containing dielectric material 407 are thought to result in different etching mechanisms and behaviors during the etching process in operation 308. Therefore, selective etching can be achieved by utilizing structures with different geometric configurations on the substrate. The different geometric configurations between the residue 408 and the metal-containing dielectric material 407 provide different etching surface areas, allowing different amounts of etching species to come into contact with the residue 408 and the metal-containing dielectric material 407, respectively. For example, the residue 408 often has a round, elliptical, circular, or irregular shape, while the metal containing the dielectric material 407 often has a longitudinal bulk structure. Figure 5 shows one embodiment of the reaction mechanism of the etching mixed gas to the residue 408 and the metal-containing dielectric material 407. The round, elliptical, and circular shapes of the residue 408 provide a larger surface area compared to the metal-containing dielectric material 407, allowing more reactive species of the etching gas mixture to react with the residue 408, expose it to the residue 408, and consequently form volatile byproducts that can be removed from the substrate surface (e.g., pumped out from the processing chamber). The larger surface area reacting with the residue 408 results in a relatively high etching / removal rate, and consequently, the residue 408 can be removed from the substrate 401 at a higher etching / removal rate than the metal-containing dielectric material 407. As a result, a selective etching process is obtained, selectively removing the residue 408 from the substrate 401 without damaging the metal-containing dielectric material 407 or excessive attacking. As shown in Figure 5, the round, elliptical, and circular shapes of the residue 408 allow the reactive etchant to move around the residue 408, as indicated by arrow 502. In contrast, the bulk structure of the metal-containing dielectric material 407 has a relatively strong bonding structure and only the upper surface 506 is exposed for reaction. Therefore, the reactants of the etching mixed gas selectively react with the dangling bonds or residues 504 (as a relatively weak bonding structure) from the upper surface 506 of the metal-containing dielectric material 407.As a result, the etching / removal rate on the upper surface 506 of the metal-containing dielectric material 407 is relatively slower than the etching / removal rate on the outer periphery of the residue 408, thus preferentially providing the desired selective etching process on the region where the residue 408 is located.
[0048]
[0052] In one example, the etching gas mixture contains BCl3, Cl2, and Ar. During etching, the BCl3 and Cl2 gases are dissociated into B* and Cl* reactive species, such as ions or radicals, for the reaction. The chlorine-reactive species (e.g., Cl*) is thought to react with the residue 408, which is also a metal-containing dielectric material from the substrate 401, without actively attacking the metal-containing dielectric material 407. In one example, the residue 408 contains a hafnium-containing oxide (HfOx), such as an HfO2 material. The chlorine-reactive species (e.g., Cl*) can react efficiently with the HfO2 material, removing the residue 408 from the substrate. In another example, the etching gas mixture contains BCl3, NF3, and Ar. The fluorine-reactive species (e.g., F*) can also react efficiently with the HfO2 material, removing the residue 408 from the substrate. Therefore, chlorine and fluorine-reactive species (e.g., Cl* and F*) are both good species that react with the HfO2 material to efficiently remove residue 408 from the substrate 401.
[0049]
[0053] In one embodiment, the residue 408 has a diameter 510 that is less than 30 nm but greater than 2 nm, such as between approximately 12 nm and 25 nm, or between approximately 9 nm and 10 nm. The metal-containing dielectric material 407 has a width 512 that is greater than 50 nm, such as between approximately 80 nm and 90 nm.
[0050]
[0054] While supplying the etching mixed gas in operation 308, several processing parameters can be controlled. In one embodiment, the RF source power may be supplied to the plasma processing chamber 100 between approximately 100 watts and approximately 3000 watts, for example, approximately 300 watts, with or without RF bias power. If RF bias power is used, the RF bias power may be controlled between approximately 1 watt and approximately 500 watts. The pressure in the processing chamber may be controlled in a pressure range greater than 2 mTorr but less than 500 mTorr, for example, between approximately 5 mTorr and approximately 200 mTorr, for example, approximately 150 mTorr. The substrate pedestal may be maintained between 0°C and 250°C, between 50°C and 100°C, for example, at 90°C.
[0051]
[0055] After the residue 408 is removed from the substrate 401, as shown in Figure 4C, a relatively clean surface is obtained after a selective deposition process to selectively form the metal-containing dielectric material 407 on the substrate 401, with relatively little residue 408 present.
[0052]
[0056] In the optional operation 310, if any residue or residual material that needs to be removed from the substrate 401 still exists after the etching process in operation 308, an additional CMP process may be performed to improve removal efficiency and performance. The CMP process performed in operation 310 is the same as the CMP process performed in operation 306.
[0053]
[0057] Thus, a method for removing residue after selective deposition is provided. This method utilizes an etching mixture gas containing at least one halogen-containing gas to remove the residue. The residue may include hafnium-containing oxides (HfOx), such as HfO2 material. The CMP treatment may be optionally performed before or after the etching treatment to enhance the residue removal performance and efficiency.
[0054]
[0058] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is defined by the following claims.
Claims
1. A method for removing residue from a substrate, A selective deposition process is performed to form a metal-containing dielectric material on a capping layer disposed on a substrate, wherein a residue remains on an interface layer disposed on the substrate adjacent to the capping layer, and A residue removal process is performed to selectively remove residues having a round, elliptical, circular, or irregular shape from the substrate. Includes, A method comprising: the capping layer comprising a metallic material; the interface layer comprising a dielectric material; the capping layer being embedded in an adhesive layer; the adhesive layer being embedded in an insulating layer disposed on the substrate; and the metal-containing dielectric material being a high dielectric constant material having a dielectric constant greater than 12.
2. The aforementioned metal-containing dielectric material is a hafnium-containing oxide (HfO ｘ ), AlN, WSiO ２ WSi, AlON, TiN, TaN, TiON, TaON, Zirconium Oxide (ZrO ｘ ), titanium oxide (TiO ｘ ), tantalum oxide (TaO ｘ ), niobium oxide (NbOx), iron oxide (FeO ｘ ), yttrium oxide (YO ｘ ) and aluminum oxide (AlO ｘ The method according to claim 1, manufactured from a material selected from the group consisting of ).
3. The method according to claim 1, wherein the residue removal treatment is an etching treatment.
4. The method according to claim 1, wherein the residue has a diameter of less than 30 nm but greater than 2 nm.
5. A method for removing residue from a substrate, A selective deposition process is performed by atomic layer deposition to form a metal-containing dielectric material on a capping layer placed on a substrate, wherein a residue remains on the interface layer placed on the substrate adjacent to the capping layer, and A residue removal process is performed to remove residue from the aforementioned substrate. Includes, A method wherein the capping layer comprises a metallic material, the interface layer comprises a dielectric material, the capping layer is embedded in an adhesive layer, the adhesive layer is embedded in an insulating layer disposed on the substrate, and the residue has a diameter of less than 30 nm but greater than 2 nm.