Nitride semiconductor equipment

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); a drift layer (12) provided above the substrate (10); an aperture structure layer (14) provided above the drift layer (12); an electron travel layer (20) and an electron supply layer (22) that are provided in that order above the aperture structure layer (14); a threshold value adjustment layer (24) and a gate electrode (26) that are provided in that order above the electron supply layer (22); a source electrode (28) at least partially provided atop the electron supply layer (22); and a drain electrode (30) provided on the substrate (10) on the side opposite the drift layer (12). The aperture structure layer (14) includes: a current-conducting section (16) that is located below the threshold value adjustment layer (24) and that includes a first impurity; and a current block section (18) provided around the current-conducting section (16). The concentration of the first impurity in the electron travel layer (20) is lower than the concentration of the first impurity in the current-conducting section (16).

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device.

Background Art

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large bandgap, have a high breakdown electric field strength, and have the feature that the saturation drift velocity of electrons is larger than that of GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors. Therefore, research and development of power transistors using nitride semiconductors, which are advantageous for increasing output power and withstand voltage, have been carried out. <从这里开始,我将按照要求对每一行进行翻译,确保准确翻译并保留所有标签和格式。]]

[0003] For example, Patent Document 1 discloses a vertical field effect transistor (FET: Field Effect Transistor) including a regrowth layer positioned to cover an opening provided in a GaN-based laminate and a gate electrode positioned on the regrowth layer along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) generated in the regrowth layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] There is room for improvement in the electrical characteristics of the above-described conventional field effect transistor.

[0006] Therefore, the present disclosure provides a nitride semiconductor device with improved electrical characteristics.

Means for Solving the Problems

[0007] A nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer of a first conductivity type provided above the substrate, a second nitride semiconductor layer provided above the first nitride semiconductor layer, an electron transport layer and an electron supply layer provided in order above the second nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type and a gate electrode provided in order above the electron supply layer, a source electrode provided at least in part on the electron supply layer, and a drain electrode provided on the substrate on the side opposite to the first nitride semiconductor layer, wherein the second nitride semiconductor layer is located below the third nitride semiconductor layer and includes a current conduction portion of the first conductivity type containing a first impurity, and a current block portion provided around the current conduction portion, the concentration of the first impurity in the electron transport layer being lower than the concentration of the first impurity in the current conduction portion. [Effects of the Invention]

[0008] According to this disclosure, nitride semiconductor devices with improved electrical properties can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view of another example of the nitride semiconductor device according to Embodiment 1. [Figure 3A] Figure 3A is a perspective view showing the current conducting section and current blocking section of the nitride semiconductor device according to Embodiment 1. [Figure 3B] Figure 3B is a perspective view of the nitride semiconductor device according to Embodiment 1. [Figure 4A] Figure 4A is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 4B] Figure 4B is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 4C] Figure 4C is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 4D] Figure 4D is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 4E] Figure 4E is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 4F] Figure 4F is a cross-sectional view showing one step in the manufacturing method of a nitride semiconductor device according to Embodiment 1. [Figure 5] Figure 5 shows the concentration distribution of impurities contained in the current block section formed through the process shown in Figure 4B. [Figure 6A] Figure 6A is a cross-sectional view showing one step in another method for manufacturing a nitride semiconductor device according to Embodiment 1. [Figure 6B] Figure 6B is a cross-sectional view showing one step in another method for manufacturing a nitride semiconductor device according to Embodiment 1. [Figure 7] Figure 7 shows the concentration distribution of impurities contained in the current-conducting section formed through the process shown in Figure 6B. [Figure 8] Figure 8 is a cross-sectional view of the nitride semiconductor device according to Embodiment 2. [Figure 9] Figure 9 is a cross-sectional view of a nitride semiconductor device according to a modified example of Embodiment 2. [Figure 10] Figure 10 is a cross-sectional view of the nitride semiconductor device according to Embodiment 3. [Figure 11] Figure 11 is a cross-sectional view of a nitride semiconductor device according to Embodiment 4. [Figure 12] Figure 12 is a cross-sectional view of a nitride semiconductor device according to a modified example 1 of Embodiment 4. [Figure 13] Figure 13 is a cross-sectional view of a nitride semiconductor device according to a modified example 2 of Embodiment 4. [Figure 14A] Figure 14A is a plan view showing a first example of the layout of the current conducting section and current blocking section of the nitride semiconductor device according to each embodiment. [Figure 14B]Figure 14B is a plan view showing the layout of the source electrode and gate electrode corresponding to the layout shown in Figure 14A. [Figure 15] Figure 15 is a plan view showing a first example of the layout of the gate electrode pad and source electrode pad of a nitride semiconductor device according to each embodiment. [Figure 16A] Figure 16A is a plan view showing a second example of the layout of the current conducting section and current blocking section of the nitride semiconductor device according to each embodiment. [Figure 16B] Figure 16B is a plan view showing the layout of the source electrode and gate electrode corresponding to the layout shown in Figure 16A. [Figure 17] Figure 17 is a plan view showing a second example of the layout of the gate electrode pad and source electrode pad of the nitride semiconductor device according to each embodiment. [Figure 18] Figure 18 is a plan view showing a modified example of the edge layout of the nitride semiconductor device shown in Figure 14A. [Figure 19] Figure 19 is a plan view showing a modified example of the edge layout of the nitride semiconductor device shown in Figure 16A. [Modes for carrying out the invention]

[0010] (Knowledge that forms the basis of this disclosure) The inventors of the present invention have found that the following problems arise with the conventional FETs described in the "Background Art" section.

[0011] In the FET disclosed in Patent Document 1, crystal defects are formed when the nitride semiconductor layer is regrown along the inner surface of the gate opening. These crystal defects appear as pits on the surface of the regrowth layer. If a gate electrode is formed on the surface of the regrowth layer where pits have formed, the gate electrode will make Schottky contact through the pits, which may cause a deterioration in the yield of the FET's forward characteristics.

[0012] In contrast, a nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer of a first conductivity type provided above the substrate, a second nitride semiconductor layer provided above the first nitride semiconductor layer, an electron transport layer and an electron supply layer provided in order above the second nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type and a gate electrode provided in order above the electron supply layer, a source electrode provided at least in part on the electron supply layer, and a drain electrode provided on the substrate on the side opposite to the first nitride semiconductor layer, wherein the second nitride semiconductor layer is located below the third nitride semiconductor layer and includes a current conduction portion of the first conductivity type containing a first impurity, and a current block portion provided around the current conduction portion, the concentration of the first impurity in the electron transport layer being lower than the concentration of the first impurity in the current conduction portion.

[0013] This allows the upper surface of the second nitride semiconductor layer to be made flat, thereby suppressing crystal defects that occur in the electron transport layer and electron supply layer formed by regrowth. As a result, pits caused by crystal defects are less likely to occur on the upper surface of the electron supply layer. Consequently, Schottky contact of the gate electrode is suppressed, which can suppress the deterioration of the yield of the FET's forward characteristics. In addition, the pinch-off characteristics of the FET are improved by lowering the impurity concentration in the electron transport layer including the channel. Thus, according to this embodiment, a nitride semiconductor device with improved electrical characteristics is realized.

[0014] Furthermore, for example, the first impurity may be Si.

[0015] This allows the current-conducting portion and the first nitride semiconductor layer to be made n-type, thereby reducing their resistance and thus lowering the on-resistance.

[0016] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include an opening that penetrates the electron supply layer and the electron transport layer and reaches the current block section, and the source electrode may be provided along the inner surface of the opening.

[0017] This allows the current block section and the source electrode to be electrically connected, thereby mitigating the electric field applied to the channel in the electron transport layer. This suppresses the occurrence of current collapse.

[0018] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include a carbon-doped fourth nitride semiconductor layer provided between the second nitride semiconductor layer and the first nitride semiconductor layer.

[0019] As a result, the carbon-doped fourth nitride semiconductor layer has high resistance, which reduces leakage current when the transistor is off and also increases its breakdown voltage.

[0020] Furthermore, for example, the fourth nitride semiconductor layer may be provided in an area that overlaps in a plan view only with respect to the current-conducting portion and the current-blocking portion.

[0021] As a result, since a fourth nitride semiconductor layer is not provided in the drain current path, it is possible to reduce the leakage current when off while suppressing the reduction in on-resistance, and also to increase the breakdown voltage of the transistor.

[0022] Furthermore, for example, the current-blocking portion may contain a second impurity different from the first impurity, and the concentration of the second impurity in the current-blocking portion may be distributed such that a peak exists in the thickness direction of the second nitride semiconductor layer, while the concentration of the first impurity in the current-conducting portion may be uniform in the thickness direction.

[0023] As a result, there is no uneven distribution of impurity concentration within the current-conducting area, thus suppressing variations in electrical resistance. Therefore, a nitride semiconductor device with less in-plane variation in on-resistance and high reliability can be realized. In addition, the current-blocking area can be formed only in the necessary region, for example, by ion implantation.

[0024] Furthermore, for example, the current-blocking portion may contain a second impurity different from the first impurity, and the concentration of the first impurity in the current-conducting portion may be distributed such that a peak exists in the thickness direction of the second nitride semiconductor layer, while the concentration of the second impurity in the current-blocking portion may be uniform in the thickness direction.

[0025] This allows current-conducting sections to be formed only in the necessary areas, for example, by ion implantation.

[0026] Furthermore, for example, the second impurity may be Mg.

[0027] This makes it possible to block the current flowing through the n-type first nitride semiconductor layer by making the current blocking section p-type.

[0028] Furthermore, for example, the electron supply layer may have a recess provided above the current conduction portion and below the third nitride semiconductor layer.

[0029] This allows for a partial increase in the thickness of the electron supply layer, thereby increasing the carrier concentration of 2DEG generated within the electron transport layer. Consequently, the channel resistance can be reduced, and the on-resistance can be lowered.

[0030] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include a current diffusion layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer, wherein the carrier concentration of the first conductivity type is higher than that of the first nitride semiconductor layer.

[0031] This allows the current to diffuse laterally, thus reducing the on-resistance.

[0032] Furthermore, for example, the interface between the current conducting portion and the current blocking portion may be perpendicular to the main surface of the substrate.

[0033] This makes the interface between the current conducting section and the current blocking section perpendicular, allowing for, for example, the precise arrangement of multiple current conducting sections.

[0034] Furthermore, for example, the current conducting portion may be surrounded by the current blocking portion in a plan view.

[0035] This reduces the area in which the gate electrode and drain electrode face each other without passing through the current block. In other words, the gate-drain facing area is reduced, which reduces the feedback capacitance of the FET.

[0036] Furthermore, for example, the nitride semiconductor device may include a plurality of current-conducting portions, and the plurality of current-conducting portions may be arranged periodically in a plan view.

[0037] This reduces the region where the gate electrode and drain electrode face each other without passing through the current block section, thereby reducing the feedback capacitance of the FET.

[0038] Furthermore, for example, the nitride semiconductor device comprises a plurality of source electrodes, the plurality of current conducting portions are periodically arranged in a plan view along a first direction and a second direction perpendicular to the first direction, each of the plurality of source electrodes has a plan view shape that extends in the second direction and is positioned between two of the current conducting portions aligned in the first direction, and the gate electrode may be continuous with respect to the plurality of source electrodes.

[0039] This allows, for example, the source electrode and the source electrode pad to be connected using lead wiring extending in a second direction. In this case, the overlap between the source electrode and the gate electrode can be reduced, thereby suppressing the occurrence of FET failure due to gate-source short circuits.

[0040] Furthermore, for example, the nitride semiconductor device may comprise a plurality of source electrodes, the plurality of current conduction portions may be arranged on each side of a plurality of virtual hexagons tiled in a plan view, the plurality of source electrodes may be located in the center of the plurality of virtual hexagons, and the gate electrodes may be continuous with the plurality of source electrodes.

[0041] This allows for a close-packed structure, which in turn allows for a sufficiently low on-resistance per unit area.

[0042] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure further comprises a gate electrode pad located above the gate electrode and electrically connected to the gate electrode, wherein the gate electrode pad may be located at the end in a third direction and in the central part in a fourth direction perpendicular to the third direction in a plan view.

[0043] As a result, in the fourth direction, the gate electrode pad is located in the center, allowing for uniform application of the gate voltage to the gate electrode in the fourth direction. Furthermore, in the third direction, the gate electrode pad is located at the edge, preventing wire crossing when connecting the gate electrode pad and source electrode pad to a mounting substrate using wire bonding.

[0044] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure further comprises a gate electrode pad located above the gate electrode and electrically connected to the gate electrode, wherein the gate electrode pad may be located in the center in a third direction and also in the center in a fourth direction perpendicular to the third direction in a plan view.

[0045] As a result, the gate electrode pad is located in the center of the plane, allowing for a uniform application of the gate voltage to the gate electrode.

[0046] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include one or more ring-shaped nitride semiconductor regions of the second conductivity type arranged to surround the current block portion in a plan view.

[0047] This allows for the mitigation of electric field concentration through a ring-shaped nitride semiconductor region (a so-called guard ring) provided at the end of the nitride semiconductor device.

[0048] Furthermore, for example, the nitride semiconductor region may contain a third impurity, and the concentration of the third impurity within the nitride semiconductor region may be distributed such that a peak exists in the thickness direction of the second nitride semiconductor layer.

[0049] This allows, for example, the formation of a guard ring through ion implantation.

[0050] Furthermore, for example, the nitride semiconductor region may contain a third impurity, and the concentration of the third impurity within the nitride semiconductor region may be uniform with respect to the thickness direction of the second nitride semiconductor layer.

[0051] This allows, for example, the formation of a guard ring through epitaxial growth.

[0052] Furthermore, a method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes: a first step of forming a first nitride semiconductor layer of a first conductivity type on a substrate; a second step of forming a second nitride semiconductor layer on the first nitride semiconductor layer; a third step of forming an electron transport layer and an electron supply layer in that order on the second nitride semiconductor layer; a fourth step of forming a third nitride semiconductor layer of a second conductivity type on the electron supply layer; a fifth step of forming a gate electrode on the third nitride semiconductor layer; a sixth step of forming a source electrode on the electron supply layer; and a seventh step of forming a drain electrode on the substrate opposite to the first nitride semiconductor layer, wherein the second step includes a film deposition step of forming a nitride semiconductor film and an implantation step of forming a current conduction portion or current block portion of the first conductivity type by ion implanting impurities into only a portion of the deposited nitride semiconductor film.

[0053] As a result, current blocking or current conducting portions are formed by ion implantation, allowing the upper surface of the second nitride semiconductor layer to remain flat. Since the electron transport layer and electron supply layer are formed sequentially above the second nitride semiconductor layer with a flat upper surface, crystal defects are less likely to occur in the electron transport layer and electron supply layer. Therefore, pits that occur on the surface of the electron supply layer are suppressed, and Schottky contact between the gate electrode and the electron supply layer can be suppressed. Consequently, the deterioration of the yield of the forward characteristics of the FET is suppressed, and nitride semiconductor devices with improved electrical characteristics can be manufactured.

[0054] Furthermore, for example, the nitride semiconductor film may be a semiconductor film of the second conductivity type, the impurity may be an impurity of the first conductivity type, and the current-conducting portion may be formed in the implantation step by ion implantation of the impurity of the first conductivity type.

[0055] This allows current-conducting sections to be easily formed in the desired shape by ion implantation.

[0056] Furthermore, for example, the nitride semiconductor film may be a semiconductor film of the first conductivity type, the impurity may be an impurity of the second conductivity type, and the current blocking portion may be formed in the implantation step by ion implantation of the impurity of the second conductivity type.

[0057] This allows for easy formation of current-conducting regions through epitaxial growth. Since there is no uneven distribution of impurity concentration within the current-conducting regions, variations in electrical resistance are suppressed. Therefore, it is possible to manufacture nitride semiconductor devices with low in-plane on-resistance variation and high reliability.

[0058] The embodiments will be described in detail below with reference to the drawings.

[0059] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0060] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0061] Furthermore, in this specification, terms indicating relationships between elements such as parallel or orthogonal, terms indicating the shape of elements such as rectangles or trapezoids, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges, such as differences of a few percent.

[0062] In this specification and in the drawings, the x, y, and z axes represent the three axes of a three-dimensional Cartesian coordinate system. The x and y axes are parallel to the first side and the second side perpendicular to the first side of the rectangle, respectively, when the plan view shape of the substrate is rectangular. The z axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction". In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction".

[0063] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided (the positive side of the z-axis) is considered "up" or "upper," and the side of the substrate on which the drain electrode is provided (the negative side of the z-axis) is considered "down" or "lower."

[0064] In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0065] Furthermore, in this specification, "plan view" means the view of the nitride semiconductor device substrate from a direction perpendicular to the main surface, that is, the view of the main surface of the substrate from the front.

[0066] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0067] Furthermore, in this specification, AlGaN refers to ternary mixed crystal Al x Ga 1-xIt represents N (0 < x < 1). Hereinafter, a multi-component mixed crystal is abbreviated with an array of each constituent element symbol, for example, AlInN, GaInN, etc. For example, Al x Ga 1-x-y In y N (0 < x < 1, 0 < y < 1, and 0 < x + y < 1) is abbreviated as AlGaInN.

[0068] (Embodiment 1) [Overview] First, the overview of the nitride semiconductor device according to Embodiment 1 will be described with reference to FIG. 1.

[0069] FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to the present embodiment. As shown in FIG. 1, the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, an aperture structure layer 14, an electron traveling layer 20, an electron supply layer 22, a threshold adjustment layer 24, a gate electrode 26, a source electrode 28, and a drain electrode 30. The aperture structure layer 14 includes a current conduction portion 16 and a current blocking portion 18.

[0070] The nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 1 has a hetero structure of an AlGaN film and a GaN film.

[0071] In the hetero structure of the AlGaN film and the GaN film, due to spontaneous polarization or piezo polarization on the (0001) plane, a high-concentration two-dimensional electron gas (2DEG) is generated at the hetero interface. Therefore, even in an undoped state, a sheet carrier concentration of 1 × 10 13 cm -3 or more can be obtained.

[0072] The nitride semiconductor device 1 according to the present embodiment is a field effect transistor (FET) that uses the 2DEG generated at the AlGaN / GaN hetero interface as a channel. Specifically, the nitride semiconductor device 1 is a so-called vertical FET.

[0073] The nitride semiconductor device 1 is a normally-off type FET. In the nitride semiconductor device 1, for example, the source electrode 28 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 30. The potential applied to the drain electrode 30 is, for example, 100 V or more and 120 V or less, but is not limited thereto. When the nitride semiconductor device 1 is in the off state, a potential of 0 V or a negative potential (e.g., -5 V) is applied to the gate electrode 26. When the nitride semiconductor device 1 is in the on state, a positive potential (e.g., +5 V) is applied to the gate electrode 26.

[0074] [Configuration] Hereinafter, the details of each component included in the nitride semiconductor device 1 will be described.

[0075] The substrate 10 is a substrate made of a nitride semiconductor, and as shown in FIG. 1, has a first main surface 10a and a second main surface 10b facing each other. The first main surface 10a is the main surface (upper surface) on the side where the drift layer 12 is formed. Specifically, the first main surface 10a substantially coincides with the c-plane. The second main surface 10b is the main surface (lower surface) on the side where the drain electrode 30 is formed. The planar shape of the substrate 10 is, for example, rectangular, but is not limited thereto.

[0076] The substrate 10 has, for example, a thickness of 300 μm and a carrier concentration of 1×10 18 cm -3 and is a substrate made of n + -type GaN. Here, n-type and p-type indicate the conductivity type of the semiconductor. The n + -type represents a state in which an n-type dopant is added to the semiconductor at a high concentration, so-called heavy doping. Also, the n - -type represents a state in which an n-type dopant is added to the semiconductor at a low concentration, so-called light doping. The same applies to the p + -type and p<00000​​​​​​​​The type shown is an example of a second conductivity type. The second conductivity type is a conductivity type with the opposite polarity to the first conductivity type.

[0077] Note that the substrate 10 does not have to be a nitride semiconductor substrate. For example, the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, a silicon carbide (SiC) thin film on a silicon (Si) substrate, or a graphite substrate containing graphene.

[0078] The drift layer 12 is an example of a first nitride semiconductor layer of a first conductivity type, positioned above the substrate 10. The drift layer 12 is provided, for example, in contact with the first main surface 10a of the substrate 10.

[0079] The drift layer 12 is, for example, n with a thickness of 8 μm. - The film is made of type GaN. The donor concentration of the drift layer 12 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The range is as follows, for example 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the drift layer 12 is 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 17 cm -3 The range is as follows:

[0080] The aperture structure layer 14 is an example of a second nitride semiconductor layer provided above the drift layer 12. As shown in Figure 1, the aperture structure layer 14 includes an n-type current conduction portion 16 and a p-type current blocking portion 18. The specific configuration of the aperture structure layer 14 will be described later.

[0081] The electron transport layer 20 is provided above the aperture structure layer 14. Specifically, the electron transport layer 20 is provided on the upper surfaces of the current conduction section 16 and the current blocking section 18, respectively. The electron transport layer 20 is, for example, a film made of undoped GaN with a thickness of 150 nm.

[0082] The electron transport layer 20 has a channel region. Specifically, a two-dimensional electron gas (2DEG) is generated near the interface between the electron transport layer 20 and the electron supply layer 22. The 2DEG functions as a channel in the electron transport layer 20. The 2DEG is provided along the interface between the electron transport layer 20 and the electron supply layer 22, parallel to the first main surface 10a of the substrate 10.

[0083] Although not shown in Figure 1, an AlN film with a thickness of approximately 1 nm may be provided between the electron transport layer 20 and the electron supply layer 22. The AlN film can suppress alloy scattering and improve channel mobility.

[0084] The electron supply layer 22 is provided above the electron transport layer 20. That is, the electron transport layer 20 and the electron supply layer 22 are provided in this order from the substrate 10 side. The electron supply layer 22 is formed with a substantially uniform thickness along the upper surface of the electron transport layer 20. The electron supply layer 22 is, for example, a film made of undoped AlGaN with a thickness of 50 nm.

[0085] The electron supply layer 22 forms an AlGaN / GaN heterointerface with the electron transport layer 20. This generates a 2DEG within the electron transport layer 20. The electron supply layer 22 supplies electrons to the channel region (i.e., the 2DEG) formed in the electron transport layer 20.

[0086] The threshold adjustment layer 24 is an example of a third nitride semiconductor layer of a second conductivity type provided above the electron supply layer 22. Specifically, the threshold adjustment layer 24 is provided between the gate electrode 26 and the electron supply layer 22. The threshold adjustment layer 24 is formed with a substantially uniform thickness along the upper surface of the electron supply layer 22.

[0087] The threshold adjustment layer 24 has, for example, a thickness in the range of 100 nm to 300 nm, and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3This is a nitride semiconductor layer made of p-type GaN or AlGaN. The presence of a threshold adjustment layer 24 raises the potential at the conduction band edge of the channel portion. This allows the threshold voltage of the nitride semiconductor device 1 to be increased. Therefore, the nitride semiconductor device 1 can be realized as a normally-off type FET. In other words, the nitride semiconductor device 1 can be turned off when a potential of 0V is applied to the gate electrode 26.

[0088] The gate electrode 26 is positioned above the threshold adjustment layer 24. Specifically, the gate electrode 26 is located in a position that overlaps with the current conducting portion 16 in a plan view, and is in contact with the upper surface of the threshold adjustment layer 24. The gate electrode 26 is formed, for example, with a substantially uniform film thickness along the upper surface of the threshold adjustment layer 24.

[0089] The gate electrode 26 is formed using a conductive material such as a metal. For example, the gate electrode 26 is formed using palladium (Pd). The material for the gate electrode 26 can be a material that is Schottky-connected to the p-type GaN layer, such as nickel (Ni)-based materials, tungsten silicide (WSi), or gold (Au).

[0090] The source electrode 28 is positioned at a distance from the gate electrode 26. In this embodiment, the source electrode 28 is provided on the upper surface of the electron supply layer 22 with a gap so as not to come into contact with the threshold adjustment layer 24.

[0091] The source electrode 28 is formed using a conductive material such as a metal. As the material for the source electrode 28, for example, a material such as Ti / Al that can be ohmic connected to the n-type GaN layer by heat treatment can be used.

[0092] The drain electrode 30 is provided on the lower side of the substrate 10, that is, on the side opposite to the drift layer 12. Specifically, the drain electrode 30 is provided in contact with the second main surface 10b of the substrate 10. The drain electrode 30 is formed using a conductive material such as metal. As for the material of the drain electrode 30, similar to the material of the source electrode 28, a material that is ohmic connected to the n-type GaN layer, such as Ti / Al, can be used.

[0093] Note that while Figure 1 shows an example where the source electrode 28 is located on the upper surface of the electron supply layer 22, the design is not limited to this. As shown in Figure 2, a source opening 32 may be provided, and the source electrode 28 may be provided along the inner surface of the source opening 32.

[0094] Figure 2 is a cross-sectional view of the nitride semiconductor device 2 according to this embodiment. The nitride semiconductor device 2 differs from the nitride semiconductor device 1 in that it is provided with a source aperture 32.

[0095] The source opening 32 is an example of an opening that penetrates the electron supply layer 22 and the electron transport layer 20 and reaches the current block section 18, at a position away from the gate electrode 26 and the threshold adjustment layer 24. The source opening 32 has a bottom surface 32a and a side surface 32b.

[0096] The bottom surface 32a of the source opening 32 is part of the upper surface of the current block section 18. As shown in Figure 2, the bottom surface 32a is at the same height as the lower surface of the electron transport layer 20. Here, "same height" means that the distance from the first main surface 10a of the substrate 10 is the same. The bottom surface of the electron transport layer 20 corresponds to the interface between the electron transport layer 20 and the aperture structure layer 14. The bottom surface 32a is, for example, parallel to the first main surface 10a of the substrate 10.

[0097] Alternatively, the bottom surface 32a may be located below the lower surface of the electron transport layer 20. In other words, the source opening 32 may be formed by removing a portion of the current block section 18.

[0098] As shown in Figure 2, the source opening 32 is formed such that the opening area increases as it moves away from the substrate 10. Specifically, the side surface 32b of the source opening 32 is inclined at an angle with respect to the bottom surface 32a. In other words, the cross-sectional shape of the source opening 32 is an inverted trapezoid, or more specifically, an inverted isosceles trapezoid.

[0099] The inclination angle of the side surface 32b with respect to the bottom surface 32a may be, for example, in the range of 30° to 60°. For example, if the side surface 32b of the source opening 32 is inclined diagonally, the contact area between the source electrode 28 and the electron transport layer 20 (specifically, 2DEG) increases, making ohmic connection easier. The 2DEG is exposed on the side surface 32b of the source opening 32 and is connected to the source electrode 28 at the exposed portion.

[0100] The cross-sectional shape of the source opening 32 may be rectangular. In other words, the side surface 32b may be perpendicular to the bottom surface 32a.

[0101] In the nitride semiconductor device 2 shown in Figure 2, the source electrode 28 is provided along the inner surface of the source opening 32. Specifically, the source electrode 28 is connected to the electron supply layer 22, the electron transport layer 20, and the current block section 18. The source electrode 28 is ohmic connected to the electron transport layer 20 and the electron supply layer 22. The source electrode 28 is in direct contact with the 2DEG on its side surface 32b. This reduces the contact resistance between the source electrode 28 and the 2DEG.

[0102] Furthermore, because the source electrode 28 is in contact with the current blocking section 18, the potential of the current blocking section 18 is fixed to the potential applied to the source electrode 28. This allows the electric field applied to the channels in the electron transport layer 20 to be relaxed, thereby suppressing the occurrence of current collapse.

[0103] [Aperture structure layer] Next, the aperture structure layer 14, which is a characteristic configuration of the nitride semiconductor device 1 or 2 according to this embodiment, will be described using Figures 3A and 3B. In the following description, the nitride semiconductor device 2 will be used as an example, but the same applies to the nitride semiconductor device 1.

[0104] Figure 3A is a perspective view showing the current conducting section 16 and current blocking section 18 of the nitride semiconductor device 2 according to this embodiment. Figure 3B is a perspective view of the nitride semiconductor device 2 according to Embodiment 1.

[0105] The aperture structure layer 14 is a nitride semiconductor layer located between the drift layer 12 and the electron transport layer 20. The thickness of the aperture structure layer 14 is substantially uniform, for example, in the range of 100 nm to 1 μm. As an example, the thickness of the aperture structure layer 14 is 350 nm, but is not limited to this. The thickness of the current conduction portion 16 and the current blocking portion 18 are the same as each other.

[0106] As shown in Figure 3A, the aperture structure layer 14 includes a current-conducting portion 16 and a current-blocking portion 18. In this embodiment, one of the current-conducting portion 16 and the current-blocking portion 18 is formed by epitaxial growth of a nitride semiconductor, and the other is formed by ion implantation.

[0107] The current-conducting portion 16 is an example of a first-conductivity type current-conducting portion located in a position overlapping the gate electrode 26 in a plan view. For example, the current-conducting portion 16 is completely covered by the gate electrode 26 and the threshold adjustment layer 24. In other words, in a plan view, the current-conducting portion 16 is located inside the gate electrode 26.

[0108] The current-conducting portion 16 is formed of a nitride semiconductor containing a first impurity. The first impurity is an n-type impurity, specifically Si. The current-conducting portion 16 is a part made of n-type GaN containing Si.

[0109] The Si concentration in the current-conducting portion 16 is, for example, 1 × 10⁻⁶ 15 cm -3The above is 1 x 10 19 cm -3 The range is as follows: The Si concentration in the current-conducting portion 16 is, for example, the same as the Si concentration in the drift layer 12. In this embodiment, the Si concentration in the current-conducting portion 16 is uniform in the thickness direction (z-axis direction; also referred to as the "depth direction") of the aperture structure layer 14.

[0110] Furthermore, "uniform" means that the variation in impurity concentration is sufficiently small. Specifically, when measuring impurity concentration in the depth direction using SIMS (Secondary Ion Mass Spectrometry) analysis, it means that the impurity concentration falls within a range of 50% to 200% of the average value. In other words, "uniform" means, for example, that the average value is 1 × 10⁻⁶ 18 cm -3 In that case, 5 × 10 17 cm -3 The above 2 x 10 18 cm -3 This means that the impurity concentration falls within that range.

[0111] Furthermore, the Si concentration in the current-conducting portion 16 is higher than the Si concentration in the electron-traveling layer 20. In other words, the Si concentration in the electron-traveling layer 20 is lower than the Si concentration in the current-conducting portion 16. Lowering the Si concentration in the electron-traveling layer 20 improves the pinch-off characteristics of the nitride semiconductor device 2.

[0112] The current block section 18 is an example of a second conductive type of current block section provided around the current conduction section 16. Specifically, as shown in Figure 3A, the current block section 18 surrounds the entire circumference of the current conduction section 16.

[0113] The current block portion 18 is formed of a nitride semiconductor containing a second impurity different from the first impurity. The second impurity is a p-type impurity, specifically Mg. The current block portion 18 is a portion made of p-type GaN containing Mg.

[0114] The Mg concentration in the current block section 18 is distributed such that a peak exists in the thickness direction of the aperture structure layer 14. In other words, the Mg concentration in the current block section 18 is not uniform. For example, the average value of the Mg concentration in the current block section 18 is 1 × 10⁻⁶. 18 cm -3 The above is 1 x 10 19 cm -3 It is included in the following range.

[0115] In this embodiment, as shown in Figure 3A, the current conducting portion 16 is surrounded by the current blocking portion 18 in a plan view. In a plan view, the entire periphery of the current conducting portion 16 is surrounded by the current blocking portion 18. In other words, the interface 17 between the current conducting portion 16 and the current blocking portion 18 is formed in an annular shape in a plan view. The interface 17 is perpendicular to the first main surface 10a of the substrate 10.

[0116] The current-conducting portion 16 functions as a path for the drain current that flows when the nitride semiconductor device 2 is in the ON state. In other words, since both the drift layer 12 and the current-conducting portion 16 are n-type GaN, the drain current from the drain electrode 30 flows to the source electrode 28 through the drift layer 12, the current-conducting portion 16, and the electron transport layer 20 in that order.

[0117] Since the current block section 18 is made of p-type GaN, a pn junction is formed between it and the n-type drift layer 12. When the nitride semiconductor device 2 is ON, a reverse bias is applied to the pn junction. Therefore, no drain current flows through the current block section 18.

[0118] In this embodiment, the current conducting portion 16 and the current blocking portion 18 are located on the same layer. That is, the current conducting portion 16 and the current blocking portion 18 are at the same height from the first main surface 10a of the substrate 10. For example, the upper surface of the current conducting portion 16 and the upper surface of the current blocking portion 18 are flush and both are parallel to the first main surface 10a. The lower surface of the current conducting portion 16 and the lower surface of the current blocking portion 18 are flush and both are parallel to the first main surface 10a. In other words, both the upper and lower surfaces of the aperture structure layer 14 are planes parallel to the first main surface 10a of the substrate 10.

[0119] As a result, the electron transport layer 20 and the electron supply layer 22 can be formed sequentially on the flat upper surface of the aperture structure layer 14, thereby suppressing crystal defects that occur in the electron transport layer 20 and the electron supply layer 22. Therefore, pits caused by crystal defects are less likely to occur on the upper surface of the electron supply layer 22.

[0120] Therefore, Schottky contact of the gate electrode 26 is suppressed, which can suppress the deterioration of the yield of the forward characteristics of the FET. In addition, the pinch-off characteristics of the FET are improved by lowering the impurity concentration of the electron transport layer 20 including the channel. Thus, according to this embodiment, a nitride semiconductor device 1 or 2 with improved electrical characteristics is realized.

[0121] [Manufacturing method] Next, the manufacturing method of nitride semiconductor devices 1 and 2 according to this embodiment will be described with reference to Figures 4A to 4F. Figures 4A to 4F are cross-sectional views showing each step of the manufacturing method of nitride semiconductor devices 1 and 2 according to this embodiment.

[0122] First, as shown in Figure 4A, an n-type nitride semiconductor film 12A is formed on the first main surface 10a of the substrate 10 by crystal growth such as metal-organic vapor phase epitaxial growth (MOVPE) (first step). Note that this film formation includes not only the first step but also the film formation process which is part of the second step described later.

[0123] Next, as shown in Figure 4B, a current block section 18 is formed by ion implanting impurities into only a portion of the deposited nitride semiconductor film 12A (the ion implantation step of the second step). The impurity is, for example, Mg.

[0124] Specifically, first, a resist mask 90 of a predetermined shape is formed on the upper surface of the nitride semiconductor film 12A. The resist mask 90 is formed, for example, by applying a photosensitive resist and then patterning it into a predetermined shape by photolithography. In a plan view, the resist mask 90 has an opening in the region where the current block portion 18 is to be formed. With the resist mask 90 in place, Mg ions are implanted. The conditions for ion implantation are not particularly limited, as long as Mg can be implanted at a concentration above a certain level within a predetermined thickness range.

[0125] Figure 5 shows the concentration distribution of impurities in the current block section 18 formed through the process shown in Figure 4B. The horizontal axis represents the depth from the top surface of the nitride semiconductor film 12A, and the vertical axis represents the concentration of impurities (in this case, Mg). As shown in Figure 5, it can be seen that by increasing the ion implantation energy, impurities are implanted to deeper positions. In other words, by increasing the ion implantation energy, the thickness of the current block section 18 can be increased.

[0126] Furthermore, in ion implantation, the impurity concentration is unstable in the vicinity of the surface (i.e., the region with a depth close to 0 nm) and in deeper regions (depending on the energy level). For this reason, in the current block section 18, the impurity concentration is distributed such that a peak exists near the center in the thickness direction (depth direction).

[0127] In this way, the current-blocking portion 18 is formed by ion implantation. Also, as shown in Figure 4B, the portion located in the same layer as the current-blocking portion 18 but where ion implantation was not performed becomes the current-conducting portion 16. The region deeper than the current-blocking portion 18 and the current-conducting portion 16 (i.e., the region closer to the substrate 10) becomes the drift layer 12.

[0128] In this embodiment, both the drift layer 12 and the current-conducting portion 16 are formed by epitaxial growth. Therefore, the concentration of n-type impurities in the drift layer 12 and the concentration of n-type impurities in the current-conducting portion 16 are the same and are uniform, for example, in the thickness direction (depth direction).

[0129] Next, as shown in Figure 4C, after removing the resist mask 90, the electron transport layer 20, electron supply layer 22, and threshold adjustment layer 24 are sequentially deposited by crystal regrowth using the MOVPE method (third step). By depositing each layer continuously, the interfaces of each layer are improved, making it less likely for defects such as surface states to occur.

[0130] Next, as shown in Figure 4D, the threshold adjustment layer 24 is patterned into a predetermined shape by photolithography and etching (fourth step). Then, as shown in Figure 4E, the electron supply layer 22 and the electron transport layer 20 are patterned into a predetermined shape by photolithography and etching. This forms the source opening 32. Note that when manufacturing the nitride semiconductor device 1, it is not necessary to form the source opening 32, so the patterning of the electron supply layer 22 and the electron transport layer 20 may be omitted.

[0131] Next, as shown in Figure 4F, a gate electrode 26 is formed above the threshold adjustment layer 24 (fifth step). For example, a resist is patterned into a predetermined shape, a conductive electrode material is deposited by evaporation or sputtering, and then lifted off to form a gate electrode 26 of the predetermined shape.

[0132] Next, a source electrode 28 is formed on the electron supply layer 22 (sixth step). Specifically, the source electrode 28 is formed along the inner surface of the source opening 32. For example, the resist is patterned into a predetermined shape, a conductive electrode material is deposited by evaporation or sputtering, and then the predetermined shape of the source electrode 28 is formed by lift-off. Note that the formation of the gate electrode 26 and the formation of the source electrode 28 may be performed in any order.

[0133] Next, a drain electrode 30 is formed on the second main surface 10b of the substrate 10 (seventh step). For example, the drain electrode 30 is formed by depositing a conductive electrode material by vapor deposition or sputtering.

[0134] Through the above process, the nitride semiconductor device 1 or 2 shown in Figure 1 or Figure 2 is manufactured.

[0135] In the above explanation, an example was shown in which the current blocking section 18 is formed by ion implantation, but the current conducting section 16 may also be formed by ion implantation.

[0136] Figures 6A and 6B are cross-sectional views showing modified examples of the manufacturing methods for nitride semiconductor devices 1 and 2 according to this embodiment.

[0137] In this modified example, first, as shown in Figure 6A, a drift layer 12 and a p-type nitride semiconductor film 14A are deposited on the first main surface 10a of the substrate 10 in that order by crystal growth such as metal-organic vapor phase epitaxial growth (MOVPE) (the first and second film deposition steps).

[0138] Next, as shown in Figure 6B, a current-conducting portion 16 is formed by ion implanting impurities into only a portion of the deposited nitride semiconductor film 14A (the ion implantation step of the second step). The impurity is, for example, Si.

[0139] Specifically, first, a resist mask 91 of a predetermined shape is formed on the upper surface of the nitride semiconductor film 14A. In a plan view, the resist mask 91 has an opening in the region where the current-conducting portion 16 is to be formed. With the resist mask 91 in place, Si ions are implanted. The conditions for ion implantation are not particularly limited, as long as Si can be implanted at a concentration above a certain level within a predetermined thickness range.

[0140] Figure 7 shows the concentration distribution of impurities in the current-conducting portion 16 formed through the process shown in Figure 6B. The horizontal axis represents the depth from the top surface of the nitride semiconductor film 14A, and the vertical axis represents the concentration of impurities (in this case, Si). Figure 7 shows the case where the ion implantation energy is 200 keV, but as in the case shown in Figure 5, impurities can be implanted to deeper positions by increasing the ion implantation energy.

[0141] In ion implantation, the impurity concentration is unstable near the surface (i.e., in the region with a depth close to 0 nm) and in deeper regions (depending on the energy level). Therefore, in the current-conducting section 16, the impurity concentration is distributed such that a peak exists near the center in the thickness direction (depth direction).

[0142] In this way, the current-conducting portion 16 is formed by ion implantation. Also, as shown in Figure 6B, the portion located in the same layer as the current-conducting portion 16 (part of the nitride semiconductor film 14A) where ion implantation was not performed becomes the current-blocking portion 18. The current-blocking portion 18 is formed by epitaxial growth. For this reason, for example, the concentration of p-type impurities in the current-blocking portion 18 is uniform in the thickness direction.

[0143] (Embodiment 2) Next, Embodiment 2 will be described.

[0144] The nitride semiconductor device according to Embodiment 2 differs from Embodiment 1 in that a carbon-doped nitride semiconductor layer is provided between the drift layer and the aperture structure layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0145] Figure 8 is a cross-sectional view of the nitride semiconductor device 101 according to this embodiment. As shown in Figure 8, the nitride semiconductor device 101 includes a carbon-doped layer 134 in addition to the configuration of the nitride semiconductor device 2 according to Embodiment 1.

[0146] The carbon-doped layer 134 is an example of a fourth nitride semiconductor layer doped with carbon (C), provided between the aperture structure layer 14 and the drift layer 12. In this embodiment, the carbon-doped layer 134 is provided between the current-conducting portion 16 and the current-blocking portion 18 and the drift layer 12. That is, in a plan view, the carbon-doped layer 134 overlaps the current-conducting portion 16 and the current-blocking portion 18.

[0147] The carbon-doped layer 134 is, for example, a film made of carbon-doped GaN. The carbon concentration of the carbon-doped layer 134 is, for example, 2 × 10⁻⁶ 16 cm -3 The above is 1 x 10 20 cm -3 The range is as follows, for example 1 × 10 18 cm -3 That is the case.

[0148] The thickness of the carbon-doped layer 134 is, for example, between 20 nm and 1 μm, and is 200 nm as an example. The carbon-doped layer 134 is formed, for example, by epitaxial growth after the formation of the drift layer 12. Alternatively, the carbon-doped layer 134 may be formed by ion implantation after the formation of the drift layer 12.

[0149] The carbon-doped layer 134 is a high-resistance layer with higher resistance than the drift layer 12, the current-conducting portion 16, and the current-blocking portion 18. By stacking the carbon-doped layer 134 and the current-blocking portion 18, the breakdown voltage of the nitride semiconductor device 101 can be further increased.

[0150] Note that the shape of the carbon-doped layer 134 is not limited to the example shown in Figure 8.

[0151] Figure 9 is a cross-sectional view of a nitride semiconductor device 102 according to a modified example of this embodiment. As shown in Figure 9, the nitride semiconductor device 102 has a carbon doped layer 135 instead of the carbon doped layer 134 compared to the nitride semiconductor device 101.

[0152] The carbon-doped layer 135 is provided in a region that overlaps only with the current-blocking portion 18 of the current-conducting portion 16 in a plan view. In other words, the carbon-doped layer 135 is not provided in a region that overlaps with the current-conducting portion 16 in a plan view. The carbon-doped layer 135 can be formed, for example, by selectively implanting n-type impurities into a carbon-doped layer 134 that is formed over the entire surface, but only in a region that overlaps with the current-conducting portion 16 in a plan view. Alternatively, the carbon-doped layer 135 may be formed by selectively implanting carbon into a n-type nitride semiconductor film 12A shown in Figure 4A or a drift layer 12 shown in Figure 6A, but only in a region that overlaps with the current-blocking portion 18 in a plan view.

[0153] The nitride semiconductor device 102, like the nitride semiconductor device 101, can further increase the breakdown voltage. In addition, in the nitride semiconductor device 102, since the carbon-doped layer 135 is not provided on the drain current path from the drift layer 12 to the current conduction section 16, an increase in on-resistance can be suppressed.

[0154] Furthermore, the nitride semiconductor device 101 or 102 may not be provided with a source opening 32, similar to the nitride semiconductor device 1 in Embodiment 1.

[0155] (Embodiment 3) Next, Embodiment 3 will be described.

[0156] The nitride semiconductor device according to Embodiment 3 differs from Embodiment 1 in that the electron supply layer has a recess structure. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0157] Figure 10 is a cross-sectional view of the nitride semiconductor device 201 according to this embodiment. As shown in Figure 10, the nitride semiconductor device 201 has an electron supply layer 222 instead of the electron supply layer 22 compared to the nitride semiconductor device 2.

[0158] The electron supply layer 222 differs from the electron supply layer 22 in that it has a recess 223. The recess 223 is a recess that extends from the upper surface of the electron supply layer 222 toward the substrate 10. In a plan view, the recess 223 is located in a position that overlaps the gate electrode 26, the threshold adjustment layer 24, and the current conduction portion 16. In a plan view, the end of the recess 223 on the source electrode 28 side overlaps the current block portion 18. In other words, in a plan view, the recess 223 is larger than the current conduction portion 16 and smaller than the threshold adjustment layer 24. For example, in a plan view, the recess 223 is slightly larger than the current conduction portion 16 and completely covers the current conduction portion 16. Also, in a plan view, the threshold adjustment layer 24 is slightly larger than the recess 223 and completely covers the recess 223.

[0159] By providing recesses 223, the electron supply layer 222 can be divided into thin and thick sections. In other words, the electron supply layer 222 is thinner in the sections with recesses 223, while maintaining channel controllability by the gate electrode 26. On the other hand, the electron supply layer 222 can be made thicker in the sections without recesses 223, and the concentration of 2DEG generated in the electron transport layer 20 can be increased in the region directly beneath these thickened sections. By increasing the concentration of 2DEG, the on-resistance can be reduced.

[0160] In Figure 10, the threshold adjustment layer 24 is not uniform in thickness and is provided to fill the recess 223, but this is not the case. For example, the threshold adjustment layer 24 may be uniform in thickness. That is, the threshold adjustment layer 24 may be provided along the inner surface of the recess 223, and its upper surface may be recessed in a shape that follows the recess 223. In this case, the gate electrode 26 may be provided with a uniform thickness and curved, or it may be provided to fill the recess on the upper surface of the threshold adjustment layer 24.

[0161] Furthermore, the nitride semiconductor device 201 may also include a carbon-doped layer 134 or 135, similar to Embodiment 2 or its modified form. Alternatively, the nitride semiconductor device 201 may not have a source opening 32, similar to the nitride semiconductor device 1 of Embodiment 1.

[0162] (Embodiment 4) Next, Embodiment 4 will be described.

[0163] The nitride semiconductor device according to Embodiment 4 differs from Embodiment 1 in that a current diffusion layer is provided between the aperture structure layer and the drift layer. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0164] Figure 11 is a cross-sectional view of the nitride semiconductor device 301 according to this embodiment. As shown in Figure 11, the nitride semiconductor device 301 includes a current diffusion layer 336 in addition to the structure of the nitride semiconductor device 2.

[0165] The current diffusion layer 336 is a nitride semiconductor layer provided between the drift layer 12 and the aperture structure layer 14, with a higher n-type carrier concentration than the drift layer 12. The current diffusion layer 336 is, for example, an n-type semiconductor layer with a thickness of 0.2 μm. + This is a film made of type GaN. The impurity concentration (donor concentration) of the current diffusion layer 336 is, for example, 1 × 10⁻⁶ 16 cm -3 The above is 1 x 10 18 cm-3 The range is as follows, for example 1 × 10 17 cm -3 That is the case. Furthermore, the current diffusion layer 336 is n + AlGaN layer of type n + The structure may be a laminated structure with a GaN layer of the same type. Alternatively, the current diffusion layer 336 may be a graphite layer containing graphene.

[0166] The current diffusion layer 336 is provided between the current conducting section 16 and the current blocking section 18 and the drift layer 12. In other words, in a plan view, the current diffusion layer 336 overlaps with the current conducting section 16 and the current blocking section 18.

[0167] The current diffusion layer 336 may be formed, for example, by epitaxial growth after the formation of the drift layer 12. Alternatively, the current diffusion layer 336 may be formed by ion implantation after the formation of the drift layer 12.

[0168] Because the current diffusion layer 336 is provided, the drain current diffuses laterally within the current diffusion layer 336. Therefore, the drift layer 12 can be widely used as a drain current path, thereby reducing the on-resistance of the nitride semiconductor device 301.

[0169] Furthermore, the nitride semiconductor device 301 may also include a carbon-doped layer 134 or 135, similar to the embodiment 2.

[0170] Figure 12 is a cross-sectional view of a nitride semiconductor device 302 according to a modification 1 of this embodiment. As shown in Figure 12, the nitride semiconductor device 302 includes a carbon-doped layer 134 in addition to the configuration of the nitride semiconductor device 301. The carbon-doped layer 134 is the same as in Embodiment 2.

[0171] Figure 13 is a cross-sectional view of a nitride semiconductor device 303 according to a modified example 2 of this embodiment. As shown in Figure 13, the nitride semiconductor device 303 includes a carbon-doped layer 135 in addition to the configuration of the nitride semiconductor device 301. The carbon-doped layer 135 is the same as the modified example of Embodiment 2.

[0172] The carbon-doped layer 134 or 135 is provided between the aperture structure layer 14 and the current diffusion layer 336. In other words, the current diffusion layer 336 is provided between the carbon-doped layer 134 or 135 and the drift layer 12.

[0173] According to the nitride semiconductor device 302 or 303 of Modification 1 or 2, the on-resistance can be reduced by providing a current diffusion layer 336. In addition, the breakdown voltage can be increased by providing a carbon doped layer 134 or 135.

[0174] Furthermore, the nitride semiconductor device 301, 302, or 303 may, similar to Embodiment 3, include an electron supply layer 222 having a recess 223 instead of the electron supply layer 22. Alternatively, the nitride semiconductor device 301, 302, or 303 may not have a source opening 32, similar to the nitride semiconductor device 1 of Embodiment 1.

[0175] (Flat layout) The following describes the planar layout of the nitride semiconductor device according to each of the embodiments described above. The planar layout shown below is applicable to any of the nitride semiconductor devices according to each of the embodiments and their modified versions described above.

[0176] [Example 1] First, we will explain the first example of a planar layout using Figures 14A and 14B.

[0177] Figure 14A is a plan view showing a first example of the layout of the current conduction section 16 and current block section 18 of the nitride semiconductor device according to each embodiment. Figure 14B is a plan view showing the layout of the source electrode 28 and gate electrode 26 corresponding to the layout shown in Figure 14A. Note that the cross section on line II shown in Figure 14B corresponds to the cross section shown in each embodiment and each modified example.

[0178] As shown in Figure 14A, the nitride semiconductor device comprises a plurality of current-conducting portions 16. The plurality of current-conducting portions 16 are arranged periodically in a plan view. "Periodic" means that the plurality of current-conducting portions 16 are arranged with a predetermined regularity. For example, the plurality of current-conducting portions 16 are arranged at equal intervals along a predetermined direction.

[0179] In the example shown in Figure 14A, the multiple current-conducting parts 16 include multiple current-conducting parts 16a and 16b. The multiple current-conducting parts 16a are arranged periodically along the y-axis direction (second direction). Multiple columns of the multiple current-conducting parts 16a arranged along the y-axis direction are arranged along the x-axis direction (first direction). In other words, the multiple current-conducting parts 16a are arranged in a matrix in the xy-plane.

[0180] Furthermore, one current-conducting section 16b is provided between each adjacent row of current-conducting sections 16a. These current-conducting sections 16b are arranged periodically along the x-axis direction at the center in the y-axis direction.

[0181] As shown in Figure 14B, the nitride semiconductor device comprises a plurality of source electrodes 28. If a source opening 32 is provided, a source opening 32 is provided for each source electrode 28.

[0182] Each of the multiple source electrodes 28 has an elongated shape in plan view that extends in the y-axis direction. The multiple source electrodes 28 are positioned between two current-conducting portions 16a that are aligned along the x-axis direction. Specifically, each source electrode 28 is provided between each row of current-conducting portions 16a that are aligned along the y-axis direction. Also, two source electrodes 28 are aligned along the y-axis direction, with a current-conducting portion 16a positioned between them.

[0183] Both the gate electrode 26 and the threshold adjustment layer 24 are continuous, surrounding multiple source electrodes 28. In other words, the gate electrode 26 and the threshold adjustment layer 24 are each formed as a single plate that covers almost the entire surface of the substrate 10, and openings are provided only at positions corresponding to the source electrodes 28 to expose the source electrodes 28.

[0184] As shown in Figure 14B, the nitride semiconductor device includes a gate electrode pad 38. The gate electrode pad 38 is located above the gate electrode 26 and is electrically connected to the gate electrode 26. The gate electrode pad 38 is located at the end in the x-axis direction (third direction) and in the central part in the y-axis direction (fourth direction).

[0185] Furthermore, as shown in Figure 15, the nitride semiconductor device includes a source electrode pad 40 (not shown in Figure 14B). Figure 15 is a plan view showing a first example of the layout of the gate electrode pad 38 and source electrode pad 40 of the nitride semiconductor device according to each embodiment.

[0186] The source electrode pad 40 is located above the plurality of source electrodes 28 and is electrically connected to each of the plurality of source electrodes 28. As shown in Figure 15, the source electrode pad 40 is provided over almost the entire area except for the gate electrode pad 38. In other words, in a plan view, the source electrode pad 40 overlaps each of the plurality of source electrodes 28. Between the source electrode pad 40 and the plurality of source electrodes 28, there is an interlayer insulating film (not shown) that covers the gate electrode 26 and the threshold adjustment layer 24. The interlayer insulating film has openings that expose at least a portion of each of the plurality of source electrodes 28. The source electrode pad 40 and the plurality of source electrodes 28 are electrically connected through the openings provided in the interlayer insulating film.

[0187] Note that the shape of the source electrode pad 40 is not limited to the example shown in Figure 15. For example, the source electrode pad 40 may be provided for each source electrode 28 and may be formed in a comb-like shape with finger portions (lead-out wiring) extending along the y-axis. This reduces the overlap between the source electrode pad 40 and the gate electrode 26, thereby suppressing the occurrence of gate-source short circuits.

[0188] [Example 2] Next, a second example of a planar layout will be explained using Figures 16A and 16B.

[0189] Figure 16A is a plan view showing a second example of the layout of the current conduction section 16 and current block section 18 of the nitride semiconductor device according to each embodiment. Figure 16B is a plan view showing the layout of the source electrode 28 and gate electrode 26 corresponding to the layout shown in Figure 16A. Note that the cross-section on line II shown in Figure 16B corresponds to the cross-section shown in each embodiment and each modified example.

[0190] In the example shown in Figure 16A, the multiple current-conducting parts 16 are arranged on each side of multiple virtual hexagons that tile the plane in a plan view. Specifically, the multiple current-conducting parts 16 are provided in the central part of each side of multiple virtual regular hexagons that tile the plane, in an elongated shape along each side.

[0191] In the example shown in Figure 16B, each of the multiple source electrodes 28 is positioned in the center of a virtual hexagon that tiled the plane. The planar shape of each of the multiple source electrodes 28 is a regular hexagon, but it may also be circular. Six current-conducting portions 16 are provided around each corresponding source electrode 28.

[0192] In the example shown in Figure 16B, both the gate electrode 26 and the threshold adjustment layer 24 are continuous, surrounding multiple source electrodes 28. In other words, the gate electrode 26 and the threshold adjustment layer 24 are each formed as a single plate that covers almost the entire surface of the substrate 10, and openings are provided only at positions corresponding to the source electrodes 28 to expose the source electrodes 28. The shape of these openings is, for example, a regular hexagon.

[0193] As shown in the examples in Figures 16A and 16B, nitride semiconductor devices can adopt a close-packed structure, thereby significantly reducing the on-resistance per unit area.

[0194] [Variations of electrode pads] The above-described layout shows an example where the gate electrode pad 38 is located at the end, but it is not limited to this.

[0195] Figure 17 is a plan view showing a second example of the layout of the gate electrode pad 38 and source electrode pad 40 of the nitride semiconductor device according to each embodiment. As shown in Figure 17, the gate electrode pad 38 may be located in the center in both the x-axis and y-axis directions. As a result, since the gate electrode pad 38 is located in the center of the plane, the gate voltage can be applied uniformly to the gate electrode 26.

[0196] Here, the plan view shape of the gate electrode pad 38 is shown as a rectangle that is elongated in the x-axis direction, but it may also be a square. Alternatively, the plan view shape of the gate electrode pad 38 may also be a rectangle that is elongated in the y-axis direction.

[0197] Furthermore, the gate electrode pad 38 may be located at the end in the y-axis direction, or at the corner of a rectangular substrate 10 in plan view. Alternatively, the nitride semiconductor device may have multiple gate electrode pads 38. For example, two gate electrode pads 38 may be located at the positive and negative ends in the x-axis or y-axis direction.

[0198] [Guard Ring Area] Next, the structure of the end portion of the nitride semiconductor device according to each embodiment and each modified example will be described with reference to Figures 18 and 19.

[0199] Figures 18 and 19 are plan views showing modified edge layouts of the nitride semiconductor device shown in Figures 14A and 16A, respectively. As shown in Figures 18 and 19, the nitride semiconductor device comprises a plurality of guard ring regions 42.

[0200] Each of the multiple guard ring regions 42 is a ring-shaped p-type nitride semiconductor region arranged to surround the current block section 18 in a plan view. The multiple guard ring regions 42 are arranged at a predetermined distance from each other so that the outermost guard ring regions become larger rings. The distance between adjacent guard ring regions 42 is, for example, constant.

[0201] Multiple guard ring regions 42 contain p-type impurities (third impurities). The p-type impurities contained in the guard ring regions 42 are the same as the p-type impurities contained in the current block section 18, specifically Mg. However, the p-type impurities contained in the guard ring regions 42 may be different from the p-type impurities contained in the current block section 18.

[0202] The multiple guard ring regions 42 are all located on the same level as the current blocking section 18. The multiple guard ring regions 42 are formed, for example, simultaneously with the formation of the current conducting section 16 and the current blocking section 18.

[0203] For example, as shown in Figure 4B, when forming the current-blocking portion 18 by ion implantation of Mg, a resist mask 90 is used that covers not only the area where the current-conducting portion 16 should be formed, but also the area corresponding to the space between the guard ring regions 42. By ion implanting Mg using this resist mask, the current-blocking portion 18 and multiple guard ring regions 42 are formed simultaneously.

[0204] In this case, the impurity concentrations in the multiple guard ring regions 42 are the same as the impurity concentrations in the current block section 18. Specifically, the impurity concentrations in the multiple guard ring regions 42 are distributed such that a peak exists in the thickness direction.

[0205] Alternatively, as shown in Figure 6B, when forming the current-conducting portion 16 by ion implantation of Si, a resist mask 91 is used that covers not only the region where the current-blocking portion 18 should be formed, but also the region corresponding to the guard ring region 42. By ion implanting Si using this resist mask, the p-type nitride semiconductor film 14A is separated into ring shapes at the terminal end in a plan view, and multiple guard ring regions 42 are formed.

[0206] In this case, the impurity concentrations in the multiple guard ring regions 42 are the same as the impurity concentrations in the current block section 18. Specifically, the impurity concentrations in the multiple guard ring regions 42 are uniform with respect to the thickness direction.

[0207] As described above, the provision of the guard ring region 42 can alleviate electric field concentration at the termination of the nitride semiconductor device. By alleviating electric field concentration, leakage current at the termination can be reduced, and the breakdown voltage can be increased.

[0208] The planar layout described above is merely an example and is not limited to these. In other words, the shape, number, and arrangement of the current-conducting parts are all examples and can be changed as appropriate. For example, the aperture structure layer 14 may be provided with only one current-conducting part 16.

[0209] (Other embodiments) Although a nitride semiconductor device and a method for manufacturing the same according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive of, and forms constructed by combining components from different embodiments are also included within the scope of this disclosure.

[0210] For example, although the current block section 18 is shown as being composed of a second conductive type nitride semiconductor, the current block section 18 may also be composed of an insulating nitride semiconductor. For example, the current block section 18 may be doped with carbon or iron.

[0211] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the aperture structure layer 14 side. The donor concentration may be controlled by the donor Si, or by the acceptor carbon that compensates for the Si.

[0212] Furthermore, the first conductivity type is p-type, p + type, p - It is a type, and the second conductive type is n type, n + type, n - It can be a type.

[0213] Furthermore, each of the above embodiments may be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0214] This disclosure can be used as a nitride semiconductor device with improved electrical properties, and can be used, for example, as a power transistor used in power supply circuits such as the main inverter of an xEV, an on-board charger, and a general-purpose inverter for a fuel cell. [Explanation of Symbols]

[0215] 1, 2, 101, 102, 201, 301, 302, 303 Nitride semiconductor equipment 10 circuit boards 10a First main surface 10b Second main surface 12 Drift Layers 12A, 14A nitride semiconductor film 14 Aperture Structural Layers 16, 16a, 16b Current carrying part 17 Interface 18 Current Block Section 20 Electronic transport layer 22, 222 electron supply layer 24 Threshold adjustment layer 26 gate 28 Source electrodes 30 Drain electrode 32 Source openings 32a Bottom 32b side 38 Gate Pad 40 Source electrode pads 42 Guard Ring Area 90, 91 Resist Mask 134, 135 Carbon-doped layers 223 Recessed section 336 Current Diffusion Layer

Claims

1. circuit board and A first nitride semiconductor layer of a first conductivity type is provided above the substrate, A second nitride semiconductor layer is provided above the first nitride semiconductor layer, An electron transport layer and an electron supply layer are provided in order above the second nitride semiconductor layer, A third nitride semiconductor layer of a second conductivity type and a gate electrode are provided in order above the electron supply layer, A source electrode is provided on the electron supply layer, at least in part, A drain electrode provided on the substrate opposite to the first nitride semiconductor layer, The present invention comprises a carbon-doped fourth nitride semiconductor layer provided between the second nitride semiconductor layer and the first nitride semiconductor layer, The second nitride semiconductor layer is Located below the third nitride semiconductor layer, the first conductive type current conduction portion containing the first impurity, It includes a current block section provided around the current conducting section, The concentration of the first impurity in the electron transport layer is lower than the concentration of the first impurity in the current conduction portion. Nitride semiconductor equipment.

2. The fourth nitride semiconductor layer is provided in a region that overlaps in a plan view only in the current-blocking portion of the current-conducting portion and the current-blocking portion. The nitride semiconductor device according to claim 1.

3. circuit board and A first nitride semiconductor layer of a first conductivity type is provided above the substrate, A second nitride semiconductor layer is provided above the first nitride semiconductor layer, An electron transport layer and an electron supply layer are provided in order above the second nitride semiconductor layer, A third nitride semiconductor layer of a second conductivity type and a gate electrode are provided in order above the electron supply layer, A source electrode is provided on the electron supply layer, at least in part, A drain electrode provided on the substrate opposite to the first nitride semiconductor layer, The present invention comprises a current diffusion layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer, wherein the carrier concentration of the first conductivity type is higher than that of the first nitride semiconductor layer. The second nitride semiconductor layer is Located below the third nitride semiconductor layer, the first conductive type current conduction portion containing the first impurity, This includes a current block section provided around the current conducting section, The concentration of the first impurity in the electron transport layer is lower than the concentration of the first impurity in the current conduction portion. Nitride semiconductor equipment.

4. Furthermore, it has an opening that penetrates the electron supply layer and the electron transport layer and reaches the current block section, The source electrode is provided along the inner surface of the opening. A nitride semiconductor device according to any one of claims 1 to 3.

5. The current block section contains a second impurity different from the first impurity, The concentration of the second impurity in the current block is distributed such that a peak exists in the thickness direction of the second nitride semiconductor layer. The concentration of the first impurity in the current-conducting portion is uniform with respect to the thickness direction. A nitride semiconductor device according to any one of claims 1 to 4.

6. The current block section contains a second impurity different from the first impurity, The concentration of the first impurity in the current-conducting portion is distributed such that a peak exists in the thickness direction of the second nitride semiconductor layer. The concentration of the second impurity in the current block is uniform with respect to the thickness direction. A nitride semiconductor device according to any one of claims 1 to 4.

7. The electron supply layer has a recess provided above the current conduction portion and below the third nitride semiconductor layer. A nitride semiconductor device according to any one of claims 1 to 6.

8. In a plan view, the recess portion has an end on the source electrode side that overlaps the current block portion. The nitride semiconductor device according to claim 7.

9. The interface between the current conducting portion and the current blocking portion is perpendicular to the main surface of the substrate. A nitride semiconductor device according to any one of claims 1 to 8.

10. The current conducting portion is surrounded by the current blocking portion in a plan view. A nitride semiconductor device according to any one of claims 1 to 9.

11. The nitride semiconductor device comprises a plurality of current-conducting portions, The multiple current-conducting parts are arranged periodically in a plan view. The nitride semiconductor device according to claim 10.

12. The nitride semiconductor device comprises a plurality of source electrodes, The multiple current-conducting portions are arranged periodically in a plan view along a first direction and a second direction perpendicular to the first direction. Each of the multiple source electrodes has an elongated shape in plan view that extends in the second direction, and is positioned between two current-conducting portions that are aligned in the first direction. The gate electrode is continuous with respect to the plurality of source electrodes. The nitride semiconductor device according to claim 11.

13. The nitride semiconductor device comprises a plurality of source electrodes, The multiple current-conducting parts are arranged on each side of a plurality of virtual hexagons that fill the plane in a plan view. The multiple source electrodes are each positioned in the center of the multiple virtual hexagons, The gate electrode is continuous with respect to the plurality of source electrodes. The nitride semiconductor device according to claim 11.

14. Furthermore, it includes a gate electrode pad located above the gate electrode and electrically connected to the gate electrode, The gate electrode pad is located at the end in a third direction and in the central part in a fourth direction perpendicular to the third direction, in a plan view. The nitride semiconductor device according to any one of claims 11 to 13.

15. Furthermore, it includes a gate electrode pad located above the gate electrode and electrically connected to the gate electrode, The gate electrode pad is located in the center in a third direction in a plan view, and is also located in the center in a fourth direction perpendicular to the third direction. The nitride semiconductor device according to any one of claims 11 to 13.

16. Furthermore, the device comprises one or more ring-shaped second conductive nitride semiconductor regions arranged to surround the current block portion in a plan view, A nitride semiconductor device according to any one of claims 1 to 15.

17. The nitride semiconductor region contains a third impurity, The concentration of the third impurity in the nitride semiconductor region is determined by the thickness of the second nitride semiconductor layer. The distribution is such that a peak exists in each direction. The nitride semiconductor device according to claim 16.

18. The nitride semiconductor region contains a third impurity, The concentration of the third impurity within the nitride semiconductor region is uniform with respect to the thickness direction of the second nitride semiconductor layer. The nitride semiconductor device according to claim 16.

Images