Semiconductor equipment

Abstract

To impart excellent electric characteristics to a semiconductor device.SOLUTION: A semiconductor device comprises a first insulation layer, a second insulation layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulation layer. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulation layer includes a region in contact with the oxide semiconductor layer. The third conductive layer includes a region in contact with the second insulation layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are provided separated from each other. The third region is provided between the first region and the second region. The third region and the third conductive layer include an overlapping region via the second insulation layer. The first region and the second region include a portion having a higher carbon concentration than the third region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, the present invention. One aspect of this is a process, machine, manufacture, or composition. This relates to matter. Therefore, the invention disclosed more specifically in this specification One aspect of the technical field is semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, and lighting devices. Examples include power storage devices, memory devices, methods for driving them, or methods for manufacturing them. It can be listed.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices and electronic devices may include semiconductor devices. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface. It is attracting attention. The transistor in question is used in integrated circuits (ICs) and image display devices (simply as a display device and It is widely applied to electronic devices such as (also written as) transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxidative materials. Semiconductors are attracting attention.

[0005] For example, using zinc oxide or an In-Ga-Zn-based oxide semiconductor as the oxide semiconductor Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Overview of the project] [Problems that the invention aims to solve]

[0007] One aspect of the present invention aims to impart good electrical characteristics to a semiconductor device. Alternatively, one of the objectives is to provide a semiconductor device with high on-current. One of the objectives is to provide a semiconductor device suitable for [unspecified purpose]. Alternatively, a semiconductor device with high integration density. One of the objectives is to provide a device, or to provide a low-power semiconductor device. One of the objectives is to provide highly reliable semiconductor devices. Alternatively, the aim is to provide a semiconductor device that retains data even when the power supply is cut off. One objective is to provide a novel semiconductor device. Or, One of the objectives is to provide a method for manufacturing semiconductor devices.

[0008] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention relates to a transistor having an oxide semiconductor layer in a channel formation region.

[0010] One aspect of the present invention comprises a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third layers. A semiconductor device having a conductive layer and a region in contact with the first insulating layer. The region has a first conductive layer which is electrically connected to an oxide semiconductor layer, and the second conductive layer is an oxide semiconductor layer. The second insulating layer is electrically connected to the material semiconductor layer and has a region in contact with the oxide semiconductor layer. The third conductive layer has a region in contact with the second insulating layer, and the second insulating layer is a gate insulating film. It has a region that can function, and the first conductive layer is of the source electrode or drain electrode It has a region that can function as one of the two, and the second conductive layer is the source electrode or the drain The third conductive layer has a region that can function as the other electrode, and the gate electrode is The oxide semiconductor layer has regions that can function, and the first to third regions are... The first and second regions are set apart, and the third region is set apart from the first and second regions. A third region is provided between them, and the third conductive layer has an overlapping region via the second insulating layer. Furthermore, the first and second regions have portions where the carbon concentration is higher than that of the third region. This is a semiconductor device characterized by the following:

[0011] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is meant to be noticed, and is not limited to a specific number.

[0012] In the first and second regions, phosphorus, arsenic, antimony, boron, and aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, The concentration of one or more elements selected from fluorine, chlorine, titanium, zinc, and hydrogen is the third The configuration may also include a portion that is higher than the domain.

[0013] Furthermore, the first region and the second region have a configuration in which they are in contact with a hydrogen-containing nitride insulating film. That is also acceptable.

[0014] Another aspect of the present invention comprises a first insulating layer, a second insulating layer, an oxide semiconductor layer, and A semiconductor device having 1 to 3 conductive layers, wherein the oxide semiconductor layer is a first insulating layer The first conductive layer has a region in contact with the oxide semiconductor layer, and the second conductive layer is electrically connected to the oxide semiconductor layer. The layer is electrically connected to the oxide semiconductor layer, and the second insulating layer is in contact with the oxide semiconductor layer. The third conductive layer has a region that is in contact with the second insulating layer, and the second insulating layer is a gate Having a region that can function as an insulating film, the first conductive layer is a source electrode or drain The second conductive layer has a region that can function as one of the in electrodes, and the source electrode The third conductive layer has a region that can function as the other side of the drain electrode, and the third conductive layer is a gate The oxide semiconductor layer has regions that can function as electrodes, and the first to fifth regions The first region and the second region are provided separately, and the first region overlaps with the first conductive layer. The first region has a region that overlaps with the second conductive layer, and the second region has a region that overlaps with the second conductive layer. The electrical layer has a region that overlaps with the second insulating layer, and the third region is the first region and the second region A fourth region is provided between the first and third regions, and the fifth region is provided between the first and third regions. The area is located between the second and third areas, and the fourth and fifth areas are The carbon concentration is higher in the region than in the first, second, and third regions. It is a semiconductor device that is characterized by its features.

[0015] In the fourth and fifth regions, phosphorus, arsenic, antimony, boron, and aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, The concentration of one or more elements selected from fluorine, chlorine, titanium, zinc, and hydrogen is first The configuration may include portions that are higher than the first, second, and third regions.

[0016] Furthermore, the fourth and fifth regions have a configuration that includes regions in contact with a hydrogen-containing nitride insulating film. That is also acceptable.

[0017] The above semiconductor device has a fourth conductive layer formed on top of the oxide semiconductor layer via a first insulating layer. It can also be a structured configuration.

[0018] The oxide semiconductor layer has a first and a second oxide semiconductor layer, and from the first insulating layer side the second The configuration may also consist of an oxide semiconductor layer followed by a first oxide semiconductor layer. The first oxide semiconductor layer may be provided so as to cover the second oxide semiconductor layer.

[0019] In the above oxide semiconductor layer configuration, the first and second oxide semiconductor layers are made of In and Zn. , has M (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) The first oxide semiconductor layer has a larger atomic ratio of M to In than the second oxide semiconductor layer. It is preferable.

[0020] Furthermore, the oxide semiconductor layer has first to third oxide semiconductor layers, and from the first insulating layer side, The oxide semiconductor layer is provided in the order of a third oxide semiconductor layer, a second oxide semiconductor layer, and a first oxide semiconductor layer. The configuration may also be such that the first oxide semiconductor layer is a second oxide semiconductor layer and the It may be provided so as to cover the oxide semiconductor layer 3.

[0021] In the above oxide semiconductor layer configuration, the first to third oxide semiconductor layers consist of In and Zn, M (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) The first and third oxide semiconductor layers have an atomic ratio of M to In that is the same as the second oxide semiconductor layer. It is preferable that it be larger than this.

[0022] Furthermore, the above oxide semiconductor layer can be made of non-single crystals and has crystals oriented along the c axis. It is preferable to do so.

[0023] Another aspect of the present invention involves forming an oxide semiconductor film on an insulating surface, and on the oxide semiconductor film A first resist mask is formed, and the oxide semiconductor film is selected using the first resist mask. By etching the surface, an oxide semiconductor layer is formed, and the first resist mask is removed. A first insulating film is formed on the oxide semiconductor layer, and a conductive film is formed on the first insulating film. A second resist mask is formed on top, and the conductive film and the first resist mask are used to form the conductive film and the first resist mask. A laminate consisting of a first insulating layer and a conductive layer is formed by selectively etching the insulating film. This also exposes the first and second regions of the oxide semiconductor layer, and In the treatment process, impurities are added to the first and second regions to form oxygen deficiencies, and the second region The dyst mask is peeled off, revealing the first and second regions of the oxide semiconductor layer, the first insulating layer, and a second insulating film containing hydrogen is formed on the conductive layer, and the first region and By diffusing hydrogen into the second region, the resistance of both the first and second regions is reduced. This is a method for manufacturing a semiconductor device characterized by the following features. [Effects of the Invention]

[0024] By using one aspect of the present invention, good electrical characteristics can be imparted to a semiconductor device. Alternatively, it is possible to provide a semiconductor device with high on-current. Alternatively, it is suitable for high-speed operation. We can provide semiconductor devices with high integration density. Alternatively, it is possible to provide low-power semiconductor devices. Alternatively, reliable semiconductor devices. A conductive device can be provided. Alternatively, a semiconductor that retains data even when the power supply is cut off. We can provide a device. Or, we can provide a novel semiconductor device. Alternatively, a method for manufacturing the above-mentioned semiconductor device can be provided.

[0025] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0026] [Figure 1] Top view and cross-sectional view illustrating a transistor. [Figure 2] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 3] Top view and cross-sectional view illustrating a transistor. [Figure 4] A cross-sectional diagram illustrating a transistor. [Figure 5] Top view and cross-sectional view illustrating a transistor. [Figure 6] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 7] Top view and cross-sectional view illustrating a transistor. [Figure 8] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 9] Top view and cross-sectional view illustrating a transistor. [Figure 10] A cross-sectional diagram illustrating a transistor. [Figure 11] Top view and cross-sectional view illustrating a transistor. [Figure 12] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 13] Top view and cross-sectional view illustrating a transistor. [Figure 14] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 15] Top view and cross-sectional view illustrating a transistor. [Figure 16] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 17] Top view and cross-sectional view illustrating a transistor. [Figure 18] A cross-sectional diagram illustrating a transistor. [Figure 19] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 20] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 21] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 22] A top view illustrating the display device. [Figure 23] A cross-sectional view illustrating a display device. [Figure 24] A cross-sectional view illustrating a display device. [Figure 25] A diagram illustrating the method for manufacturing transistors. [Figure 26] A diagram illustrating the method for manufacturing transistors. [Figure 27] A diagram illustrating an example of a display device configuration and a circuit diagram of a pixel. [Figure 28] A diagram illustrating the display module. [Figure 29] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 30] Cross-sectional view and circuit diagram of a memory device. [Figure 31] A diagram illustrating an example of RF tag configuration. [Figure 32] A diagram illustrating an example of a CPU configuration. [Figure 33] Circuit diagram of a memory element. [Figure 34] A diagram illustrating the structure of a transistor. [Figure 35] A diagram illustrating the structure of a transistor. [Figure 36] A diagram illustrating the structure of a transistor. [Figure 37] A diagram illustrating the structure of a transistor. [Figure 38] A diagram illustrating the structure of a transistor. [Figure 39] Cross-sectional view and band structure of a transistor. [Figure 40] A diagram illustrating the computational model. [Figure 41] A diagram illustrating the initial and final states. [Figure 42] A diagram illustrating the activation barrier. [Figure 43] A diagram illustrating the initial and final states. [Figure 44] A diagram illustrating the activation barrier. [Figure 45] A diagram illustrating the transition levels of VoH. [Figure 46] A diagram illustrating electronic devices. [Figure 47] A diagram illustrating an example of RF tag usage. [Figure 48] Cross-sectional TEM image of a transistor. [Figure 49] Cross-sectional TEM image of a transistor. [Figure 50] A diagram showing the Id-Vg characteristics of a transistor. [Figure 51] A diagram showing the results of a gate bias-temperature stress test. [Figure 52] A diagram showing the results of a gate bias-temperature stress test. [Figure 53] A diagram showing the results of a gate bias-temperature stress test. [Figure 54] A diagram illustrating a sample for SIMS analysis. [Figure 55] A diagram illustrating the results of SIMS analysis. [Figure 56] A diagram illustrating the results of SIMS analysis. [Figure 57] A diagram illustrating the temperature dependence of resistivity. [Figure 58] A schematic diagram illustrating the CAAC-OS film deposition model, and cross-sectional views of the pellet and CAAC-OS. [Figure 59] A schematic diagram illustrating the nc-OS film deposition model, and a diagram showing the pellet. [Figure 60] A diagram illustrating pellets. [Figure 61] A diagram illustrating the forces applied to the pellet on the surface being formed. [Figure 62] A diagram illustrating the movement of pellets on the surface being formed. [Figure 63] A diagram illustrating the crystal structure of InGaZnO4. [Figure 64] A diagram illustrating the structure of InGaZnO4 before atomic collisions. [Figure 65] A diagram illustrating the structure of InGaZnO4 after atomic collisions. [Figure 66] A diagram illustrating the trajectories of atoms after a collision. [Figure 67] Cross-sectional HAADF-STEM images of CAAC-OS and the target. [Figure 68] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 69] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Modes for carrying out the invention]

[0027] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0028] Furthermore, in this specification, etc., when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, and when X and Y are functionally connected, This includes the case where X and Y are directly connected. Here, X and Y are objects (for example) For example, it is assumed to be a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc. Therefore And, not limited to predetermined connection relationships, for example, connection relationships shown in a diagram or text, but also including diagrams or This includes relationships other than those explicitly stated in the text.

[0029] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between modes.

[0030] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0031] Note that if it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. If this is the case (i.e., if X and Y are connected with another element or circuit in between) (when X and Y are functionally connected) and when X and Y are functionally connected (i.e., when there is no other circuit between X and Y) (When they are functionally connected with a sash in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) Therefore, if you explicitly state that they are electrically connected, then simply state that they are connected. This is equivalent to the case where it is explicitly stated only that it is.

[0032] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope. Note that these expressions are just examples, and The method of representation is not limited to these. Here, X, Y, Z1, and Z2 are the object (e.g., the device). (This refers to elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0035] Furthermore, in this specification, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. One example of such a substrate is a semiconductor. Substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, We have plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates, tungsten substrates, substrates having tungsten foil, flexible substrates, laminated Examples include laminated films, paper containing fibrous materials, or base films. One of the glass substrates. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda fountains. Examples include glass. One example of a flexible substrate is polyethylene terephthalate (PET). ), represented by polyethylene naphthalate (PEN) and polyethersulfone (PES) These include flexible plastics or synthetic resins such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or poly Examples include polyvinyl chloride. Examples of base films include polyester, polyamide, and polyvinyl chloride. These include reimide, inorganic vapor-deposited films, or paper. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, characteristics, size, and Alternatively, it can manufacture transistors with less variation in shape, high current capacity, and small size. This is possible. When a circuit is constructed using such transistors, the circuit consumes less power. This allows for increased power output or higher integration of circuits.

[0036] Furthermore, even if a flexible substrate is used as the substrate and transistors are formed directly on the flexible substrate, That's fine. Alternatively, a release layer may be provided between the substrate and the transistor. The release layer is half a layer on top of it. After partially or completely completing the conductive device, it is separated from the circuit board and transferred to another circuit board. It can be used. In this case, the transistor can be mounted on substrates with poor heat resistance or flexible substrates. Yes, it is possible. The aforementioned release layer may include, for example, an inorganic film consisting of a tungsten film and a silicon oxide film. This involves using a layered structure configuration, or a configuration in which an organic resin film such as polyimide is formed on the substrate. It is possible.

[0037] In other words, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates on which the transistor is transposed. Examples include, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or (This includes regenerated fibers (acetate, cupro, rayon, recycled polyester, etc.), leather These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0038] (Embodiment 1) In this embodiment, a transistor according to one aspect of the present invention will be described with reference to the drawings.

[0039] A transistor according to one aspect of the present invention is made of silicon (including strained silicon), germanium, and silicon Germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium Phosphorus, gallium nitride, organic semiconductors, or oxide semiconductors are used in the channel formation region. This is possible. In particular, it includes oxide semiconductors with a larger band gap than silicon. It is preferable to form a flannel-forming region.

[0040] For example, the above oxide semiconductor may be at least indium (In) or zinc (Zn) Preferably contains. More preferably In-M-Zn oxide (where M is Al, Ti, Ga Composition containing oxides (metals such as Ge, Y, Zr, Sn, La, Ce, or Hf) It is considered complete.

[0041] In the following, unless otherwise specified, the channel formation region includes an oxide semiconductor as an example. Let me explain about Rangista.

[0042] Figures 1(A) and 1(B) are a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Figure 1(A) is a top view, and the cross-section in the direction of the dashed line A1-A2 shown in Figure 1(A) is shown in Figure 1 This corresponds to (B). Also, the cross-section in the direction of the dashed line A3-A4 shown in Figure 1(A) is shown in Figure 2(A). Alternatively, it corresponds to Figure 2(B). Note that in the above drawing, some elements have been enlarged for clarity. The diagram is reduced or abbreviated. Also, the direction of the dashed line A1-A2 is the channel length direction. The direction of the dashed line A3-A4 is sometimes referred to as the channel width direction.

[0043] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. The region where the gate electrode overlaps with the part of the semiconductor through which current flows when the zistor is ON. , or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the other element. In a zista, the channel length is not necessarily the same across all regions. That is, one channel The channel length of a transistor may not be fixed to a single value. Therefore, in this specification... The channel length is one of the following values ​​in the region where the channel is formed: maximum value, minimum value. Alternatively, use the average value.

[0044] Furthermore, channel width refers to, for example, the semiconductor (or transistor) when it is in the ON state. The region where the part through which current flows and the gate electrode overlap, or the region where a channel is formed. This refers to the length of the portion in the region where the source and drain face each other. In a transistor, the channel width is not necessarily the same across all regions. That is, The channel width of a transistor may not be fixed to a single value. Therefore, this specification In the book, the channel width is any one value, the maximum value, in the region where the channel is formed. Use the minimum or average value.

[0045] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger.

[0046] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0047] Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined.

[0048] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0049] The transistor 101 has an insulating layer 120 that is in contact with the substrate 110, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a gate insulating film 160 in contact with the oxide semiconductor layer 130, and a gate insulating film The gate electrode layer 170 in contact with the film 160, the oxide semiconductor layer 130, and the gate insulating film 160 An insulating layer 175 covering the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175, Electrical connections are made between the oxide semiconductor layer 130 and the insulating layer 180 through openings provided in the insulating layer 175 and the insulating layer 180. A source electrode layer 140 and a drain electrode layer 150 are connected by gas, and formed on the above configuration It has an insulating layer 185 and, if necessary, an insulating layer 19 in contact with the insulating layer 185. A planarization film (0) or the like may be provided.

[0050] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0051] Furthermore, the gate electrode layer 170 is formed of two layers: a conductive layer 171 and a conductive layer 172. As shown in the illustration, it may be a single layer or a stack of three or more layers.

[0052] Furthermore, the source electrode layer 140 is formed of two layers: a conductive layer 141 and a conductive layer 142. As shown in the diagram, it may be a single layer or a lamination of three or more layers. Conductive layer 151 and conductive layer The same applies to the drain electrode layer 150 formed in 152.

[0053] Furthermore, when the channel width is shortened, the oxide semiconductor layer 130 is shown as in Figure 2(A). It is preferable that the surface be formed to have curvature. The curvature of the upper surface allows the upper part The coating properties of the formed film can be improved. However, if the channel width is relatively long... As shown in Figure 2(B), the upper part of the oxide semiconductor layer 130 may have a flat region. The explanation regarding the channel width can also be applied to other transistors disclosed herein. .

[0054] A transistor according to one aspect of the present invention comprises a gate electrode layer 170, a source electrode layer 140, and a drain. The in electrode layer 150 has a self-aligned structure in which there is no overlapping region. The transistor has extremely low parasitic capacitance between the gate electrode layer, source electrode layer, and electrode layers. Therefore, it is suitable for high-speed operation applications.

[0055] The oxide semiconductor layer 130 in transistor 101 has a region 231 (so Between region 231 and region 232 (drain region) and region 231 and region 232 A region 233(ch) is provided and overlaps with the gate electrode layer 170 via the gate insulating film 160. It has a channel area.

[0056] Here, regions 231 and 232 are regions in contact with the insulating layer 175 as shown in Figure 1(B). It has regions. If an insulating material containing hydrogen is used for the insulating layer 175, regions 231 and 232 This can reduce the resistance.

[0057] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride films and aluminum nitride films can be used.

[0058] Furthermore, regions 231 and 232 contain impurities that form oxygen vacancies and increase conductivity. The following may be added. Examples of impurities that form oxygen vacancies in the oxide semiconductor layer include phosphorus. Arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, aluminum Gon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon One or more of the following methods can be used. The method of adding the impurity is as follows: Plasma treatment method, ion implantation method, ion doping method, plasma immersion ion Plantation methods can be used.

[0059] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0060] Furthermore, as a method for adding the above-mentioned impurities, a plasma treatment method that is easy to handle over large areas will be used. This is preferable. For example, a pair of substrates on which transistors are formed are biased. It is placed on one of the electrodes (the cathode side), and a high frequency is applied between the pair of electrodes in an argon atmosphere under reduced pressure. Wave power (such as 13.56 MHz) is applied to generate argon plasma for processing. At this time, a portion of the gate electrode layer 170 is sputtered and deposited on the edge of the gate insulating film 160. As a result, regions 231 and 232 and the gate electrode layer 170 become short-circuited. There is.

[0061] Therefore, when performing a plasma treatment method, the gate electrode layer 170 and the gate insulating film 16 With the resist mask for forming the pattern of 0 left on the gate electrode layer 170, Razma treatment is preferable.

[0062] Plasma processing is performed while the resist mask remains on the gate electrode layer 170. Because sputtering of the electrode layer 170 is suppressed, regions 231 and 232 and the gate electrode layer This prevents short circuits with 170 and reduces gate leakage current. Because a portion of the mask is sputtered, for example, if the process is performed with argon plasma, Argon and carbon can be added to regions 231 and 232 as described above. When carbon is added to an oxide semiconductor layer, oxygen vacancies are formed, thus the oxide semiconductor The conductivity of the layer can be further increased.

[0063] In other words, regions 231 and 232 in transistor 101 are oxygen-deficient as described above. The concentration of impurities that form damage is higher in the region than in region 233. Furthermore, in the oxygen deficiency Because of the presence of hydrogen, regions 231 and 232 are areas where the hydrogen concentration is higher than that of region 233. It has such a configuration. By forming a transistor, the source region and drain region are formed. This allows for lower resistance in the input region and increases the on-current of the transistor. .

[0064] Furthermore, elements that form oxygen vacancies in the oxide semiconductor layer are referred to as impurities (impurity elements). Let me explain. Typical examples of impurity elements include boron, carbon, nitrogen, fluorine, and aluminum. Examples include silicon, phosphorus, chlorine, and noble gas elements. A typical example of a noble gas element is helium. There are neon, argon, krypton, and xenon.

[0065] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of impurity elements, oxygen vacancies are formed. Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide semiconductor This increases conductivity, making it a conductor. A conductive oxide semiconductor is called an oxide conductor. It is possible. Generally, oxide semiconductors have a large energy gap, so they are sensitive to visible light. It is transparent. On the other hand, oxide conductors are oxide semiconductors that have donor levels near the conduction band. It is a conductor. Therefore, the effect of absorption by the donor level is small, and oxidation with respect to visible light. It has light transmittance comparable to that of a semiconductor.

[0066] Here, in a film formed of an oxide conductor (hereinafter referred to as the oxide conductor layer), the resistance The temperature dependence of the rate will be explained using Figure 57.

[0067] Here, a sample having an oxide conductive layer was prepared. As the oxide conductive layer, an oxide semiconductor was used. The oxide conductive layer (OC_SiN) is formed when the conductive layer comes into contact with the silicon nitride film. x ), In a doping apparatus, argon is added to the oxide semiconductor layer and in contact with the silicon nitride film. The oxide conductive layer (OC_Ar dope+SiN) formed by this process x ), or plastic In the Zuma processing apparatus, the oxide semiconductor layer is exposed to argon plasma, and the silicon nitride film The oxide conductive layer (OC_Ar plasma + SiN) formed by contact with the plasma is formed by contact with the plasma. x ) make It was manufactured. Note that the silicon nitride film contains hydrogen.

[0068] Oxide conductive layer (OC_SiN x The method for preparing a sample containing ) is shown below. On a glass substrate After forming a 400nm thick silicon oxidnitride film by plasma CVD, oxygen plastic By exposing the silicon oxidizride film to Zuma and adding oxygen ions, oxygen is released upon heating. A silicon oxide nitride film was formed. Next, a silicon oxide nitride film that releases oxygen upon heating was formed. A sputtering target with an atomic ratio of In:Ga:Zn=5:5:6 was used on the film. A 100 nm thick In-Ga-Zn oxide film is formed by sputtering, and then subjected to 450°C nitrogen. After heat treatment in a nitrogen atmosphere, it was further heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Next, a silicon nitride film with a thickness of 100 nm was formed using plasma CVD. Next, 35 The material was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 0°C.

[0069] Oxide conductive layer (OC_Ar dope + SiN x The method for preparing a sample containing ) is shown below. A 400 nm thick silicon oxide nitride film is formed on a glass substrate by plasma CVD. Afterward, by exposing it to oxygen plasma and adding oxygen ions to the silicon oxidnitride film, heating occurs. A silicon oxidoxide-nitride film that releases oxygen was formed by this process. Next, oxygen was released by heating. On a silicon oxide nitride film, sputtering with an atomic ratio of In:Ga:Zn=5:5:6 A 100 nm thick In-Ga-Zn oxide film was formed using a sputtering method with a GET. Then, after heat treatment in a nitrogen atmosphere at 450°C, a mixed gas atmosphere of nitrogen and oxygen at 450°C... It was heat-treated with gas. Next, using a doping device, the In-Ga-Zn oxide film was accelerated The voltage is 10kV, and the dose is 5 × 10 14 / cm 2 Add argon to In-G Oxygen vacancies were formed in an α-Zn oxide film. Next, a 100 nm thick film was created using plasma CVD. A silicon nitride film was formed. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. The treatment was performed.

[0070] A method for manufacturing a sample containing an oxide conductor layer (OC_Ar plasma + SiN x ) is shown below. On a glass substrate, a silicon oxynitride film with a thickness of 400 nm was formed by plasma CVD method. After that, it was exposed to oxygen plasma to form a silicon oxynitride film that releases oxygen by heating. Next, an In-Ga-Zn oxide film with a thickness of 100 nm was formed on the silicon oxynitride film that releases oxygen by heating by sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn = 5:5:6, and heat-treated in a nitrogen atmosphere at 450 °C. After that, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 °C. Next, in a plasma treatment apparatus, argon plasma was generated, and oxygen deficiency was formed by colliding accelerated argon ions with the In-Ga-Zn oxide film. Next, a 100 nm thick silicon nitride film was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. An argon plasma was generated in the plasma treatment apparatus, and oxygen deficiency was formed by colliding accelerated argon ions with the In-Ga-Zn oxide film. Next, a 100 nm thick silicon nitride film was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. An argon plasma was generated in the plasma treatment apparatus, and oxygen deficiency was formed by colliding accelerated argon ions with the In-Ga-Zn oxide film. Next, a 100 nm thick silicon nitride film was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. An argon plasma was generated in the plasma treatment apparatus, and oxygen deficiency was formed by colliding accelerated argon ions with the In-Ga-Zn oxide film. Next, a 100 nm thick silicon nitride film was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. The treatment was performed.

[0071] Next, the resistivity measurement results of each sample are shown in Fig. 57. Here, the resistivity was measured by the four-terminal van-der-Pauw method. In Fig. 57, the horizontal axis represents the measurement temperature, and the vertical axis represents the resistivity. The measurement results of the oxide conductor layer (OC_SiN ) are indicated by square marks, the measurement results of the oxide conductor layer (OC_Ar plasma + SiN x ) are indicated by triangular marks, and the measurement results of the oxide conductor layer (OC_Ar dope + SiN ) are indicated by circular marks. x The measurement results of the oxide conductor layer (OC_Ar plasma + SiN ) are indicated by triangular marks, and the measurement results of the oxide conductor layer (OC_Ar dope + SiN x ) are indicated by circular marks.

[0072] Although not shown in the diagram, the oxide semiconductor layer that does not come into contact with the silicon nitride film has high resistivity and resistance Measuring the resistivity was difficult. For this reason, the oxide conductive layer has a lower resistivity than the oxide semiconductor layer. It becomes clear that...

[0073] As can be seen from Figure 57, the oxide conductor layer (OC_Ar dope + SiN x ) and acid Compound conductor layer (OC_Ar plasma+SiN x ) in a place with oxygen deficiency and hydrogen In total, the variation in resistivity is small. Typically, the variation in resistivity is small between 80K and 290K. The rate of change is less than ±20%. Or, the resistivity changes between 150K and 250K. The rate of motion is less than ±10%. That is, oxide conductors are degenerate semiconductors, and the conduction band edge and f It is presumed that the ferrolevel is in agreement with or nearly in agreement with the ferrolevel. For this reason, the oxide conductor layer is By using it as the source and drain regions of a transistor, the oxide conductive layer and the source The contact with the conductive film, which functions as the drain electrode and the contact electrode, becomes ohmic contact, and oxidation occurs. By reducing the contact resistance between the material conductive layer and the conductive film that functions as the source electrode and drain electrode, It is possible. Also, because the resistivity of oxide conductors has low temperature dependence, the oxide conductor layer and the source electricity The contact resistance with the conductive film, which functions as both the electrode and drain electrode, has minimal variation, resulting in high reliability. It is possible to fabricate transistors.

[0074] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 3(A) and 3(B). Figure 3(A) is a top view of transistor 102, and the dashed line B1-B shown in Figure 3(A) The cross-sections in two directions correspond to Figure 3(B). Also, the dashed line B3-B4 direction shown in Figure 3(A) The cross-section is the cross-section in the channel width direction of transistor 101 shown in Figures 2(A) and (B). It is the same as above. Note that in the above drawing, some elements have been enlarged, reduced, or omitted for clarity. The diagram is abbreviated. Also, the direction of the dashed line B1-B2 is the channel length direction, and the direction of the dashed line B3- The B4 direction is sometimes referred to as the channel width direction.

[0075] The transistor 102 has an insulating layer 120 that is in contact with the substrate 110 and an oxide layer that is in contact with the insulating layer 120. A material semiconductor layer 130 and a source electrode layer 140 that is electrically connected to the oxide semiconductor layer 130 The drain electrode layer 150 and the gate insulating film 160 in contact with the oxide semiconductor layer 130, A gate electrode layer 170 in contact with the insulating film 160, an oxide semiconductor layer 130, and a gate insulating film 1 60, an insulating layer covering the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170. Layer 175, insulating layer 180 in contact with insulating layer 175, and insulating layer 1 formed on the above configuration It has 85 and, if necessary, an insulating layer 190 (planarization film) in contact with the insulating layer 185. It may also be possible to have such provisions.

[0076] Furthermore, the source electrode layer 140 and drain electrode layer 150 of transistor 102 are made of oxide. Points directly formed on the semiconductor layer 130, and the configuration of the source region and drain region. Except for one other feature, it has the same configuration as transistor 101.

[0077] Furthermore, the oxide semiconductor layer 130 in transistor 102 is located in a separate region 33 Provided between region 1 and region 332, and region 331 and region 332, and gate insulating A region 333 that overlaps with the gate electrode layer 170 via the film 160, and regions 331 and 333 The region 334 provided between them, and the region 335 provided between the region 332 and the region 333 have.

[0078] In the transistor 102, the region 331 has a region in contact with the source electrode layer 140, and the region 332 has a region in contact with the drain electrode layer 150. Therefore, the regions 331 and the region 332 are used as the source electrode layer 140 and the drain electrode layer 150, and oxygen is absorbed by the metal material, resulting in oxygen deficiency and n-type conversion to reduce the resistance.

[0079] Also, the regions 334 and 335 do not contact the source electrode layer 140 and the drain electrode layer 150, but have a region in contact with the insulating layer 175 containing hydrogen. Due to the interaction between the oxygen deficiency generated in the regions 334 and 335 during the process up to the formation of the insulating layer 175 and the hydrogen diffusing from the insulating layer 175 into the regions 334 and 335, the regions 334 and 3 35 become low-resistance n-type.

[0080] Therefore, the regions 331 and 334 can act as source regions, and the regions 332 and 335 can act as drain regions.

[0081] <M Note that impurities for increasing oxygen deficiency may be added to the regions 334 and 335 in the same manner as the regions 231 and 232 of the transistor 101. <000098'6>

[0082] At this time, when adding impurities by plasma treatment, since a part of the gate electrode layer 170 may be sputtered and deposited at the end of the gate insulating film 160, it is preferable to perform plasma treatment in the same manner as the transistor 101 while leaving a resist mask on the gate electrode layer 170. is performed.

[0083] Since plasma processing is performed in this state, sputtering of the gate electrode layer 170 is suppressed. Prevention of short circuits between regions 334 and 335 and the gate electrode layer 170 and gate leakage current Flow can be reduced. Also, because a part of the resist mask is sputtered, for example When processing is performed with argon plasma, argon is present in regions 334 and 335. Carbon can be added. As mentioned above, carbon is added to the oxide semiconductor layer. Because oxygen vacancies are formed, the conductivity of the oxide semiconductor layer can be further increased.

[0084] In other words, regions 334 and 335 in transistor 102 form an oxygen vacancy. The concentration of impurities for this purpose is higher in regions 331, 332, and 333. In addition, since hydrogen enters the oxygen vacancy, regions 334 and 335 have a hydrogen concentration. It has a portion that is higher than region 333. A transistor is formed by this configuration. This allows for lower resistance in both the source and drain regions, and the transistor's The current can be increased.

[0085] Furthermore, the widths of regions 334 and 335 in the channel length direction are preferably 100 nm or less. Furthermore, in the case of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, it is also possible to use a configuration that does not involve the low-resistance modification described above.

[0086] Furthermore, a transistor according to one aspect of the present invention is an oxide semiconductor, as shown in Figures 4(A) and (B). A conductive layer 172 may be provided between the body layer 130 and the substrate 110. The conductive layer is a second By using it as a gate electrode layer (back gate), further increases in on-current and threshold Voltage control is possible. Note that in the cross-section in the channel length direction shown in Figure 4(A) The width of the conductive layer 172 is shortened so that it does not overlap with the source electrode layer 140, drain electrode layer 150, etc. It is also acceptable to avoid this. Furthermore, the width of the conductive layer 172 may be made wider than the width of the gate electrode layer 170. It can be shortened.

[0087] To increase the on-current, for example, the gate electrode layer 170 and the conductive layer 172 are set to the same potential. It can be driven as a double-gate transistor. Also, to control the threshold voltage... This can be achieved by supplying a constant potential different from that of the gate electrode layer 170 to the conductive layer 172. To make layer 170 and conductive layer 172 at the same potential, for example, as shown in Figure 4(C), The electrode layer 170 and the conductive layer 172 can be electrically connected via the contact hole. Oh, Figures 4(A), (B), and (C) were shown as examples of modified versions of transistor 101, but The configuration can also be applied to transistor 102 shown in Figure 3.

[0088] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 5(A) and (B). Figure 5(A) is a top view of transistor 103, and the dashed line C1-C shown in Figure 5(A) The cross-sections in two directions correspond to Figure 5(B). Also, the dashed line C3-C4 direction shown in Figure 5(A) The cross-section corresponds to Figure 6(A) or Figure 6(B). Note that in the above drawings, for clarity... Some elements are enlarged, reduced, or omitted in the illustration. Also, the dashed line C1-C2 direction is shown. The direction indicated by the dashed line C3-C4 is sometimes referred to as the channel length direction, and the direction indicated by the dashed line C3-C4 is sometimes referred to as the channel width direction.

[0089] The transistor 103 shown in Figures 5(A) and (B) has an oxide semiconductor layer 130 and an insulating layer 120. Except for the fact that the oxide semiconductor layer 130b and oxide semiconductor layer 130c are formed in that order from the side, The configuration is the same as that of transistor 101.

[0090] For example, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c have the following compositions: Different oxide semiconductor layers can be used.

[0091] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 7(A) and 7(B). Figure 7(A) is a top view of transistor 104, and the dashed line D1-D shown in Figure 7(A) The cross-sections in two directions correspond to Figure 7(B). Also, the dashed line D3-D4 direction shown in Figure 7(A) The cross-section corresponds to Figure 8(A) or Figure 8(B). Note that in the above drawings, for clarity... Some elements are enlarged, reduced, or omitted in the illustration. Also, the dashed line D1-D2 direction. The direction indicated by the dashed line D3-D4 is sometimes referred to as the channel length direction, and the direction indicated by the dashed line D3-D4 is sometimes referred to as the channel width direction.

[0092] The transistor 104 shown in Figures 7(A) and (B) has an oxide semiconductor layer 130b. Except for being covered by a body layer 130c, the other configurations are the same as those of transistor 103. ru.

[0093] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 9(A) and (B). Figure 9(A) is a top view of transistor 105, and the dashed line E1-E shown in Figure 9(A) The cross-sections in two directions correspond to Figure 9(B). Also, the dashed line E3-E4 direction shown in Figure 9(A) The cross-section is the same as the cross-section in the channel width direction of transistor 103 shown in Figure 6. Note that in the above drawings, some elements have been enlarged, reduced, or omitted for clarity. It is. Also, the direction of the dashed line E1-E2 is the channel length direction, and the direction of the dashed line E3-E4 is the channel length direction. This is sometimes referred to as the width direction of the panel.

[0094] The transistor 105 shown in Figures 9(A) and (B) has an oxide semiconductor layer 130 and an insulating layer 120. Except for the fact that the oxide semiconductor layer 130b and oxide semiconductor layer 130c are formed in that order from the side, The configuration is the same as that of transistor 102. Oxide semiconductor layer 130 of transistor 105 Like transistor 104, the oxide semiconductor layer 130b is covered by the oxide semiconductor layer 130c. It can also be configured in this way.

[0095] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 10(A), (B), and (C), A conductive layer 172 may be provided between the oxide semiconductor layer 130 and the substrate 110. By using the layer as a second gate electrode layer (back gate), further increases in on-current and The threshold voltage can be controlled. Note that the channel length direction shown in Figure 10(A) In the cross-section, the width of the conductive layer 172 is shortened, and the source electrode layer 140 and drain electrode layer 15 It is also acceptable to ensure that it does not overlap with 0, etc. Furthermore, the width of the conductive layer 172 is set to the gate electrode layer 17 The width may be shorter than 0. Also, Figures 10(A), (B), and (C) show transistor 10 Although shown as an example of a variation of 4, this form is represented by transistors 103 and 105 It can also be applied to...

[0096] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 11(A) and (B). Figure 11(A) is a top view of transistor 106, and the dashed line F shown in Figure 11(A) The cross-section in the 1-F2 direction corresponds to Figure 11(B). Also, the dashed line F3 shown in Figure 11(A) -The cross-section in the F4 direction corresponds to Figure 12(A) or Figure 12(B). Note that in the above drawings, For clarity, some elements have been enlarged, reduced, or omitted in the illustration. Also, dashed lines are used. The direction from F1 to F2 is referred to as the channel length direction, and the direction from the dashed line F3 to F4 is referred to as the channel width direction. There are cases where this is the case.

[0097] The transistor 106 shown in Figures 11(A) and (B) has an oxide semiconductor layer 130 and an insulating layer 12 From the 0 side, oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c Except for the points formed in sequence, the other configurations are the same as those of transistor 101.

[0098] For example, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 13 For 0c, oxide semiconductor layers with different compositions can be used.

[0099] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 13(A) and (B). Figure 13(A) is a top view of transistor 107, and the dashed line G shown in Figure 13(A) The cross-section in the 1-G2 direction corresponds to Figure 13(B). Also, the dashed line G3 shown in Figure 13(A) -The cross-section in the G4 direction corresponds to Figure 14(A) or Figure 14(B). Note that in the above drawings, For clarity, some elements have been enlarged, reduced, or omitted in the illustration. Also, dashed lines are used. The direction from G1 to G2 is referred to as the channel length direction, and the direction from the dashed line G3 to G4 is referred to as the channel width direction. There are cases where this is the case.

[0100] The transistor 107 shown in Figures 13(A) and (B) consists of an oxide semiconductor layer 130a and an oxide semiconductor layer. Except for the fact that the material semiconductor layer 130b is covered by the oxide semiconductor layer 130c, the other configurations This is the same as transistor 106.

[0101] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 15(A) and (B). Figure 15(A) is a top view of transistor 108, and the dashed line H shown in Figure 15(A) The cross-section in the 1-H2 direction corresponds to Figure 15(B). Also, the single-point chain shown in Figure 15(A) The cross-section in the direction of line H3-H4 corresponds to Figure 16(A) or Figure 16(B). Therefore, for clarity, some elements have been enlarged, reduced, or omitted in the illustration. The direction of the dashed line H1-H2 is called the channel length direction, and the direction of the single dashed line H3-H4 is called the channel width direction. It may be referred to as such.

[0102] The transistor 108 shown in Figures 15(A) and (B) consists of an oxide semiconductor layer 130a and an oxide semiconductor layer. Except for the fact that a portion of the material semiconductor layer 130b is covered by the oxide semiconductor layer 130c, Its configuration is the same as that of transistor 106.

[0103] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 17(A) and (B). Figure 17(A) is a top view of transistor 109, and the dashed line I shown in Figure 17(A) The cross-section in the direction of 1-I2 corresponds to Figure 17(B). Also, the dashed line I3 shown in Figure 17(A) -The cross-section in the I4 direction is the same as the cross-section in the channel width direction of transistor 108 shown in Figure 16. They are the same. Note that in the above diagram, some elements have been enlarged, reduced, or omitted for clarity. This is illustrated in the diagram. Also, the direction of the dashed line I1-I2 is the channel length direction, and the direction of the dashed line I3-I The four directions are sometimes referred to as the channel width directions.

[0104] The transistor 109 shown in Figures 17(A) and (B) has an oxide semiconductor layer 130 and an insulating layer 12 From the 0 side, oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c Except for the points formed in order, the other configurations are the same as transistor 102. The oxide semiconductor layer 130 of transistor 109 is used for transistor 107 or transistor 108 In the case of sea urchin, oxide semiconductor layer 130a and oxide semiconductor layer 130b or a part thereof is an oxide semiconductor The structure may also be one in which it is covered with a conductive layer 130c.

[0105] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 18(A), (B), and (C), A conductive layer 172 may be provided between the oxide semiconductor layer 130 and the substrate 110. By using the layer as a second gate electrode layer (back gate), further increases in on-current and The threshold voltage can be controlled. Note that the channel length direction shown in Figure 18(A) In the cross-section, the width of the conductive layer 172 is shortened, and the source electrode layer 140 and drain electrode layer 15 It is also acceptable to ensure that it does not overlap with 0, etc. Furthermore, the width of the conductive layer 172 is set to the gate electrode layer 17 The width may be shorter than 0. Also, Figures 18(A), (B), and (C) show transistor 10 As an example of a variation of 7, this form includes transistors 106, 108 and It can also be applied to transistor 109.

[0106] In one aspect of the present invention, a transistor (transistors 101 to 109) is Even in the misaligned configuration, the gate electrode layer 170 is connected to the oxide semiconductor via the gate insulating film 160. The channel width direction of the body layer 130 is electrically surrounded, and the on-current is increased. The structure of the transistor is a surrounded channel (s-channel) structure. It is called construction.

[0107] Furthermore, a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In a transistor having the oxide semiconductor layer 130, the two or three layers of material By appropriately selecting the material, it is possible to pass an electric current through the oxide semiconductor layer 130b. The current flowing through the conductive layer 130b reduces the effects of interfacial scattering, resulting in a high on-current. This can be achieved. Furthermore, increasing the thickness of the oxide semiconductor layer 130b improves the on-current. This is possible. For example, if the thickness of the oxide semiconductor layer 130b is 100 nm to 200 nm That's good too.

[0108] By using a transistor with the above configuration, good electrical characteristics can be imparted to the semiconductor device. It is possible.

[0109] This embodiment can be appropriately combined with other embodiments shown herein. .

[0110] (Embodiment 2) In this embodiment, the components of the transistor shown in Embodiment 1 will be described in detail. ru.

[0111] The substrate 110 is not merely a support material, but also has other devices such as transistors formed on it. A substrate may also be used. In this case, the gate electrode layer 170 and source electrode layer 14 of the transistor 0, and one or more of the drain electrode layers 150 are electrically connected to the other devices mentioned above. It's fine if you do that.

[0112] For example, the substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. It can also be used. In addition, single-crystal semiconductor substrates made of silicon or silicon carbide, multi-bonded Crystal semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Silico A board such as an on-insulator can be used.

[0113] The insulating layer 120 has the role of preventing the diffusion of impurities from the substrate 110, as well as oxide semiconductors. It can play a role in supplying oxygen to the conductive layer 130. Therefore, the insulating layer 120 is acid Preferably, it is an insulating film containing elements, and is an insulating film containing more oxygen than the stoichiometric composition. It is more preferable that the surface temperature of the film be between 100°C and 700°C, preferably 1 In the TDS method, which is performed by heat treatment between 00°C and 500°C, oxygen is converted to oxygen atoms. The amount released is 1.0 × 10 19 atoms / cm 3 The membrane is as described above. If the substrate 110 is a substrate on which other devices are formed, the insulating layer 120 is an interlayer insulating film. It also functions as a surface. In that case, CMP (Chemical Chemical Processing) is used to make the surface flat. It is preferable to perform a planar treatment using methods such as mechanical polishing. .

[0114] For example, the insulating layer 120 contains aluminum oxide, magnesium oxide, silicon oxide, and oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating films such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0115] In this embodiment, transistor 106, transistor 107, transistor 10 8 and the oxide semiconductor layer 130 that transistor 109 has 0a, oxide semiconductor layer 130b and oxide semiconductor layer 130c are arranged in order from the insulating layer 120 side. This explanation will primarily focus on the case of a stacked three-layer structure.

[0116] Furthermore, the oxide semiconductor layer 130 is one of the transistors 101 and 102. In the case of a layer, a layer corresponding to the oxide semiconductor layer 130b described above should be used.

[0117] Also, transistors 103, 104, and 105 are oxidized. If the material semiconductor layer 130 consists of two layers, then the layer corresponding to the oxide semiconductor layer 130b and the oxide semiconductor layer 130b are also included. A laminate in which layers corresponding to the conductive layer 130c are stacked sequentially from the insulating layer 120 side can be used. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c can also be swapped. Cut.

[0118] Furthermore, if there are four or more oxide semiconductor layers 130, for example, as described in this embodiment... A configuration in which other oxide semiconductor layers are stacked on top of the three-layer oxide semiconductor layer 130, or the three-layer structure The configuration can be such that another oxide semiconductor layer is inserted at any interface in the above.

[0119] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used. Electron affinity is the energy difference between the vacuum level and the top of the valence band (ions). From the potential, the energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) It can be calculated by subtracting (P).

[0120] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. It contains one or more metallic elements, for example, the energy at the lower end of the conduction band is the oxide semiconductor layer 13 Greater than 0b, at least 0.05eV, 0.07eV, 0.1eV, or 0.15eV. If present, it approaches the vacuum level within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with an oxide semiconductor.

[0121] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 Among the 0s, a channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. It will be accomplished.

[0122] Furthermore, the oxide semiconductor layer 130a contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the interface when the oxide semiconductor layer 130b and the insulating layer 120 are in contact In comparison, interface states are formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. This becomes less likely to occur. The interface level may form a channel, so the transistor The key voltage may fluctuate. Therefore, an oxide semiconductor layer 130a is provided. This can reduce variations in electrical characteristics such as the threshold voltage of transistors. Furthermore, the reliability of the transistor can be improved.

[0123] Furthermore, the oxide semiconductor layer 130c contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, when the oxide semiconductor layer 130b and the gate insulating film 160 are in contact, Compared to the interface, at the interface between oxide semiconductor layer 130b and oxide semiconductor layer 130c, Scattering of A becomes less likely. Therefore, by providing the oxide semiconductor layer 130c This allows for an increase in the field-effect mobility of the transistor.

[0124] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain Al, Ti, Ga Ge, Y, Zr, Sn, La, Ce, or Hf are used in a material higher than the oxide semiconductor layer 130b. Materials containing the atoms in a specific ratio can be used. Specifically, materials with an atomic ratio of 1.5 times or more are preferred. The ratio should be at least twice, and more preferably at least three times. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in the oxide semiconductor layer. The monocrystalline semiconductor layer 130a and the oxide semiconductor layer 130c are more acidic than the oxide semiconductor layer 130b. It can be said that primary defects are less likely to occur.

[0125] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The oxide semiconductors that can be used as c are at least indium (In) or sub-album. It is preferable that it contains lead (Zn). Alternatively, it is preferable that it contains both In and Zn. Furthermore, in order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, Preferably, both include a stabilizer.

[0126] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Examples include aluminum (Al) or zirconium (Zr). Also, other stabilizers... These are lanthanides: lanthanum (La), cerium (Ce), and praseodymium (P). r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Examples include rhodium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). .

[0127] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and in-Zn oxide. Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn acid In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn acid In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide Materials, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide are used. It is possible.

[0128] For example, in-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. It means an oxide containing In, Ga, and Zn. Good. Also, in this specification, a film composed of In-Ga-Zn oxide is referred to as an IGZO film. They also call them that.

[0129] Also, InMO3(ZnO) m Materials represented as (m>0, and m is not an integer) It may be included. Note that M is one selected from Ga, Y, Zr, La, Ce, or Nd. This indicates a metallic element or multiple metallic elements. Also, In2SnO5(ZnO) n (n>0, and You may also use materials represented by n (where n is an integer).

[0130] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c are At least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn, La) When it is an In-M-Zn oxide containing a metal such as Ce or Hf, the oxide semiconductor layer 1 30a is In:M:Zn=x1:y1:z1 [atomic ratio], oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], oxide semiconductor layer 130c is In:M:Z If n = x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 become y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1 greater than y2 / x2. The ratio should be 5 times or more, preferably 2 times or more, and more preferably 3 times or more. At this time, the oxide semi In the conductor layer 130b, if y2 is greater than or equal to x2, the electrical characteristics of the transistor are stabilized. This is possible. However, when y2 becomes more than 3 times x2, the field-effect mobility of the transistor Because this would cause a decrease in the value, it is preferable that y2 be less than three times x2.

[0131] In the oxide semiconductor layer 130a and oxide semiconductor layer 130c, the fields excluding Zn and O In the mixture, the atomic ratio of In and M is preferably such that In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 7 The atomic content should be 5% or more. Also, the oxide semiconductor layer 130b should be excluding Zn and O. The atomic ratio of In and M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than 0 omic%, more preferably In is 34 atomic% or more, and M is 66 atomic%. It should be less than c%.

[0132] Furthermore, the oxide semiconductor layer 130b is composed of oxide semiconductor layer 130a and oxide semiconductor layer 130 It is desirable to have a higher indium content than carbon. In oxide semiconductors, heavy metals are primarily used for the s-railway. The pathway contributes to carrier conduction, and by increasing the In content, more s-trajectories are formed. Because the pathways overlap, oxides with a composition where In is greater than M are those with In equal to or less than M. Compared to the oxide that forms the final product, it has higher mobility. Therefore, it is incorporated into the oxide semiconductor layer 130b. By using oxides with a high zinc content, transistors with high field-effect mobility can be realized. It is possible.

[0133] The thickness of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is 3 nm to 100 nm. The following is preferably 3 nm to 50 nm. Also, the thickness of the oxide semiconductor layer 130b The wavelength is 3 nm to 200 nm, preferably 10 nm to 150 nm, and more preferably The wavelength shall be between 10 nm and 100 nm. In addition, the oxide semiconductor layer 130b is an oxide semiconductor It is preferable that the body layer 130a and the oxide semiconductor layer 130c are thicker than the body layer 130a.

[0134] Furthermore, in order to impart stable electrical characteristics to transistors using an oxide semiconductor layer as the channel This involves reducing the impurity concentration in the oxide semiconductor layer and making the oxide semiconductor layer intrinsically or substantially intrinsically Making it intrinsic (type i) is effective. Here, essentially intrinsic means the capacitance of the oxide semiconductor layer. Rear density is 1×10 19 / cm 3 It should be less than 1 × 10⁻⁶ 15 / cm 3 Not yet It must be full, more preferably 1 × 10 13 / cm 3 It is most preferably less than 1 x 10 8 / cm 3 Less than 1 × 10 -9 / cm 3 This refers to something that is greater than or equal to the above.

[0135] Furthermore, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main component are present. Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, making them carrier-dense. This increases the degree of the problem. Furthermore, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide semiconductor layer It is preferable to reduce the impurity concentration in the 130c layer and at each interface.

[0136] To make an oxide semiconductor layer intrinsically or substantially intrinsically, SIMS (Secondary In ion mass spectrometry analysis, for example, oxide semiconductors At a certain depth in the body layer, or in a certain region of the oxide semiconductor layer, the silicon concentration 1 x 10 19 atoms / cm 3Less than 5 × 10 18 atoms / cm 3 less than More preferably 1 × 10 18 atoms / cm 3 It shall be less than . Also, the hydrogen concentration is, for example For example, at a certain depth in the oxide semiconductor layer, or in a certain region of the oxide semiconductor layer , 2×10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 Below Below, fer 1 × 10 19 atoms / cm 3 More preferably 5 × 10 1 8 atoms / cm 3 The following applies. Furthermore, the nitrogen concentration is, for example, in the deep oxide semiconductor layer. In that region, or in a region of the oxide semiconductor layer, 5 × 10 19 ate / c m 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 1 8 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following ru.

[0137] Furthermore, if the oxide semiconductor layer contains crystals, and if silicon or carbon is present in high concentrations, the oxide will be affected. This can reduce the crystallinity of the semiconductor layer. This includes, for example, a certain depth in the oxide semiconductor layer, or a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1 × 10⁻⁶ 19 atoms / cm 3 Less than 5 × 10 1 8 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than It is sufficient that it has a portion. Also, for example, at a certain depth in the oxide semiconductor layer, In a region of the oxide semiconductor layer, the carbon concentration is set to 1 × 10⁻⁶. 19 atoms / cm 3 less than Preferably 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 at oms / cm 3 It is sufficient to have a portion that is less than [a certain value].

[0138] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor film in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current normalized by the transistor's channel width. This makes it possible to reduce the voltage to several yA / μm to several zA / μm.

[0139] Furthermore, silicon-containing insulating films are often used as gate insulating films for transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is a transient in one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating film, like a sta, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface. This can occur, and the field-effect mobility of the transistor may decrease. From this perspective as well It is preferable to keep the region that forms the channel of the oxide semiconductor layer away from the gate insulating film. .

[0140] Therefore, the oxide semiconductor layer 130 is divided into oxide semiconductor layer 130a and oxide semiconductor layer 130b By using a stacked structure of oxide semiconductor layer 130c, channels are formed in oxide semiconductor layer 130b. A transistor can be formed that has high field-effect mobility and stable electrical characteristics. It can form a ta.

[0141] Band structure of oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In this structure, the energy at the lower end of the conduction band changes continuously. This is because the oxide semiconductor layer 1 By making the compositions of 30a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c similar, This can also be understood from the fact that oxygen readily diffuses between them. Therefore, oxide semiconductor layer 130a The oxide semiconductor layer 130b and oxide semiconductor layer 130c are laminates of layers with different compositions. However, it can also be said that it is continuous in terms of physical properties, and in the drawings of this specification, the laminate is The interfaces are represented by dotted lines.

[0142] The oxide semiconductor layers 130, which are stacked with a common main component, are not simply stacked one layer at a time. Continuous junctions (in this case, U-shaped junctions where the energy at the lower end of the conduction band changes continuously between each layer) The structure is prepared so that a well structure (U-shaped well) is formed. That is, each layer If impurities that form defect levels such as trap centers or recombination centers are present at the interface A layered structure is formed in such a way. If impurities are mixed between the layers of the stacked oxide semiconductor layers, When this occurs, the continuity of the energy band is lost, and carriers are trapped or re-established at the interface. It disappears due to the combination.

[0143] For example, oxide semiconductor layer 130a and oxide semiconductor layer 130c have In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), oxide semiconductor layer 130b has In:Ga:Zn=1:1:1, 2: In-Ga-Zn oxides such as 1:3, 5:5:6, or 3:1:2 (atomic ratio). The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and The atomic ratios of the oxide semiconductor layer 130c are, respectively, positive of the above atomic ratios as an error. Includes a 20% fluctuation in index.

[0144] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b becomes a well, and the oxide In a transistor using a semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. This is achieved. Furthermore, the energy at the lower end of the conduction band of the oxide semiconductor layer 130 changes continuously. Therefore, it can also be called a U-shaped well. Furthermore, channels formed in this configuration... This can also be called an embedded channel.

[0145] Furthermore, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, and the silicon oxide film, etc. Near the interface with the insulating film, trap levels can form due to impurities and defects. Due to the presence of the semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 This allows us to move 0b away from the trap level.

[0146] However, the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c - When the difference between this and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductive layer 130b may exceed the energy difference and reach the trap level. The electrons that become the charge of the eggplant are trapped in the trap level, which affects the threshold voltage of the transistor. It shifts in the positive direction.

[0147] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the oxide semiconductor layer 130 a and the energy at the lower end of the conduction band of oxide semiconductor layer 130c, and oxide semiconductor layer 130b It is necessary to create a difference of a certain magnitude between the energy at the lower end of the conduction band and the energy at each The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0148] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0149] The gate insulating film 160 contains aluminum oxide, magnesium oxide, silicon oxide, and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more types of tantalum oxide can be used. Also, the gate insulating film 160 is The above materials may be laminated. Furthermore, the gate insulating film 160 may contain lanthanum (La) and nitrogen. It may also contain impurities such as zirconium (Zr).

[0150] Furthermore, an example of the layered structure of the gate insulating film 160 will be described. The gate insulating film 160 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0151] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, the physical film thickness can be made larger than the equivalent oxide film thickness, Even when the valence oxide film thickness is 10 nm or less or 5 nm or less, leakage due to tunnel current The current can be reduced. In other words, it is possible to realize a transistor with a small off-current. It is possible. Furthermore, hafnium oxide having a crystalline structure is similar to hafnium oxide having an amorphous structure. It has a higher relative permittivity compared to [unclear]. Therefore, it is used as a transistor with a small off-current. For this purpose, it is preferable to use hafnium oxide having a crystalline structure. Examples of crystalline structures Examples include monoclinic and cubic crystal systems. However, one aspect of the present invention is not limited to these. I can't.

[0152] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This may occur. The interface level may function as a trap center. Therefore, When hafnium oxide is placed in close proximity to the channel region of a transistor, the interface levels Therefore, the electrical characteristics of the transistor may deteriorate. To reduce the influence of the interface state, To achieve this, another film is placed between the transistor's channel region and the hafnium oxide. It is sometimes preferable to separate them from each other by doing so. This membrane has a buffering function. The buffering film may be a film included in the gate insulating film 160, or an oxide semiconductor film. It may also be a film included in the conductive film. That is, the film having a buffering function may be silicon oxide. Silicon oxide nitride, oxide semiconductors, etc., can be used. The film contains, for example, a semiconductor with a larger energy gap than the semiconductor that forms the channel region. Alternatively, an insulator may be used. Or, a film having a buffering function may have, for example, a channel region. A semiconductor or insulator with lower electron affinity than the semiconductor is used. Alternatively, a semiconductor with a buffering function is used. For example, the film may have a semiconductor with a higher ionization energy than the semiconductor that forms the channel region. Use a conductor or insulator.

[0153] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, the channel region and the hafny oxide If you place an insulator with a larger energy gap than hafnium oxide between the um and the other material... Alternatively, if a semiconductor or insulator with a lower electron affinity than hafnium oxide is placed in the environment, Good. Alternatively, for films with buffering properties, a higher ionization energy than hafnium oxide is used. A semiconductor or insulator can be placed. By using such an insulator, the interface state This makes it less likely for trapped charges to be released, and allows the charge to be retained for a long period of time. can.

[0154] Examples of such insulators include silicon oxide and silicon oxide-nitride. In order to trap charges in the interface levels within the insulating film 160, charges must be released from the oxide semiconductor layer 130. To move electrons toward the electrode layer 170, a specific example is to use high temperature ( For example, under temperatures between 125°C and 450°C (typically between 150°C and 300°C), The potential of the source electrode layer 170 is kept higher than the potential of the source electrode and drain electrode for more than 1 second. Generally, you should maintain it for more than one minute.

[0155] In this way, a desired amount of electrons is trapped in the interface state of the gate insulating film 160, etc. The threshold voltage shifts to the positive side. The voltage of the gate electrode layer 170, or the applied voltage... By adjusting the timing, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. This is possible. Furthermore, if charge can be captured, within the gate insulating film 160 It is not necessary. A laminated film with a similar structure may be used for other insulating layers.

[0156] The gate electrode layer 170 can be made of, for example, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, M Conductive films such as o, Ru, Ag, Mn, Nd, Sc, Ta, and W can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may be used. This may also be a laminate of multiple materials selected from alloys of the material and conductive nitrides of the above material. Typical examples include tungsten, tungsten and titanium nitride layers, and tungsten and titanium nitride. Laminated tantalum can be used. Also, low-resistance Cu or Cu-Mn alloys can be used. Alternatively, a laminate of the above material with a Cu or Cu-Mn alloy may be used. In this embodiment, The conductive layer 171 is made of tantalum nitride and the conductive layer 172 is made of tungsten, and the gate electrode layer 170 It forms.

[0157] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is preferable. As mentioned above, by using an insulating film containing hydrogen as the insulating layer 175, oxidation A portion of the semiconductor layer can be made n-type. Furthermore, the nitride insulating film blocks moisture and other elements. It also acts as a protective film, which can improve the reliability of transistors.

[0158] Furthermore, it is preferable that an insulating layer 180 is formed on the insulating layer 175. This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Cone, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, rayon oxide Using an insulating film containing one or more of tantalum, neodymium oxide, hafnium oxide, and tantalum oxide This is possible. Furthermore, the oxide insulating layer may be a laminate of the above-mentioned materials.

[0159] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the gate insulating film 160 to form oxides. Since it can be diffused into the channel formation region of the semiconductor layer 130, Oxygen can be supplied to the oxygen deficiency formed in the region. Therefore, a stable transient The electrical properties of the sta can be obtained.

[0160] The source electrode layer 140 and the drain electrode layer 150 contain, for example, Al, Cr, Cu, and Ta. Materials selected from Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the said metal materials A single layer or multiple layers of the material can be used. Typically, Ti, which readily bonds with oxygen, can be used. Also, because the subsequent process temperature can be relatively high, it is good to use W, which has a high melting point. It is preferable. Furthermore, even when using a laminate of the above material with low-resistance alloys such as Cu or Cu-Mn, Good. In this embodiment, conductive layer 141 and conductive layer 151 are coated with W, conductive layer 142 and conductive A source electrode layer 140 and a drain electrode layer 150 are formed in the electrode layer 152 using Cu.

[0161] The above material has the property of extracting oxygen from oxide semiconductor films. Therefore, when in contact with the above material... In some regions of the oxide semiconductor layer, oxygen is desorbed from the oxide semiconductor film, forming oxygen vacancies. The small amount of hydrogen contained in the membrane enters the oxygen vacancy, causing the region to become distinctly n-type. Therefore, the n-type region becomes the source or drain of the transistor. It can be made to work.

[0162] The source electrode layer 140, the drain electrode layer 150, and the insulating layer 180 have an insulating protective film. It is preferable to form layer 185. The insulating layer 185 is an insulating layer similar to the insulating layer 175. A film can be used. Furthermore, an aluminum oxide film can be used as the insulating layer 185. It can also do this. The aluminum oxide film is effective against both hydrogen, water and other impurities, and oxygen. The film has a high barrier effect that prevents the passage of light. Therefore, aluminum oxide film is used in transistors. Hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors during and after the manufacturing process. To prevent the inclusion of impurities such as the oxide semiconductor layer 130, and to prevent the main components of the oxide semiconductor layer 130 from being mixed in. Preventing the release of oxygen, a component material, from the oxide semiconductor layer, and eliminating the need for oxygen from the insulating layer 120. It is suitable for use as a protective film that has an effect of preventing release. It is also possible to diffuse the oxygen contained in the film into the oxide semiconductor layer.

[0163] Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, and the channel width shrinks. When reduced, the ON current decreases.

[0164] In transistors 103 to 109 according to one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be made larger.

[0165] Furthermore, in a transistor according to one aspect of the present invention, as described above, the oxide semiconductor layer 130 is Because the gate electrode layer 170 is formed so as to electrically surround the width direction of the flannel, the oxide For the semiconductor layer 130, in addition to the gate electric field from the vertical direction, a gate electric field from the lateral direction is also present. A field is applied. That is, a gate field is applied to the entire channel formation layer. As a result, the effective channel width is expanded, allowing for an even higher on-current.

[0166] Furthermore, in transistors 106 to 109 of one aspect of the present invention, the channel is shaped By forming the oxide semiconductor layer 130b on the oxide semiconductor layer 130a, the interface state This has the effect of making it difficult to form, and makes the oxide semiconductor layer 130b the middle layer of the three-layer structure. This also has the effect of eliminating the influence of impurities from above and below. In addition to improving the on-current of the transistor as described above, it also stabilizes the threshold voltage and the S value (sub The threshold value can be reduced. Therefore, Icut (gate voltage VG) This can reduce the current (at 0V) and thus reduce power consumption. By stabilizing the threshold voltage of the transistor, the long-term reliability of semiconductor devices is improved. This is possible. Furthermore, the transistor according to one aspect of the present invention has reduced degradation of electrical characteristics associated with miniaturization. Because this is suppressed, it can be said to be suitable for forming highly integrated semiconductor devices.

[0167] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0168] (Embodiment 3) In this embodiment, an oxide semiconductor that can be used in a transistor according to one aspect of the present invention is provided. Let's explain conductive films.

[0169] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0170] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0171] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0172] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) is used. Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors (such as ke Oxide Semiconductors).

[0173] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and nc-OS.

[0174] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses order but lacks long-range order.

[0175] Conversely, in the case of oxide semiconductors, which are inherently stable, a completely amorphous (complete) semiconductor is possible. It cannot be called an oxide semiconductor (ely amorphous). Furthermore, it is not isotropic. For example, an oxide semiconductor (having a periodic structure in a minute region) is made of a completely amorphous oxide It cannot be called a semiconductor. However, a-like OS exhibits periodicity in a minute region. Although it has a structure, it is porous and has an unstable structure. Therefore, in terms of physical properties, it is amorphous oxidation. It can be said to be similar to a semiconductor.

[0176] <caac-os> First, let me explain CAAC-OS.

[0177] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0178] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur.

[0179] The following describes CAAC-OS as observed by TEM. Figure 19(A) shows, This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, done in Japan. This is performed using an atomic-resolution analytical electron microscope, such as the JEM-ARM200F, manufactured by this electronics company. It is possible.

[0180] Figure 19(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 19(A). Figure 19(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is such that the surface forming the CAAC-OS film (also called the surface to be formed) Alternatively, it reflects the irregularities of the upper surface and is parallel to the surface or upper surface of the CAAC-OS that is formed.

[0181] As shown in Figure 19(B), CAAC-OS has a characteristic atomic arrangement. Figure 19(C) The characteristic atomic arrangement is shown with auxiliary lines. Figures 19(B) and 19(C) Therefore, the size of each pellet is approximately 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. Therefore, Lett can also be called a nanocrystal (nc). AC-OS, CANC (C-Axis Aligned nanocrystals) It can also be called an oxide semiconductor having [a certain characteristic].

[0182] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the To 5100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 19(D).) The tilt between the pellets observed in Figure 19(C) The area where the condensation is occurring corresponds to region 5161 shown in Figure 19(D).

[0183] Furthermore, Figure 20(A) shows the Cs in the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 20(A). Magnified Cs-corrected high-resolution TEM images are shown in Figures 20(B), 20(C), and 20(B), respectively. As shown in Figure 20(D). From Figures 20(B), 20(C), and 20(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0184] Next, the CA was analyzed by X-ray diffraction (XRD). Let's discuss AC-OS. For example, CAAC-OS, which has an InGaZnO4 crystal. In contrast, when structural analysis is performed using the out-of-plane method, as shown in Figure 21(A)... In some cases, a peak may appear at a diffraction angle (2θ) near 31°. This peak is in InGaZ Since it is attributed to the (009) plane of the nO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0185] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31°. In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak indicates that some of the crystals in CAAC-OS do not have c-axis orientation. This indicates that the more preferable CAAC-OS is the structural solution by the out-of-plane method. Analysis revealed a peak around 31° for 2θ, but no peak around 36° for 2θ.

[0186] On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 21(B). Furthermore, if it is a single-crystal oxide semiconductor of InGaZnO4, then fixing 2θ to around 56°, φs If this occurs, the pi is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 21(C). Six lines are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0187] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 68(A) (limited field transmission electron diffraction) is produced. Sometimes a pattern (also called a diffraction pattern) may appear. This diffraction pattern is indicative of InGaZnO4. The spot originates from the (009) plane of the crystal. Therefore, electron diffraction also reveals... The pellets contained in CAAC-OS have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be seen that it is oriented in a vertical direction. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. Figure 68(B) shows the diffraction pattern when an electron beam with a diameter of 300 nm is incident on the surface. Figure 68 (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also shows that It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. Note that the first ring in Figure 68(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be caused by the (100) surface, etc. Also, the second ring in Figure 68(B) is (110) This is thought to be caused by the surface, etc.

[0188] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is needed. CAAC-OS can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0189] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0190] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers It can become a source of emissions. Furthermore, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, it may act as a carrier source by capturing hydrogen.

[0191] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, the carrier density is set to 8 × 10⁻⁶. 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 The above can be achieved. This is called an intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0192] <nc-os> Next, I will explain nc-OS.

[0193] nc-OS is a region in which the crystalline part can be confirmed in high-resolution TEM images, and is clearly It has regions where the crystalline portion cannot be confirmed. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm. Oxide semiconductors with a crystal size greater than 10 nm and less than or equal to 100 nm are subjected to microcrystalline oxidation. It is sometimes called a solid semiconductor. nc-OS, for example, in high-resolution TEM images, shows grain boundaries. It may not be possible to confirm this clearly. Furthermore, nanocrystals are the pellets in CAAC-OS. They may share the same origin. Therefore, in the following, the crystalline portion of nc-OS will be referred to as a pellet. There are cases where this happens.

[0194] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. In some cases, it may be difficult to distinguish between them. For example, with nc-OS, X has a larger diameter than the pellet. When using lines, out-of-plane analysis detects peaks that indicate crystal planes. It is not released. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50n) is required. When electron diffraction is performed using an electron beam (of m or greater), a diffraction pattern similar to a halo pattern can be observed. It is measured. On the other hand, compared to nc-OS, the size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam of a certain diameter, spots can be observed. When nanobeam electron diffraction is performed on c-OS, a high-brightness ring-shaped pattern is observed. A region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this is the case.

[0195] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ).

[0196] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0197] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0198] a-like OS exhibits porosity (also called voids) in high-resolution TEM images. In some cases, the crystalline region can be clearly identified in high-resolution TEM images. It has a region where the crystalline part cannot be identified, and a region where the crystalline part cannot be identified.

[0199] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0200] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS ( Prepare Sample B (referred to as Sample B) and CAAC-OS (referred to as Sample C). The sample is also an In-Ga-Zn oxide.

[0201] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts.

[0202] The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0203] Figure 69 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 69, a-lik It can be seen that the crystalline portion of eOS increases in proportion to the cumulative amount of electron irradiation. As shown in (1) in Figure 69, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the initial nucleus), which was initially 4.2 × 10¹⁶ in size, changed when the cumulative irradiation dose reached 4.2 × 10¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS And CAAC-OS has a cumulative electron dose of 4.2 × 10⁻⁶ from the start of electron irradiation. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. Specifically, Figure As shown in (2) and (3) of 69, regardless of the cumulative dose of electrons, nc-OS and The size of the crystalline portion of CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively. It becomes clear that...

[0204] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It can be seen that it cannot be seen. That is, a-like OS is nc-OS and CAAC-O Compared to S, it is clear that it has an unstable structure.

[0205] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0206] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0207] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, the density equivalent to that of a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals.

[0208] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0209] This embodiment can be appropriately combined with other embodiments shown herein. .

[0210] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to the drawings.

[0211] In this specification, a display device refers to an image display device or a light source (illumination device, etc.). It also refers to connectors, such as FPC and TCP (Tape Carrier). A module with a package attached, and a printed circuit board is located beyond the TCP. Modules in which the drive circuit is directly mounted using the COG method, or modules in which the drive circuit is directly mounted on the display element. All wires are also included in the display device.

[0212] Figure 22 is a top view of a display device 500 according to one embodiment of the present invention. Note that in Figure 22, the diagram is clear. For clarity, some elements are enlarged, reduced, made transparent, or omitted in the illustration.

[0213] The display device 500 includes a pixel section 502 provided on a substrate 501, and a mechanism for driving the pixel section. The circuit section 504 and circuit section 505, and the pixel section 502, circuit section 504 and circuit section 50 A sealing material 512 is arranged to surround 5, and a base is provided facing the substrate 501. It has a board 507 and, for example, a signal line drive circuit (sourced The circuit section 505 may, for example, have a scan line drive circuit (gate driver). It is possible.

[0214] Substrates 501 and 507 are bonded together by a sealing material 512. Also, in Figure 22 Although not shown in the diagram, a display element is provided between substrate 501 and substrate 507. That is, a pixel. Section 502, circuit section 504, circuit section 505, and display element are connected to the substrate 501 and sealing material 51 It is sealed by 2 and substrate 507.

[0215] Furthermore, the display device 500 is located in the area surrounded by the sealing material 512 on the substrate 501. F is electrically connected to the pixel section 502, circuit section 504, and circuit section 505 in different regions. PC terminal section 508 (FPC: Flexible printed circuit) is provided. It gets kicked.

[0216] Furthermore, an FPC 516 is connected to the FPC terminal 508, and the pixel section is controlled by the FPC 516. Various signals are supplied to 502, circuit section 504 and circuit section 505. Also, pixel section 50 2. Signal lines 510 are connected to circuit section 504, circuit section 505, and FPC terminal section 508, respectively. They are connected. Various signals supplied by FPC516 are transmitted via signal line 510. It is supplied to the pixel section 502, the circuit section 504, and the circuit section 505.

[0217] In Figure 22, an example configuration is shown in which the circuit for driving the pixel section 502 is arranged in two regions. As shown, the configuration of the circuit is not limited to this. For example, the circuit can be combined into a single region. They may be arranged in this manner. Alternatively, the circuit may be divided into three or more parts and arranged in this manner. Only one of 504 and the circuit section 505 is formed on the substrate 501, and the other circuit is removed. You can add it to your order.

[0218] Furthermore, the circuit for driving the pixel unit 502 is the same as the transistor included in the pixel unit 502. It may be a configuration in which it is formed on a substrate 501, or COG (Chip On Glas It may also be a configuration in which IC chips are implemented, such as in s). That's fine.

[0219] Furthermore, the pixel section 502, circuit section 504, and circuit section 505 of the display device 500 are The device has multiple transistors in which the Nell-forming region is formed of an oxide semiconductor layer.

[0220] Transistors using oxide semiconductor layers have high mobility, thus reducing the area occupied by the transistor. This can be done to improve the aperture ratio. Furthermore, by using this transistor... Circuit sections 504 and 505 can also be formed on the same substrate as the pixel section 502. Furthermore, this transistor has an extremely low off-current, which allows for longer holding times of image signals, etc. This allows for a lower frame rate, thereby reducing the power consumption of the display device. It can be made to happen.

[0221] Furthermore, the oxide semiconductor layer preferably has crystals oriented along the c-axis. If an oxide semiconductor layer having the crystal is used in the channel formation region of the star, for example, a display device When bending the 500mm section, cracks are less likely to occur in the oxide semiconductor layer, thus improving reliability. It can be improved.

[0222] Therefore, by using a transistor with an oxide semiconductor layer, for example, amorphous silicon This allows for the formation of display devices that are superior to those using silicon layers or polycrystalline silicon layers.

[0223] The display elements included in the display device 500 typically include liquid crystal elements and light-emitting elements. It is possible.

[0224] Next, the liquid crystal display device 500a will be described. Figure 23 shows the liquid crystal elements in the display device 500. This is a cross-sectional view of the dashed line J1-J2 shown in Figure 22 when it is used.

[0225] The liquid crystal display device 500a includes a substrate 501, a first element layer, a second element layer, and a substrate 507 However, they are stacked in the order described above.

[0226] In Figure 23, the first element layer consists of transistors 550 and 552, and a planar insulating film 570. The second element layer includes a connecting electrode 560 and a conductive film 572. And, insulating film 534, colored layer 536 (color filter), light-shielding layer 538 (black matrix It has the above elements (Rix). In addition, the first element layer and the second element layer have the above elements Some of these may not be included. Also, other elements may be included.

[0227] Here, the first element layer and the second element layer are sealed by the liquid crystal layer 576 and the sealing material 512. This forms the liquid crystal element 575.

[0228] The liquid crystal display device 500a includes a wiring section 511, a pixel section 502, and a first circuit section 50 It has 4 and an FPC terminal section 508. The routing wiring section 511 is a signal line 510 It holds.

[0229] Furthermore, in the liquid crystal display device 500a, the pixel section 502 has a transistor 550, and the circuit section 3 This example illustrates a configuration in which transistors 552 are provided at point 04.

[0230] In Figure 23, the configuration of transistors 550 and 552 is an example. Not limited to these. Transistors 550 and 552 are appropriately sized (channel The length and channel width, or the number, can be changed. Also, in Figure 23... Although circuit section 505 is not shown, it can have the same configuration as circuit section 504.

[0231] The signal line 510 of the routing section 511 is connected to the source electrode layer of the transistor 550. It can be formed in the process of forming the drain electrode layer.

[0232] The FPC terminal section 508 includes a connecting electrode 560, an anisotropic conductive film 580, and an FPC 516. Furthermore, the connecting electrode 560 connects to the source electrode layer and drain electrode of the transistor 550. It can be formed in the layer formation process. In addition, the connecting electrode 560 has FPC516 The terminals are electrically connected via an anisotropic conductive film 580.

[0233] Furthermore, the signals connected to the transistors used in the pixel section and the drive circuit section. It is preferable to use wiring that contains copper as the wire. This reduces signal delays caused by wiring resistance, etc.

[0234] Furthermore, in Figure 23, a planar insulating film is shown on transistors 550 and 552. 570 is provided.

[0235] The planarizing insulating film 570 can be polyimide resin, acrylic resin, polyimideamide resin, Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin. It can be used. Furthermore, by stacking multiple insulating films formed from these materials, A planar insulating film 570 may be formed. Alternatively, a configuration without the planar insulating film 570 may be provided. That's good too.

[0236] Furthermore, one of the source electrode layer and drain electrode layer of transistor 550 is conductive The film 572 is electrically connected. The conductive film 572 is formed on the planar insulating film 570 and is a pixel It functions as an electrode, that is, one of the electrodes of the liquid crystal element. The conductive film 572 is visible light In this case, it is preferable to use a light-transmitting conductive film. For example, indium It is preferable to use a material containing one element selected from (In), zinc (Zn), and tin (Sn).

[0237] The liquid crystal element 575 has a conductive film 572, a conductive film 574, and a liquid crystal layer 576. 574 is provided on the substrate 507 side and functions as a counter electrode. The liquid crystal shown in Figure 23. The display device 500a controls the liquid crystal layer 5 by the voltage applied to the conductive film 572 and the conductive film 574. By changing the orientation state of 76 elements, the transmission and opacity of light can be controlled to display an image. can.

[0238] Although not shown in Figure 23, on the side of the conductive films 572 and 574 that is in contact with the liquid crystal layer 576 Alternatively, each component may be configured with an alignment film. In addition, polarizing members, phase difference members, and anti-reflective coatings may be used. Optical components (optical substrates) such as stoppers may be provided as appropriate. For example, polarizing substrates and position Circular polarization using a phase-difference substrate may also be used. Furthermore, backlights and sidelights may be used as light sources. You may use any of these.

[0239] Furthermore, a spacer 578 is provided between substrate 501 and substrate 507. This is a columnar spacer obtained by selectively etching the insulating film, and is located in the liquid crystal layer 57 It is provided to control the film thickness (cell gap) of 6. Note that spacer 578 is provided. A spherical spacer may also be used.

[0240] The liquid crystal materials constituting the liquid crystal layer 576 include thermotropic liquid crystals, low molecular weight liquid crystals, and polymers. Liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials, depending on the conditions, can be classified into cholesteric phase, smectic phase, cubic phase, and It exhibits iralnematic phase, isotropic phase, etc.

[0241] Furthermore, when employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases, and as the temperature of cholesteric liquid crystal is increased, the cholesteric phase This phase appears just before the transition from the blue phase to the isotropic phase. The blue phase only appears within a narrow temperature range. Therefore, to improve the temperature range, a liquid crystal composition containing several weight percent or more of chiral agents was added. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. It has a short response speed, is optically isotropic so orientation processing is unnecessary, and has low dependence on the viewing angle. Furthermore, since an alignment film does not need to be provided, rubbing treatment is also unnecessary. This prevents electrostatic discharge (ESD) damage caused by electrostatic discharge, and also prevents defects and breakage of liquid crystal displays during the manufacturing process. This can reduce losses.

[0242] Furthermore, when using liquid crystal elements as display elements, TN (Twisted Nematic) Modes, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmetry ric aligned Micro-cell) mode, OCB (Optical C Compensated Birefringence) mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro Modes such as electric liquid crystal can be used.

[0243] Furthermore, normally black liquid crystal display devices, such as those employing vertical alignment (VA) mode, are also available. It may also be used as a hyper-type liquid crystal display device. Several vertical alignment modes can be listed, but for example... For example, MVA (Multi-Domain Vertical Alignment) Code, PVA (Patterned Vertical Alignment) mode, ASV mode and other modes can be used.

[0244] Furthermore, the display method in the pixel section 502 may be a progressive method, an interlaced method, etc. It can be used. Furthermore, the color elements controlled by pixels when displaying color are RGB. It is not limited to the three colors (R represents red, G represents green, and B represents blue). For example, R pixels and G pixels. It may consist of four pixels: a pixel of color B and a pixel of color W (white). Alternatively, a pentile arrangement Thus, two of the RGB colors constitute one color element, and two different colors are selected based on the color element. You can select and configure them as follows. Alternatively, you can add one or more colors such as yellow, cyan, and magenta to RGB. This is also acceptable. Furthermore, the size of the display area for each dot of the color element may differ. Furthermore, the disclosed invention is not limited to a color display device, but also includes a monochrome display device. It can also be applied to display devices.

[0245] Next, we will describe the EL display device 500b using a light-emitting element. Figure 24 shows the display device 5 A cross-sectional view of the dashed line J1-J2 shown in Figure 22 when a light-emitting element is used for 00. Note that explanations that overlap with those for the liquid crystal display device 500a described above will be omitted.

[0246] The EL display device 500b includes a substrate 501, a first element layer 610, and a second element layer 611. The substrates 507 are stacked in the order described above.

[0247] In Figure 24, the first element layer 610 consists of transistors 550 and 552 and a planar insulating film 5 70, connecting electrode 560, light-emitting element 680, insulating film 530, signal line 510, connection It has an electrode 560. The second element layer 611 also has an insulating film 534 and a colored layer 536. It has a light-shielding layer 538 and a sealing layer. The first element layer 610 and the second element layer 611 are a sealing layer It is sealed by 632 and the sealing material 512. The first element layer 610 and the second In the element layer 611, some of the above elements may not be included. Also, other than the above It may also include the following elements.

[0248] The light-emitting element 680 has a conductive film 644, an EL layer 646, and a conductive film 648. The display device 500b displays an image when the EL layer 646 of the light-emitting element 680 emits light. It can display.

[0249] An insulating film 530 is provided on the conductive film 644 on the planarized insulating film 570. This covers a portion of the conductive film 644. The conductive film 644 has a high reflectivity to the light emitted by the EL layer. A conductive film is used, and the conductive film 648 is a conductive film that has high light transmittance to the light emitted by the EL layer. Thus, the light-emitting element 680 can be made into a top-emission structure. Also, the conductive film 64 4 uses a conductive film with high light transmittance to the light, and conductive film 648 has a reflectance to the light By using a highly conductive film, the light-emitting element 680 can be made into a bottom emission structure. Furthermore, both conductive film 644 and conductive film 648 have a conductive film that is highly transparent to the light in question. By using this, a dual emission structure can be achieved.

[0250] Furthermore, a colored layer 536 is provided in a position that overlaps with the light-emitting element 680, and overlaps with the insulating film 530. A light-shielding layer 538 is provided in the position, the routing wiring section 511, and the circuit section 504. The color layer 536 and the light-shielding layer 538 are covered with an insulating film 534. The light-emitting element 680 is insulated from the insulating film. The space between the films 534 is filled with a sealing layer 632. In the EL display device 500b, Although an example has been given of a configuration in which a colored layer 536 is provided, the configuration is not limited thereto. For example, an EL layer When 646 is formed by color separation, even if a colored layer 536 is not provided, good.

[0251] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0252] (Embodiment 5) In this embodiment, a transistor included in a display device according to one aspect of the present invention will be described. do.

[0253] The transistors included in one embodiment of the present invention's display device do not necessarily have to have a uniform structure. For example, a transistor included in the pixel section of a display device and the drive cycle for driving the pixel section. By using transistors with different configurations in the circuit, each is given electrical characteristics suitable for its respective purpose. This allows for improved reliability of the display device.

[0254] Furthermore, the transistors included in the drive circuit section have a double-gate structure, thereby creating an electric field. It is also possible to use transistors with high effective mobility.

[0255] Furthermore, the channel lengths of the transistors in the drive circuit and the pixel may differ. Specifically, the channel length of the transistors included in the drive circuit section should be less than 2.5 μm, or 1. The size can be between 45 μm and 2.2 μm. On the other hand, the transistors included in the pixel area The channel length can be 2.5 μm or more, or 2.5 μm to 20 μm. .

[0256] The channel length of the transistor included in the drive circuit is less than 2.5 μm, preferably 1.4 μm. By setting the size to between 5 μm and 2.2 μm, the transistors included in the pixel area are compared to the transistors in the pixel area. It is possible to increase the field effect mobility and thus increase the on-current. As a result, A drive circuit section capable of high-speed operation can be manufactured.

[0257] Furthermore, the high field-effect mobility of the transistors included in the drive circuit allows for a greater number of input terminals. It can be reduced.

[0258] The liquid crystal display device 500a shown in Figure 23 and the EL display device 500b shown in Figure 24 have pixel sections. The transistor 101 shown in Figure 1 is used as the transistor included in the drive circuit section. This is an example where transistor 104, shown in Figure 7, is used as the transistor to be used.

[0259] The transistors included in the pixel section respond to light irradiation from the backlight or EL element. A highly reliable transistor is desired. For example, one with an atomic ratio of In:Ga:Zn = 1:1:1. Alternatively, the film can be deposited using a sputtering method with a target material having an In:Ga:Zn ratio of 5:5:6. By using an oxide semiconductor layer in the channel formation region, a highly reliable channel can be formed against light irradiation. It can form a lunger.

[0260] On the other hand, transistors with high field-effect mobility are desirable for the drive circuit section. For example, using a material with an atomic ratio of In:Ga:Zn = 3:1:2 as the target. By using an oxide semiconductor layer deposited by sputtering as the channel formation region, the field effect transfer It is possible to form transistors with high precision.

[0261] In this embodiment, by making the oxide semiconductor layer of one of the transistors a stacked structure, the above Figures 25 and 26 show a method for easily manufacturing two types of transistors on the same substrate. This will be explained using the following. Note that the left side of the diagram shows the transistor used in the pixel section, as shown in Figure 1. An example of a cross-section in the channel length direction of transistor A, which has a similar configuration to transistor 101, is shown. Also, on the right side of the drawing, there is a transistor 10 shown in Figure 7, which is used in the drive circuit section. An example of a cross-section in the channel length direction of transistor B, which has a similar configuration to 4, is shown. The sign of an element common to both transistor A and transistor B should be applied to only one of them.

[0262] First, an insulating layer 120 is formed on the substrate 110. The type of substrate 110 and the insulating layer 120 The material can be described in the description of Embodiment 2. The insulating layer 120 is made by sputtering. They can be formed using methods such as CVD and MBE.

[0263] Furthermore, ion implantation, ion doping, and plasma immersion ions can be applied to the insulating layer 120. Oxygen may be added using methods such as the implantation method. By adding oxygen... This makes it possible to further facilitate the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130. Cut.

[0264] Furthermore, the surface of the substrate 110 is an insulator, and impurities will spread to the oxide semiconductor layer 130 that will be provided later. If there is no effect from dispersion, the insulating layer 120 can be omitted.

[0265] Next, on the insulating layer 120, the oxide semiconductor layer 130b of the transistor for the drive circuit is formed. The oxide semiconductor film 130B is deposited using sputtering, CVD, MBE, etc. ru.

[0266] Next, a resist mask 821 is formed in the drive circuit region using lithography (Figure 25). (See (A)). Then, using the resist mask, the oxide semiconductor film 130B is selectively removed. The oxide semiconductor layer 130b is formed by cutting (see Figure 25(B)).

[0267] Next, an oxide semiconductor film 130C is formed so as to cover the oxide semiconductor layer 130b.

[0268] Oxide semiconductor films are deposited using a multi-chamber type deposition system equipped with a load-lock chamber (e.g., spa It is preferable to deposit the film using a sputtering apparatus. Each chamber in the sputtering apparatus is acid To remove as much water and other impurities as possible from the semiconductor, a cryopump is used. High vacuum evacuation using an adsorption type vacuum pump (5 × 10 -7 Pa~1×10 -4 Pa degree The ability to perform the film deposition (up to a certain temperature) and the substrate to be film-deposited must be heated to 100°C or higher, preferably 500°C or higher. It is preferable that it be heated. Alternatively, a combination of a turbomolecular pump and a cold trap may be used. To prevent gases containing carbon components or moisture from flowing back into the chamber from the exhaust system, This is preferable. Also, using an exhaust system that combines a turbomolecular pump and a cryopump That's good too.

[0269] To obtain high-purity intrinsic oxide semiconductors, not only is the chamber evacuated to a high vacuum, but spa It is also necessary to increase the purity of the sputtering gas. The oxygen gas and argon gas used as sputtering gas are The dew point is -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using highly purified gas, the amount of moisture and other substances incorporated into the oxide semiconductor film can be minimized. It can be prevented.

[0270] The oxide semiconductor film 130B and the oxide semiconductor film 130C contain the oxide described in Embodiment 2. Materials for the semiconductor layer 130b and oxide semiconductor layer 130c can be used. In terms of form, for example, an oxide semiconductor film 130B has In:Ga:Zn=3:1:2 [original In-Ga-Zn oxide with a [number of particles] ratio, oxide semiconductor film 130C with In:Ga:Zn=1: In-Ga-Zn oxides with an atomic ratio of 1:1 or In:Ga:Zn=5:5:6 are used. They are present. Furthermore, the atomic ratios of oxide semiconductor film 130B and oxide semiconductor film 130C are, respectively, The above atomic ratio includes a variation of plus or minus 20% as an error. Also, the film deposition method is sharp When using the T method, the above materials can be used as targets for film deposition.

[0271] Furthermore, it is preferable to use the sputtering method for depositing oxide semiconductor films. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc., can be used.

[0272] After the formation of the oxide semiconductor film 130C, a first heat treatment may be performed. The first heat treatment is At a temperature of 250°C to 650°C, preferably 300°C to 500°C, an inert gas is used. This can be done in a smoky atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the first heat treatment is an inert gas atmosphere, after which the desorbed oxygen is replenished. To achieve this, the process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The first heat treatment This enhances the crystallinity of the oxide semiconductor film 130B and the oxide semiconductor film 130C, and further improves insulation. Layer 120, oxide semiconductor film 130B, and oxide semiconductor film 130C release hydrogen, water, and other impurities. Pure substances can be removed. The first heat treatment is performed on the oxide semiconductor layer 130, which will be described later. This may be performed after etching to form the stack of b and the oxide semiconductor layer 130c.

[0273] Next, a resist mask 822 is formed in the pixel area using lithography. Tomask 823 is used in the drive circuit region for oxide semiconductor layer 130b and oxide semiconductor film 1 It is formed on a laminate consisting of 30C (see Figure 25(C)).

[0274] Next, using the above resist mask, the oxide semiconductor film 130C is selectively etched. An oxide semiconductor layer 130c is formed in the pixel region. Also, an oxide semiconductor layer 1 is formed in the drive circuit region. A stack consisting of 30b and an oxide semiconductor layer 130c is formed (see Figure 25(D)). In this case, the oxide semiconductor layer 130c in the drive circuit region covers the oxide semiconductor layer 130b. It is formed in this way.

[0275] Next, the oxide semiconductor layer of the pixel region and the oxide semiconductor layer 130b of the drive circuit region An insulating film 160a, which will serve as a gate insulating film, is formed on a stack made of oxide semiconductor layers 130c. The insulating film 160a can be used as the gate insulating film 160 described in Embodiment 3. It can be formed using any material. For forming the insulating film 160a, sputtering, CVD, and MBE methods can be used. These can be used.

[0276] Next, conductive films 171a and 172, which will form the gate electrode layer 170, are placed on the insulating film 160a. a is formed. Conductive film 171a and conductive film 172a form the gate as described in Embodiment 2. It should be formed from a material that can be used for the electrode layer 170. Conductive film 171a and conductive film For the formation of 172a, sputtering, CVD, MBE, etc. can be used (Figure 2). 6(A)).

[0277] Next, a resist mask 824 is formed on the conductive film 172a, and using the resist mask The conductive film 172a, conductive film 171a, and insulating film 160a are selectively etched, and A gate electrode layer 170 and a gate insulating film 160 are formed.

[0278] Next, with the resist mask 824 formed in the above process remaining, region 231 and region By adding impurity 830, which forms an oxygen vacancy in 232, the resistance is reduced, and the source region and the It forms a rain region (see Figure 26(B)). For example, argon is used as the impurity 830. It is added using a plasma treatment method.

[0279] The above resist mask is altered by argon plasma, so oxygen ashing is performed to remove it. It is preferable to remove it.

[0280] Next, an insulating layer 175 is formed on the above configuration. The material of the insulating layer 175 is as described in Embodiment 2. You can refer to this. Also, the insulating layer 175 can be made using sputtering, CVD, MBE, etc. It can be formed with.

[0281] Next, an insulating layer 180 is formed on the insulating layer 175 (see Figure 26(C)). The material can be described in the description of Embodiment 2. Furthermore, the insulating layer 180 is sputtered. It can be formed using methods such as CVD, MBE, etc.

[0282] Next, a resist mask is formed on the insulating layer 180, and the insulating layer 1 is formed using the resist mask. Selectively etch 80 and the insulating layer 175, leading to regions 231 and 232 Forms a contact hole.

[0283] Next, a conductive film is formed to cover the contact hole, and the conductive film is selectively etched. The conductive film is formed by this process. The material can be described in the description of Embodiment 2. Furthermore, the conductive film is sputtered. It can be formed using methods such as CVD, MBE, etc.

[0284] Next, an insulating layer 185 is formed on the above configuration (see Figure 26(D)). Material of the insulating layer 185 For further details, please refer to the description of Embodiment 3. Also, the insulating layer 185 is formed by sputtering, It can be formed using methods such as CVD and MBE.

[0285] Furthermore, plasma treatment, ion implantation, and ion treatment are performed on the insulating layer 180 and / or insulating layer 185. Using methods such as doping and plasma immersion ion implantation, oxygen Oxygen may be added. By adding oxygen, insulating layer 180 and / or insulating layer 1 This makes it even easier to supply oxygen from 85 to the oxide semiconductor layer.

[0286] Next, a second heat treatment may be performed. The second heat treatment is performed under the same conditions as the first heat treatment. This can be done. The second heat treatment results in insulating layer 120, insulating layer 180, insulating layer 18 From step 5, excess oxygen is more easily released, reducing oxygen vacancies in the oxide semiconductor layer. ru.

[0287] In the above process, a transistor having a stacked oxide semiconductor layer and a single-layer structure A transistor having an oxide semiconductor layer can be easily formed on the same substrate. It has a pixel section that is capable of high-speed operation, has minimal degradation from light illumination, and has excellent display quality. A display device can be manufactured.

[0288] In this embodiment, various films such as metal films, semiconductor films, and inorganic insulating films are typically... These can be formed by sputtering or plasma CVD, but other methods, such as heat It may also be formed by the CVD (Chemical Vapor Deposition) method. An example of a thermal CVD method is MOCVD (Metal Organic Chemical). (Atomic Layer Deposition) and ALD (Atomic Layer Deposition) Examples include the eposition method.

[0289] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0290] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0291] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber, and sequentially supplying the raw material gases for the reaction. The gas may be introduced into a chamber, and the film deposition may be carried out by repeating the sequence of gas introduction. Switching between each switching valve (also called a high-speed valve) allows for the processing of two or more raw materials. The gases are supplied to the chamber in sequence, and the first raw material gas is supplied in order to prevent the mixing of multiple raw material gases. Simultaneously or afterward, an inert gas (such as argon or nitrogen) is introduced, and the second source Introducing a carrier gas. If an inert gas is introduced at the same time, the inert gas will be used as a carrier. It becomes a gas, and an inert gas may also be introduced simultaneously when introducing the second raw material gas. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the second The raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate to form the first layer. Then, it reacts with a second raw material gas that is introduced later, and the second layer is laminated on top of the first layer to form a thin film. This process is repeated multiple times while controlling the gas introduction sequence until the desired thickness is achieved. This allows for the formation of a thin film with excellent step coverage. The thickness of the thin film is determined by repeating the gas introduction sequence. Because it can be adjusted by the number of repetitions, precise film thickness adjustment is possible, and fine F It is suitable for creating extracorporeal membranes (ETs).

[0292] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -ZnO X (X>0) When forming a film, use trimethylindium and trimethylgal Trimethylindium and dimethylzinc can be used. The chemical formula for trimethylindium is It is In(CH3)3. Also, the chemical formula for trimethylgallium is Ga(CH3)3. Yes. Also, the chemical formula for dimethylzinc is Zn(CH3)2. Furthermore, combinations of these... Not limited to wasabi, triethylgallium (chemical formula Ga(C2)) can be used instead of trimethylgallium. H5)3) can also be used, and diethylzinc (chemical formula Zn(C2) H5)2) can also be used.

[0293] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrak The raw material gas is vaporized dimethylamide hafnium (TDMAH), and the oxidizing agent is O Two types of gases, O3, are used. Furthermore, the chemical reaction of tetrakisdimethylamidehafnium... The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(eth Examples include methylamide (hafnium).

[0294] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent And vaporize a liquid containing an aluminum precursor compound (such as trimethylaluminum TMA). Two types of gases are used: the raw material gas and H2O as the oxidizing agent. The chemical formula for nium is Al(CH3)3. Other material liquids include Tris(dimethyl) Aluminum (Aluminum), Triisobutylaluminum, Aluminum Tris(2,2, Examples include 6,6-tetramethyl-3,5-heptanedione.

[0295] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0296] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by simultaneously introducing gas and H2 gas. Note that B2H6 gas can be used instead. SiH4 gas may also be used.

[0297] For example, oxide semiconductor films, such as In-Ga-ZnO, can be deposited using an ALD (Advanced Laser Deposition) system. X (X>0) When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. Then an In-O layer is formed, and after that, Ga(CH3)3 gas and O3 gas are introduced simultaneously to G An aO layer is formed, and then Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. To achieve. Note that the order of these layers is not limited to this example. Also, by mixing these gases, In - Mixed compound layers such as Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers may be formed. Furthermore, H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas. While it is also possible to use [another gas], it is preferable to use O3 gas that does not contain H. Also, In(CH3) Instead of gas 3, In(C2H5)3 gas may be used. Alternatively, Ga(CH3)3 gas may also be used. Alternatively, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. You can.

[0298] This embodiment can be appropriately combined with other embodiments shown herein. .

[0299] (Embodiment 6) This embodiment describes an example of the configuration of a display device using a transistor according to one aspect of the present invention. explain.

[0300] [Example Configuration] Figure 27(A) is a top view of a display device according to one embodiment of the present invention, and Figure 27(B) is an embodiment of the present invention. This describes a pixel circuit that can be used when applying liquid crystal elements to the pixels of a display device in one embodiment. This is a circuit diagram for doing so. Also, Figure 27(C) shows the pixels of a display device according to one embodiment of the present invention. This is a circuit diagram illustrating a pixel circuit that can be used when applying an EL element. .

[0301] The transistors placed in the pixel area can be formed according to the above embodiment. Since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A portion of the drive circuit, which can be constructed using a single-type transistor, is identical to the transistors in the pixel section. It is formed on a substrate. In this way, the pixel portion and the driving circuit are formed with the transistors shown in the above embodiment. By using this, a highly reliable display device can be provided.

[0302] An example of a top view of an active-matrix display device is shown in Figure 27(A). The display device's substrate. On 700 are the pixel section 701, the scan line drive circuit 702, the scan line drive circuit 703, and the signal line drive circuit. It has a drive circuit 704. Multiple signal lines extend from the signal line drive circuit 704 to the pixel section 701. They are arranged in an extended manner, and multiple scan lines are driven by scan line drive circuit 702 and scan line drive circuit 703 They are arranged in an extended manner. Furthermore, the intersection regions of the scan lines and signal lines each have display elements. The pixels are arranged in a matrix. Also, the substrate 700 of the display device is FPC (Fl Timing control via connection parts such as a Printed Circuit It is connected to a circuit (also called a controller or control IC).

[0303] Figure 27(A) shows the scan line drive circuit 702, scan line drive circuit 703, and signal line drive circuit 70 4 is formed on the same substrate 700 as the pixel section 701. Therefore, the drive circuit provided externally Since the number of such components is reduced, costs can be reduced. Also, outside the circuit board 700 When a moving circuit is added, it becomes necessary to extend the wiring, increasing the number of connections between wires. When the drive circuit is placed on the 700, the number of connections between the wires can be reduced, improving reliability. This can improve production efficiency or yield.

[0304] [Liquid crystal display device] Furthermore, an example of the pixel circuit configuration is shown in Figure 27(B). Here, as an example, a VA-type liquid crystal display... This shows a pixel circuit that can be applied to the pixels of a display device.

[0305] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0306] The gate wiring 712 of transistor 716 and the gate wiring 713 of transistor 717 are They are separated so that different gate signals can be applied. Meanwhile, data line 714 This is used in common in transistors 716 and 717. Transistor 7 16 and transistor 717 may be replaced with transistors as described in the above embodiment. Yes, it is possible. This makes it possible to provide a highly reliable liquid crystal display device.

[0307] A first pixel electrode layer electrically connected to transistor 716, and an electrical connection between transistor 717 and transistor 717. The shape of the second pixel electrode layer that connects to the first pixel electrode layer will be described. The shape of the electrode layers is separated by slits. The first pixel electrode layer spreads out in a V-shape. The second pixel electrode layer has a shape, and is formed to surround the outside of the first pixel electrode layer.

[0308] The gate electrode of transistor 716 is connected to the gate wiring 712, and the gate electrode of transistor 717 The gate electrode is connected to gate wiring 713. Gate wiring 712 and gate wiring 713 By applying different gate signals, the operating timing of transistors 716 and 717 is determined. By varying the parameters, the alignment of the liquid crystals can be controlled.

[0309] Furthermore, the capacitive wiring 710, the gate insulating film which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0310] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in each pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. ru.

[0311] Note that the pixel circuit shown in Figure 27(B) is not limited to this. For example, as shown in Figure 27(B) A new switch, resistor, capacitive element, transistor, sensor, or logic circuit can be added to the pixel. You may add things like this.

[0312] [Organic EL display device] Another example of a pixel circuit configuration is shown in Figure 27(C). Here, a display using an organic EL element is shown. The pixel structure of the device is shown.

[0313] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0314] Figure 27(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown in which two lampistors are used for one pixel. Note that the metal oxide film in one aspect of the present invention is It can be used in the channel formation region of an n-channel type transistor. The basic circuit can be fitted with digital time-based gradation driving.

[0315] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0316] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light-emitting element. It has a sub-element 724 and a capacitive element 723. The switching transistor 721 is a The source electrode layer is connected to scan line 726, and the first electrode (source electrode layer and drain electrode layer) One side is connected to signal line 725, and the second electrode (the other side of the source electrode layer and drain electrode layer) is connected to signal line 725. ) is connected to the gate electrode layer of the drive transistor 722. In 22, the gate electrode layer is connected to the power line 727 via the capacitive element 723, and the first electrode is electrically... The power line 727 is connected, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is identical. It is electrically connected to a common potential line formed on the substrate.

[0317] Other embodiments include the switching transistor 721 and the driving transistor 722. The transistors described below can be used as appropriate. This allows for highly reliable organic LEDs. A display device can be provided.

[0318] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GND. The forward threshold of the light-emitting element 724 The high and low power supply potentials are set so that they are equal to or greater than the value voltage, and the potential difference between them is used to power the light-emitting element 724 By applying a current to the light-emitting element 724, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is... Includes high-value voltage.

[0319] Furthermore, the capacitive element 723 is replaced by the gate capacitance of the drive transistor 722, thus saving space. It can be abbreviated. Regarding the gate capacitance of the drive transistor 722, the channel formation region and the gate A capacitance may be formed between the electrode layer and the electrode layer.

[0320] Next, we will explain the signal input to the drive transistor 722. Voltage input Voltage drive method In this case, the driving transistor 722 is either fully on or completely off. A video signal like this is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for the drive. It is applied to the gate electrode layer of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0321] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 72 A voltage greater than or equal to the sum of the forward voltage of 4 and the threshold voltage Vth of the drive transistor 722 is required. The video signal is input so that the drive transistor 722 operates in the saturation region. Then, current is passed to the light-emitting element 724. Also, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, a current corresponding to the video signal is supplied to the light-emitting element 724. It can perform analog grayscale driving.

[0322] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 27(C). For example, Figure 27 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or You can add circuits and other components.

[0323] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 27, the low potential The source electrode (first electrode) is on the side with the high potential, and the drain electrode (second electrode) is on the high potential side with the electrical currents. The configuration is designed to connect them precisely. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. The second gate electrode is connected to the source electrode via wiring (not shown) at a potential lower than the potential applied to the source electrode. The configuration should be such that it can accept the potential values ​​exemplified above.

[0324] For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having a sub-element and a light-emitting element, can be used in various forms or It can have various elements. Display elements, display devices, light-emitting elements, or light-emitting devices are, for example, EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) (etc.), transistors (transistors that emit light in response to current), electron emission elements, liquid crystal elements Electronic ink, electrophoretic elements, grating light bulbs (GLV), plasma displays Using PDP (Photographic Display Panel) and MEMS (Micro-Electro-Mechanical Systems) Display elements, digital micromirror devices (DMDs), DMSs (digital micromirrors) Shutter), MIRASOL (registered trademark), IMOD (Interference Module) MEMS display elements (mechanisms), shutter-type MEMS display elements, optical interference type MEMS display elements , electrowetting elements, piezoelectric ceramic displays, carbon nanotubes It has at least one display element that uses electrical or magnetic A display medium having properties such as contrast, brightness, reflectance, and transmittance that change due to atmospheric effects. It is acceptable to have them. An example of a display device using EL elements is an EL display. An example of a display device using an electron emission element is a field emission display ( FED) or SED flat-panel display (SED: Surface-conductive) Examples include liquid crystal elements (e.g., ion Electron-emitter Display). An example of a display device using this method is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples include displays. Electronic ink, electronic powder fluid (registered trademark), or electrophoretic elements. Examples of display devices used include electronic paper. (Note: Semitransmissive liquid crystal displays...) When realizing ray or reflective liquid crystal displays, some or all of the pixel electrodes are, The goal is to have it function as a reflective electrode. For example, a part or all of the pixel electrodes. The part should be made of aluminum, silver, etc. Furthermore, in that case, the reflective electrode It is also possible to install memory circuits such as SRAM below it. This further reduces consumption It can reduce power consumption.

[0325] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0326] (Embodiment 7) In this embodiment, a display module to which a semiconductor device according to one aspect of the present invention is applied is shown in Figure We will use item 28 to provide the explanation.

[0327] The display module 8000 shown in Figure 28 consists of an upper cover 8001 and a lower cover 8002. In between, the touch panel 8004 is connected to the FPC8003, and the FPC8005 is connected to the touch panel 8004. Display panel 8006, backlight unit 8007, frame 8009, printed circuit board It has 8010 and battery 8011. Furthermore, it has a backlight unit 8007 and battery Features such as the Lee 8011 and Touch Panel 8004 may not be available.

[0328] A semiconductor device according to one aspect of the present invention can be used, for example, as a display panel 8006.

[0329] The upper cover 8001 and the lower cover 8002 are the touch panel 8004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the RU8006.

[0330] The touch panel 8004 is a resistive or capacitive touch panel. It can be used superimposed on 006. Also, the opposing substrate (encapsulation substrate) of the display panel 8006. It is also possible to give the display panel 8 a touch panel function. It is also possible to install a light sensor in each pixel of 006 to create an optical touch panel. Alternatively, an electrode for a touch sensor is provided within each pixel of the display panel 8006, and a capacitive type touch panel is installed. It is also possible to use Nell.

[0331] The backlight unit 8007 has a light source 8008. The light source 8008 is used as the backlight. A configuration using a light-diffusing plate, which is provided at the end of unit 8007, may also be used.

[0332] Frame 8009 provides protection for the display panel 8006, as well as the operation of the printed circuit board 8010. It has the function of an electromagnetic shield to block electromagnetic waves generated by [unclear]. The Mu8009 may also function as a heat sink.

[0333] The printed circuit board 8010 is a power supply circuit and a signal for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. This is also fine, or a separate battery 8011 may be used. The battery 8011 can be omitted.

[0334] Furthermore, the display module 8000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0335] This embodiment can be appropriately combined with other embodiments shown herein. .

[0336] (Embodiment 8) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. I will explain by referring to it.

[0337] [Cross-sectional structure] Figure 29(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Semiconductor shown in Figure 29(A) The device has a transistor 2200 made of a first semiconductor material at the bottom and a second semiconductor material at the top. It has a transistor 2100 made of a conductive material. Figure 29(A) shows the second semiconductor As the transistor 2100 using the material, the transistor exemplified in the previous embodiment is suitable An example of its use is shown. Note that the area to the left of the dashed line is a cross-section of the transistor in the direction of the channel length. The right side shows a cross-section in the channel width direction.

[0338] It is preferable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum (e.g., gallium arsenide, indium phosphide, gallium nitride, organic semiconductors) and the second semiconductor The material can be an oxide semiconductor. Alternatively, single-crystal silicon can be used as a material other than an oxide semiconductor. Transistors using such materials can easily operate at high speeds. On the other hand, transistors using oxide semiconductors Rangitors have a low off-current.

[0339] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either type of transistor is acceptable, and the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses a synthetic semiconductor, the materials and structure used are as follows: However, it is not necessary to limit the specific configuration of the semiconductor device shown here to what is presented.

[0340] In the configuration shown in Figure 29(A), an insulating film 2201 and an insulating film are placed on top of the transistor 2200. Transistor 2100 is provided via 2207. Also, transistor 2200 Multiple wires 2202 are provided between the transistor 2100 and the transistor. Multiple plugs 2203 embedded in the edge film allow wiring to be provided in the upper and lower layers, respectively. The electrodes are electrically connected. Also, the insulating film 2204 covering the transistor 2100 and The wiring 2205 is on the insulating film 2204 and has the same conductivity as the pair of electrodes of the transistor 2100. A wiring 2206 obtained by processing a film is provided.

[0341] In this way, by stacking two types of transistors, the circuit footprint is reduced. Multiple circuits can be arranged at a higher density.

[0342] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer, Hydrogen in the insulating film provided near the semiconductor film of transistor 2200 is in the silicon dung. This terminates the ring bond and improves the reliability of transistor 2200. On the other hand, When an oxide semiconductor is used for the transistor 2100 located in the upper layer, transistor 21 Hydrogen in the insulating film placed near the semiconductor film generates carriers in the oxide semiconductor. This can be one of the contributing factors, and therefore can reduce the reliability of transistor 2100. Therefore, an oxide layer is found on the upper layer of the transistor 2200 using silicon-based semiconductor material. When stacking transistors 2100 made of solid semiconductor material, hydrogen diffusion occurs between them. Providing an insulating film 2207 that has the function of preventing this is particularly effective. As a result of step 7, the reliability of transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, which affects transistor 2100. Reliability can also be improved at the same time.

[0343] Examples of insulating film 2207 include aluminum oxide, aluminum oxide nitride, and galvanic oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0344] Furthermore, the transistor 2100, which is composed of an oxide semiconductor film, is covered by the transistor A block film 2208 (transistor) has the function of preventing hydrogen diffusion on the 2100. It is preferable to form an insulating layer (corresponding to the insulating layer 180 in transistors 101 to 103). The lock film 2208 can be made of the same material as the insulating film 2207, especially oxidation It is preferable to use aluminum. The aluminum oxide film contains impurities such as hydrogen and moisture. It has a high blocking effect, preventing the permeation of both substances and oxygen through the membrane. Therefore, an aluminum oxide film is used as the block film 2208 covering the transistor 2100. This prevents the desorption of oxygen from the oxide semiconductor film contained in transistor 2100. Furthermore, it is possible to prevent the ingress of water and hydrogen into the oxide semiconductor film.

[0345] Note that the 2200 transistor is not only a planar type transistor, but also various types It can be a transistor. For example, a FIN type, a TRI-GATE (transistor) It can be a transistor of the lygate type, etc. An example of a cross-sectional view in that case is shown below. As shown in Figure 29(D), an insulating film 2212 is provided on the semiconductor substrate 2211. The conductive substrate 2211 has a thin protrusion (also called a fin) at its tip. An insulating film may be provided. When forming the protrusions, the insulating film is provided on the semiconductor substrate 2 This acts as a mask to prevent the 211 from being etched. The convex part does not have to have a thin tip; for example, it may be a roughly rectangular convex part, or it may have a thick tip. It may also be a convex portion. A gate insulating film 2214 is provided on the convex portion of the semiconductor substrate 2211. It is kicked, and a gate electrode 2213 is provided on it. The semiconductor substrate 2211 is The source region and drain region 2215 are formed here. Although 2211 shows an example having a protrusion, the semiconductor device according to one aspect of the present invention is not limited to this. It is not specified. For example, it is acceptable to process an SOI substrate to form a semiconductor region having a protrusion. do not have.

[0346] [Circuit Configuration Example] In the above configuration, the connection configuration of the electrodes of transistor 2100 and transistor 2200 is different. By generating the signal, various circuits can be constructed. Below, one aspect of the present invention is described. This section describes an example of a circuit configuration that can be realized using semiconductor devices.

[0347] [CMOS circuit] The circuit diagram shown in Figure 29(B) is a p-channel type transistor 2200 and an n-channel type transistor This is a so-called CMO (Continuously Multi-Motorized) configuration, where two Rangitar 2100s are connected in series, and each gate is connected. This shows the configuration of an S-circuit.

[0348] [Analog switch] Furthermore, the circuit diagram shown in Figure 29(C) shows the relationship between transistor 2100 and transistor 2200. This shows a configuration where the source and drain are connected. With this configuration, It can function as a so-called analog switch.

[0349] [Examples of storage devices] Using a transistor according to one aspect of the present invention, the stored contents can be preserved even when power is not supplied. Figure 30 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0350] The semiconductor device shown in Figure 30(A) is a transistor 3200 using a first semiconductor material and a second It has a transistor 3300 and a capacitive element 3400 made of two semiconductor materials. The transistor 3300 used is the transistor described in the above embodiment. It is possible.

[0351] Figure 30(B) shows a cross-sectional view of the semiconductor device shown in Figure 30(A). Now, the configuration shown has a back gate added to transistor 3300, but the back gate A configuration without this feature is also acceptable.

[0352] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. The 3300 transistor has a low off-current, so by using it... It is possible to retain memory content for a long period of time. In other words, it does not require a refresh operation. To avoid this, or to create a semiconductor memory device with an extremely low refresh frequency. This makes it possible to significantly reduce power consumption.

[0353] In Figure 30(A), wiring 3001 is electrically connected to the source electrode of transistor 3200. The wiring 3002 is then electrically connected to the drain electrode of transistor 3200. Furthermore, wiring 3003 connects to either the source or drain electrode of transistor 3300. Electrically connected, wiring 3004 is electrically connected to the gate electrode of transistor 3300. And the gate electrode of transistor 3200 is connected to the socket of transistor 3300. The other electrode of the drain electrode and one of the electrodes of the capacitive element 3400 are electrically connected. The wiring 3005 is electrically connected to the other electrode of the capacitive element 3400.

[0354] In the semiconductor device shown in Figure 30(A), the potential of the gate electrode of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, retain, and read information in the following ways: ru.

[0355] This section explains how to write and retain information. First, the potential of wiring 3004 is set by the transistor Set the potential to the point where transistor 3300 is ON, and turn on transistor 3300. As a result, the potential of wiring 3003 is the gate electrode of transistor 3200, and the capacitive element 3 It is given to 400. That is, a predetermined charge is given to the gate of transistor 3200. (to be written). Here, a charge that gives two different potential levels (hereinafter referred to as Low level) It is assumed that either a low charge or a high-level charge is applied. Then, wiring Set the potential of 3004 to the potential at which transistor 3300 is in the off state, and then set transistor 3 By turning off 300, the charge applied to the gate of transistor 3200 To be retained (retained).

[0356] Because the off-current of transistor 3300 is extremely small, the gate of transistor 3200 The electric charge is retained for a long period of time.

[0357] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to wiring 3001... In this state, when an appropriate potential (readout potential) is applied to wiring 3005, transistor 3200 Depending on the amount of charge held in the gate, wiring 3002 takes on different potentials. Generally, If the transistor 3200 is an n-channel type, then the gate electrode of the transistor 3200 will have a High Apparent threshold V when level charge is given th_H is transistor 320 Apparent threshold V when a low-level charge is applied to a terminal electrode with zero charge. th_L This is because it becomes lower. Here, the apparent threshold voltage is defined as the transistor 3200 Refers to the potential of the wiring 3005 required to set it to the "on state". Therefore, by setting the potential of the wiring 3005 to the potential V0 between V and V th_H and V th_L , the charge applied to the gate of the transistor 3200 can be determined. For example, in writing, when a high-level charge is applied, if the potential of the wiring 3005 becomes V0 (> V ), the transistor 3200 will be in the "on state". When a low-level charge is applied, even if the potential of the wiring 3005 becomes V0 (< V ), the transistor 3 th_H ) 200 will remain in the "off state". Therefore, by determining the potential of the wiring 3002, the information stored can be read out. th_L ) and the transistor 3 200 remains in the "off state". Thus, by determining the potential of the wiring 3002, the stored information can be read.

[0358] When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. If the information is not read in this way, a potential such that the transistor 3200 is in the "off state" regardless of the state of the gate, that is, a potential smaller than V , may be applied to the wiring 3005. Or, a potential such that the transistor 3200 is in the "on state" regardless of the state of the gate, that is, a potential larger than V , may be applied to the wiring 3005. th_H

[0359] th_L

[0360] The semiconductor device shown in FIG. 30(C) is different from FIG. 30(A ) in that it does not have the transistor 3200. In this case as well, the information writing and holding operations are possible by the same operation as described above.

[0360] Next, the information reading will be described. When the transistor 3300 is in the on state, the floating The idle wiring 3003 and the capacitive element 3400 are electrically connected, and the wiring 3003 and the capacitive element 34 Charge is redistributed between 00 and 00. As a result, the potential of wiring 3003 changes. Wiring 300 The change in potential at 3 is the potential at the first terminal of the capacitive element 3400 (or the potential at the capacitive element 3400) It takes on different values ​​depending on the charge accumulated therein.

[0361] For example, let V be the potential of the first terminal of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and let C be the wiring The capacitance component of 3003 is CB, and the potential of wiring 3003 before charge redistribution is VB0. Therefore, the potential of wiring 3003 after the charge has been redistributed is (CB × VB0 + C × V) / (CB+C). Therefore, the state of the memory cell is the first state of the capacitive element 3400. If the terminal potential can take two states, V1 and V0 (V1 > V0), then maintaining potential V1... In this case, the potential of wiring 3003 (=(CB×VB0+C×V1) / (CB+C)) is, The potential of wiring 3003 when V0 is held is (=(CB×VB0+C×V0) / (CB It can be seen that it will be higher than +C).

[0362] Then, by comparing the potential of wiring 3003 with a predetermined potential, information can be read out. ru.

[0363] In this case, the first semiconductor material described above was applied to the drive circuit for driving the memory cell. A transistor is used, and a second semiconductor material is applied to transistor 3300. The zistas can be stacked on top of the drive circuit.

[0364] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0365] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as degradation of the gate insulating film are less likely to occur. In other words, the semiconductor device according to the disclosed invention In this configuration, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory, and reliability The quality improves dramatically. Furthermore, the on and off states of the transistors allow for the processing of information. Because data is recorded, high-speed operation can be easily achieved.

[0366] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0367] (Embodiment 9) In this embodiment, an RF including a transistor or memory device as described in the previous embodiment is used. Tags will be explained with reference to Figure 31.

[0368] The RF tag in this embodiment has a memory circuit inside, and stores the necessary information in the memory circuit. Furthermore, it uses non-contact means, such as wireless communication, to exchange information with the outside world. Due to its characteristics, RF tags are used to identify items by reading individual information about those items. It can be used in body recognition systems, etc. However, in order to use it for these purposes, For the first time, a high level of reliability is required.

[0369] The configuration of an RF tag will be explained using Figure 31. Figure 31 shows an example of the configuration of an RF tag. This is a lock diagram.

[0370] As shown in Figure 31, the RF tag 800 is connected to the communicator 801 (also known as an interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit 8 It has a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration may be made using a material capable of doing so, for example, an oxide semiconductor. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This can be prevented. In other words, the output of the demodulation circuit can be made more linear with respect to the input of the demodulation circuit. It is possible. Furthermore, the data transmission format involves a pair of coils positioned opposite each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that use induced electromagnetic fields for communication, and methods that use radio waves for communication. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment uses any of these methods. It can also be used for this purpose.

[0371] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins.

[0372] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9.

[0373] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation.

[0374] Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose.

[0375] Furthermore, the circuits described above can be selected or omitted as needed.

[0376] Here, the memory device described in the previous embodiment can be used in the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off, It can be suitably used in RF tags. Furthermore, a memory circuit according to one aspect of the present invention is a memory for writing data. Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to avoid any difference in the maximum communication distance between reading and writing. Furthermore, To prevent malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0377] Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will provide data to ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. This eliminates the need for post-shipment customer management, making it easier to handle customer issues related to products after they have been shipped.

[0378] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0379] (Embodiment 10) This embodiment describes a CPU including the storage device described in the previous embodiment.

[0380] Figure 32 shows a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing the example configuration.

[0381] The CPU shown in Figure 32 is an ALU1191 (ALU: Arithmet) mounted on board 1190. IC logic unit, arithmetic circuit, ALU controller 1192, instruction Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc. are used. ROM1199 and ROM interface 1189 are It may also be provided on a separate chip. Of course, the CPU shown in Figure 32 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including the CPU or arithmetic circuit shown in Figure 32 is considered as one core, and multiple such cores are included Alternatively, the configuration may be such that each core operates in parallel. Furthermore, the CPU performs internal calculations. The number of bits that can be handled by circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 64 bits. This can be represented as a bit, etc.

[0382] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0383] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal. Also, the interrupt controller 1194 controls the CPU's program. During execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and masking. The system makes a judgment and processes based on the state. The register controller 1197 determines the address of register 1196. It generates a value and reads or writes to register 1196 depending on the CPU state.

[0384] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates CLK2, and the internal clock signal CLK2 is the above It supplies power to various circuits.

[0385] In the CPU shown in Figure 32, a memory cell is located in register 1196. The transistors shown in the previous embodiment can be used as the 1196 memory cells. ru.

[0386] In the CPU shown in Figure 32, the register controller 1197 receives information from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. .

[0387] Figure 33 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data is lost when the power is cut off, and a memory element 1200 which loses stored data when the power is cut off. A circuit 1202 that prevents data from volatilizing, a switch 1203, a switch 1204, and a logic element It comprises a sub-element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 1202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has a diode, a resistor, an inductor, etc., as needed. It may also have other elements such as a t-axis.

[0388] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 120 of circuit 1202 The gate of transistor 9 is input to ground potential (0V) or a potential that turns off transistor 1209. The configuration will continue to be such that the first gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0389] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of transistor 1213, and the second of switch 1203. The terminals correspond to the source and drain of transistor 1213, and switch 1203 is The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. Continuity or non-conductivity between terminals (i.e., the on or off state of transistor 1213) ) is selected. The first terminal of switch 1204 is the source and drain of transistor 1214. Corresponding to one side of the input, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of the Rangista 1214 is selected.

[0390] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One side of this is electrically connected to the gate of transistor 1210. Here, the connection part Let the minute be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminal of switch 1203 (source and drain of transistor 1213) On the other hand, the first terminal of switch 1204 (the source and drain of transistor 1214) is the first terminal of switch 1204. It is electrically connected to the second terminal of switch 1204 (the terminal of transistor 1214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 1203 (the other terminal of the source and drain of transistor 1213) ) and the first terminal of switch 1204 (one of the source and drain of transistor 1214) ) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 1207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other of the pair of electrodes of the capacitive element 1207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0391] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0392] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0393] Note that in transistor 1209 in Figure 33, the second gate (second gate electrode: buck) The diagram shows a configuration having gates. The first gate receives a control signal WE, and the second gate... The control signal WE2 can be input to the terminal. The control signal WE2 is a signal with a constant potential and This should be done. The constant potential can be, for example, the ground potential GND or the potential of transistor 1209. A potential smaller than the -potential is selected. At this time, the control signal WE2 is the transistor This is a potential signal used to control the threshold voltage of transistor 1209, and the Ic of transistor 1209. ut can be further reduced. Also, the control signal WE2 has the same potential signal as the control signal WE. It may also be a number. Note that transistor 1209 is a transistor without a second gate. You can also use a ZISTA.

[0394] The source and drain of transistor 1209 are connected to the data held in circuit 1201. The corresponding signal is input. In Figure 33, the signal output from circuit 1201 is the transistor An example is shown where the source and drain of switch 1203 are input. The signal output from the second terminal (the other end of the source and drain of transistor 1213) is: The logic element 1206 inverts its logic value, resulting in an inverted signal, which is then transmitted via circuit 1220. This is then input to circuit 1201.

[0395] Note that in Figure 33, the second terminal of switch 1203 (source and terminal of transistor 1213) The signal output from the other side of Rain is routed through logic element 1206 and circuit 1220. An example of input to path 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from (the other side of the source and drain of transistor 1213) is the inverse of the logic value. It may be input to circuit 1201 without being converted. For example, within circuit 1201, If there is a node that holds a signal that is the inverted logical value of the signal input from the input terminal The second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from this node can be input to the node in question.

[0396] Furthermore, in Figure 33, among the transistors used in the memory element 1200, Transistors other than TA1209 are made of a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. A transistor can be formed where a channel is created at 0. For example, a silicon layer or It can be a transistor in which a channel is formed on a silicon substrate. Also, a memory element. All transistors used in the 1200 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a transistor. Alternatively, the memory element 1200 can be anything other than transistor 1209. It may also include transistors in which the channel is formed by an oxide semiconductor layer, and the remaining A transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be used as a transistor.

[0397] For example, a flip-flop circuit can be used in circuit 1201 in Figure 33. Furthermore, logic elements such as inverters and clocked inverters can be used as logic elements 1206. It is possible.

[0398] In a semiconductor device according to one aspect of the present invention, while the memory element 1200 is not supplied with a power supply voltage, The data stored in circuit 1201 is transferred to the capacitive element 1208 provided in circuit 1202. It can be held by.

[0399] Furthermore, transistors in which channels are formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer has crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, memory element 1 Even when no power voltage is supplied to 200, the signal held by the capacitive element 1208 will persist for a long period of time. The memory element 1200 is thus preserved. It is possible to hold data.

[0400] Furthermore, by providing switches 1203 and 1204, the pre-charge function is activated. Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0401] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory element 1200 is restored. After that, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210 ( It can be converted to an ON state or an OFF state and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal It is possible to read it accurately.

[0402] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0403] In this embodiment, although the memory element 1200 was described as an example of being used in a CPU, the memory element 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R It can also be applied to F-ID (Radio Frequency Identification). It is possible.

[0404] This embodiment can be appropriately combined with other embodiments shown herein. .

[0405] (Embodiment 11) In this embodiment, modified examples of a transistor according to one aspect of the present invention are shown in Figures 34 to 38. We will explain using this method.

[0406] The transistor shown in Figure 34 is an oxide semiconductor formed on an insulating layer 753 on a substrate 751. Layer 755, an insulating layer 757 in contact with the oxide semiconductor layer 755, and an acid layer in contact with the insulating layer 757. It has a conductive layer 759 superimposed on a synthetic semiconductor layer 755. The insulating layer 757 is a gel It functions as an insulating layer. Furthermore, the conductive layer 759 functions as a gate electrode layer. do.

[0407] Furthermore, the nitride insulating layer 765 in contact with the oxide semiconductor layer 755, and the nitride insulating layer 765 An insulating layer 767 is provided on the transistor. In addition, a nitride insulating layer 765 and an insulating layer are provided on the transistor. At the opening of the edge layer 767, the conductive layers 768 and 769 in contact with the oxide semiconductor layer 755 are It is provided in the transistor. Note that conductive layers 768 and 769 are the source electrode layer and the drain It functions as an in-electrode layer.

[0408] In the transistor shown in Figure 34(A), the oxide semiconductor layer 755 overlaps with the conductive layer 759. A channel region 755a is formed in the region, and the channel region 755a is flanked by an impure region. It has regions containing material elements, i.e., low-resistance regions 755b and 755c. It also has a conductive layer 768 769 is in contact with the low-resistance regions 755b and 755c. The conductive layers 768 and 769 are... It functions as wiring.

[0409] Alternatively, as shown in the transistor in Figure 34(B), in the oxide semiconductor layer 755, No impurity elements are added to regions 755d and 755e that are in contact with the electroplating 768 and 769. Alternatively, the regions 755d and 755e that are in contact with the conductive layers 768 and 769 and the channel Between region 755a and region 755a, there are regions containing impurity elements, i.e., low-resistance regions 755b and 755c. It has. Furthermore, when a voltage is applied to the conductive layers 768 and 769, regions 755d and 755e are formed. Because it is conductive, it functions as both a source region and a drain region.

[0410] Note that the transistor shown in Figure 34(B) has conductive layers 768 and 769 formed, and then the conductive layer Using layers 759 and conductive layers 768 and 769 as masks, impurity elements are added to the oxide semiconductor layer. It can be formed by doing so.

[0411] In the conductive layer 759, the edges of the conductive layer 759 may be tapered. That is, the insulating layer The angle θ1 between the surface where 757 and the conductive layer 759 are in contact and the side surface of the conductive layer 759 is less than 90°. Full, or 30° to 85°, or 45° to 85°, or 60° to 85° It may be less than or equal to a degree. The angle θ1 may be less than 90°, or 30° or more and 85° or less, By setting the angle to 45° to 85° or 60° to 85°, the insulating layer 757 and the conductor It is possible to improve the coverage of the nitride insulating layer 765 on the side surface of the electrical layer 759.

[0412] Next, we will describe modified examples of the low-resistance regions 755b and 755c. Note that Figure 34(C) Figure 34(F) is an enlarged view of the vicinity of the oxide semiconductor layer 755 shown in Figure 34(A). Here, the channel length L is the distance between a pair of low-resistance regions.

[0413] As shown in Figure 34(C), in the cross-sectional shape in the channel length direction, channel region 755a And the boundary between the low-resistance regions 755b and 755c is the edge of the conductive layer 759 via the insulating layer 757. The part is identical or nearly identical. That is, in the top surface shape, the channel region 755a and The boundary between the low-resistance regions 755b and 755c coincides with or approximately coincides with the edge of the conductive layer 759. It is.

[0414] Alternatively, as shown in Figure 34(D), in the cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region is an offset region. It is possible. The length of the offset region in the channel length direction is denoted as Loff. If there are multiple offset regions, the length of one offset region is called Loff. , included in the channel length L. Also, Loff is less than 20% of the channel length L, or 10 It is less than %, or less than 5%, or less than 2%.

[0415] Alternatively, as shown in Figure 34(E), in the cross-sectional shape in the channel length direction, the low-resistance region 7 55b and 755c have regions that overlap with the conductive layer 759 via the insulating layer 757. The region functions as an overlap region. The overlap region in the channel length direction The length is denoted as Lov. Lov is less than 20% of the channel length L, or less than 10%, or It is less than 5% or less than 2%.

[0416] Alternatively, as shown in Figure 34(F), in the cross-sectional shape in the channel length direction, the channel region There is a low-resistance region 755f between 755a and the low-resistance region 755b, and the channel region 755a There is a low resistance region 755g between the low resistance region 755c and the low resistance region 755f, 755 g has a lower concentration of impurity elements and higher resistivity than the low-resistivity regions 755b and 755c. In this case, the low-resistance regions 755f and 755g overlap with the insulating layer 757, but the insulating layer 757 and the conductive layer It may overlap with the 759 electrode layer.

[0417] Note that in Figures 34(C) to 34(F), the explanation of the transistor shown in Figure 34(A) is used. As explained above, the transistor shown in Figure 34(B) is also shown in Figures 34(C) to 34(F) The structure of ) can be applied as appropriate.

[0418] In the transistor shown in Figure 35(A), the end of the insulating layer 757 is located outside the end of the conductive layer 759. It is located on the side. That is, the insulating layer 757 has a shape that protrudes from the conductive layer 759. Since it is possible to keep the nitride insulating layer 765 away from the Nell region 755a, nitride insulating To suppress nitrogen, hydrogen, etc. contained in layer 765 from entering channel region 755a. It is possible.

[0419] The transistor shown in Figure 35(B) has tapered insulating layer 757 and conductive layer 759. Furthermore, the angles of each tapered portion are different. That is, the insulating layer 757 and the conductive layer 759 are in contact. The angle θ1 between the surface and the side surface of the conductive layer 759, and the oxide semiconductor layer 755 and the insulating layer 757 The angle θ2 between the contact surface and the side surface of the insulating layer 757 is different. The angle θ2 is 90 It may be less than 30° or between 30° and 85°, or between 45° and 70°. For example, when angle θ2 is smaller than angle θ1, the coverage of the nitride insulating layer 765 increases. When angle θ2 is greater than angle θ1, the nitride insulating layer 765 is moved away from the channel region 755a. Because it is possible for nitrogen, hydrogen, etc. contained in the nitride insulating layer 765 to enter the channel area This can prevent it from entering region 755a.

[0420] Next, modified examples of the low-resistance regions 755b and 755c are shown in Figures 35(C) to 35(F). This will be explained using the following. Figures 35(C) to 35(F) show the oxides shown in Figure 35(A). This is a magnified view of the vicinity of semiconductor layer 755.

[0421] As shown in Figure 35(C), in the cross-sectional shape in the channel length direction, channel region 755a The boundary between the low-resistance regions 755b and 755c is between the edge of the conductive layer 759 and the insulating layer 757. And they match or roughly match. That is, in the top shape, channel region 755a and The boundary between the low-resistance regions 755b and 755c coincides with or nearly coincides with the edge of the conductive layer 759. They are doing it.

[0422] Alternatively, as shown in Figure 35(D), in the cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region is used as an offset region. It is possible. That is, in the upper surface shape, the edges of the low-resistance regions 755b and 755c are the insulating layer 75 The edges of 7 coincide or nearly coincide, and do not overlap with the edges of the conductive layer 759.

[0423] Alternatively, as shown in Figure 35(E), in the cross-sectional shape in the channel length direction, the low-resistance region 7 55b and 755c have regions that overlap with the conductive layer 759 via the insulating layer 757. The region is called the overlap region. That is, in the top surface shape, the low resistance region 755b, 755 The end of c overlaps with the conductive layer 759.

[0424] Alternatively, as shown in Figure 35(F), in the cross-sectional shape in the channel length direction, the channel region There is a low-resistance region 755f between 755a and the low-resistance region 755b, and the channel region 755a There is a low resistance region 755g between the low resistance region 755c and the low resistance region 755f, 755 g has a lower concentration of impurity elements and higher resistivity than the low-resistivity regions 755b and 755c. In this case, the low-resistance regions 755f and 755g overlap with the insulating layer 757, but the insulating layer 757 and the conductive layer It may overlap with the 759 electrode layer.

[0425] Note that in Figures 35(C) through 35(F), the explanation of the transistor shown in Figure 35(A) is used. As explained above, even in the transistor shown in Figure 35(B), Figures 35(C) to 35(F) The structure of ) can be applied as appropriate.

[0426] The transistor shown in Figure 36(A) has a multilayer structure for the conductive layer 759, and is in contact with the insulating layer 757. It has a conductive layer 759a and a conductive layer 759b in contact with the conductive layer 759a. The end of the electrolytic layer 759a is located outside the end of the conductive layer 759b. That is, conductive layer 759 'a' has a shape that protrudes from the conductive layer 759b.

[0427] Next, we will describe modified examples of the low-resistance regions 755b and 755c. Note that Figure 36(B) Figures 36(E), 37(A), and (B) show the oxide semiconductor layer 755 shown in Figure 36(A). This is a magnified view of the surrounding area.

[0428] As shown in Figure 36(B), in the cross-sectional shape in the channel length direction, channel region 755a And the boundary between the low-resistance regions 755b and 755c is the conductive layer 759a included in the conductive layer 759 The edges are aligned or nearly aligned via the insulating layer 757. That is, in the upper surface shape, The boundary between the channel region 755a and the low-resistance regions 755b and 755c is the edge of the conductive layer 759. This is a match or near-match.

[0429] Alternatively, as shown in Figure 36(C), in the cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region is an offset region. It is possible. That is, in the upper surface shape, the edges of the low-resistance regions 755b and 755c are the conductive layer 75 It does not overlap with the end of the number 9.

[0430] Alternatively, as shown in Figure 36(D), in the cross-sectional shape in the channel length direction, the low-resistance region 7 55b and 755c have regions that overlap with conductive layer 759, in this case conductive layer 759a. The region is called the overlapping region. That is, in the top surface shape, the low resistance region 755b, 75 The edge of 5c overlaps with the conductive layer 759a.

[0431] Alternatively, as shown in Figure 36(E), in the cross-sectional shape in the channel length direction, the channel region There is a low-resistance region 755f between 755a and the low-resistance region 755b, and the channel region 755a There is a low-resistance region 755g between the low-resistance region 755c and the conductive layer 759. Because it passes through a and is added to the low-resistance regions 755f and 755g, the low-resistance regions 755f and 7 55g has a lower concentration of impurity elements and higher resistivity than the low-resistance regions 755b and 755c. Note that in this case, the low-resistance regions 755f and 755g overlap with the conductive layer 759a, but the conductive layer It may overlap with 759a and the conductive layer 759b.

[0432] Alternatively, as shown in Figure 37(A), in the cross-sectional shape in the channel length direction, the conductive layer 759 The end of a is located outside the end of the conductive layer 759b, and the conductive layer 759a has a tapered shape. This may also be the case. That is, the surface in contact with the insulating layer 757 and the conductive layer 759a, and the conductive layer 759a The angle formed by the sides is less than 90°, or 5° to 45°, or 5° to 30°. That's fine.

[0433] Furthermore, the end of the insulating layer 757 may be located outside the end of the conductive layer 759a.

[0434] Furthermore, the sides of the insulating layer 757 may be curved.

[0435] Furthermore, the insulating layer 757 may have a tapered shape. That is, the oxide semiconductor layer 755 and The angle between the surface that the insulating layer 757 is in contact with and the side surface of the insulating layer 757 is less than 90°, preferably 3°. An angle between 0° and 90° is also acceptable.

[0436] The oxide semiconductor layer 755 shown in Figure 37(A) consists of a channel region 755a and a channel region 7 The low resistance region 755f, 755g sandwiching 55a, and the low resistance region sandwiching 755f, 755g Resistance regions 755h and 755i, and the low resistance region 755 that encloses the low resistance regions 755h and 755i. b, 755c are present. Impurity elements pass through the insulating layer 757 and the conductive layer 759a to low Because it is added to the resistance ranges 755f, 755g, 755h, and 755i, the low resistance range 755 f, 755g, 755h, and 755i have lower resistance regions than 755b and 755c, due to the presence of impurity elements. It has a low concentration and high resistivity.

[0437] The oxide semiconductor layer 755 shown in Figure 37(B) consists of a channel region 755a and a channel region 7 The low resistance region 755h, 755i surrounding 55a, and the low resistance region 755h, 755i surrounding the low It has resistance regions 755b and 755c. Impurity elements pass through the insulating layer 757 to reduce resistance. Because it is added to regions 755h and 755i, the low-resistance regions 755h and 755i are low-resistance regions Regions 755b and 755c have lower concentrations of impurity elements and higher resistivity.

[0438] Furthermore, in the channel length direction, the channel region 755a overlaps with the conductive layer 759b, resulting in low resistance The anti-conductive regions 755f and 755g overlap with the conductive layer 759a, which protrudes to the outside of the conductive layer 759b. Therefore, the low-resistance regions 755h and 755i are the insulating layer 7 that protrudes outside the conductive layer 759a. Overlapping with 57, the low-resistance regions 755b and 755c are provided outside the insulating layer 757.

[0439] As shown in FIGS. 36(E) and FIGS. 37(A) and (B), the oxide semiconductor layer 755 has low-resistance regions 755f, 755g, 755h, and 755i where the concentration of impurity elements is lower and the resistivity is higher than in the low-resistance regions 755b and 755c. By having these, it is possible to relax the electric field in the drain region and reduce the variation in the threshold voltage of the transistor. Note that FIG. 37(C) is an enlarged view of the vicinity of the end of the conductive layer 759 in the channel width direction of the transistor shown in FIGS. 37(A) and (B).

[0440]

[0441] The transistor shown in FIG. 38(A) has an oxide semiconductor layer 755 including a channel region 755a and low-resistance regions 755b and 755c. The low-resistance regions 755b and 755c have regions with a smaller film thickness than the channel region 755a. Typically, the low-resistance regions 755b and 755c have regions where the thickness is 0.1 nm or more and 5 nm or less smaller than the channel region 755a.

[0442]

[0443]

[0444] The insulating layers 753b and 757a have energies (E v_o s ) and the energy at the lower end of the conduction band (E c_os ) during which the nitrogen oxide level density is low It can be formed using a physical insulating film. v_os and E c_os Between nitrogen oxides As an oxide insulating film with low nitrogen oxide density, a silicon oxidiznitride film with low nitrogen oxide emission, Alternatively, aluminum oxide nitride films that emit less nitrogen oxides can be used. The insulating layers 753b and 757a have an average film thickness of 0.1 nm to 50 nm, or 0. It is between 5nm and 10nm.

[0444] Furthermore, silicon oxidnitride films with low nitrogen oxide emissions can be analyzed using the temperature-dependent desorption gas analysis method (TDS). In (Thermal Desorption Spectroscopy), nitrogen This is a membrane that releases more ammonia than oxides, and is typically characterized by ammonia release. Quantity 1 × 10 18 pieces / cm 3 The above 5 x 10 19 pieces / cm 3 The following applies. Note that ammonia The amount released is when the film surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This refers to the amount released due to the heat treatment described below.

[0445] The insulating layers 753a and 757b are formed using an oxide insulating film that releases oxygen upon heating. This is possible. Furthermore, the insulating layers 753a and 757b have an average film thickness of 5 nm to 1000 nm. The following, or between 10nm and 500nm.

[0446] Typical examples of oxide insulating films that release oxygen upon heating include silicon oxide nitride films and silicon oxide films. Examples include aluminum oxide films.

[0447] Nitrogen oxides (NO x (where x is between 0 and 2, preferably between 1 and 2), typically NO2 Alternatively, NO forms energy levels in insulating layer 753 and insulating layer 757, etc. These energy levels are acid It is located within the energy gap of the nitrogen oxide semiconductor layer 755. Therefore, the nitrogen oxide acts as an insulator. When diffused to the interface between layers 753, 757 and oxide semiconductor layer 755, the energy level is transferred to the insulating layer 75 3. Electrons may be trapped on the 757 side. As a result, the trapped electrons Because it remains near the interface between insulating layers 753, 757 and oxide semiconductor layer 755, transistor This shifts the threshold voltage in the positive direction.

[0448] Furthermore, nitrogen oxides react with ammonia and oxygen during heat treatment. Insulating layer 753a The nitrogen oxides contained in 757b are absorbed into the insulating layers 753b and 757a during the heat treatment. Because it reacts with the ammonia present, the nitrogen oxides contained in insulating layers 753a and 757b are low It is reduced. Therefore, at the interface between the insulating layers 753, 757 and the oxide semiconductor layer 755, Electrons are less likely to be trapped.

[0449] As insulating layers 753b and 757a, E v_os and E c_os Between the levels of nitrogen oxides By using an oxide insulating film with low capacitance, the threshold voltage shift of the transistor can be reduced. This makes it possible to reduce variations in the electrical characteristics of the transistor.

[0450] Furthermore, the heat treatment in the transistor manufacturing process typically involves heating to temperatures above 300°C but below the substrate strain point. After heat treatment, the insulating layers 753b and 757a were measured at an ESR of 100K or less. In the spectrum, the first signal has a g value between 2.037 and 2.039, and the first signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966. A third signal is observed. Note that the split of the first and second signals The width, as well as the split width of the second and third signals, is determined by the X-band ESR measurement. The value is approximately 5mT. Also, the first signal is when the g value is between 2.037 and 2.039. , a second signal with a g value of 2.001 or higher and 2.003 or lower, and a second signal with a g value of 1.964 or higher The sum of the spin densities of the third signal, which is less than or equal to 0.966, is 1 × 10¹⁸ spins / c m 3 It is less than 1 × 10¹⁷ spins / cm², typically 1 × 10¹⁷ spins / cm². 3 The above is 1 x 10¹⁸ spins. s / cm 3 It is less than.

[0451] Furthermore, in ESR spectra below 100K, the g value is between 2.037 and 2.039. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value of 1. The third signal, between 964 and 1.966, represents nitrogen oxides (NOx, where x is between 0 and 2). This corresponds to a signal originating from (preferably 1 or more and 2 or less). Typical examples of nitrogen oxides include: These include nitric oxide, nitrogen dioxide, etc. That is, the first one has a g value of 2.037 or more and 2.039 or less. A signal, a second signal with a g value between 2.001 and 2.003, and a g value of 1.96 The smaller the sum of the spin densities of the third signal, which is between 4 and 1.966, the less likely it is to be an oxide. It can be said that the nitrogen oxide content in the insulating layer is low.

[0452] Furthermore, the heat treatment in the transistor manufacturing process, typically involving temperatures above 300°C but below the substrate strain point, is also a factor. After heat treatment, the oxide insulating layer containing nitrogen and having a low defect rate is SIMS (Secondary Electron Microwave Oxide). The nitrogen concentration measured by (Ion Mass Spectrometry) It is less than 6 × 10²⁰ atoms / cm³.

[0453] The substrate temperature is 220°C or higher, or 280°C or higher, or 350°C or higher, and silane and Using a plasma CVD method with nitrous oxide, an oxidation process that contains nitrogen and has a low defect rate is performed. By forming a material insulating layer, it is possible to create a dense and highly rigid film.

[0454] The transistor shown in Figure 38(C) consists of an oxide semiconductor layer 755, an insulating layer 757, and a conductive layer An insulating layer 775 is provided between 759 and the nitride insulating layer 765. The insulating layer 775 is shown in Figure 3. The insulating layers 753b and 757a of 8(B) are oxide insulating materials containing nitrogen and with a low defect content. It can be formed using the marginal layer.

[0455] Furthermore, in the cross-sectional shape in the channel length direction, the channel region 755a and the low-resistance region 755 Between b, there is a low-resistance region 755f, and between the channel region 755a and the low-resistance region 755c It has a low resistance region of 755g. Low resistance regions 755f and 755g are located in the low resistance region 755b. The concentration of impurity elements is lower than that of 755c, and the resistivity is higher. Note that here, the low-resistivity region 7 55f and 755g overlap with the insulating layer 775 that is in contact with the sides of the insulating layer 757 and the conductive layer 759. This is the region. Note that the low-resistance regions 755f and 755g are the insulating layer 757 and the conductive layer 759. It's okay if it overlaps with that.

[0456] The transistor shown in Figure 38(D) has an insulating layer 757 and a channel of oxide semiconductor layer 755. It is in contact with region 755a, as well as with the low-resistance regions 755b and 755c. Also, the insulating layer... 757 has lower resistance regions 755b and 755 compared to the region adjacent to the channel region 755a. The film thickness in the region in contact with c is thin, and typically the average film thickness is between 0.1 nm and 50 nm. Or it is between 0.5 nm and 10 nm. As a result, the oxide semiconductor is transmitted through the insulating layer 757. It is possible to add impurity elements to the conductive layer 755, and also to the nitride insulating layer 765. The hydrogen present can be moved to the oxide semiconductor layer 755 via the insulating layer 757. As a result, low-resistance regions 755b and 755c can be formed.

[0457] Furthermore, the insulating layer 753 has a multilayer structure of insulating layers 753a and 753b, and releases oxygen when heated. Using the oxide insulating layer produced, an insulating layer 753a is formed, containing nitrogen and having a low defect rate. An insulating layer 753b is formed using an oxide insulating layer. Furthermore, it contains nitrogen and has a low defect rate. An insulating layer 757 is formed using an oxide insulating layer that does not contain nitrogen and has a small number of defects. The oxide semiconductor layer 755 can be covered with an oxide insulating layer. As a result, the insulating layer 75 The oxygen contained in 3a is transferred to the oxide semiconductor layer 755 by heat treatment, and the oxide semiconductor While reducing oxygen vacancies in the channel region 755a of layer 755, insulating layers 753b, 7 The ability to reduce carrier trapping at the interface between 57a ​​and the oxide semiconductor layer 755 is It is possible. As a result, it is possible to reduce the threshold voltage shift of the transistor. This reduces variations in the electrical characteristics of the transistor.

[0458] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0459] (Embodiment 12) The following describes the band structure in an arbitrary cross-section of a transistor according to one embodiment of the present invention. ru.

[0460] Figure 39(A) is a cross-sectional view of a transistor according to one aspect of the present invention.

[0461] The transistor shown in Figure 39(A) has an insulating layer 401 on the substrate 400 and on the insulating layer 401 A conductive layer 404a, a conductive layer 404b on the conductive layer 404a, and a conductive layer 40 on the insulating layer 401 Insulating layer 402a on 4a and conductive layer 404b, and insulating layer 402b on insulating layer 402a And, the semiconductor layer 406a on the insulating layer 402b, and the semiconductor layer 406b on the semiconductor layer 406a , an insulating layer 412 on semiconductor layer 406b, a conductive layer 414a on insulating layer 412, and a conductive layer 4 The conductive layer 414b on 14a, the insulating layer 402b, the semiconductor layer 406a, and the semiconductor layer 406 The insulating layer 408 on b, on the insulating layer 412, on the conductive layer 414a and on the conductive layer 414b, An insulating layer 418 on the edge layer 408, and conductive layers 416a1 and 416 on the insulating layer 418 b1 and conductive layer 416a2 on conductive layer 416a1 and conductive layer 416b1 respectively and On the conductive layer 416b2, on the insulating layer 418, on the conductive layer 416a2 and on the conductive layer 416b2 It has an insulating layer 428 and

[0462] The insulating layer 401 is designed to suppress the intrusion of impurities into the channel formation region of the transistor. It may have the ability to do so. For example, the conductive layer 404b may be made of copper or a semiconductor layer 406a or When the semiconductor layer 406b contains impurities, the insulating layer 401 blocks copper and the like. It may have a function.

[0463] The laminate of conductive layer 404a and conductive layer 404b is collectively referred to as conductive layer 404. It may function as the gate electrode of a transistor. Also, the conductive layer 404 In some cases, it may have the function of shielding the channel formation region of a transistor from light.

[0464] The insulating layer 402a and insulating layer 402b together are called the insulating layer 402. The insulating layer 402 is It may function as a gate insulating layer for the transistor. Also, insulating layer 402a, In some cases, it has the function of suppressing the intrusion of impurities into the channel formation region of the transistor. Yes, there is. For example, conductive layer 404b may be a semiconductor layer 406a or semiconductor layer 406b made of copper or similar material. When impurities are present, the insulating layer 402a has the function of blocking copper and the like. There is a match.

[0465] Semiconductor layer 406a and semiconductor layer 406b together are called semiconductor layer 406. Region 6 may function as a channel formation region for the transistor.

[0466] Furthermore, the semiconductor layer 406a overlaps with the insulating layer 412, the conductive layer 414a, the conductive layer 414b, etc. It has regions 407a1 and 407b1 that are not insulating. In addition, the semiconductor layer 406b is insulating Regions 407a2 and regions that do not overlap with layer 412, conductive layer 414a, conductive layer 414b, etc. Region 407b2 is present. Regions 407a1 and 407b1 are insulating of semiconductor layer 406a. In regions with lower resistance than the regions overlapping with layer 412, conductive layer 414a, conductive layer 414b, etc. Furthermore, regions 407a2 and 407b2 are conductive, insulating layer 412 of semiconductor layer 406b This region has lower resistance than the region overlapping with layer 414a, conductive layer 414b, etc. Regions with low carrier density can also be called regions with high carrier density.

[0467] Furthermore, regions 407a1 and 407a2 are collectively referred to as region 407a. Regions 07b1 and 407b2 are collectively referred to as region 407b. Regions 407a and 4 07b may function as the source and drain regions of a transistor. ru.

[0468] The conductive layer 414a and conductive layer 414b together are called the conductive layer 414. The conductive layer 414 is It may function as the gate electrode of a transistor. Alternatively, the conductive layer 414 is It may have the function of shielding light from the channel formation region of the transistor.

[0469] The insulating layer 412 may function as a gate insulating layer for the transistor.

[0470] The insulating layer 408 is designed to suppress the intrusion of impurities into the channel formation region of the transistor. It may have the ability to do so. For example, conductive layers 416a2 and 416b2 may be made of copper, etc. When the semiconductor layer 406a or semiconductor layer 406b has impurities, the insulating layer 40 8 may have a function to block copper and other materials.

[0471] The insulating layer 418 may function as an interlayer insulating layer of the transistor. For example, The presence of an insulating layer 418 can reduce parasitic capacitance between each wiring of the transistor. ru.

[0472] The conductive layer 416a1 and conductive layer 416a2 together are called the conductive layer 416a. 416b1 and conductive layer 416b2 together are called conductive layer 416b. Furthermore, the conductive layer 416b functions as the source electrode and drain electrode of the transistor. There are cases where this occurs.

[0473] The insulating layer 428 is designed to suppress the intrusion of impurities into the channel formation region of the transistor. It may have the ability.

[0474] Here, in Figure 39(B), in the K1-K2 cross section including the channel formation region of the transistor... It shows a band structure. Note that semiconductor layer 406a has a higher energy gauge than semiconductor layer 406b. Let's assume the top is slightly small. Also, insulating layers 402a, 402b and 412 are If the energy gap is sufficiently larger than that of semiconductor layers 406a and 406b Also, semiconductor layer 406a, semiconductor layer 406b, insulating layer 402a, insulating layer 402b The Fermi level (denoted as Ef) of the insulating layer 412 is the intrinsic Fermi level of each. (Denoted as Ei) is the position. Also, the work function of conductive layer 404 and conductive layer 414 This is assumed to be at the same position as the Fermi level.

[0475] When the gate voltage is set to be greater than or equal to the transistor's threshold voltage, semiconductor layer 406a and semiconductor layer Due to the energy difference at the lower end of the conduction band between 406b and 406a, electrons preferentially enter semiconductor layer 406a. It flows through it. In other words, it can be estimated that electrons are embedded in the semiconductor layer 406a. The energy at the bottom of the conduction band is denoted as Ec, and the energy at the bottom of the valence band is denoted as Ev. .

[0476] Therefore, a transistor according to one aspect of the present invention reduces interfacial scattering by embedding electrons. The impact is reduced. Therefore, the transistor according to one aspect of the present invention has a channel resistance It's small.

[0477] Next, Figure 39(C) shows the L1-L2 region including the source or drain region of the transistor. The band structure in the cross-section is shown. Note that this refers to regions 407a1, 407b1, and 407a Regions 2 and 407b2 are in a degenerate state. Also, in region 407b1, the semiconductor layer The Fermi level in 406a is assumed to be approximately the same as the energy at the bottom of the conduction band. Also, region 407b In step 2, the Fermi level of semiconductor layer 406b is assumed to be approximately the same as the energy of the lower edge of the conduction band. The same applies to regions 407a1 and 407a2.

[0478] At this time, a conductive layer 416b having the function of a source electrode or drain electrode, and a region 407b2 and the region are in ohmic contact because the energy barrier is sufficiently small. 407b2 and region 407b1 are in ohmic contact. Similarly, the source electrode or The conductive layer 416a, which functions as a drain electrode, and region 407a2 are energy Because the barrier is small enough, ohmic contact occurs. Also, region 407a2 and region 407a 1 and , will be in ohmic contact. Therefore, conductive layer 416a and conductive layer 416b, Electrons are smoothly transferred between semiconductor layer 406a and semiconductor layer 406b. This can be understood.

[0479] As described above, the transistor according to one aspect of the present invention has a source electrode and a drain The transfer of electrons between the electrode and the channel formation region is smooth, and the channel resistance is low. It is a small transistor. In other words, it is a transistor with excellent switching characteristics. It becomes clear that...

[0480] This embodiment can be appropriately combined with other embodiments shown herein. .

[0481] (Embodiment 13) In this embodiment, the effects of oxygen vacancies in the oxide semiconductor layer and hydrogen entering those oxygen vacancies are considered. I will explain about that.

[0482] <(1). V o Ease and stability of H formation > When an oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, at room temperature, H is preferred. It diffuses along the ab plane. Also, during the heat treatment at 450°C, H diffuses along the ab plane and c Diffusion occurs in each axial direction. Therefore, here, oxygen-deficient V is added to IGZO. o If H is oxygen deficiency V o Let's explain whether it's easy to enter or not. Here, oxygen deficiency V o inside V is a state where H exists. o It is denoted as H.

[0483] The calculation used the InGaZnO4 crystal model shown in Figure 40. Here, V o H in H V o It exits and activates the reaction pathway that binds to oxygen (E a ) to NEB (Nudg The calculation was performed using the (ed Elastic Band) method. The calculation conditions are shown in Table 1.

[0484] [Table 1]

[0485] Furthermore, in the InGaZnO4 crystal model, there are differences in the metal elements to which oxygen is bonded and the number of such elements. As shown in Figure 40, there are oxygen sites 1 to 4. Here, oxygen deficiency V o Calculations were performed for oxygen sites 1 and 2, which are prone to forming oxygen deposits.

[0486] First, oxygen deficiency V o As oxygen site 1 that is likely to form, 3 In and 1 Zn Calculations were performed on the bound oxygen sites.

[0487] The initial model is shown in Figure 41(A), and the final model is shown in Figure 41(B). , in the initial state and the final state, the calculated activation barrier (E a ) is shown in Figure 42. The initial state here refers to an oxygen deficiency V o The state in which H is inside (V o H) and the final state is , oxygen deficiency V o And, in a state where oxygen and H are bonded together with one Ga and two Zn (H It is a structure that has -O).

[0488] The calculation results show an oxygen deficiency V o For the H atom inside to bond with another O atom, an energy of approximately 1.52 eV is required. While necessary, the H bonded to O is oxygen-deficient. o To enter, you need approximately 0.46 eV. Energy was needed.

[0489] Here, the activation barrier obtained by calculation (E a From equation 1, the reaction frequency (Γ) is calculated. In addition, in formula 1, k B is the Boltzmann constant, and T is the absolute temperature.

[0490]

number

[0491] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of [1 / sec]. The frequency with which H moves from the model shown in Figure 41(A) to the model shown in Figure 41(B) is 5.52. ×10 0 It was [1 / sec]. Also, from the model shown in Figure 41(B) to Figure 41(A) The frequency with which H moves to the model shown is 1.82 × 10⁻⁶. 9 It was [1 / sec]. Furthermore, H diffusing in IGZO is near oxygen-deficient V o If there is V o H is easily formed, DanV o When H is formed, oxygen deficiency V o It can be said that it is difficult for it to be released.

[0492] Next, oxygen deficiency V o As oxygen site 2 that readily forms a bond, one Ga and two Zn are bonded together. Calculations were performed on the oxygen sites.

[0493] The initial state model is shown in Figure 43(A), and the final state model is shown in Figure 43(B). , in the initial state and the final state, the calculated activation barrier (E a ) is shown in Figure 44. The initial state here refers to an oxygen deficiency V o The state in which H is inside (V o H) and the final state is , oxygen deficiency V o And, in a state where oxygen and H are bonded together with one Ga and two Zn (H It is a structure that has -O).

[0494] The calculation results show an oxygen deficiency V o For the H inside to bond with another O, an energy of approximately 1.75 eV is required. While necessary, the H bonded to O is oxygen-deficient. o To enter, you need approximately 0.35 eV. Energy was needed.

[0495] Furthermore, the activation barrier (E) obtained by calculation a ) and from the above formula 1, the reaction frequency (Γ) is calculated. I took it out.

[0496] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of [1 / sec]. The frequency with which H moves from the model shown in Figure 43(A) to the model shown in Figure 43(B) is 7.53. ×10 -2 It was [1 / sec]. Also, from the model shown in Figure 43(B) to Figure 43(A) The frequency with which H moves to the model shown is 1.44 × 10 10 It was [1 / sec]. And then, once V o When H is formed, oxygen deficiency V o It can be said that H is not easily released from there.

[0497] From the above, it can be concluded that H in IGZO diffuses easily during annealing, and oxygen-deficient V o If Oxygen Deficiency V o Enter inside V o It was found that it is more likely to become H.

[0498] <(2). V o H transition level > Oxygen deficiency in IGZO o If H exists, then <(1). V o Ease of H formation As shown in the section on stability and performance, the calculation using the NEB method indicates that the oxygen deficiency V o H is V o H is formed It is easy to do, and furthermore V o H can be said to be stable. Therefore, V o H is involved in carrier trap To find out if they agree, V o The transition level of H was calculated.

[0499] The calculation used an InGaZnO4 crystal model (112 atoms). The oxygen site is shown in Figure 40. V for oxygen site 1 and site 2 o An H-model was created, and the transition levels were calculated. The conditions are shown in Table 2.

[0500] [Table 2]

[0501] By adjusting the mixing ratio of the exchange term to obtain a band gap close to the experimental value, defect-free The band gap of the InGaZnO4 crystal model is 3.08 eV, which is different from the experimental value of 3.15 eV. The results were similar to those for eV.

[0502] The transition level (ε(q / q')) of a model with defect D is calculated by the following equation 2. Note that ΔE(D q ) is the formation energy at charge q of defect D, and is calculated from equation 3. It will be done.

[0503]

number

[0504]

number

[0505] In equations 2 and 3, E tot (D q ) is the total charge q of the model including defect D Energy, E tot (bulk) is the total energy of a defect-free model (perfect crystal), Δ n i μ is the number of increases or decreases in atom i related to the defect. i ε is the chemical potential of atom i. VBM is defective The energy at the top of the valence band, ΔV, in a model without this. q This is a supplement to the electrostatic potential. positive term, E F This is the Fermi energy.

[0506] Calculated V o The transition levels of H are shown in Figure 45. The numerical values ​​in Figure 45 represent the depth from the lower end of the conduction band. Yes. From Figure 45, V relative to oxygen site 1 o The transition level of H is 0.05 below the lower end of the conduction band. The presence of eV, V relative to oxygen site 2 o The transition level of H is 0.11 eV below the lower edge of the conduction band. Because each V o H is thought to be involved in electron trapping. That is, V o It was revealed that H would act as a donor. Also, V o H-Satsu IGZO is It was revealed that it is electrically conductive.

[0507] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0508] (Embodiment 14) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) (To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof.) This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention This includes mobile phones, game consoles including portable models, mobile data terminals, e-readers, and video cameras. , cameras such as digital still cameras, goggle-type displays (head-mounted displays) (Ray), navigation systems, sound reproduction devices (car audio, digital audio) Players, photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 46. vinegar.

[0509] Figure 46(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control Keys 907, Stylus 908 It has the following features. The portable game console shown in Figure 46(A) has two display units 903 and a display unit. Although it has part 904, the number of display units that a portable game console has is not limited to this. .

[0510] Figure 46(B) shows a portable data terminal, comprising a first housing 911, a second housing 912, and a first display unit 9 13. It has a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 913 The first housing 911 is provided, and the second display unit 914 is provided in the second housing 912. Furthermore, the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing 9 in the connection unit 915. It may also be configured to switch according to the angle between 12 and 12. Also, the first display unit 913 and A display device in which at least one of the second display unit 914 is provided with a function as a position input device. You may also use a touch panel. Note that the function as a position input device is provided by the display device. It can be added by providing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device. It is possible.

[0511] Figure 46(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, and a keyboard. It includes a board 923, a pointing device 924, and the like.

[0512] Figure 46(D) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 It has 33, etc. The display unit 932 may be a touch panel.

[0513] Figure 46(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It could also be configured to switch according to the angle between 2 and 3.

[0514] Figure 46(F) is a regular passenger car, consisting of the body 951, wheels 952, dashboard 953, and It has Ito 954, etc.

[0515] This embodiment can be appropriately combined with other embodiments shown herein. .

[0516] (Embodiment 15) In this embodiment, an example of the use of an RF tag according to one aspect of the present invention will be shown with reference to Figure 47. Let me explain. RF tags have a wide range of applications, such as banknotes, coins, securities, and bearer tags. Bonds, certificates (such as driver's licenses and residence certificates, see Figure 47(A)), vehicles (such as bicycles, see Figure 47(A)), etc. See 47(B)), packaging containers (wrapping paper, bottles, etc., see Figure 47(C)), recording media ( DVDs (see Figure 47(D)) and videotapes, personal belongings (bags, glasses, etc.), food items, Plants, animals, human bodies, clothing, household goods, medical products including drugs and pharmaceuticals, or electronic devices ( Articles such as liquid crystal displays, EL displays, television equipment, or mobile phones, or It can be used by attaching it to luggage tags (see Figures 47(E) and (F)) attached to each item. .

[0517] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This enhances security against theft and other crimes.

[0518] As described above, the RF tag according to one aspect of the present invention can be used for each of the applications listed in this embodiment. This reduces the operating power, including the power required for writing and reading information, thus extending the maximum communication distance. It becomes possible to store information for a long period of time. Furthermore, even when the power is cut off, information can be stored for an extremely long period of time. Because it can retain data for extended periods, it can be suitably used in applications where the frequency of writing and reading is low. Cut.

[0519] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible. (Embodiment 16)

[0520] <Film deposition model> The following describes the film deposition models for CAAC-OS and nc-OS.

[0521] Figure 58(A) shows the deposition process of CAAC-OS by sputtering. This is a schematic diagram of the interior.

[0522] Target 5130 is bonded to the backing plate. Multiple magnets are placed beneath the backing plate. Therefore, a magnetic field is generated on target 5130. The magnetic field of the magnet is used for film deposition. The sputtering method that increases the speed is called magnetron sputtering.

[0523] Target 5130 has a polycrystalline structure, and each of its grains contains a cleavage plane. Oh, I'll explain the details of the cleavage plane later.

[0524] The substrate 5120 is positioned facing the target 5130, and the distance d(t The distance between the board and the substrate (also called the TS distance) is preferably 0.01m or more and 1m or less. The depth should be between 0.02 m and 0.5 m. The deposition chamber should be mostly filled with deposition gas (e.g., acid Filled with a mixed gas containing 50% or more by volume of argon, or oxygen, and 0.0 The pressure is controlled to be between 1 Pa and 100 Pa, preferably between 0.1 Pa and 10 Pa. Then, by applying a voltage above a certain level to target 5130, discharge begins, and plasma This is confirmed. Furthermore, a high-density plasma region is formed by the magnetic field on target 5130. In the high-density plasma region, the deposition gas is ionized, generating ion 5101. Ion 5101 is, for example, the cation of oxygen (O + ) and the cation of argon (Ar + ) and so on.

[0525] Ion 5101 is accelerated toward target 5130 by the electric field, and eventually reaches target 5 It collides with 130. At this time, the sputtered particles are flat or pellet-shaped from the cleavage plane. Pellet 5100a and pellet 5100b are detached and knocked out. 5100a and pellet 5100b undergo structural changes due to the impact of collisions with ion 5101. Distortion may occur.

[0526] Pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangle plane. These are sputtered particles. Also, pellet 5100b has a hexagonal, for example, regular hexagonal plane. These are flat or pellet-shaped sputtered particles. Note that pellet 5100a and Pellet 5100b and other flat or pellet-shaped sputtered particles are collectively referred to as pellet 5 It is called 100. The planar shape of pellet 5100 is not limited to triangles or hexagons, for example. In some cases, the shape may consist of two to six triangles joined together. For example, a regular triangle (regular triangle) In some cases, two polygons (or rhombus) can be joined together to form a quadrilateral (or rhombus).

[0527] The thickness of pellet 5100 is determined by the type of film-forming gas used, etc. The reason will be explained later. The thickness of the pellet 5100 is preferably uniform. Also, the sputtered particles have a uniform thickness. A pellet-like shape is preferable to a thick, cube-like shape.

[0528] Pellet 5100 receives an electric charge as it passes through the plasma, causing its sides to be negative or positive. It may become charged. Pellet 5100 has oxygen atoms on its side, and these oxygen atoms are negatively charged. It can become charged. For example, pellet 5100a may have negatively charged oxygen atoms on its sides. An example of this is shown in Figure 60. In this way, by having the sides carry charges of the same polarity, The loads repel each other, making it possible to maintain a flat shape. If S is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom will be negatively charged. It may be electrically charged. Or, bonded with indium, gallium, and zinc atoms. Oxygen atoms can become negatively charged.

[0529] As shown in Figure 58(A), for example, the pellet 5100 flies through the plasma like a kite. And it flutters up onto the substrate 5120. The pellet 5100 is charged. Therefore, when it approaches an area where other pellets 5100 have already accumulated, a repulsive force is generated. Here, a magnetic field is generated on the upper surface of the substrate 5120, oriented parallel to the upper surface of the substrate 5120. Furthermore, since a potential difference is applied between the substrate 5120 and the target 5130, Current is flowing from the substrate 5120 to the target 5130. Therefore, pellet 5100 is exerted on the upper surface of substrate 5120 by the action of a magnetic field and electric current, thereby generating a force (Lore It is subjected to a force (see Figure 61). This can be understood using Fleming's left-hand rule. Yes, it is possible. In order to increase the force applied to the pellet 5100, the upper surface of the substrate 5120 In this configuration, the magnetic field parallel to the upper surface of the substrate 5120 is 10G or greater, preferably 20G or greater. Furthermore, it is preferable to provide a region where the G is 30G or more, and more preferably 50G or more. Alternatively, on the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is present on the substrate 1.5 times or more, preferably 2 times or more, the magnetic field perpendicular to the upper surface of 5120 It is preferable to provide a region where the ratio is 3 times or more, and more preferably 5 times or more.

[0530] Furthermore, the substrate 5120 is heated, and friction between the pellet 5100 and the substrate 5120 is... Which resistance is low. As a result, as shown in Figure 62(A), pellet 5 100 moves as if gliding across the top surface of substrate 5120. The movement of pellet 5100 is as follows: This occurs with the flat surface facing the substrate 5120. Subsequently, as shown in Figure 62(B), When it reaches the sides of other piled-up pellets 5100, the sides fuse together. At that time, oxygen atoms on the side surface of pellet 5100 are removed. Due to the removed oxygen atoms, Because oxygen vacancies in CAAC-OS can be filled, CAAC-OS with a low defect level density It becomes S.

[0531] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms rearrange, The structural strain caused by the impact of ON 5101 is relieved. The strain-relieved pellet 510 0 is almost a single crystal. Because pellet 5100 is almost a single crystal, pellet 5 Even if the 100 pellets are heated after bonding together, the expansion and contraction of the 5100 pellets themselves is minimal. This is impossible. Therefore, the gaps between pellets 5100 will widen, causing defects such as grain boundaries. It does not form depressions or crevasses. Also, flexible metal atoms, etc., can be placed in the gaps. The sides of the 5100 pellets, which are laid out and oriented in different directions, are connected like a highway. It is thought that...

[0532] Based on the above model, it is thought that the pellets 5100 will accumulate on the substrate 5120. Therefore, unlike epitaxial growth, if the surface to be formed does not have a crystalline structure... It can be seen that CAAC-OS can be deposited even in this case. For example, substrate 5120 Even if the upper surface (the surface to be formed) has an amorphous structure, it is possible to deposit CAAC-OS. That is the case.

[0533] Furthermore, CAAC-OS can be applied not only to flat surfaces but also to the substrate 5120, which is the surface to be formed on. It can be seen that even if the surface has irregularities, the pellets 5100 will be arranged according to that shape. For example, if the top surface of the substrate 5120 is atomically flat, then the pellet 5100 is flat with plane ab. Because the flat plates, which are the horizontal planes, are placed side by side with their downward-facing surfaces, they have a uniform thickness, are flat, and possess high crystallinity. A layer is formed. Then, when n layers (where n is a natural number) are stacked, CA AC-OS can be obtained (see Figure 58(B)).

[0534] On the other hand, even if the upper surface of the substrate 5120 has irregularities, CAAC-OS can still use pellets 510 The structure consists of n layers (where n is a natural number) in which zeros are juxtaposed along a convex surface. (Substrate 51) Because 20 has an uneven surface, CAAC-OS is prone to gaps forming between pellets 5100. There is a fit. However, intermolecular forces act between pellets 5100, and even if there are irregularities between the pellets The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is achieved. This can be done using CAAC-OS (see Figure 58(C)).

[0535] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates, etc. Even if there are particles present, uniform film formation is possible.

[0536] Because CAAC-OS is deposited using this model, the sputtered particles have no thickness. Pellet-like form is preferable. Note that if the sputtered particles are in the form of thick cubes... In cases where the surface facing the substrate 5120 is not constant, and the thickness and crystal orientation cannot be made uniform, be.

[0537] The film formation model described above allows for high crystallinity even on a film-forming surface having an amorphous structure. A CAAC-OS having the following characteristics can be obtained.

[0538] Furthermore, CAAC-OS is a film deposition model that has zinc oxide particles in addition to pellet 5100. Therefore, it can also be explained.

[0539] Because zinc oxide particles have a smaller mass than pellets 5100, they reach substrate 5120 first. On the upper surface of the substrate 5120, zinc oxide particles preferentially undergo crystal growth in the horizontal direction. This forms a thin zinc oxide layer. The zinc oxide layer has c-axis orientation. The c-axis of the lead layer crystals is oriented parallel to the normal vector of the substrate 5120. The zinc oxide layer is Therefore, to serve as a seed layer for growing CAAC-OS, the CAAC-OS It has the function of enhancing crystallinity. The zinc oxide layer has a thickness of 0.1 nm to 5 nm. Most are between 1 nm and 3 nm. Because the zinc oxide layer is sufficiently thin, the grain boundaries are almost... It's almost impossible to confirm.

[0540] Therefore, in order to deposit highly crystalline CAAC-OS, a higher composition than stoichiometric is required. It is preferable to use a target containing zinc in a certain proportion.

[0541] Similarly, nc-OS can be understood by the film deposition model shown in Figure 59. The only difference between Figure 59 and Figure 58(A) is whether or not the substrate 5120 is heated.

[0542] Therefore, the substrate 5120 is not heated, and between the pellet 5100 and the substrate 5120 As a result, the pellet 5100 is in a state of high resistance such as friction. Because it cannot move by gliding across the top surface of 20, it falls and accumulates irregularly. And you can get nc-OS.

[0543] <cleavage plane> The following describes the cleavage plane of the target described in the CAAC-OS film deposition model. do.

[0544] First, the cleavage plane of the target will be explained using Figure 63. Figure 63 shows InGaZn The crystal structure of O4 is shown. Note that in Figure 63(A), the c-axis is oriented upwards and the direction is parallel to the b-axis. The structure of the InGaZnO4 crystal observed from this point is shown. Also, Figure 63(B) shows the c-axis. The structure of the InGaZnO4 crystal observed from a direction parallel to the vector is shown.

[0545] The energy required for cleavage at each crystal plane of an InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using pseudopotentials and density functional programming with plane wave basis variables. Gram (CASTEP) is used. Note that for pseudopotentials, an ultra-soft type pseudopotential is used. We will use Tential. Furthermore, we will use GGA PBE as the functional. Also, cutoff... The energy is assumed to be 400 eV.

[0546] The energy of the structure in its initial state is derived after performing structural optimization, including cell size. Furthermore, the energy of the structure after cleavage on each plane is determined by the atomic distribution, with the cell size fixed. This is derived after optimizing the structure of the placement.

[0547] Based on the crystal structure of InGaZnO4 shown in Figure 63, the first face, second face, and third face are shown. A structure is created by cleaving along one of the fourth faces, and a structural optimization calculation is performed with a fixed cell size. Perform the following. Here, the first plane is the crystal plane between the Ga-Zn-O layer and the In-O layer, (0 01) It is a crystal plane parallel to the plane (or ab plane) (see Figure 63(A)). The second plane is This is a crystal plane between Ga-Zn-O layers, and is the (001) plane (or ab) plane. The third plane is a crystal plane parallel to the (110) plane (see Figure 63(A)). This is a crystal plane (see Figure 63(B)). The fourth plane is parallel to the (100) plane (or bc plane). It is a row crystal plane (see Figure 63(B)).

[0548] Under the above conditions, the energy of the structure after cleavage is calculated for each facet. Next, the structure after cleavage The difference between the energy of the structure in its initial state is divided by the area of ​​the cleavage plane. Next, the cleavage energy, which is a measure of the ease of cleavage at each surface, is calculated. Energy is the kinetic energy of electrons and the interatomic and atomic energy of atoms within a structure. - This energy takes into account the interactions between electrons and between electrons.

[0549] The calculation results show that the cleavage energy of the first surface is 2.60 J / m 2 , cleavage energy of the second surface It is 0.68 J / m³ 2 The cleavage energy of the third face is 2.18 J / m 2 , the fourth face The energy is 2.12 J / m³. 2 It was found that this is the case (see table below).

[0550] [Table 3]

[0551] This calculation shows that in the crystal structure of InGaZnO4 shown in Figure 63, the second plane The cleavage energy is lowest at this point. That is, between the Ga-Zn-O layer and the Ga-Zn-O layer. It can be seen that this is the plane that is most easily cleaved (cleavage plane). Therefore, in this specification, When referring to a cleavage plane, it means the second plane, which is the easiest plane to cleave.

[0552] Because there is a cleavage plane on the second surface between the Ga-Zn-O layers, Figure 6 The InGaZnO4 crystal shown in 3(A) can be separated by two second planes equivalent to the plane. Yes, it is possible. Therefore, when colliding ions or other elements with a target, the most cleavage energy is... - The smallest wafer-like unit (which we call a pellet) is cleaved at the lowest surface. It is thought that they will be ejected as units. In that case, the InGaZnO4 pellets will be The structure consists of three layers: a Ga-Zn-O layer, an In-O layer, and another Ga-Zn-O layer.

[0553] Also, the first plane (which is the crystal plane between the Ga-Zn-O layer and the In-O layer, and the (001) plane) Or, a crystal plane parallel to the ab plane, a crystal plane parallel to the third plane (110), a crystal plane parallel to the fourth plane Because the cleavage energy of the plane (a crystal plane parallel to the (100) plane (or bc plane)) is low. This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0554] Next, classical molecular dynamics calculations were performed to determine that InGaZ, which has a homologous structure, is the target. Assuming an nO4 crystal, the target is spalled with argon (Ar) or oxygen (O). The cleavage plane in the case of cutting is evaluated. The InGaZnO4 crystal used in the calculation (268 The cross-sectional structure of the 8-atom atom is shown in Figure 64(A), and the top surface structure is shown in Figure 64(B). Note that Figure 64( The fixed layer shown in A) is a layer in which the arrangement of atoms is fixed so that their positions do not change. Also, see Figure 6. The temperature-controlled layer shown in 4(A) is a layer that is always kept at a constant temperature (300K).

[0555] For classical molecular dynamics calculations, we use Materials Explorer 5 from Fujitsu Limited. Use 0. Note that the initial temperature is 300K, the cell size is constant, and the time step size is 0.01 feet. The calculation assumes a mutosecond time and 10 million steps. Under these conditions, the atom is subjected to 300e. By applying energy V, atoms are introduced into the cell from a direction perpendicular to the ab-plane of the InGaZnO4 crystal. To inject.

[0556] Figure 65(A) shows argon being injected into a cell containing the InGaZnO4 crystal shown in Figure 64. The atomic arrangement 99.9 picoseconds (psec) after the initial reaction is shown. Also, Figure 65(B) shows the cell This shows the atomic arrangement 99.9 picoseconds after oxygen is incident on the atom. Note that in Figure 65, Figure 64( A) shows a portion of the fixed layer omitted.

[0557] From Figure 65(A), within 99.9 picoseconds after argon enters the cell, as shown in Figure 63(A) Cracks arise from the cleavage plane corresponding to the second plane shown. Therefore, InGaZnO4 When argon strikes a crystal, if the top surface is considered the second surface (0th), then the second surface (2 It can be seen that a large crack occurs in the second (second) position.

[0558] On the other hand, as shown in Figure 65(B), within 99.9 picoseconds after oxygen enters the cell, as shown in Figure 63(A) It can be seen that cracks originate from the cleavage plane corresponding to the second plane shown in ). However, oxygen is impacted If impact occurs, a large crack will form on the second (first) face of the InGaZnO4 crystal. It becomes clear that...

[0559] Therefore, the top surface of the target containing the InGaZnO4 crystal having a homologous structure When atoms (ions) collide, the InGaZnO4 crystal cleaves along the second plane, and the plane becomes flat. It can be seen that the plate-shaped particles (pellets) are detached. Also, at this time, the size of the pellets is It was found that the amount of oxygen collides with the gas is smaller than the amount of argon collides with the gas. ru.

[0560] Furthermore, the above calculations suggest that the detached pellets contain damaged areas. The damaged area included is a place where the defects caused by the damage can be repaired by reacting them with oxygen. There is a match.

[0561] Therefore, we investigated whether the size of the pellets differs depending on the type of atoms colliding with them. ru.

[0562] Figure 66(A) shows argon being injected into a cell containing the InGaZnO4 crystal shown in Figure 64. Then, the trajectories of each atom from 0 picoseconds to 0.3 picoseconds are shown. Therefore, Figure 6 6(A) corresponds to the period between Figure 64 and Figure 65(A).

[0563] As shown in Figure 66(A), argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), the sub It can be seen that lead reaches near the sixth layer (Ga-Zn-O layer). The argon that strikes is repelled outwards. Therefore, the InGaZnO4 crystals When argon is impacted onto the jelly, a crack appears on the second surface (second) in Figure 64(A). It is thought that it will be included.

[0564] Furthermore, Figure 66(B) shows the cell containing the InGaZnO4 crystal shown in Figure 64, into which oxygen is introduced. The trajectory of each atom from 0 picoseconds to 0.3 picoseconds after irradiation is shown. Therefore, Figure 66(B) corresponds to the period between Figure 64 and Figure 65(A).

[0565] On the other hand, as shown in Figure 66(B), oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that zinc does not reach the fifth layer (In-O layer). Furthermore, the acid that collided with gallium... The element is ejected to the outside. Therefore, acid is applied to a target containing InGaZnO4 crystals. When the elements collide, it is thought that a crack will form on the second surface (first) in Figure 64(A). ru.

[0566] This calculation also shows that when atoms...

Claims

1. A semiconductor device having a transistor, A first conductive layer and A first insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the first insulating layer, A second conductive layer having a region located above the oxide semiconductor layer, A second insulating layer having a region located above the oxide semiconductor layer, A third conductive layer having a region located above the second insulating layer, A third insulating layer having a region located above the third conductive layer, The first conductive layer functions as the first gate electrode of the transistor. The first insulating layer functions as the first gate insulating layer of the transistor. The oxide semiconductor layer has the function of a channel formation region for the transistor. The second conductive layer functions as the source electrode or drain electrode of the transistor. The second insulating layer functions as the second gate insulating layer of the transistor. The third conductive layer functions as the second gate electrode of the transistor. In a first cross-sectional view obtained by cutting along the channel length direction of the transistor, the oxide semiconductor layer has a first region, a second region, and a third region. The first region is in contact with the second insulating layer, The second region is in contact with the third insulating layer, The third region is in contact with the second conductive layer, In the first cross-sectional view, the second region is positioned between the first region and the third region. In the first cross-sectional view, the first region, the second region, and the third region are arranged above the first conductive layer. In a second cross-sectional view taken along the channel width direction of the transistor, the second insulating layer has a fourth region in contact with the oxide semiconductor layer and a fifth region in contact with the first insulating layer. In the second cross-sectional view, the fourth region and the fifth region are positioned above the first conductive layer. A semiconductor device in which, in the second cross-sectional view, the third insulating layer has a region in contact with the first insulating layer and a region above the first conductive layer in contact with the edge of the second insulating layer.

2. In claim 1, The semiconductor device comprises an oxide semiconductor layer containing indium oxide.

3. In claim 1, The aforementioned oxide semiconductor layer has an In-Ga-Zn oxide, and is a semiconductor device.

Images