Manufacturing method for semiconductor devices

Abstract

A method for manufacturing a semiconductor device is provided. [Solution] The method includes: step A forming a conductive material and a dielectric material sequentially on a semiconductor unit along the growth direction; step B forming a photoresist material on the dielectric material along the growth direction; step C forming a photoresist layer by patterning the photoresist material; step D forming a dielectric layer and a conductive layer, respectively, by patterning the dielectric material and the conductive material using the photoresist layer as a mask; and step E removing the photoresist layer and patterning the semiconductor unit using the dielectric layer as a mask.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a high electron mobility transistor.

Background Art

[0002] A high electron mobility transistor (HEMT) is widely applied to integrated circuits as a field effect transistor (FET).

[0003] An HEMT uses two materials with different band gaps to form a heterojunction, and a conductive channel of two-dimensional electron gas (2DEG) is naturally formed at the junction, so it has high electron mobility.

[0004] As shown in FIG. 1, in a conventional method for manufacturing a high electron mobility transistor, a barrier layer 92, a p-type doping material 93', and a conductor material 94' are sequentially formed on a semiconductor layer 91 along a growth direction G.

[0005] As shown in FIG. 1, a first photoresist layer 95 patterned on the conductor material 94' is formed along the growth direction G.

[0006] Using the first photoresist layer 95 as a mask, the conductor material 94' is patterned to form a conductor layer 94 as shown in FIG. 2.

[0007] Thereafter, as shown in FIG. 3, a second photoresist layer 96 patterned on the conductor layer 94 is formed along the growth direction G.

[0008] Using the second photoresist layer 96 as a mask, the p-type doping material 93' is patterned to form a p-type doping layer 93 as shown in FIG. 4.

[0009] However, the above method requires the patterning of the conductive material 94' and the p-type doping material 93' by two separate photolithography processes using photoresists, making the manufacturing process complex.

[0010] Furthermore, in photolithography using two photoresist layers, the pattern of the first photoresist layer 95 and the pattern of the second photoresist layer 96 should theoretically overlap perfectly, and the pattern of the conductive layer 94 and the pattern of the p-type doping layer 93 should theoretically overlap perfectly. However, due to deviations in the aiming of the exposure equipment, the positions of the conductive layer 94 and the p-type doping layer 93 often shift, resulting in a decrease in manufacturing yield.

[0011] Furthermore, Figures 8A to 8J of Patent Document 1 also disclose a technique for patterning using photolithography with two photoresists. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Patent No. 7175727 [Overview of the project] [Problems that the invention aims to solve]

[0013] The object of the present invention is to provide a method for manufacturing a semiconductor device that can mitigate at least one of the drawbacks of the prior art. [Means for solving the problem]

[0014] The present invention comprises step A, in which a conductive material and a dielectric material are sequentially formed on a semiconductor unit along the growth direction, Step B involves forming a photoresist material on the dielectric material along the growth direction, Step C involves patterning the aforementioned photoresist material to form a photoresist layer, Step D of patterning the dielectric material and the conductor material using the photoresist layer as a mask to form a dielectric layer and a conductor layer, respectively; providing a method for manufacturing a semiconductor device, including: Step E of removing the photoresist layer and patterning the semiconductor unit using the dielectric layer as a mask.

Advantages of the Invention

[0015] The method for manufacturing a semiconductor device according to the present invention simultaneously patterns the dielectric layer and the conductor layer using a photoresist layer, and then patterns the semiconductor unit using the patterned dielectric layer as a mask. Therefore, only photolithography using a single photoresist is required, and the manufacturing process can be simplified.

[0016] In addition, since photolithography using two photoresists is not required, there is no deviation due to the alignment of the exposure apparatus, and there is no misalignment due to alignment between the conductor layer and the semiconductor unit, significantly improving the manufacturing yield.

Brief Description of the Drawings

[0017] [Figure 1] It is a diagram showing a conventional method for manufacturing a semiconductor device. [Figure 2] It is a diagram showing a conventional method for manufacturing a semiconductor device. [Figure 3] It is a diagram showing a conventional method for manufacturing a semiconductor device. [Figure 4] It is a diagram showing a conventional method for manufacturing a semiconductor device. [Figure 5] It is a flowchart showing the method for manufacturing a semiconductor device according to the present invention. [Figure 6] It is a diagram showing Steps A to B in FIG. 5. [Figure 7] It is a diagram showing Steps C to D in FIG. 5. [Figure 8] It is a diagram showing Step E in FIG. 5. [Figure 9] It is a diagram showing Step E in FIG. 5. [Figure 10] It is a diagram showing step F in FIG. 5. [Figure 11] It is a diagram showing step F in FIG. 5.

Embodiments for Carrying Out the Invention

[0018] Before explaining the present invention in more detail, it should be noted that, if considered appropriate, reference signs or the end portions of reference signs are repeated between figures to indicate corresponding or similar elements, and these can optionally have similar characteristics.

[0019] Hereinafter, the present invention will be described in detail.

[0020] As shown in FIG. 5, an embodiment of the method for manufacturing a semiconductor device of the present invention includes steps A to F, which will be described below in conjunction with the drawings.

[0021] The direction X shown in FIGS. 6 to 11 is defined as the growth direction X, and the direction Y shown in FIGS. 6 to 11 is defined as the width direction Y orthogonal to the growth direction X.

[0022] As shown in FIG. 6, in step A, a conductor material 2' and a dielectric material 3' are sequentially formed on the semiconductor unit 1 along the growth direction X.

[0023] Specifically, the semiconductor unit 1 has a semiconductor layer 11 and a III-V compound layer 12 in sequence along the growth direction X.

[0024] The III-V compound layer 12 has a barrier layer 121 and a doped layer 122 along the growth direction X.

[0025] The barrier layer 121 is formed of, for example, aluminum gallium nitride (AlGaN), but is not limited thereto.

[0026] The doped layer 122 is formed by, for example, a p-type doped III-V compound, but is not limited to that. The constituent material of the doped layer 122 includes magnesium-doped gallium nitride (GaN). For example, the doped layer 122 is formed by magnesium-doped gallium nitride.

[0027] Specifically, the conductive material 2' is formed in the doped layer 122 of the III-V compound layer 12 along the growth direction X. That is, the conductive material 2' is formed on the upper surface of the doped layer 122 of the III-V compound layer 12 in Figure 6.

[0028] The conductive material 2' can be a metal or a ceramic material. For example, the conductive material 2' can be titanium nitride.

[0029] The dielectric material 3' can be silicon nitride or silicon oxide.

[0030] In step B, a photoresist material 4' is formed on the dielectric material 3' along the growth direction X. That is, the photoresist material 4' is formed on the upper surface of the dielectric material 3' in Figure 6 along the growth direction X.

[0031] As shown in Figure 7, in step C, the photoresist material 4' is patterned to form the photoresist layer 4.

[0032] Specifically, after patterning the photoresist material 4', the formed photoresist layer 4 has a specific pattern, which may be, but is not limited to, a gate pattern.

[0033] In step D, the photoresist layer 4 is used as a mask to pattern the dielectric material 3' and the conductive material 2' to form the dielectric layer 3 and the conductive layer 2, respectively.

[0034] Specifically, in step D, a dry etching method such as anisotropic etching, for example, reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, is used to synchronously transfer a specific pattern on the photoresist layer 4 to the dielectric layer 3 and the conductor layer 2. The doped layer 122 is also connected to the underside of the conductor layer 2.

[0035] As shown in Figures 8 and 9, in step E, the photoresist layer 4 is removed, and the dielectric layer 3 is used as a mask to pattern the dope layer 122 of the semiconductor unit 1.

[0036] Specifically, in step E, a specific pattern on the dielectric layer 3 is transferred to the doped layer 122 by an anisotropic etching method.

[0037] A specific pattern in the conductive layer 2 is determined by the photoresist layer 4, a specific pattern in the doped layer 122 of the semiconductor unit 1 is determined by the dielectric layer 3, and a specific pattern in the dielectric layer 3 is determined by the photoresist layer 4.

[0038] Therefore, no deviation due to aiming occurs between the conductive layer 2 and the semiconductor unit 1.

[0039] In other words, the outer edge of the conductor layer 2 in the width direction Y is aligned with the outer edge of the doped layer 122 of the semiconductor unit 1 in the width direction Y.

[0040] As shown in Figures 10 and 11, in step F, after removing the dielectric layer 3, the conductive layer 2 is etched to shrink the outer edge of the conductive layer 2 inward relative to the outer edge of the semiconductor unit 1 along the width direction Y.

[0041] Specifically, in step F, the conductive layer 2 is etched using an isotropic etching method, such as wet etching, to reduce the thickness of the conductive layer 2 along the growth direction X and also reduce its width along the width direction Y.

[0042] The outer edge of the etched conductive layer 2 shrinks inward along the width direction Y relative to the outer edge of the semiconductor unit 1, creating a distance between the outer edge of the conductive layer 2 and the outer edge of the doped layer 122 of the semiconductor unit 1.

[0043] Before step F is performed, the outer edge of the conductor layer 2 is aligned with the outer edge of the doped layer 122 of the semiconductor unit 1. After the conductor layer 2 is isotropically etched in step F, as shown in Figure 11, the distances between each of the outer edges of the conductor layer 2 in the width direction Y and each of the outer edges of the doped layer 122 in the width direction Y are the first distance W1 and the second distance W2. If manufacturing process errors can be ignored, the first distance W1 and the second distance W2 are the same, and a symmetrical gate structure is formed.

[0044] A stepped gate structure is formed by designing the width of the conductor layer 2 to be smaller than the width of the doped layer 122 below it, along the width direction Y.

[0045] A symmetrical gate structure ensures stable performance for the transistor.

[0046] Before wet etching in step F, the outer edge of the conductor layer 2 is aligned with the outer edge of the semiconductor unit 1 and has a flat sidewall surface. Compared to the uneven sidewall surface of the conventional technology (shown in Figure 4), this reduces the likelihood of footing defects (structural defects at the bottom of the gate structure) occurring during the wet etching process, allowing for the more precise formation of a symmetrical gate structure. As a result, the transistor exhibits stable static electrical characteristics, stable dynamic electrical characteristics, and excellent reliability.

[0047] Therefore, compared to the prior art, the present invention is not limited by the aiming limits of the exposure apparatus and can more accurately form a symmetrical gate structure in a simpler process.

[0048] Furthermore, in step F of this embodiment, the dielectric layer 3 is removed before etching the conductive layer 2, but it is also possible to etch the conductive layer 2 directly without removing the dielectric layer 3. In that case, the thickness of the conductive layer 2 does not decrease, but only its width decreases.

[0049] According to the above, the semiconductor manufacturing method of the present invention involves simultaneously patterning the dielectric layer 3 and the conductive layer 2 with a photoresist layer 4, and then patterning the semiconductor unit 1 using the patterned dielectric layer 3 as a mask. Therefore, only one photolithography with photoresist is required, and the manufacturing process can be simplified.

[0050] Furthermore, since two photolithography processes using photoresist are not required, there is no deviation due to the aiming of the exposure equipment, and there is no misalignment of the aiming between the conductive layer 2 and the semiconductor unit 1, which can significantly increase the manufacturing yield.

[0051] Therefore, the objective of the present invention can be achieved.

[0052] The above embodiments are illustrative in illustrating the principles and effects of the present invention and do not limit it. Those skilled in the art can make some modifications and alterations to the above embodiments, provided they do not deviate from the spirit and scope of the invention. Therefore, all modifications and alterations made by those skilled in the art, provided they do not deviate from the spirit of the invention, should also be considered to fall within the scope of protection of the present invention. [Industrial applicability]

[0053] The semiconductor manufacturing method of the present invention is suitable for semiconductor manufacturing. [Explanation of Symbols]

[0054] 1 Semiconductor Unit 11 Semiconductor layer 12 III-V compound layer 121 Barrier layer 122 Doping layer 2 Conductor layers 2' Conductor material 3 Dielectric layer 3' Dielectric materials 4. Photoresist layer 4' Photoresist material Steps A-F W1 First distance W2 2nd Distance X growth direction Y width direction

Claims

1. Step A involves sequentially forming conductive material and dielectric material on a semiconductor unit along the growth direction, Step B involves forming a photoresist material on the dielectric material along the growth direction, Step C involves patterning the aforementioned photoresist material to form a photoresist layer, Step D involves using the aforementioned photoresist layer as a mask to pattern the dielectric material and the conductive material to form a dielectric layer and a conductive layer, respectively. A method for manufacturing a semiconductor device, comprising step E, which involves removing the photoresist layer and patterning the semiconductor unit using the dielectric layer as a mask.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising step F of etching the conductive layer to reduce the outer edge of the conductive layer inward relative to the outer edge of the semiconductor unit along a width direction perpendicular to the growth direction.

3. The method for manufacturing a semiconductor device according to claim 2, wherein in step F, the dielectric layer is removed before etching the conductive layer.

4. The semiconductor unit has a doped layer connected to the lower side of the conductive layer, The distances between each of the outer edges on both sides of the conductor layer in the width direction and each of the outer edges on both sides of the doped layer in the width direction are the first distance and the second distance, respectively. The method for manufacturing a semiconductor device according to claim 2 or claim 3, wherein the first distance and the second distance are the same.

5. In step A, the semiconductor unit has, in order along the growth direction, a semiconductor layer and a III-V compound layer, The method for manufacturing a semiconductor device according to claim 1, wherein the conductive material is formed in the III-V compound layer along the growth direction.

6. The III-V compound layer has a barrier layer and a doped layer along the growth direction, The method for manufacturing a semiconductor device according to claim 5, wherein the doped layer is patterned in step E.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the constituent material of the doped layer includes magnesium-doped gallium nitride.

8. The method for manufacturing a semiconductor device according to claim 1, wherein in step A, the conductive material is titanium nitride.

9. The method for manufacturing a semiconductor device according to claim 1, wherein in step A, the dielectric material is silicon nitride or silicon oxide.

Images