Semiconductor equipment

Abstract

To provide a novel and nonvolatile latch circuit and a semiconductor device using the latch circuit.SOLUTION: A semiconductor device comprises: a latch part having a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element; and a data holding part for holding data, and the latch part and the data holding part compose a nonvolatile latch circuit. In the data holding part, a transistor which uses an oxide semiconductor as a semiconductor material for composing a channel formation region is used as a switching element. The semiconductor device further comprises an inverter electrically connected to a source electrode or a drain electrode of the transistor. By using the above-described transistor, data held by the latch part can be written in gate capacitance of the inverter or in separately prepared capacitance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a non-volatile logic circuit in which the stored logic state is not erased even when the power is turned off, and This relates to semiconductor devices using the same. In particular, to non-volatile latch circuits and semiconductor devices using the same. Regarding body devices. [Background technology]

[0002] Non-volatile logic circuits incorporate the property of "non-volatility," where memories are not erased even when the power is turned off. Integrated circuits integrating JIC have been proposed. For example, non-volatile using ferroelectric elements. A latch circuit has been proposed as a non-volatile logic (Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2003 / 044953 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, non-volatile latch circuits using ferroelectric elements offer reliability in terms of rewrite cycles and low voltage. There are challenges in the process of polarization. Also, ferroelectric elements are polarized by the electric field applied to the element, and this polarization The residual polarization retains information. However, if this residual polarization is small, the effects of variability become significant. This can lead to increased noise levels or the need for high-precision readout circuits.

[0005] In view of these problems, one embodiment of the present invention relates to a novel non-volatile latch circuit and a device using the same. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0006] In one embodiment of the present invention, the output of a first element is electrically connected to the input of a second element, and the second element A latch section having a loop structure in which the output of the child is electrically connected to the input of the first element, and It has a data holding part that holds the data of the latch part, and the latch part and the data holding part are used to A volatile latch circuit is formed. The data holding section constitutes a channel formation region. A transistor using an oxide semiconductor as the semiconductor material is used as a switching element. Furthermore, an input electrically connected to the source or drain electrode of this transistor. It has a transistor. Using the above transistor, the data held in the latch is It can be written to the gate capacity of the converter or to a separately prepared capacity. Using a transistor, data written to the gate capacitance of the inverter or a separately prepared capacitance It can retain data.

[0007] In other words, one embodiment of the present invention comprises a latch unit and a data holding unit that holds data from the latch unit. It has a data holding unit which has a transistor and an inverter and the transistor The channel formation region has an oxide semiconductor layer and serves as the source electrode and drain electrode of the transistor. One of the electrodes is electrically connected to the wiring to which the output signal is supplied, and is the source electrode of the transistor. The other end of the drain electrode is electrically connected to the inverter input, and the inverter output is A non-volatile latch circuit is formed by electrically connecting to the wiring to which the input signal is applied. It is something that will be accomplished.

[0008] In the above, the data holding unit can have a capacitor in addition to the transistor and inverter. The above capacity can be used for writing and holding data held in the latch section. One electrode of the above capacitance is connected to the other electrode of the transistor's source and drain electrodes. It can be used by connecting it electrically.

[0009] In the above, the latching section has a first element and a second element, and the output of the first element is the The input of the second element is electrically connected, and the output of the second element is electrically connected to the input of the first element. It has a continuous loop structure. In addition, the input to the first element is the distribution to which the input signal is applied. The output of the first element is electrically connected to the wire to which the output signal is supplied. It has a structure in which an inverter is used as the first element and the second element is An inverter can be used. Also, for example, if NAND is used as the first element, A clocked inverter can be used as the second element.

[0010] In the above, the transistor receives the data held in the latch section from the data holding section. It has the function to write to the gate capacity of the converter or a separately prepared capacity. The transistor writes to the gate capacitance of the inverter in the data holding unit or to a separately prepared capacitance. It has the functionality to store complex data.

[0011] In the above, an oxide semiconductor layer formed from an oxide semiconductor material is used as the channel formation region. The transistor used had, for example, a channel width W of 1 × 10⁻⁶. 4 A channel with a length of 3 μm in μm Even for a component, the off-current at room temperature is 1 × 10⁻⁶ -13 A or below, subthresholds A characteristic with an ing value (S value) of approximately 0.1 V / dec. (gate insulating film thickness 100 nm) was obtained. Therefore, the off-current when the voltage between the gate and source electrodes is approximately zero, i.e. The leakage current is significantly smaller compared to transistors using silicon. Therefore, the channel Using a transistor with an oxide semiconductor layer in the layer formation region as a switching element. And even after the power supply voltage to the latch circuit is cut off, the data stored in the data retention section's capacity It can retain the electric charge. In other words, the data written to the data storage unit This can be maintained in the same state. Also, the supply of power voltage to the latch circuit is restarted. After that, the data stored in the data storage unit can be read. It can restore the logic state to what it was before the power supply voltage was cut off. Furthermore, it exhibits high temperature characteristics. It is possible to obtain a device that has a sufficiently low off-current and a sufficiently high on-current even at high temperatures. For example, this The Vg-Id characteristics of a transistor are as follows: off-current and on-current within the range of -25°C to 150°C. Data has been obtained showing that flow, mobility, and S value have little temperature dependence. Thus, this development One form of this device has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even after the power is turned off. This provides a non-volatile latch circuit in which the logic state does not disappear.

[0012] In the above, by using a non-volatile latch circuit, various logic circuits can be provided. This is possible. Furthermore, various semiconductor devices using the above logic circuits can be provided. For example, among the multiple block circuits that a logic circuit has, one or more blocks that are not used The power supply voltage to the latch circuit can be stopped. The above non-volatile latch circuit is used. This means that even after the power supply voltage to the block circuit is stopped, the logic state of the block circuit is recorded. It can continue to be memorized. Also, after the supply of the power voltage to the block circuit is restarted the stored logical state can be read out. Thereby, it can be restored to the logical state before the supply of the power voltage is stopped

[0013] In the above, the oxide semiconductor layer can use materials of In-Ga-Zn-O system, In-Sn-O system, In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z n-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn -O system, In-O system, Sn-O system, Zn-O system. Also, the oxide semiconductor layer can use one containing indium, gallium, and zinc. Also the hydrogen concentration of the oxide semiconductor layer is 5×10 19 / cm 3 or less, preferably 5×10 18 / cm 3 or less, more preferably 5×10 <00,00007> / cm 3 or less, more preferably 1×10 16 / cm 3 or less, more preferably 1×10 16 / cm 3 and can be less than. Also, the oxide the carrier concentration of the semiconductor layer is 1×10 14 / cm 3 less, preferably 1×10 12 / cm 3 less, more preferably 1×10 11 / cm 3 and can be less than. Also, the off-current of the transistor at room temperature can be 1×10 A or less. -13

[0014] In the above, the transistor using the oxide semiconductor may be a bottom gate type​​ It may also be a top gate type. It may also be a bottom contact type, or top It may also be a contact type. Bottom gate transistors have at least an insulating surface. A gate electrode, a gate insulating film on the gate electrode, and a portion of the gate insulating film that overlaps with the gate electrode. The top-gate type transistor has an oxide semiconductor layer that forms a channel-forming region. , an oxide semiconductor layer which forms a channel-forming region on at least the insulating surface, and on the oxide semiconductor layer It has a gate insulating film and a gate electrode that overlaps with an oxide semiconductor layer on the gate insulating film. Bottom-contact transistors have channels formed on the source and drain electrodes. It has an oxide semiconductor layer that forms a region. Top-contact transistors form channels. The region has an oxide semiconductor layer on which the source electrode and drain electrode are located.

[0015] In this specification, terms such as "above" and "below" refer to the positional relationship of the constituent elements, meaning "directly above". Or, it does not necessarily mean "directly below". For example, "gate on the gate insulating layer If the expression is "electrode," then exclude those that include other components between the gate insulating layer and the gate electrode. Do not remove it. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation, and there is no particular reason to use them. This also includes the inverted versions of the same thing, unless otherwise specified.

[0016] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0017] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" may be used interchangeably. It shall be done.

[0018] Furthermore, in this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0019] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also... Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities. [Effects of the Invention]

[0020] According to one embodiment of the present invention, an oxide semiconductor is used as the semiconductor material constituting the channel formation region. By using the transistor as a switching element in the data retention section, temperature operation It operates stably over a wide range, even at high temperatures, and retains its stored logical state even when the power is turned off (non-volatile). A latch with an automatic latch circuit or a data retention unit with a sufficiently long refresh period. The circuit can be realized. Data can be written by switching transistors. Because of this process, there is virtually no limit to the number of rewrites. Furthermore, the writing voltage is controlled by the transistor. The threshold voltage is around 1V, allowing operation at low voltages. For example, the operating voltage is around 1V. Or it can be reduced to less than that. Also, the charge accumulated in the capacity of the data storage unit is Because it is retained as data, the variation is greater compared to when the residual polarization component is used as data. It is less susceptible to the effects of wind and allows for easy data retrieval.

[0021] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, in logic circuits using non-volatile latch circuits, the power supply for unused blocks is also affected. Power consumption can be reduced by turning it off. Also, even if the power is turned off, the logical state Because it remembers the state, it can remember when the system starts up when the power is turned on, and when the power is turned off. This makes it possible to shut down the system quickly and with low power consumption. [Brief explanation of the drawing]

[0022] [Figure 1] A diagram showing an example of a non-volatile latch circuit configuration. [Figure 2] A diagram showing an example of the configuration of a non-volatile latch circuit. [Figure 3] A diagram showing an example of a cross-section and a plan view of an element in a non-volatile latch circuit. [Figure 4] A diagram illustrating an example of a method for fabricating elements of a non-volatile latch circuit. [Figure 5] A diagram illustrating an example of a method for fabricating elements of a non-volatile latch circuit. [Figure 6] A diagram illustrating an example of a method for fabricating elements of a non-volatile latch circuit. [Figure 7] A diagram showing an example of the cross-sectional configuration of an inverse staggered transistor using an oxide semiconductor. [Figure 8] The energy band diagram (schematic diagram) in the A-A' section of Figure 7. [Figure 9](A) shows the state where a positive potential (+VG) is applied to the gate (GE1), and (B) shows the state where a negative potential (-VG) is applied to the gate (GE1). [Figure 10] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 11] This diagram shows the energy required for hot carrier injection in silicon (Si). [Figure 12] This figure shows the energy required for hot carrier implantation in an In-Ga-Zn-O oxide semiconductor (IGZO). [Figure 13] This diagram shows the energy required for hot carrier injection in silicon carbide (4H-SiC). [Figure 14] A figure showing the results of device simulations regarding short-channel effects. [Figure 15] A figure showing the results of device simulations regarding short-channel effects. [Figure 16] A diagram showing the CV characteristics. [Figure 17] A diagram showing the relationship between Vg and (1 / C)². [Figure 18] A diagram showing an example of a non-volatile latch circuit configuration. [Figure 19] A diagram illustrating an example of the configuration and operation of a non-volatile latch circuit. [Figure 20] A diagram illustrating an example of the configuration and operation of a non-volatile latch circuit. [Figure 21] A diagram illustrating an example of the configuration and operation of a non-volatile latch circuit. [Figure 22] A diagram showing an example of a non-volatile latch circuit configuration. [Figure 23] A diagram showing an example of a semiconductor device using a non-volatile latch circuit. [Figure 24] A diagram showing an example of a non-volatile latch circuit configuration. [Figure 25] A diagram showing an example of evaluation results for a non-volatile latch circuit. [Modes for carrying out the invention]

[0023] Embodiments and examples of the present invention will be described below with reference to the drawings. However, The present invention is not limited to the following description. The present invention may deviate from its spirit and scope. Those skilled in the art will readily understand that its form and details can be changed in various ways without modification. Therefore, the present invention is based on the following embodiments and examples. It is not to be interpreted as being limited to this. Furthermore, when explaining the configuration of the present invention using drawings, Symbols that refer to the same thing are used consistently across different drawings.

[0024] Furthermore, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment is In some cases, the figures may be exaggerated for clarity. Therefore, the scale may not necessarily reflect the actual values. Not limited.

[0025] Furthermore, the ordinal numbers used in this specification, such as 1st, 2nd, and 3rd, refer to the constituent elements. This is a designation added for identification purposes only and does not limit the number of such designations.

[0026] (Embodiment 1) This embodiment describes the configuration, operation, and non-volatile latch circuit, which is one aspect of the disclosed invention. Regarding the method for fabricating elements of a volatile latch circuit, see Figures 1, 2, 3 to 6, and Figure This will be explained with reference to Figures 7 through 17.

[0027] <Configuration and operation of non-volatile latch circuits> Figure 1(A) shows a latch unit 411 and a data holding unit 401 that holds the data of the latch unit. The configuration of the non-volatile latch circuit 400 is shown. Figure 1(B) shows the data holding unit 4 This shows the configuration of 01.

[0028] The non-volatile latch circuit 400 shown in Figure 1(A) is such that the output of the first element (D1) 412 is The input of the second element (D2) 413 is electrically connected, and the output of the second element (D2) 413 is A latch section 41 having a loop structure that is electrically connected to the input of the first element (D1) 412. It has 1 and a data holding unit 401 that holds data from the latch unit.

[0029] The input of the first element (D1) 412 is connected to wiring 414 to which the input signal of the latch circuit is applied. They are electrically connected. The output of the first element (D1) 412 is given the output signal of the latch circuit. It is electrically connected to the available wiring 415.

[0030] If there are multiple inputs to the first element (D1) 412, one of them is used as the input signal for the latch circuit. The second element (D2) 413 can be electrically connected to the wiring 414 to which the number is assigned. If there are multiple inputs, connect one of them electrically to the output of the first element (D1) 412. It can be continued.

[0031] The first element (D1) 412 uses an element whose output is the inverted version of the input signal. It is possible. For example, the first element (D1) 412 has an inverter and a NAND (NAND) ), NOR (Natural Orbital Ratio), clocked inverter, etc. can be used. Also, the second element (D2)413 can use an element whose output is the inverted version of the input signal. For example, the second element (D2) 413 contains an inverter, NAND, and NOR. (Noah), clocked inverters, etc. can be used.

[0032] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region. The transistor 402 is used as a switching element. One of the source and drain electrodes is electrically connected to the wiring 415 to which the output signal is supplied. It is continued. Also, the data holding unit 401 is the source electrode of this transistor 402 and The other end of the drain electrode has a capacitor 404 and an inverter 403 that are electrically connected to it. That is, the source electrode and the other of the drain electrode of transistor 402 are connected to the capacitor 404. One of the electrodes is electrically connected to the input (input terminal) of inverter 403. One electrode of capacitance 404, the input of inverter 403, and the source electrode of transistor 402 We will refer to the node to which the drain electrode and the other electrode are electrically connected as node S. A potential Vc is applied to the other electrode of the 404 capacitance electrode.

[0033] Furthermore, the output of inverter 403 is electrically connected to wiring 414 to which the input signal is supplied. The inverter 403 has transistors 420 and 421. The source electrode of the Rangitor 420 is electrically connected to a high-level power supply voltage VDD. The source electrode of transistor 421 is electrically connected to the low-level power supply voltage VSS. Yes, they are.

[0034] The inverter 403 is not limited to the configuration shown in Figure 1(B), but can also be configured as shown in Figure 2(A), for example. Alternatively, it may be constructed using N-channel transistors 420 and 421. Furthermore, a configuration with a buffer at the output is also acceptable. Also, instead of inverter 403, senser A sensor circuit may also be used. For example, a differential amplifier type sense amplifier circuit as shown in Figure 2(B) A path may also be used. A differential amplifier type sense amplifier circuit as shown in Figure 2(B) has N channels. The transistors are: 421 (a type of transistor), 501 and 502 (an N-channel type transistor), and 502 (an N-channel type transistor). It consists of transistors 503-506. In all cases, the input (input terminal) is floating It is important that it is in a high-impedance state.

[0035] This oxide semiconductor transistor 402 holds data in the latch portion 411 The machine writes the data to the capacity 404 of the data holding unit 401 and the gate capacity of the inverter 403. It has the ability. In addition, transistor 402 has the capacitance 404 and the data holding unit 401. The converter 403 has a function to retain the data written to its gate capacity.

[0036] Writing, holding, and reading data held in the latch unit 411 to the data holding unit 401. Let's explain the output and rewriting process. First, the gate electrode of transistor 402 is connected to The potential supplied to turn on transistor 402 is turned on. This allows the data held in the latch, i.e., the output signal, to be supplied to the wiring 4. A potential of 15 is applied to one electrode of the capacitor 404 and the input terminal of the inverter 403. As a result, the capacitance of one electrode of capacitance 404 and the gate capacitance of inverter 403 are determined by the wiring 415. Charge is accumulated (written) according to the potential. Then, the gate electrode of transistor 402 The potential at which transistor 402 is in the off state is used, and transistor 402 is turned off. By doing so, the energy is stored in one electrode of the capacity 404 and the gate capacity of the inverter 403. The charged charge is retained. This capacitor 404 and inverter 403 Data can be read by reading the potential of the input terminal (read ). Data can be rewritten in the same way as writing and retaining the data described above.

[0037] The oxide semiconductor layer of transistor 402 is an In-Ga-Zn-O system, In-Sn- O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series It is desirable to use Al-Zn-O, In-O, Sn-O, and Zn-O based materials. stomach.

[0038] The oxide semiconductor layer has been purified to a high degree by thoroughly removing impurities such as hydrogen. This is desirable. Specifically, the hydrogen concentration of the oxide semiconductor layer should be 5 × 10⁻⁶. 19 / cm 3 Below, wish Mashikuha 5 x 10 18 / cm 3 The following is more preferable: 5 x 10 17 / cm 3 Below, more desired Mashiku is 1 x 10 16 / cm 3 The following is more preferable: 1 × 10 16 / cm 3 Less than. Furthermore, the carrier concentration in the oxide semiconductor layer is 1 × 10⁻⁶ 14 / cm 3 Less than, preferably 1 × 10 12 / cm 3 Less than 1 × 10 11 / cm 3 It can be less than. Furthermore, an oxide semiconductor layer with a sufficiently reduced hydrogen concentration and high purity is a common silicon material. Carrier in a silicon wafer (a silicon wafer with trace amounts of impurity elements such as phosphorus and boron added) A concentration (1 × 10 14 / cm 3Compared to the degree, it takes a carrier concentration value that is sufficiently small. .

[0039] Thus, the hydrogen concentration is sufficiently reduced and the purity is increased, and the carrier concentration is sufficiently low, i By using typed or substantially i-typed oxide semiconductors, extremely excellent off-current characteristics can be achieved. A transistor 402 with a channel width W of 1 × 10⁻⁶ can be obtained. 4 μm Even with a channel length L of 3 μm, if the drain voltage Vd applied to the drain electrode is + In the case of 1V or +10V, the gate voltage Vg applied to the gate electrode is from -5V In the -20V range, the off-current at room temperature is 1 × 10⁻⁶ -13 It is less than or equal to A. Also, temperature In terms of characteristics, the goal is to obtain a transistor with sufficiently low off-current and sufficiently high on-current even at high temperatures. This is possible. For example, the Vg-Id characteristics of transistor 402 are in the range of -25°C to 150°C. In this case, data was obtained showing that the temperature dependence of the off-current, on-current, mobility, and S value is small. The hydrogen concentration in the oxide semiconductor layer is determined by secondary ion mass spectrometry (SIMS). This was measured using econdary ion mass spectrometry. ru.

[0040] Furthermore, the oxide semiconductor constituting the oxide semiconductor layer is not particularly limited as long as it has a non-single crystal structure. For example, amorphous structure, microcrystalline (microcrystal, nanocrystal, etc.) structure, multi Crystalline structure, structure containing microcrystals or polycrystals within an amorphous structure, microcrystals or polycrystalline crystals on the surface of an amorphous structure Various structures can be applied, such as structures in which crystals are formed.

[0041] Thus, the hydrogen concentration is sufficiently reduced and the purity is increased, and the carrier concentration is sufficiently low, i A transistor 402 using a typed or substantially i-typed oxide semiconductor is switched By using it as a latching element, even after the power supply voltage to the latch circuit 400 is stopped, The charge stored in the capacity 404 of the data holding unit 401 and the gate capacity of the inverter 403 is extremely It can be retained for a long period of time. That is, the data is written to the data retention unit 401. It can retain complex data for extremely long periods of time. Also, latch circuit 4 After the power supply voltage to 00 is restarted, the data held in the data holding unit 401 The data can be read. This restores the logic to the state it was in before the power supply was cut off. This can be achieved. In this way, the hydrogen concentration is sufficiently reduced and the purity is increased, and the carrier concentration is Transistor 40 using a sufficiently low, i-type or substantially i-type oxide semiconductor By using 2 as a switching element, it has a wide temperature operating range and operates stably even at high temperatures. This invention realizes a novel non-volatile latch circuit in which the stored logical state is not erased even when the power is turned off. It is possible.

[0042] Of the elements in the non-volatile latch circuit 400, elements other than the transistor 402 are semi-volatile. Other materials besides oxide semiconductors can be used as conductive materials. For example, single-crystal silicon, crystalline silicon, etc. can be used. Elements other than ZISTA 402 can be provided on a substrate containing semiconductor material. The substrates include silicon wafers and SOI (Silicon on Insulation). r) Substrates, silicon films on insulating surfaces, etc. can be used. Materials other than oxide semiconductors By using this, high-speed operation becomes possible.

[0043] Furthermore, among the elements of the non-volatile latch circuit 400, elements other than the transistor 402 are It is also possible to use oxide semiconductors as semiconductor materials.

[0044] <Planar and cross-sectional configurations of elements in a non-volatile latch circuit> Figure 3 shows the transistor 402 of the non-volatile latch circuit described above, and transistor 402 This is an example of the configuration of elements other than transistor 402. Here, as elements other than transistor 402, data Let's take the transistor 421 of the inverter 403 of the holding unit 401 as an example. Other elements besides transistor 402 shall have the same or similar configuration as transistor 421. This is possible. Elements such as capacitor 404 are transistor 402 or other transistors. It can be formed using the film that makes up the element. Figure 3(A) shows a cross-section, and Figure 3(B) shows... The lines A1-A2 and B in Figure 3(B) are shown. Here, Figure 3(A) is shown as lines A1-A2 and B in Figure 3(B). This corresponds to the cross-section in 1-B2. As shown in Figures 3(A) and 3(B), acid is present at the bottom. A transistor 421 made of a material other than an oxide semiconductor is provided, and an oxide semiconductor is used on the upper part. A transistor 402 is provided.

[0045] Transistor 421 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108a provided on 6, and a gate provided on the gate insulating layer 108a Electrode 110a and source electrode or drain electrode 1 which are electrically connected to the impurity region 114 It has 30a, a source electrode or a drain electrode 130b.

[0046] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Furthermore, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from the plane, A high-concentration impurity region 120 exists, and a metal compound region 124 is located on the high-concentration impurity region 120. There is also an element isolation insulating layer 1 surrounding the transistor 421 on the substrate 100. 06 is provided, and the interlayer insulating layer 126 and interlayer are provided so as to cover the transistor 421. An insulating layer 128 is provided. Source electrode or drain electrode 130a, source electrode Alternatively, the drain electrode 130b is formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the opening. In other words, the source electrode and The drain electrode 130a and the source electrode or drain electrode 130b are located in the metal compound region 1. 24 is electrically connected to the high-concentration impurity region 120 and the impurity region 114. Furthermore, the gate electrode 110a is connected to the source electrode or drain electrode 130a or source electrode Alternatively, an electrode 130c, provided similarly to the drain electrode 130b, is electrically connected. .

[0047] Transistor 402 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0048] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided to be inserted. Also, similar to the gate electrode 136d, the source electrode or drain Electrode 136a is in contact with in electrode 130a and is in contact with source electrode or drain electrode 130b. Electrode 136b is in contact with electrode 130c, and electrode 136c is formed accordingly.

[0049] Furthermore, a protective layer is placed on top of the transistor 402 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Simultaneously with the formation of electrode 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and layer Through the opening provided in the inter-insulating layer 146, electrodes 136a, 136b, and 136c Electrodes 150a, 150b, and 150c are formed in contact with the surface.

[0050] Here, the oxide semiconductor layer 140 is purified to a high degree by sufficiently removing impurities such as hydrogen. It is desirable that the hydrogen concentration of the oxide semiconductor layer 140 be 5 × 10⁻¹⁰. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 should be 5 × 10⁻¹⁰. 19 / cm 3 The following is preferable: 5 x 10 18 / cm 3 The following is more preferable: 5 x 10 17 / cm 3 The following is more preferable: 1 × 1016 / cm 3 The following is more preferable: 1 × 10 16 / cm 3 It shall be less than 1. Also, the carrier concentration of the oxide semiconductor layer 140 is 1 × 10⁻⁶. 14 / cm 3 Less than, preferably 1 × 10 12 / cm 3 Less than 1 × 10 11 / cm 3 Not yet It can be satisfied. In addition, the hydrogen concentration has been sufficiently reduced and the oxide semiconductor has been purified to a high degree. Layer 140 is a typical silicon wafer (with trace amounts of impurity elements such as phosphorus and boron added). Carrier concentration (1 × 10) in silicon wafer 14 / cm 3 (To the extent of) It takes on a small carrier concentration value in minutes. In this way, the hydrogen concentration is sufficiently reduced and high purity is achieved. Therefore, an i-type or substantially i-type oxide semiconductor with a sufficiently low carrier concentration is used. By doing so, it is possible to obtain transistor 402 with extremely excellent off-current characteristics. If the channel width W is 1 × 10 4 Even if the element has a channel length L of 3 μm in μm, the drain When the drain voltage Vd applied to the electrode is +1V or +10V, the gate electrode When the applied gate voltage Vg is in the range of -5V to -20V, the off-current at room temperature is 1 × 10 -13 It is less than or equal to A. Note that the hydrogen concentration in the oxide semiconductor layer is determined by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectroscopy) It has been established.

[0051] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0052] In other words, in the elements of the non-volatile latch circuit shown in Figure 3, transistor 421 The gate electrode 110a and the source electrode or drain electrode 142a of the transistor 402 However, via electrodes 130c, 136c, 150c, 154c and 150d They are electrically connected.

[0053] <Method for fabricating elements of a non-volatile latch circuit> Next, an example of a method for fabricating the elements of the non-volatile latch circuit described above will be explained. First, I will explain how to fabricate transistor 421 at the bottom, referring to Figure 4. Next, the method for fabricating the upper transistor 402 will be explained with reference to Figures 5 and 6. .

[0054] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 4(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. An example will be shown. Generally speaking, an "SOI substrate" is a substrate with silicon semiconductor on an insulating surface. This refers to a substrate having a conductive layer, but in this specification, it refers to a substrate having a silicon on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. This also includes the following.

[0055] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 4(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of materials such as silicon nitride can be used. In order to control the threshold voltage of the transistor, an impurity is used to impart n-type conductivity. Elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of condensate, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This is possible. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. You can use materials like um and gallium.

[0056] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 4(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0057] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0058] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0059] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment can be performed using, for example, He, Ar, Kr, X This process is carried out using a mixture of gases such as noble gases (e), oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen. This is possible. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm to 100 nm. It can be less than or equal to m.

[0060] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0061] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a. Form the gate electrode 110a (see Figure 4(C)).

[0062] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see Figure 4(C)). Then, By adding phosphorus (P) or arsenic (As) to the semiconductor region 104, impurities with a shallow junction depth are removed. Region 114 is formed (see Figure 4(C)). Note that an n-type transistor is formed here. Although phosphorus or arsenic is added for this purpose, when forming a p-type transistor, boron (B) is used. Or impurity elements such as aluminum (Al) can be added. Note that in the impurity region 114 As a result of the formation, a channel formation region 11 is formed below the gate insulating layer 108a of the semiconductor region 104. Formation 6 is created (see Figure 4(C)). Here, the concentration of the added impurities should be set as appropriate. This is possible, but when semiconductor devices are miniaturized to a high degree, it is desirable to increase the concentration. Furthermore, here, the process of forming the impurity region 114 after forming the insulating layer 112 is described. Although this method is used, it is also used as a step to form the insulating layer 112 after forming the impurity region 114. good.

[0063] Next, the sidewall insulating layer 118 is formed (see Figure 4(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110a and the impurity region are removed. It would be good to expose the top surface of 114.

[0064] Next, cover the gate electrode 110a, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region in contact with the impurity region 114, phosphorus (P) and arsenic (As) and other substances are added to form a high-concentration impurity region 120. Then, the insulating layer is removed. Remove the gate electrode 110a, sidewall insulating layer 118, high-concentration impurity region 120, etc. A metal layer 122 is formed to cover it (see Figure 4(E)). This metal layer 122 is formed by vacuum deposition. It can be formed using various film deposition methods such as sputtering and spin coating. The metal layer 122 reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metallized layer. It is desirable to form the composite using metallic materials. Examples of such metallic materials include: Examples include titanium, tantalum, tungsten, nickel, cobalt, and platinum.

[0065] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 4(F)). Furthermore, if polycrystalline silicon or the like is used as the gate electrode 110a, A metal compound region will also be formed in the area of ​​0a that is in contact with the metal layer 122.

[0066] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0067] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 4(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic. Although it has a two-layer structure consisting of an edge layer 126 and an interlayer insulating layer 128, the configuration of the interlayer insulating layer is not limited to this. No. After the formation of the interlayer insulating layer 128, its surface is subjected to CMP or etching treatment, etc. Therefore, it is desirable to flatten it.

[0068] Subsequently, an opening is formed in the interlayer insulating layer that extends to the metal compound region 124, and the opening Then, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are connected. Form (see Figure 4(H)). Source electrode or drain electrode 130a or source electrode or The drain electrode 130b is, for example, subjected to PVD or CVD methods in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed using methods such as etching or CMP. It can be formed by removing [something].

[0069] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. It removes essential elements such as tungsten, titanium, and titanium nitride, while also improving the flatness of the surface. This can be done. In this way, the source electrode or drain electrode 130a, source electrode Alternatively, by planarizing the surface including the drain electrode 130b, a good result can be obtained in a later process. This makes it possible to form suitable electrodes, wiring, insulating layers, semiconductor layers, and so on.

[0070] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, The electrode that comes into contact with electrode 110a (for example, electrode 130c in Figure 3(A)) They can be formed together. Source electrode or drain electrode 130a, source electrode or There are no particular limitations on the material that can be used as the drain electrode 130b, and various conductive materials are available. Electrical materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten. Conductive materials such as stainless steel, aluminum, copper, neodymium, and scandium can be used. Cut.

[0071] As a result, a transistor 421 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0072] <Method for fabricating the upper transistor> Next, using Figures 5 and 6, the process of fabricating the transistor 402 on the interlayer insulating layer 128 is described. The process will be explained. Figures 5 and 6 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 402, and is therefore located at the bottom of transistor 402. Details regarding transistors such as transistor 421 have been omitted.

[0073] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 5(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using materials containing inorganic insulating materials such as ru.

[0074] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 5(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching can be done using wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a ching. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film method. Materials that can be used to form the conductive layer 134 include Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as scandium, as well as alloys and compounds of these materials (e.g., nitrides). It is possible.

[0075] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, sole Function to reduce contact resistance with the drain electrode or electrode 130b, electrode 130c, etc. It has. Furthermore, the titanium nitride film formed thereafter suppresses the diffusion of conductive materials. It has the function of [unclear]. In addition, after forming a barrier film with titanium or titanium nitride, plating is performed. A copper film may be formed according to the law.

[0076] After forming the conductive layer 134, the conductive layer 1 is formed using methods such as etching and CMP. Remove a portion of 34 to expose the insulating layer 132, and then remove electrode 136a, electrode 136b, electrode 1 36c, forming the gate electrode 136d (see Figure 5(C)). Note that the conductive layer 134 By removing a portion, electrodes 136a, 136b, 136c, and gate electrode 136d are formed. When doing so, it is desirable to process the surface so that it becomes flat. In this way, insulating layer 13 2. Planarize the surfaces of electrode 136a, electrode 136b, electrode 136c, and gate electrode 136d. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0077] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 5(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0078] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0079] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something desirable.

[0080] Of course, if it can form a good insulating layer as a gate insulating layer, purified acid Even when using a synthetic semiconductor layer, other methods such as sputtering and plasma CVD are used. The law can be applied. Furthermore, the film quality and interface properties can be modified by heat treatment after formation. An insulating layer may be applied. In any case, the film quality of the gate insulating layer 138 is good. In addition, it is possible to reduce the interface state density with the oxide semiconductor layer and form a good interface. Just form it.

[0081] Furthermore, 85℃, 2×10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, if impurities are added to the oxide semiconductor, the impurities and the oxide semiconductor... The bonds with the main component are broken by a strong electric field (B: bias) and high temperature (T: temperature), and The resulting uncoupled hands induce a drift in the threshold voltage (Vth).

[0082] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, and as described above, By improving the interface characteristics with the insulating layer, stable transients are achieved even under BT testing. It is possible to obtain the result.

[0083] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 5(E)).

[0084] Examples of oxide semiconductor layers include In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer. In this embodiment, an oxide semiconductor Using an In-Ga-Zn-O metal oxide target as the conductive layer, amorphous oxide The semiconductor layer will be formed by sputtering. By adding ricon, its crystallization can be suppressed, for example, SiO2 An oxide semiconductor layer may be formed using a target containing 2% to 10% by weight of the material.

[0085] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A metal oxide target with zinc as the main component can be used. In addition, In, Ga, and a metal oxide target containing Zn (composition ratio: In2O3:Ga2O3:Zn) You can also use a molar ratio such as O=1:1:1. Furthermore, In, Ga, and Zn... As a metal oxide target containing In2O3:Ga2O3:ZnO=1:1:2[m [mol ratio], or composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [mol ratio] You may use targets that have the following properties. The filling density of the metal oxide target should be 90% or more. The percentage is 0% or less, preferably 95% or more (for example, 99.9%). High-filling metal oxides By using a target, a dense oxide semiconductor layer is formed.

[0086] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). Preferably, it is a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). For example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). Preferably, it is a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less).

[0087] When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced.

[0088] As formation conditions, for example, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa, DC power of 0.5 kW, atmosphere is oxygen (oxygen flow rate ratio 100%). These conditions can be applied. Note that using a pulsed DC power supply will remove dust. This is preferable because it reduces the amount of noise and results in a uniform film thickness distribution. The thickness of the oxide semiconductor layer is 2 nm or less. The wavelength should be 200 nm or less, preferably 5 nm to 30 nm. The appropriate thickness varies depending on the conductive material, so the thickness should be selected appropriately according to the material being used. good.

[0089] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced and plastic Reverse sputtering is performed to generate sputter, and dust adhering to the surface of the gate insulating layer 138 is removed. It is preferable to remove it. Here, reverse sputtering is defined as in normal sputtering, sputtering Instead of colliding ions with the target, by colliding ions with the treatment surface... This refers to a method of modifying the surface. One method involves colliding ions with the treated surface. A high-frequency voltage is applied to the processing surface in an argon atmosphere to generate plasma near the substrate. There are methods such as this. Furthermore, nitrogen, helium, oxygen, etc. can be used instead of an argon atmosphere. good.

[0090] The above oxide semiconductor layer can be etched using either dry etching or wet etching. You may also use this. Of course, you can also use both in combination. To create the desired shape... To enable etching, etching conditions (etching gas, etching solution, etc.) can be adjusted according to the material. Set the appropriate settings (watching time, temperature, etc.).

[0091] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( Examples include CCl4, etc. Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride) are used. Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C) HF3, etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Gases to which noble gases such as argon (Ar) have been added may also be used.

[0092] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0093] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, A mixture of ammonia, water, and hydrogen peroxide can be used. Alternatively, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0094] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. A heat treatment is performed at 450°C under atmospheric pressure for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. Prevent re - mixing of water and hydrogen without contact.

[0095] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the workpiece by heat conduction from a medium such as heated gas, or by thermal radiation. For example, it may be an apparatus that uses an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus. The LRTA apparatus is an apparatus that heats the workpiece by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high - pressure sodium lamps, high - pressure mercury lamps, etc. The GRTA apparatus is an apparatus that performs heat treatment using high - temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the workpiece during heat treatment are used.

[0096] For example, as the first heat treatment, a GRTA treatment can be performed in which a substrate is introduced into an inert gas heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the substrate is taken out from the inert gas.

[0097] Using GRTA treatment enables high - temperature heat treatment in a short time. Also, because it is a short - time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0098] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or noble gases (helium, neon, argon, etc.) and free of water, hydrogen, etc. For example, 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0098] Furthermore, when an electric furnace is used for the first heat treatment, the atmosphere is switched when the heat treatment cools down. This can be done. For example, the atmosphere during heat treatment can be an inert gas such as nitrogen, or helium, etc. The atmosphere is initially composed of noble gases such as ON and argon, and the atmosphere is switched to an oxygen-containing atmosphere during cooling. It can be referred to as a gas. Examples of oxygen-containing atmospheres include oxygen gas or a mixture of oxygen and nitrogen gas. A gas mixture can be used. When using this oxygen-containing atmosphere, Preferably, it does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas and nitrogen gas used. The degree should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, ( In other words, it is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0099] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or more, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0100] Furthermore, microcrystals (with a particle size of 1 nm or less) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer will have a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm). In some cases, it may be the case.

[0101] Furthermore, by arranging microcrystals within an amorphous material, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to use an In-Ga-Zn-O metal oxide target to acid When forming a crystalline semiconductor layer, electrically anisotropic In2Ga2ZnO7 crystal grains are used. By forming oriented microcrystalline regions, the electrical properties of the oxide semiconductor layer can be changed. can.

[0102] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the material in a specific direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. It holds.

[0103] Furthermore, the oxide semiconductor layer having the above-mentioned microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. Also, the Zn content is related to the In or Ga content. By using a smaller sputtering target, it is possible to form the material more favorably.

[0104] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0105] Furthermore, the above heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. This can also be called dehydration treatment, dehydrogenation treatment, etc. The process involves forming an oxide semiconductor layer, and then placing a source electrode or drain on the oxide semiconductor layer 140. After stacking the electrodes, a protective insulating layer is formed on the source electrode or drain electrode, etc. This can be done at the appropriate timing. The principle can be applied not just once, but multiple times.

[0106] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 5(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0107] The conductive layer is produced using PVD (Physical Vapor Deposition), including sputtering. CVD (Chemical Vapor) methods such as the CVD method and plasma CVD method. It can be formed using the Deposition method. Furthermore, the material for the conductive layer is... Choose from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The elements mentioned above, or alloys containing the aforementioned elements, can be used. Instead, manganese, magnesium, zirconium, beryllium, thorium, and yttrium One or more of the following materials may be used. In addition, aluminum may be used. Choose from tan, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Materials consisting of one or more of the specified elements may be used. The conductive layer has a single-layer structure. It is also acceptable to use a laminated structure of two or more layers. For example, aluminum containing silicon. Single-layer structure of the film, two-layer structure in which a titanium film is laminated on an aluminum film, titanium film and aluminum Examples include a three-layer structure in which a um film and a titanium film are stacked. Also, In-Ga-Zn- O series, In-Sn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system oxides A conductive film can be used. In this case, compared with the material used for the oxide semiconductor layer 140 It is preferable to use materials with high conductivity or low resistivity for the oxide conductive film. The conductivity of a conductive film can be increased by increasing the carrier concentration. The carrier concentration can be increased by increasing the hydrogen concentration. Also, the carrier concentration of oxide conductive films Carrier concentration can be increased by increasing oxygen deficiency.

[0108] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0109] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance between the source electrode or the lower end of the drain electrode 142b. When performing exposures where the channel length (L) is less than 25 nm, the range is several nm to several tens of nm. And using extremely short wavelength ultra-ultraviolet light, Exposure for chromosome formation is performed. Exposure with ultra-ultraviolet light provides high resolution and a large depth of field. Therefore, The design will result in a transistor channel length (L) of less than 25 nm. It is possible to set the channel length (L) to between 10 nm and 1000 nm. It is possible, and the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, This prevents a significant increase in power consumption.

[0110] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0111] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The conductive layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0112] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. A resist mask is formed using a multi-gradation mask, and this is used for etching. The process may be carried out. A resist mask formed using a multi-gradation mask has multiple thicknesses. It takes on a stepped shape, and can be further deformed by ashing, so different It can be used in multiple etching processes to create patterns. In other words, a single multi-gradation The mask creates a resist mask that corresponds to at least two different patterns. This can be achieved. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography can be reduced. Since the graphics process can also be reduced, the process can be simplified.

[0113] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the exposed oxide semiconductor layer surface Adhering water and other substances are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may go.

[0114] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 5(G)).

[0115] The protective insulating layer 144 is formed by methods such as sputtering, which introduces impurities such as water and hydrogen into the protective insulating layer 144. It can be formed using appropriate methods that do not involve condensation. Furthermore, its thickness is at least 1 nm. The above applies. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, Examples include silicon oxide nitride and silicon oxide nitride. Furthermore, their structure can be a single-layer structure. A laminated structure is also acceptable. The substrate temperature when forming the protective insulating layer 144 should be above room temperature and up to 300°C. The following is preferable, and the atmosphere should be a noble gas atmosphere (typically argon) or an oxygen atmosphere. Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferred.

[0116] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... Oxygen extraction occurs in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, the protective insulating layer 14 In step 4, it is important to avoid using hydrogen in the formation process, as this will minimize the amount of hydrogen used. be.

[0117] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are free from hydrogen, hydroxyl groups, or moisture. This is for the purpose of doing so.

[0118] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the film is formed in the said deposition chamber. The concentration of impurities in the protective insulating layer 144 can be reduced.

[0119] The sputtering gas used when forming the protective insulating layer 144 may be hydrogen, water, hydroxyl groups or Impurities such as hydrides are removed to a concentration of several ppm or less (preferably, several ppb or less). It is preferable to use a highly purified gas from which the gas has been removed.

[0120] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the converter.

[0121] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be carried out while maintaining a constant heating temperature, or from room temperature to over 100°C. The process involves repeatedly raising the temperature to 200°C and then lowering it back to room temperature. This may also be done. Furthermore, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. By performing the heat treatment in the manner described above, the heating time can be shortened. It can be performed as an alternative to heat treatment, or before or after a second heat treatment.

[0122] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 6(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide Formation of interlayer insulating layer 146 is possible using materials containing inorganic insulating materials such as ru. Afterward, it is desirable to planarize the surface using methods such as CMP or etching. It's nice.

[0123] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 6(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0124] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is at the interface The oxide film is reduced, and the lower electrode (here, electrode 136a, electrode 136b, electrode 136c, so Contact with the source electrode or drain electrode 142a, source electrode or drain electrode 142b) It has the function of reducing contact resistance. Furthermore, the titanium nitride film that is formed afterward is a conductive material. It has a barrier function that suppresses the diffusion of the material. In addition, a barrier film made of titanium or titanium nitride. After forming the material, a copper film may be formed by a plating method.

[0125] After forming the conductive layer 148, the conductive layer 148 is formed using methods such as etching and CMP. By removing a portion of it and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 1 50c, electrode 150d, and electrode 150e are formed (see Figure 6(C)). Note that the above conductive layer Remove a portion of 148 to obtain electrodes 150a, 150b, 150c, 150d, and When forming the 150e pole, it is desirable to process the surface so that it is flat. Sea urchin, interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By flattening the surface of electrode 150e, a good electrode, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form marginal layers, semiconductor layers, and the like.

[0126] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 6(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0127] When transistor 402 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 atoms / cm 3 The following applies, and also, at room temperature, transistor 402 The off-current is 1 × 10 -13 It becomes A or less. By applying a highly purified oxide semiconductor layer 140, a transistor 40 with excellent characteristics is obtained. 2 can be obtained. Also, transistor 42 using a material other than an oxide semiconductor at the bottom. A semiconductor with excellent properties having 1 and a transistor 402 made of oxide semiconductor on top. The device can be manufactured.

[0128] Furthermore, as a semiconductor material that can be compared to oxide semiconductors, silicon carbide (for example, 4H) is a suitable example. There is -SiC). Oxide semiconductors and 4H-SiC have several things in common. The riac density is one example. According to the Fermi-Dirac distribution, the minority of oxide semiconductors The career is 10 -7 / cm 3 It is estimated to be around 6.7 in 4H-SiC. ×10 -11 / cm 3 Similarly, it is an extremely low value. The intrinsic carrier density of silicon (1. 4 x 10 10 / cm 3 If you compare it to other things, you can clearly see that its degree is extraordinary. Cut.

[0129] Furthermore, the energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-S Since the energy bandgap of iC is 3.26 eV, it is a wide-bandgap semiconductor. In this respect, oxide semiconductors and silicon carbide have something in common.

[0130] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. Semiconductor processes using silicon carbide generally operate at temperatures between 1500°C and 2000°C. Because heat treatment is required, it is difficult to create a stacked structure with semiconductor elements using other semiconductor materials. This is because such high temperatures can destroy semiconductor substrates and semiconductor elements. On the other hand, oxide semiconductors can withstand temperatures of 300-500°C (below the glass transition temperature, and at most around 700°C). It can be fabricated by heat treatment at 5 degrees, and integrated circuits can be formed using other semiconductor materials. As described above, it becomes possible to form semiconductor devices using oxide semiconductors.

[0131] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment, compared to silicon carbide. This has the advantage of significantly reducing energy costs.

[0132] Furthermore, in oxide semiconductors, the Institute for Solid State Physics (IPSJ) has established DOS (density of state) and other properties. Many studies have been conducted, but these studies do not aim to significantly reduce the use of DOS itself. Does not include. In one aspect of the disclosed invention, water and hydrogen, which can be causes of increased DOS, are used as oxides. By removing it from the conductor, a highly purified oxide semiconductor is fabricated. This is the DOS itself It is based on the idea of ​​significantly reducing the amount of things we own. And by doing so, it is extremely excellent. This enables the manufacture of industrial products.

[0133] Furthermore, it supplies oxygen to the unbonded metals that occur due to oxygen deficiency, and the oxygen vacancies By reducing DOS, an even higher purity (type i) oxide semiconductor can be achieved. This is also possible. For example, by forming an oxygen-rich oxide film in close proximity to the channel-forming region. By supplying oxygen from the oxide film, it is possible to reduce DOS caused by oxygen vacancies.

[0134] Defects in oxide semiconductors include levels below the conduction band of 0.1-0.2 eV due to excess hydrogen, and oxygen... These are believed to be caused by deep energy levels due to deficiencies, etc. In order to eliminate these defects, I believe the technological concept of thoroughly removing hydrogen and supplying sufficient oxygen is correct. It can be obtained.

[0135] Furthermore, although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, impurities, In particular, the i-type is achieved by removing water and hydrogen. In this respect, unlike silicon, This is not simply a matter of adding impurities to create type i, but rather involves a completely new technological concept.

[0136] <Conductivity mechanism of transistors using oxide semiconductors> Here, the conductivity mechanism of an oxide semiconductor transistor is shown using Figures 7 to 10. Let me explain. Note that the following explanation assumes an ideal situation for the sake of ease of understanding. Not everything may reflect reality. Furthermore, the following explanation is merely one possible interpretation. It should be noted that this is merely a matter of fact and does not affect the effectiveness of the invention.

[0137] Figure 7 shows a cross-section of an inverse staggered transistor (thin-film transistor) using an oxide semiconductor. This is a diagram. An oxide semiconductor layer (O) is placed on the gate electrode (GE1) via a gate insulating layer (GI). A (S) is provided, and a source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided to cover the main electrode (S) and the drain electrode (D).

[0138] Figure 8 shows the energy band diagram (schematic diagram) in the A-A' section of Figure 7. In diagram 8, the black circles (●) represent electrons, and the white circles (○) represent holes, with their respective charges (-q, +q). ) has a positive voltage (V) across the drain electrode. D After applying >0), the dashed line represents the gate voltage. When no voltage is applied to the pole (V G (=0), the solid line represents a positive voltage (V) across the gate electrode. G Mark >0) This shows the case where voltage is applied. When no voltage is applied to the gate electrode, the high potential barrier is due to This indicates an off state where no carriers (electrons) are injected from the electrode to the oxide semiconductor, resulting in no current flow. On the other hand, applying a positive voltage to the gate lowers the potential barrier, allowing current to flow. To show a certain state.

[0139] Figure 9 shows a schematic diagram of the energy bands in the cross-section B-B' in Figure 7. Figure 9(A) shows a positive voltage (V) applied to the gate electrode (GE1). G The given state is >0. This indicates the ON state, where carriers (electrons) flow between the source electrode and the drain electrode. Furthermore, Figure 9(B) shows a negative voltage (V) applied to the gate electrode (GE1). G With <0) applied This indicates the off state (where minority carriers are not flowing).

[0140] Figure 10 shows the vacuum level and the work function of the metal (φ M ), Relationship of electron affinity (χ) of oxide semiconductors This indicates.

[0141] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band.

[0142] On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E F ) is the band gap The centrally located true Fermi level (E i It is located away from the conduction zone and closer to it. It is known that in oxide semiconductors, some hydrogen acts as a donor, which is one of the factors that causes n-type semiconductors. It is being done.

[0143] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By increasing the purity in such a way, it is made into true (type i), or attempted to be made into true. .

[0144] In other words, instead of adding impurity elements to create type i, the goal is to remove as many impurities as possible, such as hydrogen and water. This process is characterized by producing highly purified type i (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the true Fermi level (E i ) to the same extent as It is possible.

[0145] Band gap (E) of oxide semiconductors g The voltage is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that makes up the source electrode and drain electrode is: It is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface... Therefore, a Schottky-type barrier is not formed for electrons.

[0146] At this time, as shown in Figure 9(A), electrons are in the gate insulating layer and the highly purified oxide semiconductor. It moves near the interface (the lowest, most energetically stable part of the oxide semiconductor).

[0147] Furthermore, as shown in Figure 9(B), when a negative potential is applied to the gate electrode (GE1), a decimal Since the number of holes, which are the carriers, is practically zero, the current will be a value very close to zero. ru.

[0148] In this way, high purity is achieved by minimizing the presence of elements other than the main components of oxide semiconductors (impurity elements). By converting to a certain degree, it becomes intrinsic (type i) or substantially intrinsic, thus creating a boundary with the gate insulating layer. Surface properties are important. Therefore, the gate insulating layer must form a good interface with the oxide semiconductor. The ability to do so is required. Specifically, for example, in the power supply frequency range from the VHF band to the microwave band. Insulating layers are fabricated using CVD methods with high-density plasma, or by sputtering methods. It is preferable to use an insulating layer or the like that is manufactured.

[0149] To improve the purity of the oxide semiconductor while ensuring a good interface between the oxide semiconductor and the gate insulating layer. By doing so, for example, the channel width W of the transistor is 1 × 10 4 μm, channel length L In the case of 3 μm, 10 -13 Off-current of less than A, subthreshold of 0.1V / dec. A lud swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0150] In this way, the oxide semiconductor is processed to minimize the presence of elements other than its main component (impurity elements). Purification can improve the operation of transistors.

[0151] <Hot carrier degradation resistance of transistors using oxide semiconductors> Next, regarding the hot carrier degradation resistance of transistors using oxide semiconductors, see Figure 11 to Let's explain using Figure 13. For the sake of clarity, the following explanation assumes an ideal scenario. However, not all of these depict real-world situations. Furthermore, the following explanation is... I should add that this is merely one possible interpretation.

[0152] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). There is also drain avalanche hot carrier injection (DAHC injection). Note that the following is a simplified explanation. For simplicity, we will consider only electrons.

[0153] CHE implantation is a process in which a semiconductor layer is implanted with energy exceeding that of the gate insulating layer barrier. This refers to the phenomenon in which electrons that have become electrons are injected into the gate insulating layer, etc. Energy transfer to electrons. This is achieved by accelerating electrons in a low electric field.

[0154] DAHC injection is a process in which new electrons are generated by collisions of electrons accelerated by a high electric field. This refers to the phenomenon of injection into insulating layers, etc. The difference between DAHC injection and CHE injection is that collision ions The key difference lies in whether or not it involves avalanche breakdown due to denaturation. Furthermore, in DAHC injection, the semiconductor... Electrons with kinetic energy greater than the gap are required.

[0155] Figures 11 and 12 show silicon (Si) and In-Ga-Zn-O based oxide semiconductors (I This shows the energy required for various hot carrier injections, estimated from the band structure of GZO. In Figures 11 and 12, the left side represents CHE injection and the right side represents DAHC injection.

[0156] In silicon, degradation due to DAHC injection is more severe than that due to CHE injection. In a given atmosphere, only a very small number of carriers (e.g., electrons) are accelerated without colliding. This is due to the fact that silicon has a small band gap and is prone to avalanche yielding. Avalanche breakdown increases the number of electrons that can cross the gate insulating layer barrier, and CHE The probability of successful injection is easily exceeded.

[0157] In InGa-Zn-O oxide semiconductors, the energy required for CHE implantation is the same as in silicon. This is not significantly different from the case mentioned earlier, and the probability is still low. Also, the necessary for DAHC injection The energy required is approximately the same as the energy needed for CHE injection due to the wide band gap. ru.

[0158] In other words, the probability of CHE injection and DAHC injection is low compared to silicone, and hotkeys It has high resistance to carrier degradation.

[0159] By the way, the band gap of In-Ga-Zn-O oxide semiconductors is used as a high-voltage material. It is comparable to silicon carbide (SiC), which is attracting attention. Figure 13 shows the properties of 4H-SiC. This shows the energy required for various hot carrier injections. For CHE injection, In-Ga -Zn-O based oxide semiconductors have a slightly higher threshold and can be considered advantageous.

[0160] In summary, In-Ga-Zn-O based oxide semiconductors exhibit hot carrier degradation compared to silicon. It can be seen that it has very high resistance to carbonization and to source-drain destruction. It can be said that it achieves pressure resistance comparable to that of silicon.

[0161] <Short-channel effect in transistors using oxide semiconductors> Next, regarding the short-channel effect in an oxide semiconductor transistor, see Figure 14 and Figure 14. We will explain using 15. Note that, for the sake of ease of understanding, we will assume an ideal situation in the following explanation. However, not all of these descriptions reflect reality. Also, the following explanation is merely... I should add that this is merely one possible interpretation.

[0162] The short-channel effect becomes apparent with the miniaturization of transistors (reduction of channel length (L)). This refers to the degradation of electrical characteristics. Short-channel effect is when the effect of the drain extends to the source. This is due to the following. Specific examples of short-channel effects include a decrease in threshold voltage and the S value. This includes an increase in [something] and an increase in leakage current.

[0163] Here, we use device simulation to demonstrate how to suppress short-channel effects. The construction was verified. Specifically, the carrier concentration and the thickness of the oxide semiconductor layer were varied. Four types of models were prepared to examine the relationship between the channel length (L) and the threshold voltage (Vth). As the models, transistors with a bottom gate structure were adopted, and the carrier concentration of the oxide semiconductor was set to either 1.7×10 / cm -8 or 1.0×10 3 / cm 15 and the thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. Note that an In-Ga-Zn-O-based oxide semiconductor was used as the oxide semiconductor, and a silicon oxynitride film with a thickness of 100 nm was adopted as the gate insulating layer. The bandgap of the oxide semiconductor was assumed to be 3.15 eV, the electron affinity was assumed to be 4.3 eV, the relative permittivity was assumed to be 15, and the electron mobility was assumed to be 10 cm<00xxx086> / Vs. The relative permittivity of the silicon oxynitride film was assumed to be 4.0. The device simulation software "Atlas" manufactured by Silvaco was used for the calculation. Note that there is no significant difference in the calculation results between the top gate structure and the bottom gate structure. The calculation results are shown in FIGS. 14 and 15. FIG. 14 shows the case where the carrier concentration is 1.7×10 / cm -8 and FIG. 15 shows the case where the carrier concentration is 1.0×10 15 / cm 3 [[ID=XX]]In FIGS. 14 and 15, with a transistor having a channel length (L) of 10 μm as a reference, the change amount (ΔVth) of the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm is shown. As shown in FIG. 14, when the carrier concentration of the oxide semiconductor is 1.7×10

[0164]

[0165] -8 / cm m 3 and the thickness of the oxide semiconductor layer is 1 μm, the change amount of the threshold voltage 15 / cm " 3 is shown. As shown in FIG. 14, when the carrier concentration of the oxide semiconductor is 1.7×10 and the thickness of the oxide semiconductor layer is 1 μm, the change amount of the threshold voltage (L) is changed from 10 μm to 1 μm, the change amount (ΔVth) of the threshold voltage (Vth) is shown. As shown in FIG. 14, when the carrier concentration of the oxide semiconductor is 1.7×1 0 0 -8 / cm 3 and the thickness of the oxide semiconductor layer is 1 μm, the change amount of the threshold voltage [[ID=XX]] (ΔVth) was -3.6 V. Also, as shown in FIG. 14, the carrier concentration of the oxide semiconductor was 1.7×10 -8 / cm 3 ; when the thickness of the oxide semiconductor layer was 30 nm, the change amount (ΔVth) of the threshold voltage was -0.2 V. Also, as shown in FIG. 15, the carrier concentration of the oxide semiconductor was 1.0×10 15 / cm 3 ; when the thickness of the oxide semiconductor layer was 1 μm, the change amount (ΔVth) of the threshold voltage was -3.6 V. Also, as shown in FIG. 15, the carrier concentration of the oxide semiconductor was 1.0×10 15 / cm 3 ; when the thickness of the oxide semiconductor layer was 30 nm, the change amount (ΔVth) of the threshold voltage was -0.2 V. It can be said that the results show that the short-channel effect can be suppressed by reducing the thickness of the oxide semiconductor layer in a transistor using an oxide semiconductor. For example, when the channel length (L) is about 1 μm, even if the oxide semiconductor layer has a sufficiently high carrier concentration and its thickness is about 30 nm, it is understood that the short-channel effect can be sufficiently suppressed. [[ID=3l]]

[0166] <Carrier Concentration> The technical idea of the disclosed invention is to make the carrier concentration in the oxide semiconductor layer sufficiently low and [[ID=For example, as close as possible to intrinsic (i-type). Hereinafter, the method for obtaining the carrier concentration and the actually measured carrier concentration will be described with reference to FIGS. 16 and 17.

[0167] First, the method for obtaining the carrier concentration will be briefly described. The carrier concentration is obtained by fabricating a MOS capacitor and evaluating the result (C-V characteristics) of the C-V measurement of the MOS capacitor. It is possible to do so.

[0168] More specifically, the relationship between the gate voltage Vg and capacitance C of a MOS capacitor is plotted as C. -V characteristics are obtained, and from these CV characteristics, the gate voltage Vg and (1 / C) 2 The relationship is represented by A rough sample is obtained, and in the graph, the (1 / C) in the weak inversion region is... 2 Find the derivative of and Substituting the fractional values ​​into equation (1), the carrier concentration N d The magnitude of can be determined. In (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor. ru.

[0169]

number

[0170] Next, we will explain the carrier concentration that was actually measured using the method described above. A titanium film is formed on a lath substrate to a thickness of 300 nm, and a titanium nitride film is formed on the titanium film. Formed with a thickness of nm, an In-Ga-Zn-O based oxide semiconductor is used on the titanium nitride film. A silicon oxynitride film is formed on the oxide semiconductor layer with a thickness of 2 μm, and a silicon oxynitride film is formed on the oxide semiconductor layer for 300 μm. A sample was formed with a thickness of m, and a silver film was formed on the silicon oxynitride film with a thickness of 300 nm (MOS crystal). (Japashita) was used. The oxide semiconductor layer is a metal oxide containing In, Ga, and Zn. Sputtering using a material target (In:Ga:Zn=1:1:0.5[atom%]) It was formed by the argon-sulfonation method. The formation atmosphere for the oxide semiconductor layer was a mixed atmosphere of argon and oxygen. The ambient air (flow ratio: Ar:O2 = 30 (sccm): 15 (sccm)) was used.

[0171] Figure 16 shows the CV characteristics, and Figure 17 shows Vg and (1 / C). 2 The relationship between each is shown in the figure. (1 / C) in the weak inversion region of 17 2 The carrier obtained from the derivative of using equation (1) The concentration is 6.0 × 10 10 / cm 3 That was the case.

[0172] Thus, an i-type or substantially i-type oxide semiconductor (for example, with a carrier concentration of 1 x 10 12 / cm 3 Less than, preferably 1 × 10 11 / cm 3 By using the following, It is possible to obtain transistors with extremely excellent off-current characteristics.

[0173] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0174] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0175] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0176] (Embodiment 2) This embodiment describes the configuration of a non-volatile latch circuit, which is one aspect of the disclosed invention. An example different from Figure 1 will be explained with reference to Figure 18. Figure 18(A) shows the latch part 411 and A non-volatile latch circuit 400 having a data holding section 401 that holds data from the latch section. The configuration is shown. Figure 18(B) shows the configuration of the data holding unit 401.

[0177] Figure 18 shows an example where the configuration of the data holding unit 401 differs from that in Figure 1. Specifically, the data This is an example where the capacity of the holding section 401 (capacity 404 in Figure 1) is not provided. The other configurations are the same as in Figure 1. Since it is as described, the explanation will be omitted. The configuration of transistor 402 is the same as in Embodiment 1. .

[0178] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region. The transistor 402 is used as a switching element. The inverter 403 is electrically connected to the source electrode and the other of the drain electrode of 02. It is.

[0179] The source electrode and one of the drain electrodes of this transistor 402 are connected when an output signal is applied. It is electrically connected to wiring 415. Also, the output of inverter 403 is given an input signal. It is electrically connected to the wiring 414. The inverter 403 is connected to the transistor 420. It has transistor 421. The source electrode of transistor 420 is high level It is electrically connected to the power supply voltage VDD. The source electrode of transistor 421 is low level. It is electrically connected to the power supply voltage VSS.

[0180] This embodiment is a configuration that does not have capacity connected to node S. In this case, invert Charge is accumulated in the gate capacitance of the transistor constituting TA403. Here, preferably The gate capacitance of transistor 421 in inverter 403 is The gate capacitance of transistor 420 can be made larger than that of transistor 420. The size is determined by the transistor's channel length L, channel width W, gate insulating film thickness, and dielectric constant. It can be controlled by this. In this way, transistor 420 and transistor The proportion of the 421 gate capacity configured between VSS and node S increases, The potential of the gate electrodes of transistors 420 and 421 is affected by fluctuations in VDD. This is preferable because it makes it less likely to occur.

[0181] The inverter 403 is not limited to the configuration shown in Figure 18(B), but can also be configured as shown in Figure 2(A), for example. It can be constructed using N-channel transistors, or it can be configured with a buffer at the output. Alternatively, a sense amplifier circuit may be used instead of inverter 403. For example, see Figure 2. A differential amplifier type sense amplifier circuit as shown in (B) may also be used. In either case, It is important that the power terminal is in a floating state (high impedance state). In the circuit shown in Figure 2(A), the input charge is stored in the gate capacitance of transistor 421. Furthermore, in the circuit shown in Figure 2(B), the input charge is the gate capacity of transistor 421. It accumulates in quantity. The circuits shown in Figures 2(A) and 2(B) are mainly composed of these gate capacitances. Since it is configured between VSS and node S, the potential of the input terminal is affected by fluctuations in VDD. This is preferable because it makes it less likely to get stuck.

[0182] This oxide semiconductor transistor 402 holds data in the latch portion 411 The data has the function of writing to the gate capacitance of the inverter 403 of the data holding unit 401. Furthermore, transistor 402 controls the gate capacitance of inverter 403 of data holding unit 401. It has a function to retain the data that has been written to it.

[0183] Writing, holding, and reading data held in the latch unit 411 to the data holding unit 401. Let's explain the output and rewriting process. First, the gate electrode of transistor 402 is connected to The potential supplied to turn on transistor 402 is turned on. This allows the data held in the latch, i.e., the output signal, to be supplied to the wiring 4. A potential of 15 is applied to the input terminal of inverter 403. As a result, inverter 403 The gate capacitance accumulates (writes) a charge corresponding to the potential of wiring 415. After that, The potential of the gate electrode of transistor 402 is set to the potential at which transistor 402 is in the off state. By turning off transistor 402, the gate capacitance of inverter 403 is stored The accumulated charge is retained (held). Read the potential at the input terminal of inverter 403. This allows data to be read (read). Data can be rewritten as described above. This can be done in the same way as writing and storing data.

[0184] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0185] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0186] This embodiment can be freely combined with other embodiments.

[0187] (Embodiment 3) This embodiment describes the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. Next, we will explain this with reference to Figures 19 and 1.

[0188] Figure 19(A) shows the latch unit 411 and the data holding unit 401 which holds the data of the latch unit. Figure 19(B) shows the configuration of a non-volatile latch circuit 400 having [a certain characteristic]. An example timing chart for latch circuit 400 is shown.

[0189] Figure 19(A) is an example that specifically shows the configuration of the latch section 411 in Figure 1(A). (A) shows the configuration of the latch section 411 in Figure 1(A), in which the inverter is used as the first element. This is an example in which an inverter is used as the second element. The configuration of transistor 402 is as follows: This is the same as in the first form of implementation.

[0190] The latch section 411 has inverters 412 and 413. The output of 12 is electrically connected to the input of inverter 413, and the output of inverter 413 is It has a loop structure that is electrically connected to the input of the converter 412. Also, latch section 41 1 has switch 431 and switch 432, and via switch 432 The output of data 413 is electrically connected to the input of inverter 412.

[0191] The input to inverter 412 is supplied with the input signal to the latch circuit via switch 431. It is electrically connected to wiring 414. The output of inverter 412 is the output signal of the latch circuit. It is electrically connected to wiring 415, which is assigned a number.

[0192] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region. The transistor 402 is used as a switching element. Capacitor 404 and inverter are electrically connected to the other end of the source electrode and drain electrode of 02. It has 403.

[0193] The source electrode and one of the drain electrodes of this transistor 402 are connected when an output signal is applied. It is electrically connected to wiring 415. Also, the output of inverter 403 is connected to switch 405 It is electrically connected to wiring 414 to which an input signal is supplied via.

[0194] This oxide semiconductor transistor 402 holds data in the latch portion 411 The machine writes the data to the capacity 404 of the data holding unit 401 and the gate capacity of the inverter 403. It has the ability. In addition, transistor 402 has the capacitance 404 and the data holding unit 401. The converter 403 has a function to retain the data written to its gate capacity.

[0195] Wiring 414 is supplied with the potential of the input signal IN from the preceding circuit. The potential of wiring 415 is output The power signal OUT is supplied to the subsequent circuit. Switch 431 receives the clock signal φ1. A position is assigned. When a high-level potential is applied to the clock signal φ1, switch 431 It turns on. The potential of the clock signal φ2 is applied to switch 432. Clock signal When a high potential is applied to φ2, switch 432 turns on. Transistor 4 The gate of 02 is supplied with the potential of the control signal ST. The control signal ST is a high-level potential. When given, transistor 402 has a potential that turns it on. Switch 405 has a control The potential of the signal LD ​​is applied. When a high potential is applied to the control signal LD, Switch 405 has a potential that turns it on. During normal operation, the clock signal φ2 is It has a signal that is the inverted version of the clock signal φ1. Here, the control signal and the clock signal are high. This example shows how a transistor and a switch turn on when the level is set.

[0196] The inverter 403 of the data holding unit 401 and the inverter of the latch unit 411 412 and inverter 413 are connected to a high-level power supply voltage VDD and a low-level power supply voltage VDD, respectively. The power supply voltage VSS is given.

[0197] Next, Figure 19(B) shows the period during which the non-volatile latch circuit 400 is in operation (operating period) and the period during which it is stopped. During the stopped state period (non-operating period), the input signal IN, output signal OUT, and control signal ST are controlled. Here is an example of a timing chart for the potentials of the control signal LD, clock signal φ1, and clock signal φ2. The node S of the data holding unit 401 and the potential of the power supply voltage VDD are also shown. S represents the potential between one electrode of capacitor 404 and the input terminal of inverter 403. A fixed potential is applied to the other electrode of capacitance 404. For example, the ground potential is applied. Yes, they are.

[0198] In Figure 19(B), periods a, b, d, and e are operating periods, and period c is non-operating period. This is the operating period. Periods a and e are the normal operating periods, and the clock signal φ1, clock A high-level or low-level potential is alternately applied to the signal φ2. Period b is non-operating. This is the preparation period before the period. Period b is also called the fall-down period. Period d is the power supply voltage VDD. This is the preparation period after the system is turned on, before it enters the normal operating period. Period d is also called the startup period. say.

[0199] During normal operation (period a), the clock signal φ1 is high level, and the clock signal φ2 When a low potential is applied, switch 432 turns off and the inverter loop is disconnected. As the connection is interrupted, switch 431 turns on, and the potential of the input signal enters inverter 412. The input signal's potential is inverted by inverter 412 and output as the output signal OUT to the subsequent stage. It is applied to the circuit. When a high-level potential is applied to the clock signal φ1, the input signal If the potential is high, an output signal with a low potential is obtained. When a high potential is applied to signal φ1, if the potential of the input signal is low, This yields an output signal with a high potential. A low level, chrome signal φ1 is applied to the clock signal φ1. When a high potential is applied to the φ2 signal, switch 431 turns off, Switch 432 is turned on, forming an inverter loop, and the potential of the output signal OUT is maintained. (The data is latched). During normal operation, the control signal ST has a transient No potential is applied that would turn on Node 402. Node S retains the potential it had been holding previously. It possesses. Here, it is treated as an indefinite value.

[0200] Next, during the preparation period (period b) before the non-operating period, the control signal ST is connected to transistor 40 When a potential is applied that turns on transistor 2, transistor 402 turns on, and the output signal potential is applied. The signal is applied (written) to node S. If the potential of the output signal is high, node S The potential becomes high. Subsequently, the signal to control signal ST turns off transistor 402. A position is given, transistor 402 is turned off, and the potential of node S is floating. This state is maintained. As a result, the potential written to node S is retained (retained). The clock signals φ2 and φ1 should maintain their potentials at the end of period a. Alternatively, The clock signal φ2 is fixed at a high level and the clock signal φ1 is fixed at a low level, at the end of period a. The data may be latched. The control signal ST is transmitted to transistor 40 after the start of period b. You can either apply a potential that turns on transistor 2, or transistor 402 will turn on simultaneously with the start of period b. You may also apply a potential that results in the following:

[0201] Next, during the non-operating period (period c), the power supply is cut off and the power supply voltage VDD drops. Clock signal φ1, clock signal φ2, input signal IN, and output signal OUT are VDD-VS Any value can be taken between S. During this time, the potentials of the control signal ST and the control signal LD ​​are It is held at a low level. For example, it is held at ground potential. Non-operating period (period c) Therefore, since the potential of node S is floating, the charge accumulated at node S is It remains in this state (held). Note that when the power supply voltage VDD drops, the potential of node S is There may be some fluctuations due to the effect of capacitive coupling with the power supply potential. Of course, it accumulates at node S. The charged energy is retained, so when the power supply voltage VDD is supplied again, it will return to its original potential. .

[0202] Next, after the power supply voltage VDD is turned on, there is a preparation period (period d) before the normal operating period begins. In this state, with clock signal φ2 and clock signal φ1 fixed at a low level, the control signal When a potential is applied to LD that turns on switch 405, switch 405 turns on. The potential held at node S is inverted by inverter 403 and applied to latch unit 411. And, after the control signal LD ​​is given a potential that turns on switch 405, The lock signal φ2 and the clock signal φ1 are given the potential at the end of period a. This allows, The logical state during period d can be returned to the logical state before entering the non-operation period. The control signal LD ​​is The power may be lowered to a low level before the end of period d, or the power switch 405 may remain on until the end. You can keep your position.

[0203] Next, during the normal operating period (period e), the clock signal φ1 and the clock signal φ2 are... A low-level potential is applied, and the system enters its normal operating state. Normal operating period (period) At the start of e), clock signal φ1 and clock signal φ2 are used during the previous normal operating period ( You may start from the same potential as at the end of period a), or from the next potential state after the end of period a. You can start from here.

[0204] The potential at node S is then set to the potential at which the control signal ST turns on transistor 402. It is rewritten at that timing. Therefore, transistor 402 turns ON next to the control signal ST. The potential of node S remains unchanged until a potential that results in the above condition is applied.

[0205] Furthermore, during period d, the potential Vc of the other electrode with capacitance 404 is between VDD and VSS. You may do so. This will give node S a potential that takes into account the increment of the potential Vc, and the reading will be... This makes it possible to perform the dispensing action more stably.

[0206] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0207] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0208] This embodiment can be freely combined with other embodiments.

[0209] (Embodiment 4) This embodiment describes the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. Next, we will explain an example different from Figure 19 with reference to Figures 20 and 18. Figure 20(A) is a lap A non-volatile latch having a latch section 411 and a data holding section 401 that holds data from the latch section. The configuration of the latch circuit 400 is shown. Figure 20(B) shows the latch of the non-volatile latch circuit 400. An example of a timing chart is shown.

[0210] Figure 20 shows an example where the configuration of the data storage unit 401 differs from that in Figure 19. Specifically, the data This is an example where no specific capacity is provided for the holding section (capacity 404 in Figure 19). Other configurations are shown in Figure 19. Since it is the same as before, the explanation will be omitted.

[0211] Figure 20(A) is an example that specifically shows the configuration of the latch section 411 in Figure 18(A). Figure 20(A) shows the configuration of the latch section 411 in Figure 18(A), where the first element is an in This is an example using a converter and an inverter as the second element. The structure of the data holding unit 401. The configuration will be explained with reference to Figure 18. The configuration of transistor 402 is the same as in Embodiment 1. It is the same.

[0212] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region. The transistor 402 is used as a switching element. The inverter 403 is electrically connected to the source electrode and the other of the drain electrode of 02. It is.

[0213] The source electrode and one of the drain electrodes of this transistor 402 are connected when an output signal is applied. It is electrically connected to wiring 415. Also, the output of inverter 403 is connected to switch 405 It is electrically connected to wiring 414 to which an input signal is supplied via inverter 403. The configuration is as shown in Figure 18(B), and the inverter 403 is connected to the transistor 420 and It has transistor 421. The source electrode of transistor 420 is high level It is electrically connected to the source voltage VDD. The source electrode of transistor 421 is low level. It is electrically connected to the power supply voltage VSS.

[0214] This embodiment is a configuration that does not have capacity connected to node S. In this case, invert Charge is accumulated in the gate capacitance of the transistor connected to the input of 403. Here, More precisely, the gate capacitance of transistor 421 in inverter 403 is... The gate capacitance of transistor 420 in 03 is assumed to be greater than that of transistor 420. This includes the transistor's channel length L, channel width W, gate dielectric film thickness, dielectric constant, etc. It can be controlled more effectively. In this way, the input capacity of inverter 403 is mainly... It consists of a capacitance between VDD S and VSS, and the potential of the input terminal is less affected by fluctuations in VDD. It is preferable to become that way.

[0215] The inverter 403 is not limited to the configuration shown in Figure 18(B), but can also be configured as shown in Figure 2(A), for example. It can be constructed using N-channel transistors, or it can be configured with a buffer at the output. Alternatively, a sense amplifier circuit may be used instead of inverter 403. For example, see Figure 2. A differential amplifier type sense amplifier circuit as shown in (B) may also be used. In either case, It is important that the power terminal is in a floating state (high impedance state). In the circuit shown in Figure 2(A), the input charge is stored in the gate capacitance of transistor 421. Furthermore, in the circuit shown in Figure 2(B), the input charge is the gate capacity of transistor 421. It accumulates in quantity. The circuits shown in Figures 2(A) and 2(B) are mainly composed of these gate capacitances. Since it is configured between VSS and node S, the potential of the input terminal is affected by fluctuations in VDD. This is preferable because it makes it less likely to get stuck.

[0216] This oxide semiconductor transistor 402 holds data in the latch portion 411 It has the function of writing the data to the gate capacitance of inverter 403. 402 has the function of holding the data written to the gate capacitance of inverter 403. Yes, they are.

[0217] Figure 20(B) shows an example of a timing chart for a non-volatile latch circuit 400. Figure 20 The timing chart in (B) is almost identical to the timing chart in Figure 19(B). Therefore, I will omit the explanation.

[0218] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0219] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0220] This embodiment can be freely combined with other embodiments.

[0221] (Embodiment 5) This embodiment describes the configuration and operation of a non-volatile latch circuit, which is one aspect of the disclosed invention. Next, we will explain an example different from Figure 19 with reference to Figure 21. Figure 21(A) shows a non-volatile ra The configuration of the latch circuit 400 is shown in Figure 19(A). The configuration of the non-volatile latch circuit 400 is shown in Figure 19(A). ) is similar. Figure 21(B) shows the timing chart of the non-volatile latch circuit 400. An example is shown.

[0222] In the timing chart shown in Figure 21(B), after the power supply voltage VDD is supplied again... During period d, a potential is applied to the control signal ST that turns on transistor 402. The timing at which signal ST becomes high is when control signal LD ​​is high. It is fine as long as it is after the falling edge timing. Also, the control signal ST falls to a low level. The timing is such that clock signal φ1 and clock signal φ2 are at the same potential as at the end of period a. It is sufficient if it is within the period in which it is. During period d, transistor 402 is connected to the control signal ST. By applying an ON potential, the potential of node S can be refreshed. ru.

[0223] In the timing chart of Figure 21(B), the timings other than the control signal ST are shown in Figure 19( Since it is the same as B), the explanation will be omitted.

[0224] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0225] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0226] This embodiment can be freely combined with other embodiments.

[0227] (Embodiment 6) This embodiment is a logic having a plurality of non-volatile latch circuits, which is one aspect of the disclosed invention. The circuit configuration will be explained with reference to Figure 22.

[0228] Figure 22 shows a latch unit 411 and a data holding unit 401 that holds data from the latch unit. This shows the configuration of a logic circuit having two non-volatile latch circuits 400.

[0229] The configuration of the data holding unit 401 is the same as in Figure 1(A) or Figure 18(A). Latch unit 41 The configuration of 1 is the configuration of the latch portion 411 in Figure 1(A) or Figure 18(A), where the first element This is an example using NAND as the first element and a clocked inverter as the second element.

[0230] The latch section 411 includes a NAND 412 and a clocked inverter 413. The output of ND412 is electrically connected to the input of the clocked inverter 413, and the clocked The inverter 413 has a loop structure in which its output is electrically connected to the input of the NAND 412. The latch section 411 also has an analog switch 431.

[0231] One of the inputs to the NAND412 is connected to a latch circuit 400 via an analog switch 431. It is electrically connected to wiring 414 to which the input signal is applied. The output of the NAND412 is, The output signal of the latch circuit 400 is electrically connected to the wiring 415 to which it is supplied. Another input to D412 is electrically connected to the wiring to which the signal RSTB is given. ru.

[0232] The logic circuit shown in Figure 22 is a non-volatile latch circuit 400, and is a non-volatile latch It has circuit 400a and non-volatile latch circuit 400b. Non-volatile latch circuit 4 00a is electrically connected to wiring 414 to which the potential of the input signal is supplied from the preceding circuit. The wiring 415 to which the potential of the output signal of the non-volatile latch circuit 400a is applied is non-volatile. The potential of the input signal of the latch circuit 400b is electrically connected to the wiring 414 to which it is supplied. The non-volatile latch circuit 400b is connected to the subsequent circuit via wiring 4, which supplies the potential of the output signal. It is electrically connected to 15. In the non-volatile latch circuit 400a, the analog switch The clock signal φ1 and the inverted signal of the clock signal φ1 are applied to the 431, and the clock signal The inverter 413 is supplied with the clock signal φ2 and the inverted signal of the clock signal φ2. In the non-volatile latch circuit 400b, the analog switch 431 receives a clock signal φ When the inverted signal of 2 and the clock signal φ2 is applied, the clocked inverter 413 receives the clock signal. A signal φ1 and an inverted signal of the clock signal φ1 are given.

[0233] Using the non-volatile latch circuit according to this embodiment, the semiconductor material constituting the channel formation region A transistor using an oxide semiconductor as the material is used as the switching element in the data retention section. By using it, it has a wide temperature operating range, operates stably even at high temperatures, and retains its settings even when the power is turned off. Non-volatile latch circuits where the logic state does not disappear, or data with a sufficiently long refresh period. A latch circuit with a built-in holding mechanism can be realized. Data writing is done using a transistor. Since this is done by switching, there is virtually no limit to the number of rewrites. The input voltage is approximately the threshold voltage of the transistor, allowing for operation at low voltages. Example For example, the operating voltage can be reduced to 1V or less. Also, the charge stored in the data retention section Because the data is retained as is, it is less susceptible to the effects of variability, and the data is easy to read. It is possible to easily remove the discrepancies.

[0234] By using the non-volatile latch circuit described above, it is possible to realize a variety of logic circuits. Yes, for example, power consumption can be reduced by turning off the power to unused blocks. Yes, it is possible. Also, since it remembers its logical state even when the power is turned off, when the power is turned on... To enable fast and low-power system startup and shutdown when the power is turned off. This is possible.

[0235] This embodiment can be freely combined with other embodiments.

[0236] (Embodiment 7) In this embodiment, a semiconductor device using the non-volatile latch circuit obtained in the previous embodiment is provided. An example of an electronic device equipped with this will be explained using Figure 23. Electronic devices equipped with semiconductor devices using volatile latch circuits exhibit unprecedented superior characteristics. Therefore, a new semiconductor device using the non-volatile latch circuit is being developed. It is possible to provide electronic equipment with a shelf configuration. Semiconductor devices using this latch circuit are integrated and mounted on circuit boards, etc., and are used in various electronic devices. It will be installed inside the vehicle.

[0237] Figure 23(A) includes a semiconductor device using a non-volatile latch circuit according to the previous embodiment. It is a notebook-type personal computer, consisting of a main unit 301, a casing 302, a display unit 303, and a keyboard. -Composed of board 304, etc. The semiconductor device according to the disclosed invention is a notebook type By applying this to personal computers, it enables the creation of high-performance notebook personal computers. We can provide a computer.

[0238] Figure 23(B) includes a semiconductor device using a non-volatile latch circuit according to the previous embodiment. It is a personal digital assistant (PDA), and the main unit 311 has a display unit 313 and an external interface It is equipped with components 315 and operation buttons 314, etc. A stylus is also provided as an accessory for operation. There is 312. Applying the semiconductor device relating to the disclosed invention to a personal digital assistant (PDA). This allows us to provide a personal digital assistant (PDA) with superior performance.

[0239] Figure 23(C) includes a semiconductor device using a non-volatile latch circuit according to the previous embodiment. As an example of electronic paper, the e-book 320 is shown. The e-book 320 is housed in a casing 321. It consists of two housings, housing 321 and housing 323. Housing 321 and housing 323 are connected to shaft portion 3 It is integrated with 37, and can open and close using the shaft portion 337 as an axis. With this configuration, eBook 320 can be used just like a paper book.

[0240] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 23(C)), and on the left-hand display unit (Figure 23 (C) allows an image to be displayed on the display unit 327).

[0241] Furthermore, Figure 23(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0242] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0243] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various cards such as credit cards. By applying semiconductor devices to electronic paper, we can provide electronic paper with superior performance. It is possible.

[0244] Figure 23(D) includes a semiconductor device using a non-volatile latch circuit according to the previous embodiment. This is a mobile phone. The mobile phone consists of two casings, casing 340 and casing 341. The enclosure 341 includes a display panel 342, a speaker 343, and a microphone 34 4. Pointing device 346, camera lens 347, external connection terminal 348, etc. It is equipped with a solar cell 349 for charging the mobile phone, and It is equipped with memory slots 350, etc. The antenna is built into the housing 341. It is.

[0245] The display panel 342 has a touch panel function, and the image displayed in Figure 23(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will include a contactless IC chip, a small recording device, etc. It's also possible.

[0246] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 23(D). It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0247] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. Furthermore, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc. (Disclosed invention) By applying semiconductor devices to mobile phones, it is possible to provide mobile phones with superior performance. Cut.

[0248] Figure 23(E) includes a semiconductor device using a non-volatile latch circuit according to the previous embodiment. It is a digital camera. The digital camera consists of the main body 361, the display unit (A) 367, and the eyepiece. The structure consists of part 363, operation switch 364, display unit (B) 365, battery 366, etc. It has been done. By applying the semiconductor device according to the disclosed invention to a digital camera, excellent We can provide a digital camera with high performance.

[0249] Figure 23(F) shows a semiconductor device using a non-volatile latch circuit according to the previous embodiment. This is a television device. In the television device 370, the display unit 373 is assembled in the housing 371. It is embedded. The display unit 373 makes it possible to display images. This shows a configuration in which the housing 371 is supported by the stand 375.

[0250] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A display unit 377 that displays the information may also be provided.

[0251] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible. By applying the semiconductor device according to the disclosed invention to a television device, We can provide television equipment with superior performance.

[0252] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. Can be used together [Examples]

[0253] In this embodiment, the operation of a non-volatile latch circuit, which is one aspect of the disclosed invention, was evaluated. This indicates.

[0254] The configuration of the non-volatile latch circuit used for evaluation is shown in Figure 24. The latch circuit 400 includes a latch section 411 and a data holding section 401 that holds the data from the latch section. It has.

[0255] The latch section 411 is composed of an inverter 412, an inverter 413, and a transistor. It has a switch 431 and a switch 432 which is made of a transistor.

[0256] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region. It consists of a transistor 402, a capacitor 404, an inverter 403, and a transistor. It has a switch 405 that can be used. Note that node S has one electrode of capacitance 404 and This shows the potential at the input terminal of converter 403.

[0257] Transistor 402 was fabricated according to Figures 5(A)-(G) and 6(A)-(D), and Figure 6 A transistor with a similar structure to the one shown in (D) was used. Transistor 402 is a A channel with a channel length L=3μm and a channel width W=5μm, using a highly purified oxide semiconductor. He is a Rangista.

[0258] The inverter 412, inverter 413, inverter 403, and transistors are composed of Switch 431, switch 432 composed of transistors, and switch 431 composed of transistors The switch 405 was formed using a silicon transistor.

[0259] Wiring 414 is supplied with the potential of the input signal IN from the preceding circuit. The potential of wiring 415 is output The power signal OUT is supplied to the subsequent circuit. The potential of signal φ1 is applied to switch 431. The switch 432 is given a potential equal to the signal φ2. The gate of transistor 402 The potential of the control signal ST is applied to switch 405. The potential of the control signal LD ​​is applied to switch 405. It can be done.

[0260] Figures 25(A) and 25(B) show the evaluation results of the non-volatile latch circuit 400. Figure 25(A) shows During the write operation, the power supply voltage VDD, input signal IN, control signal ST, and output signal O are used. The results of measuring the potential of UT with an oscilloscope are shown. Figure 25(B) shows the results during readout operation. In this configuration, the potentials of the power supply voltage VDD, input signal IN, control signal LD, and output signal OUT are controlled. The results measured with a roscope are shown. Note that in the evaluation of the non-volatile latch circuit 400, The power supply voltage during power supply was set to VDD=5V and VSS=0V.

[0261] First, the potential of the output signal OUT was written to node S and held there (Figure 25(A) (See reference). The potential of the output signal OUT during writing was set to 5V, and the potential of the input signal IN was set to 0V. A potential (in this case, 5V) is applied to the control signal ST that turns on transistor 402. Turn on transistor 402 and set the potential of the output signal OUT (5V in this case) to the node. The value was given (written) to S. The period during which transistor 402 is turned on is 200 microseconds. That's what I decided.

[0262] Subsequently, the control signal ST is set to a potential that turns off transistor 402 (in this case, a potential of 0V). This was applied, turning off transistor 402 and floating the potential of node S. retention).

[0263] During writing and holding, the control signal LD ​​is at a potential (here, 0) that turns off switch 405. (Potential V) fail.

[0264] Note that during writing and holding, signals φ2 and φ1 are at the potential before the writing operation (here, signal φ1) The φ2 terminal was held at a low level (0V), and the φ1 terminal was held at a high level (5V).

[0265] Next, the power supply is cut off (also called turning off the power), and the non-volatile solution is left at room temperature for 10 minutes. The latch circuit 400 was left as is. When the power supply is stopped (also called the non-operating period), the power supply The potential of voltage VDD decreased. During this time, the potentials of control signals ST and LD were set to 0V. He held onto it.

[0266] Afterward, the power supply is restored (also called turning on the power), and the potential of the power supply voltage VDD is set to 5V. I did.

[0267] Next, the operation to read the potential of node S was performed (see Figure 25(B)). During the reading, Set the potentials of signals φ2 and φ1 to low level (0V), and switch 432, switch 431 It was turned off. In this state, the control signal LD ​​is at a potential that turns on switch 405 (here A potential of 5V was applied, and switch 405 was turned on. When switch 405 is turned on, A potential of 5V was output as the potential of the power signal OUT (readout).

[0268] The potential of the output signal OUT is such that the potential of node S is such that inverters 403 and 412 This is output via [a specific method]. Therefore, from Figure 25(B), the node [details omitted] before the power supply was cut off. The potential written to S is retained even after the power supply is cut off, and is used as the potential of the output signal OUT. It was confirmed that the output was generated. In other words, by using the non-volatile latch circuit 400, It was confirmed that the system could be restored to its logical state before the power supply interruption immediately after the power supply was restored. [Explanation of symbols]

[0269] 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108a Gate Insulation Layer 110a Shuttle bus 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulation layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Drain electrode 130b Drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Drain electrode 142b Drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit 400 latch circuit 400A latch circuit 400b latch circuit 401 Data storage unit 402 transistors 403 Inverter 404 capacity 405 Switch 411 Latch section 412 First element 413 Second element 414 Wiring 415 Wiring 420 transistors 421 Transistors 431 switches 432 switches 501 N-channel transistor 502 N-channel transistors 503 P-channel transistor 504 P-channel transistor 505 P-channel transistor 506 P-channel transistor

Claims

1. A first transistor having a crystalline silicon semiconductor, a second transistor having an oxide semiconductor, and a third transistor having a crystalline silicon semiconductor, A semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, Either the source or drain of the first transistor is electrically connected to either the source or drain of the third transistor. The gate of the first transistor is electrically connected to either the source or the drain of the second transistor. A first channel formation region is provided in the crystalline silicon semiconductor of the first transistor. A second channel formation region is provided in the oxide semiconductor of the second transistor. The first transistor has a first gate electrode above the first channel forming region, The second transistor has a second gate electrode below the second channel formation region, The third conductive layer has the function of the first gate electrode, The second insulating layer is provided above the third conductive layer, The fifth conductive layer has a region in contact with the upper surface of the third conductive layer, The oxide semiconductor is provided above the second insulating layer, The first insulating layer is provided above the oxide semiconductor, The first conductive layer has a region located above the first insulating layer, The second conductive layer has a region located above the first insulating layer, The third conductive layer is electrically connected to either the source or the drain of the second transistor via the fifth conductive layer and the first conductive layer. The fourth conductive layer has the function of the second gate electrode, The source or drain of the second transistor, the other of which is electrically connected to the second conductive layer, The first insulating layer has a first opening and a second opening, The second insulating layer has a third opening, The first conductive layer is electrically connected to the fifth conductive layer through the first opening. The first conductive layer is electrically connected to either the source or the drain of the second transistor through the second opening. The fifth conductive layer is provided in the third opening, In a plan view, the first opening has a region that overlaps with the fifth conductive layer. In a plan view, the third opening has a region that overlaps with the third conductive layer. In a plan view, the first conductive layer has a region that overlaps with the first opening and a region that overlaps with the second opening. In a plan view, the first opening does not overlap with the first channel-forming region. In a plan view, the second opening does not overlap with the first channel-forming region. A semiconductor device in which, in a plan view, the first opening does not overlap with the second opening.

2. A first transistor having a crystalline silicon semiconductor, a second transistor having an oxide semiconductor, and a third transistor having a crystalline silicon semiconductor, A semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, Either the source or drain of the first transistor is electrically connected to either the source or drain of the third transistor. The gate of the first transistor is electrically connected to either the source or the drain of the second transistor. A first channel formation region is provided in the crystalline silicon semiconductor of the first transistor. A second channel formation region is provided in the oxide semiconductor of the second transistor. The first transistor has a first gate electrode above the first channel forming region, The second transistor has a second gate electrode below the second channel formation region, The third conductive layer has the function of the first gate electrode, The second insulating layer is provided above the third conductive layer, The fifth conductive layer has a region in contact with the upper surface of the third conductive layer, The oxide semiconductor is provided above the second insulating layer, The first insulating layer is provided above the oxide semiconductor, The first conductive layer has a region located above the first insulating layer, The second conductive layer has a region located above the first insulating layer, The third conductive layer is electrically connected to either the source or the drain of the second transistor via the fifth conductive layer and the first conductive layer. The fourth conductive layer has the function of the second gate electrode, The source or drain of the second transistor, the other of which is electrically connected to the second conductive layer, The first insulating layer has a first opening and a second opening, The second insulating layer has a third opening, The first conductive layer is electrically connected to the fifth conductive layer through the first opening. The first conductive layer is electrically connected to either the source or the drain of the second transistor through the second opening. The fifth conductive layer is provided in the third opening, In a plan view, the first opening has a region that overlaps with the fifth conductive layer. In a plan view, the third opening has a region that overlaps with the third conductive layer. In a plan view, the first conductive layer has a region that overlaps with the first opening and a region that overlaps with the second opening. In a plan view, the first opening does not overlap with the first channel-forming region. In a plan view, the second opening does not overlap with the first channel-forming region. In a plan view, the first opening does not overlap with the second opening. A semiconductor device in which, in a plan view, the first gate electrode does not overlap with the second gate electrode.

3. In claim 1 or 2, The aforementioned oxide semiconductor is an In-O based oxide semiconductor, which is a semiconductor device.

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