Semiconductor equipment

JP7901230B2Active Publication Date: 2026-08-05SEMICON ENERGY LAB CO LTD

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Patent Information

Authority / Receiving Office: JP · JP
Patent Type: Patents
Current Assignee / Owner: SEMICON ENERGY LAB CO LTD
Filing Date: 2025-10-17
Publication Date: 2026-08-05

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Benefits of technology

【0021】 本発明の一形態は、新規な構成の半導体装置等を提供することができる。または本発明の一態様は、極小オフ電流を利用した記憶装置として機能する半導体装置において、製造コストの低減を図ることができる、新規な構成の半導体装置等を提供することができる。または本発明の一態様は、極小オフ電流を利用した記憶装置として機能する半導体装置において低消費電力に優れた、新規な構成の半導体装置等を提供することができる。または本発明の一態様は、極小オフ電流を利用した記憶装置として機能する半導体装置において、装置の小型化を図ることができる、新規な構成の半導体装置等を提供することができる。または本発明の一態様は、極小オフ電流を利用した記憶装置として機能する半導体装置において、読みだされるデータの信頼性に優れた、新規な構成の半導体装置等を提供することができる。

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Abstract

To provide a semiconductor device which is reduced in manufacturing cost, excellent in power consumption, reduced in size, and excellent in data reliability.SOLUTION: In the semiconductor device, the element layer 20 includes a transistor layer 40 including a plurality of transistor layers 41 _ 1 to 41 _ k over a transistor layer 30 including a transistor 31 for reading in the z-axis direction and a correction circuit 35 including transistors 32 to 34. Each of the transistor layers 41 _ 1 to 41 _ k includes a plurality of memory cells 42 each including a transistor 43 and a capacitor 44. The transistor 43 switches the conduction state between the local bit line LBL and the capacitor 44 according to the control of the word line WL connected to the gate. The local bit line LBL is connected to a gate of the transistor 31, and the word line WL switches on / off of the transistor 43 by a word signal supplied to the word line WL. An interconnect CSL that applies a fixed potential is connected to the capacitor 44.SELECTED DRAWING: Figure 2

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Claims

1. The first transistor layer and A second transistor layer having a region located on the first transistor layer, The first transistor layer has a memory cell, The second transistor layer comprises a first transistor whose gate is electrically connected to a local bit line, and a correction circuit electrically connected to the first transistor. The memory cell has a second transistor, The second transistor is electrically connected to the local bit line, The second transistor has an oxide semiconductor in the channel formation region, The correction circuit is electrically connected to the global bit line, The correction circuit has the function of holding a voltage corresponding to the threshold voltage of the first transistor at the gate of the first transistor, and is a semiconductor device.

2. The first transistor layer and A second transistor layer having a region located on the first transistor layer, The first transistor layer has a memory cell, The second transistor layer comprises a first transistor whose gate is electrically connected to a local bit line, and a correction circuit electrically connected to the first transistor. The memory cell has a second transistor, The second transistor is electrically connected to the local bit line, The second transistor has an oxide semiconductor in the channel formation region, The aforementioned oxide semiconductor is indium oxide. The correction circuit is electrically connected to the global bit line, The correction circuit has the function of holding a voltage corresponding to the threshold voltage of the first transistor at the gate of the first transistor, and is a semiconductor device.

3. In claim 1 or claim 2, The correction circuit has a third to fifth transistor, The third transistor has the function of controlling the conduction state between the gate of the first transistor and either the source or the drain of the first transistor. The fourth transistor has the function of controlling the conduction state between the source or drain of the first transistor and the wiring to which a potential is applied for current to flow through the first transistor. The fifth transistor is a semiconductor device having the function of controlling the conduction state between the source or drain of the first transistor and the global bit line.