Semiconductor equipment

Abstract

Improve the operating speed of the circuit. 【Solution means】A first transistor, a first terminal of which is connected to the gate of the first transistor and has a function of setting the potential of the gate of the first transistor to a value at which the first transistor turns on A second transistor, a third transistor having a function of setting the potential of the gate of the second transistor to a value at which the second transistor turns on and floating the gate of the second transistor A fourth transistor having a function of setting the potential of the gate of the second transistor to a value at which the second transistor turns off. With such a configuration, the potential difference between the gate and the source of the second transistor can be maintained at a value greater than the threshold voltage of the second transistor, and the operating speed can be improved. A second transistor, a third transistor having a function of setting the potential of the gate of the second transistor to a value at which the second transistor turns on and floating the gate of the second transistor A fourth transistor having a function of setting the potential of the gate of the second transistor to a value at which the second transistor turns off. With such a configuration, the potential difference between the gate and the source of the second transistor can be maintained at a value greater than the threshold voltage of the second transistor, and the operating speed can be improved. A fourth transistor having a function of setting the potential of the gate of the second transistor to a value at which the second transistor turns off. It is possible.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a display module, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect relates to an object, a method, or a manufacturing method. Or, the present invention One aspect relates to a process, a machine, a manufacture, or a composition (composition of matter). Or, one aspect of the present invention relates to a semiconductor device, a display device a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

Background Art

[0003] Development of a circuit applicable to a driving circuit such as a storage device, an image sensor, or a display device is in progress. In particular, development of a circuit composed of transistors of the same polarity is actively under way. Techniques related to such a circuit are disclosed in Patent Document 1.

[0004] In Patent Document 1, the potential difference between the gate and the source of a transistor gradually decreases. Then when the potential difference between the gate and the source of the transistor becomes equal to the threshold voltage of the transistor the transistor turns off and the node inside the circuit becomes a floating state.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] In conventional circuits, the potential difference between the gate and source of the transistor gradually decreases. Therefore, the drain current of the transistor also gradually decreases. The time required for the potential change is long, making high-speed operation difficult. Also, the transistor The W / L ratio of the tang needs to be increased, making it difficult to reduce the layout area. Furthermore, it is difficult to shorten the rise time or fall time of the signal.

[0007] One aspect of the present invention aims to provide a novel semiconductor device. One aspect of this invention aims to provide a configuration that operates at high speed or enables such operation. To do so. Alternatively, one aspect of the present invention involves reducing the layout area or making it possible to do so. One objective is to provide a configuration. Alternatively, one aspect of the present invention is to reduce the drive voltage. One of the objectives of this invention is to provide a configuration that enables or allows for the same. The embodiment involves shortening the rise time or fall time of a signal, or a configuration that makes this possible. One of the objectives is to provide [this].

[0008] Furthermore, one aspect of the present invention does not necessarily have to solve all of the above problems, but at least It is sufficient if it can solve one problem. Also, the description of the above problem does not imply the existence of other problems. This does not preclude anything. Other issues can be identified from the description in the specification, drawings, claims, etc. This becomes clear, and from the descriptions in the specification, drawings, claims, etc., other issues are not addressed. It is possible to extract it. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device having first to fourth transistors. Either the source or drain of the inverter is electrically connected to the first wiring and the first transistor The source or drain of the transistor is electrically connected to the second wiring, and the second transistor Either the source or drain of the transistor is electrically connected to the third wiring, and the second transistor The source or drain of the first transistor is electrically connected to the gate of the second transistor. One of the sources or drains of transistor 3 is electrically connected to the fourth wire, and the third The source or drain of one transistor is electrically connected to the gate of the second transistor. The source or drain of the fourth transistor is connected, and is electrically connected to the fifth wiring. The source or drain of the fourth transistor is connected to the gaseous terminal of the second transistor. It is electrically connected to the terminal.

[0010] One aspect of the present invention is a semiconductor device having first to fourth transistors. Either the source or drain of the inverter is electrically connected to the first wiring and the first transistor The source or drain of the transistor is electrically connected to the second wiring, and the second transistor Either the source or drain of the transistor is electrically connected to the third wiring, and the second transistor The source or drain of the first transistor is electrically connected to the gate of the second transistor. One of the sources or drains of transistor 3 is electrically connected to the third wiring, and the third The source or drain of one transistor is electrically connected to the gate of the second transistor. The source or drain of the fourth transistor is connected and electrically connected to the fourth wiring. The source or drain of the fourth transistor is connected to the gaseous terminal of the second transistor. It is electrically connected to the terminal.

[0011] One aspect of the present invention is a semiconductor device having first to fourth transistors. Either the source or drain of the inverter is electrically connected to the first wiring and the first transistor The source or drain of the transistor is electrically connected to the second wiring, and the second transistor Either the source or drain of the transistor is electrically connected to the third wiring, and the second transistor The source or drain of the first transistor is electrically connected to the gate of the second transistor. One of the sources or drains of transistor 3 is electrically connected to the fourth wire, and the third The source or drain of one transistor is electrically connected to the gate of the second transistor. Connected, and either the source or drain of the fourth transistor is connected to the third wiring or the fourth wiring The wire is electrically connected, and the source or drain of the fourth transistor is connected to the second transistor. It is electrically connected to the gate of the inverter.

[0012] In one embodiment of the present invention described above, the gate of the fourth transistor is the first wiring or the It may be connected to wiring 2.

[0013] One aspect of the present invention is a display module having the above-mentioned semiconductor device and an FPC.

[0014] One aspect of the present invention includes the above-mentioned display module and an antenna, an operation button or a speaker. It is an electronic device. [Effects of the Invention]

[0015] One aspect of the present invention can provide a novel semiconductor device. Or, one aspect of the present invention This can provide a configuration that enables high-speed operation. One aspect of the invention provides a configuration that reduces the layout area or makes it possible to do so. This can be done. Alternatively, one aspect of the present invention makes it possible to reduce the drive voltage or to make it possible. A configuration can be provided that allows for the rise time of a signal or It is possible to shorten the fall time or provide a configuration that makes this possible.

[0016] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract effects other than those mentioned above from the claims and other descriptions. [Brief explanation of the drawing]

[0017] [Figure 1] A diagram illustrating an example of a semiconductor device. [Figure 2] A diagram illustrating an example of a semiconductor device. [Figure 3] A diagram illustrating an example of a semiconductor device. [Figure 4] A diagram illustrating an example of a semiconductor device. [Figure 5] A diagram illustrating an example of a semiconductor device. [Figure 6] A diagram illustrating an example of a semiconductor device. [Figure 7] A diagram illustrating an example of a semiconductor device. [Figure 8] A diagram illustrating an example of a semiconductor device. [Figure 9] A diagram illustrating an example of a semiconductor device. [Figure 10] A diagram illustrating an example of a semiconductor device. [Figure 11]A diagram illustrating an example of a semiconductor device. [Figure 12] A diagram illustrating an example of a semiconductor device. [Figure 13] A diagram illustrating an example of a semiconductor device. [Figure 14] A diagram illustrating an example of a semiconductor device. [Figure 15] A diagram illustrating an example of a semiconductor device. [Figure 16] A diagram illustrating an example of a semiconductor device. [Figure 17] A diagram illustrating an example of a semiconductor device. [Figure 18] A diagram illustrating an example of a semiconductor device. [Figure 19] A diagram illustrating an example of a display device. [Figure 20] A diagram illustrating an example of a semiconductor device. [Figure 21] A diagram illustrating an example of a semiconductor device. [Figure 22] A diagram illustrating an example of a semiconductor device. [Figure 23] A diagram illustrating an example of a semiconductor device. [Figure 24] A diagram illustrating an example of a display module. [Figure 25] A diagram illustrating an example of an electronic device. [Figure 26] A diagram illustrating an example of a semiconductor device. [Modes for carrying out the invention]

[0018] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is as follows The present invention is not limited to the descriptions in the embodiments described herein, and does not depart from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be construed as being limited to the contents of the following embodiments.

[0019] Furthermore, one aspect of the present invention includes, in addition to an imaging device, an RF tag, a display device, an integrated circuit, and any other The device is included in its scope. In addition, display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Pa nel), FED (Field Emission Display), etc., and display devices having integrated circuits are included in its scope. <> nel), FED (Field Emission Display), etc., and display devices having integrated circuits are included in its scope. The display devices having integrated circuits are included in its scope.

[0020] In describing the configuration of the invention using drawings, the same reference numerals may be commonly used among different drawings to indicate the same components. In describing the configuration of the invention using drawings, the same reference numerals may be commonly used among different drawings to indicate the same components.

[0021] In addition, in this specification, etc., in the drawings or text described in a certain embodiment, it is possible to extract a part thereof to form an aspect of the invention. Therefore, when a drawing or text describing a certain part is described, the content obtained by extracting a part of the drawing or text thereof is also disclosed as an aspect of the invention and can form an aspect of the invention. And it can be said that an aspect of the invention is clear. Therefore, for example, in a drawing or text in which one or more active elements (such as transistors), wirings, passive elements (such as capacitor elements), conductive layers insulating layers, semiconductor layers, components, devices, operation methods, manufacturing methods, etc. are described, it is possible to extract a part thereof to form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors capacitor elements, etc.) to form an aspect of the invention. As another example, it is possible to extract a part thereof to form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors capacitor elements, etc.) to form an aspect of the invention. As another example, it is possible to extract a part thereof to form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors capacitor elements, etc.) to form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc. ), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors capacitor elements, etc.) to form an aspect of the invention. As another example, For example, from the sentence that states, "A has B, C, D, E, or F", By arbitrarily selecting elements, we can say, "A has B and E," and "A has E and F." "A has C, E, and F," or "A has B, C, D, and E," etc. It is possible to constitute one aspect of the invention.

[0022] Furthermore, in this specification, etc., the figures or text described in a particular embodiment may differ from the original. And, if at least one specific example is given, it is possible to derive a higher-level concept from that specific example. This will be easily understood by those skilled in the art. Therefore, in one embodiment, If at least one specific example is described in a diagram or text, the higher-level example of that specific example is... This is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It is a Noh play. And one aspect of that invention can be said to be clear.

[0023] Furthermore, in this specification, etc., at least the contents shown in the figures (even if only a part of the figures) It is disclosed as one aspect of the invention, and it is possible to constitute one aspect of the invention. Yes. Therefore, if a certain content is described in a diagram, it does not need to be stated in text. Even if it is not disclosed, its content is disclosed as one aspect of the invention, and does not constitute one aspect of the invention. It is possible to do so. Similarly, a diagram showing only a part of the figure can also be considered as one aspect of the invention. It is disclosed in this way and can constitute one aspect of the invention. One aspect of the invention can be said to be clear.

[0024] Furthermore, any content not specified in the text or drawings within the specification will be excluded. This can constitute one embodiment of the invention that defines the following: or, for a certain value, an upper limit If a numerical range is specified, such as a lower limit, you can arbitrarily narrow that range. or, by excluding one point within that scope, one aspect of the invention that partially excludes that scope is defined. This makes it possible, for example, that the prior art falls within the technical scope of one aspect of the present invention. It is possible to stipulate that it is not included.

[0025] Furthermore, in this specification, active elements (such as transistors) and passive elements (such as capacitive elements) are used. For all terminals such as those mentioned above, a person skilled in the art can, without specifying the destination of the connection, It may be possible to constitute one aspect of the invention. In other words, even without specifying the connection destination, One aspect of the explanation is clear. And the details of the connection destination are described in this specification, etc. If included, an embodiment of the invention that does not specify the connection destination is described in this specification, etc. It is sometimes possible to make a determination. Especially when there are multiple possible destinations for the terminal connection, There is no need to limit the connection destination of that terminal to a specific location. Therefore, active elements (transitions) Only certain terminals of passive elements (such as capacitors) and other passive elements (such as capacitive elements) are connected. In some cases, specifying the prior art can constitute one aspect of the invention.

[0026] Furthermore, in this specification, if a circuit is specified, at least the connection destination is identified, the business If you are an expert, you may be able to identify the invention. Or, regarding a certain circuit, However, if the function is specified, a person skilled in the art may be able to specify the invention. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even without specifying the function of a certain circuit, if the connection destination is specified, it constitutes an invention. It is disclosed as such and can constitute one aspect of the invention. Regarding a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. This has been disclosed and can constitute one aspect of the invention.

[0027] Furthermore, if it is explicitly stated in this specification, etc., that X and Y are connected. This refers to the case where X and Y are electrically connected, and the case where X and Y are functionally connected. The cases in which X and Y are directly connected are disclosed in this specification, etc. Therefore, the connection relationships are not limited to predetermined relationships, such as those shown in the diagram or text. Connections other than those shown in the diagram or text are also included in those described in the diagram or text. ru.

[0028] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0029] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0030] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, then X and This includes cases where Y is directly connected to it.

[0031] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0032] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., between X and Y) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and the source (or the X terminal) of the transistor is electrically connected to each other. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0035] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is It does not have a second connection path, and the aforementioned second connection path is via a transistor, The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor. The path between ( and ), and the first connection path is a path via Z1, and the transit The drain (or second terminal, etc.) of the terminal is electrically connected to Y via at least a third connection path. They are connected in a manner, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "The transition The source of the starter (or the first terminal, etc.) is connected via Z1 through at least the first connection path. And, electrically connected to X, the first connection path does not have a second connection path, The second connection path has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is connected to Y via Z2 by at least a third connection path. It is expressed as: "They are electrically connected, and the third connection path does not have the second connection path." It is possible. Or, "the source (or first terminal, etc.) of the transistor is less Both are electrically connected to X via Z1 through a first electrical path, and the first electrical The target path does not have a second electrical path, and the second electrical path is the transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor It is an electrical path, and the drain (or second terminal, etc.) of the transistor is at least third The electrical path is electrically connected to Y via Z2, and the third electrical path is , it does not have a fourth electrical path, and the fourth electrical path is the drain of the transistor The electrical pulse from (or the second terminal, etc.) to the source (or the first terminal, etc.) of the transistor It can be expressed as "It is S." Using similar methods of expression as these examples, the circuit configuration By defining the connection path in the transistor, the source (or first terminal) To distinguish between the drain (or second terminal, etc.) and the second terminal, and to determine the technical scope. It is possible.

[0036] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0037] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0038] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0039] A semiconductor device configuration according to one aspect of the present invention will be described with reference to Figure 1. However, this One aspect of the invention is not limited to the configuration described below.

[0040] The semiconductor device shown in Figure 1 has a circuit 100. Circuit 100 has wiring 111, wiring 113 It has the function of controlling the potential of wiring 112 based on the potentials of wiring 114 and wiring 115. Circuit 100 is based on the potential of wiring 111, wiring 113, wiring 114 and wiring 115. The signal is output to wiring 112. Then, the potential of wiring 112 is controlled by this signal. Thus, circuit 100 has the function of a logic circuit or a sequential circuit.

[0041] Circuit 100 consists of transistors 101, 102, 103, and It has a transistor 104, a capacitive element 105, and a capacitive element 106. Transistor 101 is The first terminal (also called the source or drain) is connected to wiring 111, and the second terminal The other side (also called the source or drain) is connected to wiring 112. Transistor 102 The first terminal is connected to wiring 113, and the second terminal is connected to the gate of transistor 101. The transistor 103 has its first terminal connected to wiring 114, and its second terminal connected to It is connected to the gate of transistor 102, and the gate is connected to wiring 114. 104 has its first terminal connected to wiring 115 and its second terminal connected to the gateway of transistor 102. It is connected to the first terminal of the capacitive element 105, which is connected to the wiring 112, and the second terminal is It is connected to the gate of transistor 101. Capacitive element 106 has a first terminal that is connected to the transistor The second terminal is connected to the gate of transistor 101, and the second terminal is connected to the gate of transistor 102.

[0042] The semiconductor device of this embodiment provides a novel configuration by having the above-described connection relationship. It is possible.

[0043] Note that the gate of transistor 101, the second terminal of transistor 102, and the capacitive element 105 The second terminal of or the first terminal of the capacitive element 106 is indicated as node ND1. Also, the transient The gate of transistor 102, the second terminal of transistor 103, and the second terminal of transistor 104. The child, or the second terminal of the capacitive element 106, is indicated as node ND2.

[0044] Furthermore, the potential of wiring 111, wiring 113, wiring 114, and wiring 115 is such that each wiring has a signal or It is controlled by the input of voltage, etc. For convenience, wiring 111, wiring 113 and wiring The potential of 114 shall have a high level and a low level. In other words, wiring 1 11. Each of the wires 113 and 114 has a signal having a high level and a low level. A number is entered. Then, the high-level potential is set to VH, and the low-level potential is set to VL(VH Let >VL). Also, let the potential of wiring 115 be VL. However, the potential of wiring 115 is H It may have a high level and a low level. In other words, wiring 115 has a high level A signal having both a low and a low level may be input.

[0045] Wires 111, 113, and 114 may also be called input terminals. 12 may also be called the output terminal. Also, wiring 111, wiring 112, wiring 113, and wiring You may call wire 114 a signal line. Alternatively, you may call wire 115 a power line.

[0046] Transistors 101, 102, 103, and 104 A transistor that can be used in this invention will be described. However, one aspect of the present invention is This is not limited to the transistors described below.

[0047] Transistors 101, 102, 103, and 104 Examples include transistors having amorphous silicon in the channel formation region, and channel-type transistors. A transistor having polycrystalline silicon in the channel formation region, and a transistor having single-crystal silicon in the channel formation region. A transistor having an oxide semiconductor in the channel formation region, channel type It is possible to use transistors and the like that have compound semiconductors in the compound region. In particular, A transistor having an oxide semiconductor in the semiconductor formation region (also called an OS transistor) is a transistor with an oxide semiconductor in its semiconductor formation region. It has higher mobility than transistors having amorphous silicon in the channel formation region, and It has the characteristic of having an extremely low off-current. Therefore, the channel width of the transistor can be reduced. This allows for a reduction in the layout area.

[0048] Transistors 101, 102, 103, and 104 The conductivity type or polarity will be described below. However, one aspect of the present invention is the conductivity type described below. Or, it is not limited to polarity.

[0049] Transistors 101, 102, 103, and 104 It is preferable that they have the same conductivity type. Alternatively, all of the transistors in circuit 100 It is preferable that they have the same conductivity type. Alternatively, a trap provided on the same substrate as circuit 100. It is preferable that all the converters have the same conductivity type. This simplifies the manufacturing process. This can lead to improved yield and reduced manufacturing costs.

[0050] In particular, transistor 101, transistor 102, transistor 103 and transistor 104 is preferably an N-channel type. Alternatively, the transistor in circuit 100 It is preferable that all of them be of the N-channel type. Alternatively, they may be provided on the same substrate as circuit 100. It is preferable that all transistors are of the N-channel type. This allows for the channel formation region It is possible to use an oxide semiconductor transistor (also called an OS transistor). It becomes possible. Figure 1 shows transistors 101, 102, 103 and The example shows the case where transistor 104 is an N-channel type. However, Transistor 101, transistor 102, transistor 103, and transistor 104 are P-type It may be a channel type. Alternatively, all transistors in circuit 100 may be P-channel type. Alternatively, all transistors provided on the same board as circuit 100 may be P-type transistors. A Nell type may also be used. Figure 26 shows transistors 101 and 102 from Figure 1. Transistors 103 and 104 are replaced by transistors 101p and 1 The configuration when transistors 02p, 103p, and 104p are replaced is shown. Transistor 101p, transistor 102p, transistor 103p and transistor The TA104p is a P-channel type. Furthermore, in configurations other than those shown in Figure 1, the same N-channel configuration as in Figure 26 is used. Channel-type transistors may be replaced with P-channel-type transistors.

[0051] For convenience, transistors 101, 102, and 103 are N Let's explain it assuming it's a channel type.

[0052] Transistor 101, Transistor 102, Transistor 103, Transistor 104, The functions of the capacitive elements 105 and 106 will be described. However, one aspect of the present invention The embodiments are not limited to the functions described below.

[0053] Transistor 101 controls the conduction or non-conductivity between wire 111 and wire 112. Wiring 1 When wiring 11 and wiring 112 become conductive, the potential of wiring 111 is supplied to wiring 112, and wiring 11 The potential of 2 is controlled based on the potential of wiring 111. When the potential of wiring 111 is high level If this occurs, the potential of wiring 112 will rise. In particular, if the potential of node ND1 is high level of wiring 111 If the value is higher than the sum of the potential of the wire and the threshold voltage of transistor 101, then the power of wiring 112 The voltage rises to VH. If the potential of wiring 111 is low, then the potential of wiring 112 is V It descends to L.

[0054] Transistor 102 controls the conduction or non-conductivity between wiring 113 and node ND1. When 113 and node ND1 become conductive, the potential of wiring 113 is supplied to node ND1, The potential of code ND1 is controlled based on the potential of wiring 113. When the potential of wiring 113 is high If it's a bell, the potential of node ND1 will rise. In particular, the potential of node ND2 will rise on wiring 113. If the value is higher than the sum of the high-level potential and the threshold voltage of transistor 102, then no. The potential of node ND1 rises to VH. Thus, the potential of node ND1 rises to transistor 1 01 is set to a value that turns it on. If the potential of wiring 113 is low, node ND The potential of node 1 drops to VL. Thus, the potential of node ND1, transistor 101 It will be set to a value that turns it off.

[0055] Transistor 103 controls the conduction or non-conductivity between wiring 114 and node ND2. When 114 and node ND2 are connected, the potential of wiring 114 is supplied to node ND2, The potential of ND2 is controlled based on the potential of wiring 114. When the potential of wiring 114 is high If it is a bell, the potential of node ND2 will rise. However, if the gate of transistor 103 is Because it is connected to wiring 114, the potential of node ND2 is the high-level potential of wiring 114. When the voltage rises to the value obtained by subtracting the threshold voltage of transistor 103 from the voltage, transistor 103 will turn off It becomes a floating state. And node ND2 becomes a floating state. Thus, the potential of node ND2 is Transistor 102 is set to a value that turns it on, and node ND2 enters a floating state. Also, if the potential of wiring 114 is low, transistor 103 will turn off. Wiring 114 and node ND2 become non-conductive.

[0056] As shown in Figure 2(A), the first terminal of transistor 103 is connected to wiring 116. The gate of transistor 103 may be connected to wiring 114. The potential of wiring 116 is It is preferable that it be VH. However, the potential of the wiring 116 has high level and low level. It is also possible to do so. In Figure 2(A), transistor 103 is connected to wiring 116 and node N Controls the continuity or non-continuity with D2. When wiring 116 and node ND2 are connected, wiring 1 A potential of 16 is supplied to node ND2, and the potential of node ND2 is based on the potential of wiring 116. It is controlled by the following: If the potential of wiring 116 is VH or high level, the potential of node ND2 It rises. However, since the gate of transistor 103 is connected to wiring 114, The potential of ND2 is lowered from the high-level potential of wiring 114 to the threshold voltage of transistor 103. When the value rises to the subtracted value, transistor 103 turns off. Then node ND2 floats. It enters a idle state. In this way, the potential of node ND2 becomes the value at which transistor 102 turns on. Once configured, node ND2 enters a floating state.

[0057] As shown in Figure 2(B), the first terminal of transistor 103 is connected to wiring 114. The gate of transistor 103 may be connected to the wiring 116. In Figure 2(B), Rangent 103 controls the continuity or non-continuity between wiring 114 and node ND2. Wiring 1 When 14 and node ND2 are connected, the potential of wiring 114 is supplied to node ND2, The potential of ND2 is controlled based on the potential of wiring 114. When the potential of wiring 114 is high level If the gate of transistor 103 is Because it is connected to wire 116, the potential of node ND2 is a transient from the potential of wire 116. When the voltage rises to a value obtained by subtracting the threshold voltage of transistor 103, transistor 103 turns off. Then, node ND2 becomes floating. In this way, the potential of node ND2 becomes transistor 1 02 is set to a value that turns it on, and node ND2 becomes floating. Also, wiring 1 If the potential at 14 is low, the potential at node ND2 will drop to VL. In this way, The potential of node ND2 is set to a value that turns off transistor 102.

[0058] As shown in Figure 3(A), the first terminal and gate of transistor 103 are connected to wiring 11. It may also be connected to 3. In Figure 3(A), transistor 103 is connected to wiring 113 and node N Controls the continuity or non-continuity with D2. When wiring 113 and node ND2 are connected, wiring 1 A potential of 13 is supplied to node ND2, and the potential of node ND2 is based on the potential of wiring 113. It is controlled by this. If the potential of wiring 113 is high, the potential of node ND2 will rise. However, since the gate of transistor 103 is connected to wiring 113, node ND The potential of point 2 is the value obtained by subtracting the threshold voltage of transistor 103 from the high-level potential of wiring 113. When it rises to that point, transistor 103 turns off. Then node ND2 enters a floating state. This is how the potential of node ND2 is set to a value that turns on transistor 102. At the same time, node ND2 becomes floating. Also, even if the potential of wiring 113 is at a low level As a result, transistor 104 turns off, and wiring 113 and node ND2 become non-conductive. .

[0059] As shown in Figure 3(B), the first terminal of transistor 103 is connected to wiring 116. The gate of transistor 103 may be connected to wiring 113. In Figure 3(B), Rangent 103 controls the continuity or non-continuity between wiring 116 and node ND2. Wiring 1 When 16 and node ND2 are connected, the potential of wiring 116 is supplied to node ND2, The potential of ND2 is controlled based on the potential of wiring 116. If the potential of wiring 116 is VH or If the level is high, the potential of node ND2 will rise. However, the voltage of transistor 103 Because the node is connected to wiring 113, the potential of node ND2 is at the high level of wiring 113. When the potential rises to the value obtained by subtracting the threshold voltage of transistor 103 from the potential, transistor 10 3 turns off. And node ND2 becomes floating. In this way, the power of node ND2 The position is set to a value that turns on transistor 102, and node ND2 enters a floating state. It will become.

[0060] Although not shown in the diagram, the first terminal of transistor 103 is connected to wiring 114, The gate of inverter 103 may be connected to wiring 113.

[0061] Although not shown in the diagram, the first terminal of transistor 103 is connected to wiring 113, The gate of inverter 103 may be connected to wiring 116.

[0062] Transistor 104 controls the conduction or non-conductivity between wiring 115 and node ND2. When 115 and node ND2 are connected, the potential of wiring 115 is supplied to node ND2, The potential of code ND2 is controlled based on the potential of wiring 115. The potential of wiring 115 is VL or If the level is low, the potential of node ND2 drops to VL. Thus, node ND The potential of point 2 is set to a value that turns off transistor 102.

[0063] As shown in Figure 4(A), the first terminal of transistor 104 is connected to wiring 113. It may be done. In Figure 4(A), transistor 104 is connected to wiring 113 and node ND2. Controls whether it is conductive or not. When wiring 113 and node ND2 are conductive, the potential of wiring 113 This is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 113. If the potential of wiring 113 is VL or low level, the potential of node ND2 will drop to VL. The voltage is lowered. In this way, the potential of node ND2 is set to a value that turns off transistor 102. It can be done.

[0064] As shown in Figure 4(B), the first terminal of transistor 104 is connected to wiring 114. It may be done. In Figure 4(B), transistor 104 is connected to wiring 114 and node ND2. Controls whether it is conductive or not. When wiring 114 and node ND2 are conductive, the potential of wiring 114 This is supplied to node ND2, and the potential of node ND2 is controlled based on the potential of wiring 114. If the potential of wiring 114 is VL or low level, the potential of node ND2 will drop to VL. The voltage is lowered. In this way, the potential of node ND2 is set to a value that turns off transistor 102. It can be done.

[0065] Furthermore, as shown in Figure 5(A), the gate of transistor 104 is connected to wiring 111. That's good too.

[0066] Furthermore, as shown in Figure 5(B), the gate of transistor 104 is connected to wiring 112. That's good too.

[0067] Capacitive element 105 maintains the potential difference between wiring 112 and node ND1. Node ND1 is floating If the device is idle, the potential of node ND1 changes based on the change in the potential of wiring 112. Therefore, if the potential of node ND1 increases as the potential of wiring 112 increases, node ND The potential of 1 is greater than the sum of the high-level potential of wiring 111 and the threshold voltage of transistor 101. It will get more expensive.

[0068] Note that, as shown in Figure 6(A), the capacitive element 105 may be omitted. Transistor 101 The parasitic capacitance between the second terminal and the gate causes the electrical current between wiring 112 and node ND1 to be affected. The position difference is maintained.

[0069] Capacitive element 106 maintains the potential difference between node ND1 and node ND2. Node ND2 is If the node is floating, the potential of node ND2 will change based on the change in the potential of node ND1. Therefore, if the potential of node ND2 increases as the potential of node ND1 increases, The potential of ND2 is the sum of the high-level potential of wiring 113 and the threshold voltage of transistor 102. It will be higher than that.

[0070] Note that, as shown in Figure 6(B), the capacitive element 106 may be omitted. Transistor 102 The parasitic capacitance between the second terminal and the gate between node ND1 and node ND2 The potential difference is maintained.

[0071] Note that transistors 101, 102, 103, and 1 04. Capacitive elements 105 and 106 do not need to have all of the functions described above.

[0072] Furthermore, the circuit 100, which is illustrated and explained in Figures 1, 2, 3, 4, 5, and 6, and The circuit 100 described in the diagram can be combined as appropriate.

[0073] The operation of the semiconductor device of this embodiment will be explained using the configuration shown in Figure 1 as an example. However, this One aspect of the invention is not limited to the operation described below.

[0074] The timing chart shown in Figure 7 shows the potential of wiring 111, wiring 113, and wiring 114. Potential, on or off of transistor 104, potential of node ND1, potential of node ND2, An example of the potential of wiring 112 is shown.

[0075] For convenience, we will explain this by dividing it into four periods: Period T1, Period T2, Period T3, and Period T4. For example, one frame period has periods T1 to T4.

[0076] For convenience, in period T0 immediately preceding period T1, the potential of wiring 111 is at a low level. The potential of wiring 113 is low, the potential of wiring 114 is low, and the node The potential of ND1 is VL, the potential of node ND2 is VL, and the potential of wiring 112 is VL. Let it be so. Also, since the potential of node ND1 is VL, transistor 101 is It is off. Also, since the potential of node ND2 is VL, transistor 102 is off. be.

[0077] The operation during period T1 will be explained with reference to Figure 8(A). The potential of wiring 111 is low The potential of wiring 113 remains at a low level, and the potential of wiring 114 remains at a low level. The signal changes from a low level to a high level, and transistor 104 remains off.

[0078] Because the potential of wiring 114 becomes high, transistor 103 turns on. Therefore, Because the high-level potential of wiring 114 is supplied to node ND2, the potential of node ND2 is It will rise from VL.

[0079] Subsequently, the potential of node ND2 is equal to the potential (VL) of the first terminal of transistor 102. It will be higher than the sum of the threshold voltage of ZISTA 102 (Vth102) and (VL + Vth102). Then, transistor 102 turns on. Therefore, the low-level potential of wiring 113 is at the node Because it is supplied to ND1, the potential of node ND1 remains at VL. Also, node ND1 Because the potential remains VL, transistor 101 remains off. Therefore, the wiring The potential at 112 remains at VL.

[0080] Subsequently, the potential of node ND2 is lower than the gate potential (VH) of transistor 103. It rises to the value obtained by subtracting the threshold voltage of STA103 (Vth103) (VH-Vth103). Then, transistor 103 turns off. Therefore, node ND2 becomes floating, node The potential of ND2 is maintained at VH-Vth103.

[0081] In Figure 2(A), the first terminal of transistor 103 is connected to wiring 116. Therefore, the potential of wiring 116 (e.g., VH) is supplied to node ND2.

[0082] The operation during period T2 will be explained with reference to Figure 8(B). The potential of wiring 111 is low The voltage remains at the low level, and the potential of wiring 113 changes from low level to high level, wiring 1 The potential of 14 changes from a high level to a low level, and transistor 104 remains off. ru.

[0083] Because the potential of wiring 114 becomes low, transistor 103 remains off. As a result, node ND2 remains in a floating state, and the potential of node ND2 is VH-Vth103 It will remain as is. Also, since the potential of node ND2 remains VH-Vth103, The inverter 102 remains on. Therefore, the high-level potential of wiring 113 reaches node N Because it is supplied to D1, the potential of node ND1 rises from VL. At this time, capacitive element 1 06 maintains the potential difference between node ND1 and node ND2, and node ND2 is floating. This is the state. Therefore, as the potential of node ND1 rises, the potential of node ND2 becomes VH- It will rise from Vth103.

[0084] Subsequently, the potential of node ND1 is equal to the potential (VL) of the first terminal of transistor 101. It becomes higher than the sum (VL + Vth101) of the threshold voltage of Zistor 101 (Vth101). Then, transistor 101 turns on. Therefore, the low level potential of wiring 111 is equal to wiring 1 Because it is supplied to 12, the potential of wiring 112 remains VL.

[0085] Subsequently, as the potential of node ND1 increases, the potential of node ND2 increases at transistor 102 The sum of the potential at the first terminal (VH) and the threshold voltage of transistor 102 (Vth102) When it rises to an even higher value (VH + Vth102 + α (where α is a positive number)), node ND1 The potential rises to VH.

[0086] Note that in Figure 2(B), in order to keep transistor 103 off, during period T2... It is preferable that the potential of wiring 114 remains at a high level.

[0087] In Figures 3(A) and 3(B), transistor 103 is in period T2. It only turns on after 0. To explain in more detail, when the potential of wiring 113 becomes high level. Transistor 103 turns on. Therefore, in Figure 3(A), the high level of wiring 113. The potential is supplied to node ND2, and the potential of node ND2 rises from VL. Meanwhile, Figure 3 In (B), the potential of wiring 116 (e.g., VH) is supplied to node ND2, The potential rises from VL. Subsequently, the potential of node ND2 is higher than VL+Vth102. When this happens, transistor 102 turns on. Therefore, the high-level potential of wiring 113 is It is supplied to node ND1, and the potential of node ND1 rises from VL. Then node ND When the potential of 2 becomes VH-Vth103, transistor 103 turns off, and node ND 2 enters a floating state. At this time, the potential of node ND1 increases. And the capacitive element 106 maintains the potential difference between node ND1 and node ND2. Therefore, node ND1 As the potential of [node name] increases, the potential of node ND2 rises from VH-Vht103. When the potential of node ND1 becomes higher than VL + Vth101, transistor 101 becomes Therefore, the low-level potential of wiring 111 is supplied to wiring 112, The potential at 112 remains at VL. Subsequently, as the potential at node ND1 rises, the node When the potential of ND2 rises to VH+Vth102+α, the potential of node ND1 rises to VH. It rises. Thus, in Figures 3(A) and 3(B), the periods T1 and T2 in Figure 1 are The operations can be performed together in period T2. Therefore, the operating speed can be improved. It is possible to measure this.

[0088] The operation during period T3 will be explained with reference to Figure 9(A). The potential of wiring 111 is low The voltage changes from low to high, and the potential of wiring 113 changes from high to low. As a result, the potential of wiring 114 remains at a low level, and transistor 104 switches from off to on. It changes.

[0089] Because the potential of wiring 114 remains at a low level, transistor 103 remains off. Also, transistor 104 turns on. Therefore, the potential of wiring 115 is at node ND2. As a result of the supply, the potential of node ND2 decreases from VH+Vth102+α to VL. Since the potential of node ND2 becomes VL, transistor 102 turns off. Therefore, no Node ND1 becomes floating, and the potential of node ND1 remains VH. Since the position remains VH, transistor 101 remains ON. Therefore, wiring 11 Because a high potential of 1 is supplied to wiring 112, the potential of wiring 112 rises from VL. At this time, the capacitive element 105 maintains the potential difference between the wiring 112 and node ND1. Furthermore, node ND1 is in a floating state. Therefore, as the potential of wiring 112 rises, The potential of ND1 rises from VH.

[0090] Subsequently, as the potential of wiring 112 increases, the potential of node ND1 increases. The sum of the potential at terminal 1 (VH) and the threshold voltage of transistor 101 (Vth101) is greater than When the value rises to a high value (VH + Vth101 + β (where β is a positive number)), the potential of wiring 112 It will rise to VH.

[0091] In Figure 4(A), the first terminal of transistor 104 is connected to wiring 113. Therefore, the low-level potential of wiring 113 is supplied to node ND2. Also, in Figure 4(B) Because the first terminal of transistor 104 is connected to wiring 114, wiring 114 A low-level potential is supplied to node ND2.

[0092] The operation during period T4 will be explained with reference to Figure 9(B). The potential of wiring 111 is The potential changes from low to low, and the potential of wiring 113 remains at a low level. The potential of 14 changes from a low level to a high level, and transistor 104 changes from on to off. It changes.

[0093] Because the potential of wiring 114 becomes high, transistor 103 turns on. Therefore, The high-level potential of wiring 114 is supplied to node ND2, causing the potential of node ND2 to rise. At this time, the potential of node ND1 is VH + Vth101 + β, so the transistor 101 remains ON. Therefore, the low-level potential of wiring 111 is supplied to wiring 112. Therefore, the potential of wiring 112 drops from VH to VL.

[0094] Subsequently, the potential of node ND2 is equal to the potential (VL) of the first terminal of transistor 102. When the sum of the threshold voltage of transistor 102 (Vth102) and the current voltage is higher, transistor 102 This turns on. Therefore, the low-level potential of wiring 113 is supplied to node ND1. The potential at node ND1 decreases from VH+Vth101+β to VL. Also, node ND Since the potential at point 1 becomes VL, transistor 101 turns off.

[0095] Subsequently, the potential of node ND2 is lower than the gate potential (VH) of transistor 103. When the voltage rises to the value obtained by subtracting the threshold voltage (Vth103) of transistor 103, transistor 103 This is turned off. Therefore, node ND2 becomes floating, and the potential of node ND2 becomes VH-V It will be maintained on ht103.

[0096] In Figure 2(A), the first terminal of transistor 103 is connected to wiring 116. Therefore, the potential of wiring 116 (e.g., VH) is supplied to node ND2.

[0097] The semiconductor device of this embodiment has a connection relationship that enables it to perform the above operation. The potential of node ND2 can be set to VH + Vth102 + α.

[0098] The semiconductor device of this embodiment sets the potential of node ND2 to VH + Vth102 + α. This allows the potential difference between the gate and source of transistor 102 to be the threshold of transistor 102. It can be maintained at a value greater than the specified voltage.

[0099] The semiconductor device of this embodiment uses a potential difference between the gate and source of transistor 102. By maintaining a value greater than the threshold voltage of transistor 102, the potential of node ND1 is maintained. It can be raised to VH.

[0100] The semiconductor device of this embodiment uses a potential difference between the gate and source of transistor 102. By maintaining a value greater than the threshold voltage of transistor 102, the time required for the potential change at node ND1 can be shortened. The time required for the potential change at node ND1 can be shortened.

[0101] The semiconductor device of the present embodiment can increase the potential difference between the gate and the source of transistor 101 by raising the potential of node ND1 to VH. The potential difference between the gate and the source of transistor 101 can be increased.

[0102] The semiconductor device of the present embodiment can shorten the time required for the potential change in wiring 112 by increasing the potential difference between the gate and the source of transistor 101. The time required for the potential change in wiring 112 can be shortened. That is, a signal with short rise time and fall time can be output to wiring 112. It can be output.

[0103] The semiconductor device of the present embodiment can reduce the drive voltage by increasing the potential difference between the gate and the source of transistors 101 and 102. By doing so, the power consumption can be reduced. Thus, the power consumption can be reduced.

[0104] The semiconductor device of the present embodiment can reduce the channel widths of transistors 101 and 102 by increasing the potential difference between the gate and the source of transistors 101 and 102. By doing so, the layout area can be reduced. The layout area can be reduced. It can be made smaller.

[0105] The semiconductor device of the present embodiment can shorten the time required for the potential change at node ND1 and the time required for the potential change in wiring 112, so that the operating speed can be improved. The operating speed can be improved. It can be achieved.

[0106] Transistors 101, 102, 103, and 104 The relationship between W (where W is the channel width) and L (where L is the channel length) will be explained. However, according to one of the present inventions... The embodiments are not limited to the W / L described below.

[0107] Transistor 101 drives wiring 112, and transistor 102 drives node ND1. Transistors 103 and 104 drive node ND2. And wiring The load on node 112 is often greater than the load on nodes ND1 and ND2. Therefore The W / L of transistor 101 is determined by transistors 102, 103 and , and It is preferable that the W / L of the zista 104 is greater than the transistor of the circuit 100. Among the transistors, it is preferable that transistor 101 has the largest W / L ratio. Alternatively, the circuit Among the transistors mounted on the same circuit board as transistor 100, transistor 101 has the best W / L ratio. A larger value is preferable. However, a transistor with the same or approximately the same W / L as transistor 101 is preferable. A gista may be provided. This increases the driving capability of transistor 101. This allows the load on wiring 112 to be increased. Furthermore, the transistor Because the size of transistors 102, 103 and 104 can be reduced, Ray This allows for a reduction in the area of ​​play outside the box.

[0108] Even if the potential of node ND1 rises, the potential difference between the gate and source of transistor 102 Because it is possible to maintain a value above the threshold voltage of transistor 102, transistor 1 It is possible to reduce the W / L of 02. On the other hand, when the potential of node ND2 rises, Because the potential difference between the gate and source of transistor 103 gradually decreases, A large W / L ratio is preferable for transistor 103. Therefore, the W / L ratio for transistor 103 is: It is preferable that it is larger than the W / L of transistor 102. Thus, transistor 10 Because the driving capability of 3 can be increased, the change in potential at node ND2 is required. The time can be shortened. Furthermore, the size of transistor 102 can be reduced. Therefore, the layout area can be reduced. However, transistor 102 W / L may be greater than the W / L of transistor 103.

[0109] Circuit 100 is illustrated and explained in Figures 1, 2, 3, 4, 5, and 6, etc., and is not shown in Figures 1, 2, 3, 4, 5, and 6. Transistors that can be added to the revealed circuit 100 and the configurations combining them The following will be explained. However, one aspect of the present invention is not limited to the configuration described below. .

[0110] A transistor 107 may be added to the circuit 100 described above. Figure 10(A) is shown in Figure 1. The configuration when transistor 107 is added to circuit 100 is shown. Transistor 107 is The first terminal is connected to wiring 115B, and the second terminal is connected to wiring 112. Wiring 1 The potential of 15B is preferably VL. However, the potential of wiring 115B is high level. It may have a low level. Transistor 107 is connected to wiring 115B and wiring 112. It controls the conduction or non-conductivity of the wire. When transistor 107 is turned on, the wire 115B and the wire Wiring 112 is conductive, and the potential of wiring 112 is controlled based on the potential of wiring 115B. If the potential of 115B is VL or low level, then the potential of wiring 112 will be VL. The transistor 107 preferably has the same polarity as the transistors 101 to 104. .

[0111] During the period T1, the transistor 107 turns on. Therefore, since the potential of the wiring 115B is supplied to the wiring 112, the potential of the wiring 112 becomes VL. However, during the period T1, the transistor 107 may also be off.

[0112] During the period T2, the transistor 107 turns on. Therefore, since the potential of the wiring 115B is supplied to the wiring 112, the potential of the wiring 112 becomes VL. However, during the period T2, the transistor 107 may also be off.

[0113] During the period T3, the transistor 107 turns off.

[0114] During the period T4, the transistor 107 turns on. Therefore, since the potential of the wiring 115B is supplied to the wiring 112, the potential of the wiring 112 becomes VL. However, during the period T4, the transistor 107 may also be off.

[0115] FIG. 10(A) shows that by the circuit 100 having the transistor 107, it is possible to prevent the wiring 112 from becoming a floating state and stabilize the potential of the wiring 112. Therefore, it is possible to prevent malfunction.

[0116] Note that the first terminal of the transistor 107 may be connected to the wiring 111, the wiring 113, the wiring 114, or the wiring 115. Also, the gate of the transistor 107 may be connected to the wiring 113 or the wiring 114.

[0117] A transistor 108 may be added to the circuit 100 described above. Figure 10(B) is shown in Figure 1. The configuration when transistor 108 is added to circuit 100 is shown. Transistor 108 is The first terminal is connected to wiring 115C, and the second terminal is connected to node ND1. The potential of 115C is preferably VL. However, the potential of wiring 115C is high level. It may have a low level. Transistor 108 has wiring 115C and node ND. Controls the conduction or non-conductivity with 1. When transistor 108 is turned on, the wiring 115C and Node ND1 is connected, and the potential of node ND1 is controlled based on the potential of wiring 115C. If the potential of wiring 115C is VL or low level, then the potential of node ND1 will be VL. In this way, the potential of node ND1 is set to a value that turns off transistor 101. Furthermore, transistor 108 has the same polarity as transistors 101 to 104. preferable.

[0118] During period T1, transistor 108 turns on. Therefore, the potential of wiring 115C is NO It is supplied to node ND1, and the potential of node ND1 becomes VL. However, during period T1, Transistor 108 can be turned off.

[0119] During period T2, transistor 108 is turned off.

[0120] During period T3, transistor 108 is turned off.

[0121] During period T4, transistor 108 turns on. Therefore, the potential of wiring 115C is NO It is supplied to node ND1, and the potential of node ND1 becomes VL. However, during period T4, Transistor 108 can be turned off.

[0122] Figure 10(B) shows that, because circuit 100 has transistor 108, node ND1 This prevents the element from becoming suspended and stabilizes the potential of node ND1. Therefore, This helps prevent malfunctions.

[0123] The first terminal of transistor 108 is connected to wiring 111, wiring 113, wiring 114 or It may be connected to wire 115. Also, the gate of transistor 108 is connected to wire 114. It may also be used.

[0124] Note that if both transistor 107 and transistor 108 are added to circuit 100 The gates of transistor 107 and transistor 108 may be connected. The first terminal of transistor 107 and the first terminal of transistor 108 are connected. That's fine.

[0125] Add either or both of transistors 107 or 108 to the circuit 100 described above. In addition, transistors 109 and 110 may be added. Figure 11 (A) adds transistors 107 and 108 to the circuit 100 shown in Figure 1. The configuration when transistors 109 and 110 are added is also shown. Transistor 109 has its first terminal connected to wiring 116 and its second terminal connected to the transistor The gate of transistor 107 and the gate of transistor 108 are connected, and the gate is connected to wiring 114. The transistor 110 has its first terminal connected to the wiring 114, and its second terminal connected to the The gate of transistor 107 and the gate of transistor 108 are connected, and the gate is a node Connected to ND1. Gate of transistor 107, gate of transistor 108, transistor The second terminal of transistor 109 or the second terminal of transistor 110 is indicated as node ND3. Transistor 109 controls the conduction or non-conductivity between wiring 116 and node ND3. When the transistor 109 is turned on, the wiring 116 and node ND3 become conductive, and node ND3 The potential is controlled based on the potential of wiring 116. When the potential of wiring 116 is VH or high level If so, the potential of node ND3 will rise. However, the gate of transistor 109 is Since it is connected to line 114, the potential of node ND3 is the high-level potential of wiring 114. When the voltage rises to a value obtained by subtracting the threshold voltage of transistor 109, transistor 109 turns off. And node ND3 becomes floating. In this way, the potential of node ND3 becomes The value is set so that transistor 107 or transistor 108 turns on, and the node ND3 becomes floating. Also, transistor 110 conducts between wiring 114 and node ND3. It controls whether the circuit is on or off. When transistor 110 is turned on, the wiring 114 and node ND are connected. 3 is conductive, and the potential of node ND3 is controlled based on the potential of wiring 114. Wiring 11 If the potential at node 4 is low, the potential at node ND3 will drop to VL. In this way, The potential of ND3 is set to a value that turns off transistor 107 or transistor 108. It is done. Also, transistors 109 and 110 are transistors 101 to It is preferable that it has the same polarity as 104.

[0126] During period T1, the wiring 114 becomes high level, so transistor 109 turns on. Also, because the potential of node ND1 becomes VL, transistor 110 turns off. As a result, the potential of wiring 116 is supplied to node ND3, and the potential of node ND3 rises from VL. Then, the potential of node ND3 is equal to the potential (VL) of the first terminal of transistor 107. When the sum of the threshold voltage of transistor 107 (Vth107) is higher than the transistor 107 turns on. Also, the potential of node ND3 is equal to the potential of the first terminal of transistor 108. When the value (VL) exceeds the sum of the threshold voltage of transistor 108 (Vth108), Transistor 108 turns on. Then the potential of node ND3 is that of transistor 109. The value obtained by subtracting the threshold voltage of transistor 109 (Vth109) from the gate potential (VH) When this happens, transistor 109 turns off. Therefore, node ND3 becomes floating, and The potential of ND3 is maintained at VH-Vth109.

[0127] During period T2, the potential of wiring 114 becomes low, so transistor 109 is It becomes F. Also, the potential of node ND1 is the potential (VL) of the first terminal of transistor 110. When the sum of the voltage and the threshold voltage of transistor 110 (Vth110) becomes higher, the transistor 110 turns on. Therefore, the low-level potential of wiring 114 is supplied to node ND3. Therefore, the potential of node ND3 drops from VH-Vth109 to VL. Thus, the transient Transistors 107 and 108 are turned off.

[0128] During period T3, the potential of wiring 114 remains at a low level, so transistor 10 9 will remain off. Also, the potential of node ND1 will be VH+Vth110+β. Transistor 110 remains on. Therefore, the low-level potential of wiring 114 is no The voltage is supplied to node ND3, and the potential of node ND3 remains VL. Therefore, the transistor Transistors 107 and 108 remain off.

[0129] During period T4, the potential of wiring 114 becomes high, so transistor 109 is It becomes [a certain state]. Also, because the potential of node ND1 becomes VL, transistor 110 turns off. Therefore, the potential of wiring 116 is supplied to node ND3, and the potential of node ND3 is VL or It rises. Then the potential of node ND3 is equal to the potential of the first terminal of transistor 107 (V When the sum of L) and the threshold voltage of transistor 107 (Vth107) becomes higher, Zistor 107 turns on. Also, the potential of node ND3 is at the first terminal of transistor 108. The potential of the child (VL) is higher than the sum of the threshold voltage of transistor 108 (Vth108). Then, transistor 108 turns on.

[0130] Figure 11(A) shows that circuit 100 has transistors 109 and 110. This generates a signal within circuit 100 to control transistor 107 or transistor 108. It is possible to do so. Therefore, the number of signals can be reduced.

[0131] Furthermore, as shown in Figure 11(B), the gate of transistor 109 and transistor 110 The first terminal may be connected to wiring 117. The potential of wiring 117 is high level (for example) It has VH (very high) and low levels (e.g., VL).

[0132] Furthermore, the gate of transistor 109 is connected to wiring 117, and the first of transistor 110 The terminal may be connected to wiring 114. Alternatively, the gate of transistor 109 may be connected to wiring 1 14 may be connected, and the first terminal of transistor 110 may be connected to wiring 117.

[0133] Furthermore, the second terminal of transistor 109 and the second terminal of transistor 110 are The gate of transistor 107 and the gate of transistor 108, specifically the gate of transistor 107. It may be connected only to the second terminal of transistor 109 and the transistor. The second terminal of 110 is connected to the gate of transistor 107 and the gate of transistor 108. It may be connected only to the gate of transistor 108.

[0134] Note that the first terminal of transistor 110 is connected to wire 115, wire 115B, wire 115C or It may be connected to wiring 117.

[0135] A transistor 121 may be added to the circuit 100 described above. Figure 12(A) is a modified version of Figure 1. The following shows the configuration when transistor 121 is added to the circuit 100 shown. 1 has a first terminal connected to wiring 112, and a second terminal connected to node ND1, and The terminal is connected to wiring 111. Transistor 121 is connected to wiring 112 and node ND1. It controls whether the circuit is on or off. When transistor 121 is turned on, the wiring 112 and node ND are connected. 1 and 1 are in contact. For example, during period T3, the potential of wiring 112 rises from VL and NO If the potential of node ND1 is rising from VH, the rise in the potential of node ND1 is suppressed. In both cases, the time required for the potential change of wiring 112 is shortened. However, transistor 121 Since the gate is connected to wiring 111, the potential of wiring 112 is higher than the high level of wiring 111. When the value obtained by subtracting the threshold voltage of transistor 121 from the potential of the terminal becomes, transistor 121 It turns off. Also, transistor 121 has the same polarity as transistors 101 to 104. It is preferable to have one.

[0136] During period T1, the wiring 111 becomes low level, so transistor 121 turns off. ru.

[0137] During period T2, the wiring 111 becomes low level, so transistor 121 turns off. ru.

[0138] During period T3, the wiring 111 becomes high level, so transistor 121 turns on. However, the potential of wiring 112 is less than the gate potential (VH) of transistor 121. When the voltage rises to the value obtained by subtracting the threshold voltage (Vth121) of transistor 122, 1 will be turned off.

[0139] During period T4, the wiring 111 becomes low level, so transistor 121 turns off. ru.

[0140] Figure 12(A) shows that the circuit 100 has a transistor 121, and node ND1 This prevents the potential from becoming too high. Therefore, it is connected to node ND1. This can help suppress the degradation of transistors or prevent their destruction.

[0141] A transistor 122 may be added to the circuit 100 described above. Figure 12(B) is a modified version of Figure 1. The following shows the configuration when transistor 122 is added to the circuit 100 shown. In 2, the first terminal is connected to node ND1, and the second terminal is connected to node ND2, The node is connected to wiring 113. Transistor 122 is connected to node ND1 and node ND2. It controls the conduction or non-conductivity of node ND1 and node ND1. When transistor 122 is turned on, node ND1 and node ND1 are controlled. Node ND2 and ND1 become conductive. For example, during period T2, the potential of node ND1 rises from VL. Furthermore, if the potential of node ND2 is rising from VH-Vth103, then node ND2 The rise in potential is suppressed, and the time required for the potential of node ND1 to change is shortened. However, since the gate of transistor 122 is connected to wiring 113, node ND1 The potential is the value obtained by subtracting the threshold voltage of transistor 122 from the high-level potential of wiring 113. When this happens, transistor 122 turns off. Also, transistor 122 is a transistor It is preferable that the polarity is the same as that of 101 to 104.

[0142] During period T1, the wiring 113 becomes low level, so transistor 122 turns off. ru.

[0143] During period T2, the wiring 113 becomes high level, so transistor 122 turns on. However, the potential of node ND1 is different from the gate potential (VH) of transistor 122. When the voltage rises to the value obtained by subtracting the threshold voltage (Vth122) of transistor 122, transistor 1 22 will be turned off.

[0144] During period T3, the wiring 113 becomes low level, so transistor 122 turns off. ru.

[0145] During period T4, the wiring 113 becomes low level, so transistor 122 turns off. ru.

[0146] Figure 12(B) shows that the circuit 100 has transistor 122, which enables node ND2 This prevents the potential from becoming too high. Therefore, it is connected to node ND2. This can help suppress the degradation of transistors or prevent their destruction.

[0147] A transistor 123 may be added to the circuit 100 described above. Figure 13(A) is a modified version of Figure 1. The following shows the configuration when transistor 123 is added to the circuit 100 shown. In configuration 3, the first terminal is connected to wiring 111, and the second terminal is connected to node ND1. The transistor 123 controls the continuity or non-continuity between the wiring 111 and node ND1. When the generator 123 is turned on, the wiring 111 and node ND1 become conductive, and the potential of wiring 111 This is supplied to node ND1. If the potential of wiring 111 is low, node ND1 The potential becomes VL. In this way, the potential of node ND1 turns transistor 101 off. It is set to the same value as transistors 101 to 104. It is preferable that it be polar.

[0148] During period T0, transistor 123 turns on. Therefore, the low level of wiring 111. The potential is supplied to node ND1, and the potential of node ND1 becomes VL.

[0149] During periods T1, T2, T3, and T4, transistor 123 is turned off. .

[0150] Figure 13(A) shows that the circuit 100 has transistor 123, and node ND1 The potential can be set to VL. Therefore, malfunctions can be prevented.

[0151] A transistor 124 may be added to the circuit 100 described above. Figure 13(B) is a modified version of Figure 1. The following shows the configuration when transistor 124 is added to the circuit 100 shown. In 4, the first terminal is connected to wiring 113, and the second terminal is connected to node ND2. The transistor 124 controls the continuity or non-continuity between the wiring 113 and node ND2. When the generator 124 is turned on, the wiring 113 and node ND2 become conductive, and the potential of wiring 113 This is supplied to node ND2. If the potential of wiring 113 is low, node ND2 The potential becomes VL. In this way, the potential of node ND2 turns transistor 102 off. It is set to the same value as transistors 101 to 104. It is preferable that it be polar.

[0152] During period T0, transistor 124 turns on. Therefore, the low level of wiring 113. The potential is supplied to node ND2, and the potential of node ND2 becomes VL.

[0153] During periods T1, T2, T3, and T4, transistor 124 is turned off. .

[0154] Figure 13(B) shows that the circuit 100 has transistor 124, which enables node ND2 The potential can be set to VL. Therefore, malfunctions can be prevented.

[0155] Note that if both transistor 123 and transistor 124 are added to circuit 100 The gates of transistor 123 and transistor 124 may be connected.

[0156] As illustrated in Figures 1, 2, 3, 4, 5, 6, 10, 11, 12, and 13, etc. The circuit 100 described, as well as the circuit 100 described (not shown), can be freely combined. It is possible.

[0157] Figure 14(A) shows that the first terminal and gate of transistor 103 are connected to wiring 113. The configuration (see Figure 3(A)) and the configuration in which the gate of transistor 104 is connected to wiring 111. (See Figure 5(A)) This is the configuration when combined with .

[0158] Figure 14(B) shows a configuration in which the gate of transistor 104 is connected to wiring 111 (Figure 5(A (See reference) and a configuration that adds transistor 108 (see Figure 10(B)), and transistor A configuration that adds transistors 109 and 110 (see Figure 11(B)) and a combination of This is the configuration of the case.

[0159] Furthermore, this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, The contents described in this embodiment (or even just some of the contents) may differ from the contents described in that embodiment. The content (even partial content) and / or the description in one or more other embodiments. Applying, combining, or replacing content (even partial content) This is possible. Furthermore, the contents described in each embodiment refer to various aspects in each embodiment. This refers to content described using diagrams or content described using text in the specification. Furthermore, a diagram (even a part of it) described in one embodiment may be a different part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by Furthermore, many more figures can be constructed. This is also true in the following embodiments. That is the case.

[0160] (Embodiment 2) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0161] A configuration of a semiconductor device according to one aspect of the present invention will be described with reference to Figure 15. However, One aspect of the present invention is not limited to the configuration described below.

[0162] The semiconductor device shown in Figure 15 has a circuit 200. Circuit 200 has wiring 212, wiring 21 3. Based on the potential of wiring 214 and wiring 215, N (where N is a natural number greater than or equal to 3) wiring 2 Circuit 20 has the function of controlling the potential of 11 (also indicated as wiring 211[1] to [N]). 0 is a signal based on the potential of wires 212, 213, 214, and 215. It outputs to each of 211[1] through [N]. And, based on the signal, wiring 211[ Each of the potentials from [1] to [N] is controlled.

[0163] Specifically, circuit 200 is at the potential of wiring 212, wiring 213, wiring 214, and wiring 215. Based on this, the function of sequentially activating the potential of wiring 211[1] to [N], i.e., wiring It has the function of sequentially raising the potentials of 211[1] to [N] to a high level or a low level. In 16, circuit 200 is at the potential of wiring 212, wiring 213, wiring 214 and wiring 215. Based on this, the timing for sequentially raising the potential of wiring 211[1] to [N] The chart is shown. As shown, circuit 200 functions as a shift register.

[0164] Furthermore, the potential of wiring 212, 213, 214, and 215 is such that each wiring has a signal or It is controlled by inputting voltage, etc. For example, signal CK1 is input to wiring 212. Then, signal CK2 is input to wiring 213, signal CK3 is input to wiring 214, Signal SP is input to line 215, and signal OU is input to each of the wirings 211[1] to [N]. T[1] to [N] are output. That is, signals OUT[1] to [N] are signals CK1, It has values ​​based on signals CK2, CK3 and SP. Signals CK1, CK2 and As for signal CK3, there are clock signals with different phases. Also, as for signal SP... It has a start pulse.

[0165] Circuit 200 has N circuits 201 (also referred to as circuits 201[1] to [N]). Each of the paths 201[1] to [N] is in conjunction with the circuit 100 described in Embodiment 1. In Figure 15, each of circuits 201[1] to [N] corresponds to circuit 1 shown in Figure 5(A). 00 is used.

[0166] In circuit 201[2m+1] (where m is 0 or a positive integer), the first of transistor 101 The terminal and the gate of transistor 104 are connected to wiring 214. Therefore, wiring 214 is This corresponds to wiring 111. Also, the second terminal of transistor 101 is connected to wiring 211 [2m+1 It is connected to ]. Therefore, wiring 211[2m+1] corresponds to wiring 112. Also, tra The first terminal of the converter 102 is connected to the wiring 215 or wiring 211 [2m]. Wiring 215 or wiring 211 [2m] corresponds to wiring 113. Also, transistor 1 The first terminal and gate of 03 are connected to wiring 212. Therefore, wiring 212 is wiring This corresponds to 114. Also, the first terminal of transistor 104 is connected to wiring 213. Therefore, wiring 213 corresponds to wiring 115.

[0167] In circuit 201[2m+2], the first terminal of transistor 101 and transistor 1 Gate 04 is connected to wiring 212. Therefore, wiring 212 corresponds to wiring 111. Furthermore, the second terminal of transistor 101 is connected to wiring 211[2m+2]. Wiring 211[2m+2] corresponds to wiring 112. Also, the first of transistor 102 The terminal is connected to wiring 211[2m+1]. Therefore, wiring 211[2m+1] is wiring This corresponds to 113. Also, the first terminal and gate of transistor 103 are connected to wiring 213. They are connected. Therefore, wiring 213 corresponds to wiring 114. Also, transistor 104 The first terminal is connected to wiring 214. Therefore, wiring 214 corresponds to wiring 115.

[0168] In circuit 201[2m+3], the first terminal of transistor 101 and transistor 1 Gate 04 is connected to wiring 213. Therefore, wiring 213 corresponds to wiring 111. Furthermore, the second terminal of transistor 101 is connected to wiring 211[2m+3]. Wiring 211[2m+3] corresponds to wiring 112. Also, the first of transistor 102 The terminal is connected to wiring 211[2m+2]. Therefore, wiring 211[2m+2] is wiring This corresponds to 113. Also, the first terminal and gate of transistor 103 are connected to wiring 214. They are connected. Therefore, wiring 214 corresponds to wiring 114. Also, transistor 104 The first terminal is connected to wiring 212. Therefore, wiring 212 corresponds to wiring 115.

[0169] Furthermore, as shown in Figure 17, in each of the circuits 201[1] to [N], the transient The first terminal of terminal 104 may be connected to wiring 216. Wiring 216 is connected to wiring 115. It corresponds to. Also, voltage VSS may be supplied to wiring 216. Voltage VSS is, for example, signal The values ​​corresponding to the low levels of signal CK1, signal CK2, signal CK3, and signal SP (equal to or They have (approximately equal values).

[0170] Furthermore, as shown in Figure 18, in circuit 201[2m+1], the number of transistors 103 Terminal 1 and the gate may be connected to wiring 213. Also, circuit 201[2m+2] In this configuration, the first terminal and gate of transistor 103 may be connected to wiring 214. Also, in circuit 201[2m+3], the first terminal and the gate of transistor 103 The first part may be connected to wiring 212. That is, circuit 201[i] (where i is any of 2 to N) In (a), the first terminal and gate of transistor 103 are connected to wiring 212 and wiring 21 3 and the first terminal of transistor 101 of circuit 201[i-1] of wiring 214 are connected. It may be connected to the wiring.

[0171] Note that the first terminal or gate of transistor 103 is connected to each of circuits 201[1] to [N]. The wire is connected to the circuit 100 (for example, Figures 2(A), 2(B), and 3(B)). If the (reference) is adopted, each transistor 103 of circuit 201[1] to [N] A new wiring may be provided to which the first terminal or gate is connected.

[0172] Furthermore, this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, The contents described in this embodiment (or even just some of the contents) may differ from the contents described in that embodiment. The content (even partial content) and / or the description in one or more other embodiments. Applying, combining, or replacing content (even partial content) This is possible. Furthermore, the contents described in each embodiment refer to various aspects in each embodiment. This refers to content described using diagrams or content described using text in the specification. Furthermore, a diagram (even a part of it) described in one embodiment may be a different part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by Furthermore, many more figures can be constructed. This is also true in the following embodiments. That is the case.

[0173] (Embodiment 3) This embodiment describes a display device according to one aspect of the present invention.

[0174] The configuration of a display device according to one aspect of the present invention will be described with reference to Figure 19. However, this One aspect of the invention is not limited to the configuration described below.

[0175] The display device shown in Figure 19 includes a pixel unit 301, a scan line driving circuit 302, and a signal line driving circuit 30 It has 3.

[0176] In the pixel section 301, there are N scan lines GL (also referred to as scan lines GL[1] to [N]) and M( M is a natural number greater than or equal to 2. It intersects with signal lines SL (also denoted as signal lines SL[1] through [M]). They are arranged in such a way. Additionally, a pixel 310 is placed at each intersection.

[0177] Pixel 310 has at least a display element and a transistor. The display element is a light emitter. There are liquid crystal elements. As for light-emitting elements, there are EL elements.

[0178] For example, in this specification, etc., display element, display device having a display element, light emission Light-emitting devices, which are devices having elements and light-emitting elements, can take various forms or various shapes. It may have such elements. For example, a display element, display device, light-emitting element, or light-emitting device may have the following characteristics: EL (Electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements) Children, inorganic EL elements, LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) , transistor (a transistor that emits light in response to current), electron emission element, liquid crystal element, electron Ink, electrophoretic elements, grating light bulbs (GLV), plasma displays Display elements using (PDP), MEMS (Micro-Electro-Mechanical Systems) Children, Digital Micromirror Devices (DMDs), DMS (Digital Microshutter) (Turnover), IMOD (Interference Modulation) element, shutter type MEMS display elements, optical interference type MEMS display elements, electrowetting elements, pressure At least It possesses one of these properties. In addition to these, it also has contrast and brightness due to electrical or magnetic effects. The display medium may have properties such as temperature, reflectance, and transmittance that change. One example of such a device is an EL display, which is a type of display device that uses electron-emitting elements. Examples include field emission displays (FEDs) or SED type flat panel displays. Spray (SED: Surface-conduction Electron-emi) Examples include liquid crystal displays. Liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays) Examples include spray displays, direct-view liquid crystal displays, and projection-type liquid crystal displays. Alternatively, an example of a display device using an electrophoretic element is electronic paper. When realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, one of the pixel electrodes The part or the whole should function as a reflective electrode. For example, pixel electrodes The electrodes can be made of aluminum, silver, etc., in part or all of the material. In that case, it is also possible to install a memory circuit such as SRAM below the reflective electrode. This further reduces power consumption. Note that when using LEDs, Graphene or graphite may be placed beneath the electrodes or nitride semiconductor. Graphite can also be made into a multilayer film by stacking multiple layers. In this way, graphene and By providing graphite, a nitride semiconductor, such as an n-type crystalline semiconductor, can be placed on top of it. GaN semiconductor layers and the like can be easily formed. Furthermore, a crystalline p can be formed on top of it. LEDs can be constructed by providing a GaN semiconductor layer or the like. An AlN layer may be provided between the laphite and the n-type GaN semiconductor layer having a crystal structure. Oh, the GaN semiconductor layer of the LED may be deposited by MOCVD. However, graph By providing a nut, the GaN semiconductor layer of the LED can also be formed by sputtering. It is possible.

[0179] The scan line driving circuit 302 has the function of controlling the potential of the scan lines GL[1] to [N]. The scan line drive circuit 302 outputs a scan signal to each of the scan lines GL[1] to [N]. The scan signal then controls the potential of each of the scan lines GL[1] to [N]. Furthermore, the scan line drive circuit 302 is the same as the circuit 100 described in Embodiment 1 or the embodiment It is possible to have the circuit 200 described in Embodiment 2. In such a case, for example, Each of the scan lines GL[1] to [N] corresponds to wiring 112. Alternatively, scan line GL[ [1] to [N] correspond to wiring 211[1] to [N] respectively. Also, scan line drive cycle Signals for controlling path 302 (clock signal and start pulse, etc., or signal CK1, Signals CK2, CK3, and SP, etc., are supplied from circuit 304.

[0180] The signal line drive circuit 303 has a function to control the potential or current of the signal lines SL[1] to [M]. The signal line drive circuit 303 has video signals on each of the signal lines SL[1] to [M]. The output is then determined by the video signal, which determines the potential of each signal line SL[1] through [M]. This is controlled. In addition, the signal line drive circuit 303 is the same as the circuit 10 described in Embodiment 1. It is possible to have either 0 or the circuit 200 described in Embodiment 2. Signals for controlling the line drive circuit 303 (e.g., clock signal, start pulse, video) Signals, etc., are supplied from circuit 304.

[0181] Circuit 304 supplies signals to the scan line drive circuit 302 and the signal line drive circuit 303. Therefore, it functions as a timing controller. In addition, circuit 304 is a scan line drive. Voltage may be supplied to circuit 302 and signal line drive circuit 303. In such a case, circuit 3 04 functions as a power supply circuit.

[0182] Furthermore, the scan line drive circuit 302 operates at a slower speed than the signal line drive circuit 303. Therefore The transistors in the scan line drive circuit 302 are made of oxide semiconductors, polycrystalline silicon, or non-oxide semiconductors. It is preferable to have crystalline silicon in the channel formation region. On the other hand, the signal line drive circuit 30 The transistor in 3 preferably has single-crystal silicon in the channel formation region. Therefore, the pixel unit 301 and the scanning line driving circuit 302 are provided on the same substrate, and the signal line driving circuit 3 It is preferable that 03 be provided on a separate substrate. However, the pixel section 301 and the scan line driving circuit 302 The signal line drive circuit 303 may also be provided on the same board.

[0183] Furthermore, the scanning line drive circuit 302 is the same as the circuit 100 described in Embodiment 1 or the embodiment By adopting the circuit 200 described in section 2, the scanning line drive circuit 302 has the following characteristics All transistors can be made to have the same polarity. Therefore, the pixel section 301 and the scan line drive cycle If path 302 is provided on the same substrate, then all transistors provided on that substrate are the same. It is preferable that it be polar.

[0184] Furthermore, the scanning line drive circuit 302 is the same as the circuit 100 described in Embodiment 1 or the embodiment By adopting the circuit 200 described in section 2, the layout of the scan line drive circuit 302 The area can be reduced. Therefore, the resolution of 310 pixels can be increased. Additionally, the frame size can be reduced.

[0185] Furthermore, this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, The contents described in this embodiment (or even just some of the contents) may differ from the contents described in that embodiment. The content (even partial content) and / or the description in one or more other embodiments. Applying, combining, or replacing content (even partial content) This is possible. Furthermore, the contents described in each embodiment refer to various aspects in each embodiment. This refers to content described using diagrams or content described using text in the specification. Furthermore, a diagram (even a part of it) described in one embodiment may be a different part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by Furthermore, many more figures can be constructed. This is also true in the following embodiments. That is the case.

[0186] (Embodiment 4) In this embodiment, the structure of the semiconductor device described in Embodiment 1 will be explained.

[0187] Figure 20 is a top view of the semiconductor device shown in Figure 5(A). Also, Figure 23 is a top view of the same device as shown in Figure 20. This is a cross-section AB in the top view. However, one aspect of the present invention is not limited to the configuration described below. do not have.

[0188] The semiconductor device shown in Figure 20 has conductive layers 401A to 401D and semiconductor layers 402A to 402 D has conductive layers 403A to 403I and insulating layer 404. Figure 21 shows conductive layer 40 Figure 22 shows only conductive layers 1A to 401D. Oh, the X direction is approximately perpendicular to the Y direction. Or, the X direction is the direction that intersects the Y direction. That is the case.

[0189] The insulating layer 404 has a region that becomes the gate insulating layer of transistor 101 and transistor 102 The region that will become the gate insulating layer of the transistor, and the region that will become the gate insulating layer of transistor 103, It has a region that becomes the gate insulating layer of the zista 104. The insulating layer 404 is connected to the conductive layer 4 The region sandwiched between 01A and semiconductor layer 402A, and the conductive layer 401B and semiconductor layer 402B The region sandwiched between and the region sandwiched between the conductive layer 401C and the semiconductor layer 402C, It has a region sandwiched between the conductive layer 401D and the semiconductor layer 402D. Note that the black in the figure The circles indicate contact holes in the insulating layer 404.

[0190] The insulating layer 404 is made of plasma chemical vapor deposition (PECVD). (Incident Chemical Vapor Deposition) method, sputtering By methods such as the smuggling process, silicon oxide film, silicon oxide nitride film, silicon nitride film, silicon nitride film Aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide Film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide Insulating layers containing one or more um film and neodymium oxide film can be used.

[0191] The conductive layers 401A to 401D are the same layer. Alternatively, the conductive layers 401A to 401D are the same. The material is present. Alternatively, the conductive layers 401A to 401D are formed through a process of processing the same conductive film. It was formed by [this method].

[0192] The conductive layers 401A to 401D are chromium (Cr), copper (Cu), and aluminum (A). l) Gold (Au), Silver (Ag), Zinc (Zn), Molybdenum (Mo), Tantalum (Ta) Titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (F) e) Metal elements selected from cobalt (Co), or compounds comprising the above-mentioned metal elements. They can be formed using gold or alloys combining the aforementioned metallic elements.

[0193] Furthermore, the conductive layers 401A to 401D may be a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film deposited on top of an aluminum film. Layered two-layer structure, two-layer structure with a titanium film laminated on a titanium nitride film, titanium on a titanium nitride film A two-layer structure with stacked tungsten films, tantalum nitride film or tungsten nitride film with tungsten A two-layer structure with stacked titanium films, a titanium film and an aluminum film stacked on top of the titanium film, Furthermore, there are three-layer structures in which a titanium film is formed on top of it. One of the following materials is selected from tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or nitride film made up of multiple layers may be used.

[0194] Furthermore, the conductive layers 401A to 401D are indium tin oxide and tungsten oxide. Contains indium oxide, indium zinc oxide containing tungsten oxide, and titanium oxide. Indium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, acid Apply a light-transmitting conductive material such as indium tin oxide with added silicon dioxide. It's also possible.

[0195] Furthermore, conductive layers 401A to 401D contain a Cu-X alloy film (where X is Mn, Ni, Cr, F e, Co, Mo, Ta, or Ti may be applied. By using a Cu-X alloy film... Furthermore, because it can be processed using a wet etching process, manufacturing costs can be reduced. ru.

[0196] The conductive layer 401A consists of a region that forms the gate electrode of transistor 101 and a region of capacitive element 105. It has two electrode regions and a conductive layer 401A, and an opening 401A1 and an opening It has part 401A2 and the opening 401A1 and opening 401A2 are substantially aligned in the Y direction. It has a long length.

[0197] The conductive layer 401B consists of a region that will become the gate electrode of transistor 102 and a region of capacitive element 106. It has two electrode regions and a conductive layer 401B having an opening 401B1. The opening 401B1 has an elongated length that is approximately aligned with the Y direction.

[0198] The conductive layer 401C has a region that will become the gate electrode of the transistor 103.

[0199] The conductive layer 401D has a region that will become the gate electrode of the transistor 104.

[0200] The area of ​​conductive layer 401A is equal to the area of ​​conductive layer 401B, conductive layer 401C, and conductive layer 401D. It is larger than the area. Also, the area of ​​conductive layer 401B is equal to the area of ​​conductive layer 401C and conductive layer 401D It is larger than the area of ​​[the other area].

[0201] Furthermore, the area of ​​openings 401A1 and 401A2 is larger than the area of ​​opening 401B1. It's large. Also, the width of openings 401A1 and 401A2 is greater than the width of opening 401B1. It is also large. In addition, the length in the longitudinal direction of opening 401A1 and opening 401A2 is the opening It is longer than the length of the 401B1 in the longitudinal direction.

[0202] The conductive layer 401A may have three or more openings, and the conductive layer 401B may have two or more openings. An upper opening may be provided. However, the number of openings in the conductive layer 401A is limited to the number of openings in the conductive layer 40 It is preferable that the number of openings is greater than the number of openings in 1B.

[0203] Semiconductor layers 402A to 402D are the same layer. Alternatively, semiconductor layers 402A to 402D are They have the same material. Alternatively, semiconductor layers 402A to 402D are made from the same semiconductor film. It is formed through a process.

[0204] The semiconductor layers 402A to 402D can be single-crystal semiconductors or non-single-crystal semiconductors. Examples of crystalline semiconductors include non-single-crystal silicon and non-single-crystal germanium. Silicon can be amorphous silicon, microcrystalline silicon, or polycrystalline silicon, and non-single-crystal silicon Germanium can be amorphous germanium, microcrystalline germanium, or polycrystalline germanium. These are some examples.

[0205] In particular, it is preferable to use an oxide semiconductor film as the semiconductor layer 402A to 402D. As oxide semiconductor films, In-M (where M is Ti, Ga, Sn, Y, Zr, La, Ce) Oxides (representing Nd or Hf), In-M-Zn oxides can be used. In addition, it is preferable to use In-M-Zn oxide as the oxide semiconductor film. If the film is In-M-Zn oxide, the spatula used to deposit the In-M-Zn oxide film is used. The atomic ratio of the metal elements in the tarring target is preferably such that In ≥ M and Zn ≥ M. i. As an atomic ratio of metal elements in such a sputtering target, In:M:Zn =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In: M:Zn = 3:1:2 and In:M:Zn = 4:2:4.1 are preferred. When the body film is an In-M-Zn oxide, the sputtering target is a polycrystalline In -It is preferable to use a target containing M-Zn oxide. Polycrystalline In-M-Zn oxide Using a target containing this makes it easier to form crystalline oxide semiconductor films. The atomic ratio of the oxide semiconductor film to be deposited will be adjusted as an error for the sputtering process described above. This includes a variation of plus or minus 40% in the atomic ratio of metal elements contained in the target. For sputtering targets, the atomic ratio is In:Ga:Zn=4:2:4.1 When used, the atomic ratio of the oxide semiconductor film to be formed is approximately In:Ga:Zn = 4:2:3. They may be nearby.

[0206] The oxide semiconductor film has an energy gap of 2 eV or more, preferably 2.5 eV or more. Preferably, it is 3 eV or more. Thus, an oxide semiconductor with a wide energy gap is used. This reduces the transistor's off-current.

[0207] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 1 The wavelength should be 00 nm or less, and more preferably 3 nm to 50 nm.

[0208] As the oxide semiconductor film, an oxide semiconductor film with a low carrier density is used. For example, an oxide Semiconductor films have a carrier density of 1 × 10⁻⁶ 17 pieces / cm 3 The following is preferably 1 × 10 15 pieces / cm 3 More preferably 1 × 10 13 pieces / cm 3 More preferably 1 × 101 1 per cm 3 shall be as follows. Further, the carrier density of the oxide semiconductor film is 1 × 10 5 per cm 3 or more, more preferably 1 × 10 7 per cm 3 or more may be used.

[0209] Note that these are not limited thereto, and those with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the oxide semiconductor film appropriate is preferable.

[0210] Note that as the oxide semiconductor film, an oxide semiconductor film with a low impurity concentration and a low defect level density is used to fabricate a transistor having more excellent electrical characteristics, which is preferable. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is called high purity intrinsic or substantially high purity intrinsic. The oxide semiconductor film with high purity intrinsic or substantially high purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has electrical characteristics (also called normally on) in which the threshold voltage becomes negative. In addition, the oxide semiconductor film with high purity intrinsic or substantially high purity intrinsic has a low defect level density and thus the trap level density may also be low. Also, the oxide semiconductor film with high purity intrinsic or substantially high purity intrinsic has a significantly small off-current, and the channel width is 1 × 10 6 ​μm Even with an element with a channel length L of 10 μm, the voltage between the source electrode and the drain electrode (drain In the range of 1V to 10V, the off-current is measured by a semiconductor parameter analyzer. Below the measurement limit, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less.

[0211] Therefore, the above-mentioned high-purity intrinsic, or substantially high-purity intrinsic oxide semiconductor film has a channel region Transistors in which a region is formed have small variations in electrical characteristics and are highly reliable transistors. This is possible. Furthermore, the charge trapped in the trap levels of the oxide semiconductor film disappears. The time required for this to occur is long, and it can behave as if it were a fixed charge. Therefore, A transistor in which a channel region is formed in an oxide semiconductor film with a high lap level density is electrically... The properties may become unstable. Impurities include hydrogen, nitrogen, alkali metals, or This includes earth metals such as rutile.

[0212] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atoms to form water, An oxygen vacancy is formed in the lattice (or the part where oxygen has been removed) where oxygen has been removed. The presence of hydrogen can sometimes generate electrons, which act as carriers. Additionally, some of the hydrogen can turn gold into gold. It can combine with oxygen atoms that bond with its genus atoms, generating electrons, which act as carriers. Therefore, Transistors using oxide semiconductor films containing hydrogen exhibit normally-on characteristics. Therefore, it is preferable that the oxide semiconductor film has as little hydrogen as possible. Specifically, in an oxide semiconductor film, the hydrogen concentration obtained by SIMS analysis is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferably 5 × 1019 atoms / cm 3 The following are better Mashiku is 1 x 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 below, Preferably 1 × 10 18 atoms / cm 3 The following is more preferable: 5 x 10 17 Atom s / cm 3 The following may also be used. In addition, in oxide semiconductor films, obtained by SIMS analysis The hydrogen concentration is 1 × 10 16 atoms / cm 3 In summary, 1 × 10 17 a toms / cm 3 You may leave it at that.

[0213] In oxide semiconductor films, if silicon or carbon, which are among the Group 14 elements, oxidation occurs. In a monocrystalline semiconductor film, oxygen vacancies increase, leading to n-type formation. Therefore, in an oxide semiconductor film... The concentration of silicon and carbon in the film and the concentration of silicon and carbon near the interface with the oxide semiconductor film. The concentration obtained by SIMS analysis is 2 × 10 18 atoms / cm 3 The following applies. Furthermore, the concentration of silicon and carbon in the oxide semiconductor film and the silicon near the interface with the oxide semiconductor film The concentrations of ricon and carbon (concentrations obtained by SIMS analysis) are 1 × 10⁻⁶. 17 atom / cm 3 The above is futur3×10 17 atoms / cm 3 The above is more 1x 10 18 atoms / cm 3 You may leave it at that.

[0214] In oxide semiconductor films, alkali metals or alkaline earth elements obtained by SIMS analysis The concentration of the metal is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 Atom s / cm 3 The following applies: Alkali metals and alkaline earth metals bond with oxide semiconductors. This can generate carriers, which can increase the transistor's off-current. Therefore, reducing the concentration of alkali metals or alkaline earth metals in oxide semiconductor films is necessary. This is preferable. In addition, in oxide semiconductor films, alkali gold obtained by SIMS analysis The concentration of the genus or alkaline earth metal is 5 × 10 15 atoms / cm 3 The above is preferable 1 x 10 16 atoms / cm 3 You may leave it at that.

[0215] When nitrogen is present in an oxide semiconductor film, electrons, which act as carriers, are generated, increasing the carrier density. Furthermore, it is easily converted to n-type. As a result, transients using oxide semiconductor films containing nitrogen Sta is prone to normally-on properties. Therefore, in oxide semiconductor films, nitrogen is formed. It is preferable that the nitrogen concentration obtained by SIMS analysis be reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is , 5×10 18 atoms / cm 3 The following is preferable. Also, SIMS analysis The nitrogen concentration obtained is 1 × 10⁻⁶ 16 atoms / cm 3 The above is more comfortable 5x10 16 atoms / cm 3 In summary, 1 × 10 17 atoms / cm 3 That's all. Preferably 5 x 1017 atoms / cm 3 You may leave it at that.

[0216] The oxide semiconductor films may each have a non-single-crystal structure. Non-single-crystal structures are, for example, as will be described later. CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor, including polycrystalline, microcrystalline, or amorphous structures. In non-single-crystal structures, amorphous structures have the highest defect level density, and CAAC-OS has the highest defect level density. The density of depressions is low.

[0217] The structure of oxide semiconductor films will be described below.

[0218] Oxide semiconductor films are divided into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. For example, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors. ru.

[0219] Furthermore, as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned) Crystalline Oxide Semiconductor, Polycrystalline Oxide These include semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Also, crystalline oxide semiconductors... The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Examples include semiconductors.

[0220] First, let's explain the CAAC-OS membrane.

[0221] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions.

[0222] Transmission Electron Microscope (TEM) A composite analysis image of the CAAC-OS film's bright-field image and diffraction pattern (using a scope) Also known as a high-resolution TEM image, multiple crystalline regions can be identified by observing it. On the other hand, high-resolution TEM images clearly show the boundaries between crystalline parts, i.e., grain boundaries. Also called boundary.) It is not possible to confirm. Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0223] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction approximately parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is: The surface (also called the film-forming surface) or the top surface of the CAAC-OS film reflects the unevenness of the surface on which the film is formed. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0224] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction approximately perpendicular to the sample surface. This confirms that in the crystalline region, the metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0225] X-ray diffraction (XRD) was applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is approximately aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing vertically.

[0226] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0227] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0228] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxides Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0229] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Therefore, The transistor using this oxide semiconductor film exhibits an electrical characteristic in which the threshold voltage becomes negative. Also called normally-on.) It rarely becomes high-purity intrinsic or substantially high-purity. Highly intrinsic oxide semiconductor films have few carrier traps. Transistors using body membranes exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can remain dormant for a long time, behaving almost like a fixed charge. Therefore, the impurity concentration Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. This can happen.

[0230] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0231] Next, we will explain microcrystalline oxide semiconductor films.

[0232] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0233] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peaks indicating this are detected. Also, for the nc-OS film, probes larger than the crystalline region are detected. Electron diffraction (also called limited-area electron diffraction) using an electron beam with a diameter (e.g., 50 nm or more) When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films... Nanobeam electron beams with a probe diameter close to or smaller than the size of the crystal region are used. When diffraction is performed, spots are observed. Furthermore, nanobeam electron diffraction is performed on nc-OS films. When this is done, a region of high brightness may be observed in a circular (ring-shaped) pattern. Also, When nanobeam electron diffraction is performed on an nc-OS film, multiple spots are observed within a ring-shaped region. It may be observed.

[0234] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0235] Next, we will explain amorphous oxide semiconductor films.

[0236] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0237] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0238] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0239] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like Oxide Semiconductor (OS) It is called a conductor film.

[0240] In a-like OS films, porosity (also called voids) is observed in high-resolution TEM images. In some cases, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions and regions where the crystalline portion cannot be observed. The a-like OS film is Crystallization occurs and crystalline growth is observed even with minute electron irradiation, such as that seen by TEM. This can sometimes occur. On the other hand, with a high-quality nc-OS film, even trace amounts of electricity, such as those observed by TEM, are not detected. Crystallization due to subirradiation is hardly observed.

[0241] Furthermore, the size of the crystalline portion of a-like OS films and nc-OS films was measured using high-resolution T This can be done using EM imaging. For example, the crystal of InGaZnO4 has a layered structure, The unit cell of the InGaZnO4 crystal has two Ga-Zn-O layers between the In-O layers. It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. It has a structure that is layered in a staggered manner. Therefore, the spacing between these adjacent layers is the (009) plane. It is approximately the same as the lattice plane spacing (also called the d-value), and its value, as determined by crystal structure analysis, is 0.29 nm. Therefore, we are focusing on the grid lines in high-resolution TEM images, and the spacing of the grid lines. In areas where the wavelength is between 0.28 nm and 0.30 nm, each lattice fringe is InG This corresponds to the ab-plane of the aZnO4 crystal.

[0242] Furthermore, oxide semiconductor films may have different densities depending on their structure. For example, a certain oxide semiconductor If the composition of the body membrane is known, then by comparing it with the density of a single crystal with the same composition, The structure of the oxide semiconductor film can be estimated. For example, with respect to the density of a single crystal, a- The density of the OS film is between 78.6% and 92.3%. Also, for example, single crystal Compared to the density of the nc-OS film and the CAAC-OS film, the density of the nc-OS film is 92.3% or higher. It will be less than 0%. Furthermore, an oxide semiconductor film with a density of less than 78% of the density of a single crystal is... The process of forming the film itself is difficult.

[0243] The above will be explained using a concrete example. For example, In:Ga:Zn=1:1:1[atom In an oxide semiconductor film satisfying the [number ratio], a single crystal InGaZnO4 having a rhombohedral structure. The density is 6.357 g / cm³ 3 Therefore, for example, In:Ga:Zn=1:1:1 In an oxide semiconductor film satisfying the [atomic ratio], the density of the a-like OS film is 5.0 g. / cm 3 More than 5.9g / cm 3 It becomes less than. Also, for example, In:Ga:Zn=1:1: In an oxide semiconductor film satisfying 1 [atomic ratio], the density of the nc-OS film and CAAC- The density of the OS film is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than.

[0244] Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, it is possible to calculate the density corresponding to a single crystal with a desired composition. Yes, it is possible. The density of a single crystal of the desired composition depends on the ratio of single crystals with different compositions combined. The density can be calculated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate by combining the two factors.

[0245] Furthermore, oxide semiconductor films include, for example, amorphous oxide semiconductor films, a-like OS films, and microcrystalline films. The film may be a multilayer film having two or more types of crystalline oxide semiconductor films and CAAC-OS films.

[0246] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0247] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0248] The semiconductor layer 402A has a channel formation region for the transistor 101.

[0249] The semiconductor layer 402B has a channel formation region for transistor 102.

[0250] The semiconductor layer 402C has a channel formation region for transistor 103.

[0251] The semiconductor layer 402D has a channel formation region for transistor 104.

[0252] Note that the area of ​​semiconductor layer 402A is equal to the area of ​​semiconductor layer 402B, semiconductor layer 402C and semiconductor layer 4 It is larger than the area of ​​02D. Also, the area of ​​semiconductor layer 402B is larger than that of semiconductor layer 402C and semi It is larger than the area of ​​the conductor layer 402D.

[0253] The semiconductor layer 402A is provided on the inside of the edge of the conductive layer 401A. B is provided on the inside of the edge of the conductive layer 401B. The semiconductor layer 402C is located on the conductive layer 401C It is provided on the inside of the end of the semiconductor layer 402D. The semiconductor layer 402D is provided on the inside of the end of the conductive layer 401D. This eliminates the step difference between semiconductor layers 402A and 402D, thereby suppressing the occurrence of defects. It is possible.

[0254] The conductive layers 403A to 403I are the same layer. Alternatively, the conductive layers 403A to 403I are the same. The material is present. Alternatively, the conductive layers 403A to 403I are formed through a process of processing the same conductive film. It was formed by [this method].

[0255] The conductive layers 403A to 403I may be materials applicable to the conductive layers 401A to 401D or The appropriate structure can be selected from among the available options.

[0256] The conductive layer 403A is a region that will become either the source electrode or the drain electrode of the transistor 101. It has the following characteristics. Also, the conductive layer 403A is connected to the semiconductor layer 402A. Alternatively, conductive Layer 403A has a region that is in contact with semiconductor layer 402A. Furthermore, conductive layer 403A is insulating It is connected to the conductive layer 401D via the contact holes in layer 404. Alternatively, conductive layer 40 3A has a region that is in contact with the conductive layer 401D. Furthermore, the conductive layer 403A has multiple regions 4 It has 03A1. Each of the multiple regions 403A1 has a long length along approximately the Y direction, and half It overlaps with the conductive layer 401A via the conductive layer 402A. Also, the conductive layer 403A is in region 403 Region 403A2 has an elongated length substantially along the X direction, and includes a semiconductor layer 402A and a conductive layer. It does not overlap with the 401A electrode.

[0257] The conductive layer 403B is the region that will be the source electrode or the other drain electrode of the transistor 101. It has a region that will become the first electrode of the capacitive element 105 and a region that will become the wiring 113. Alternatively, the conductive layer 403B is connected to the semiconductor layer 402A. , it has a region in contact with the semiconductor layer 402A. Furthermore, the conductive layer 403B has multiple regions 403 It has B1. Multiple regions 403B1 have elongated lengths along approximately the Y direction, and semiconductor layer 402A It overlaps with the conductive layer 401A via this. The conductive layer 403B also has region 403B2. Region 403B2 has a long length approximately along the X direction and is connected to the conductive layer 40 without passing through the semiconductor layer 402A. It overlaps with 1A. Furthermore, the conductive layer 403B has openings 403B3 and 403B4. The openings 403B3 and 403B4 have elongated sections that are substantially aligned in the Y direction.

[0258] The conductive layer 403C is a region that will become either the source electrode or the drain electrode of the transistor 102. It has a region that becomes wiring 113. Furthermore, the conductive layer 403C has a semiconductor layer 402B and They are connected. Alternatively, the conductive layer 403C has a region that is in contact with the semiconductor layer 402B. Furthermore, the conductive layer 403C has multiple regions 403C1. The multiple regions 403C1 are, It has a long length along the Y direction and overlaps with the conductive layer 401B via the semiconductor layer 402B. The electrode layer 403C has a region 403C2. Region 403C2 has an elongated length that is approximately along the X direction. Furthermore, it does not overlap with the semiconductor layer 402B and the conductive layer 401B.

[0259] The conductive layer 403D is the region that will be the source electrode or the other drain electrode of the transistor 102. It has a region that becomes the first electrode of the capacitive element 106. The conductive layer 403D is semi It is connected to the conductive layer 402B. Alternatively, the conductive layer 403D is in contact with the semiconductor layer 402B. It has a region that conducts through the contact holes of the insulating layer 404. It is connected to the conductive layer 401A. Alternatively, the conductive layer 403D has a region that is in contact with the conductive layer 401A. It has. Furthermore, the conductive layer 403D has multiple regions 403D1. Multiple regions 403D 1 has a long length approximately along the Y direction and overlaps with the conductive layer 401B via the semiconductor layer 402B. Furthermore, the conductive layer 403D has a region 403D2. Region 403D2 is approximately aligned in the X direction. It has a long length and overlaps with the conductive layer 401B without the semiconductor layer 402B in between. Also, conductive layer 403 D has an opening 403D3. The opening 403D3 has an elongated length that is approximately aligned with the Y direction.

[0260] The conductive layer 403E is a region that will become either the source electrode or the drain electrode of the transistor 103. It has. Also, the conductive layer 403E is connected to the semiconductor layer 402C. Alternatively, conductive layer 4 03E has a region that is in contact with the semiconductor layer 402C. Also, the conductive layer 403E is connected to the conductive layer 4 It is connected to 01C and the insulating layer 404 via a contact hole. Alternatively, it is connected to the conductive layer 403E. It has a region that is in contact with the conductive layer 401C.

[0261] The conductive layer 403F is the region that will be the source electrode or the other drain electrode of the transistor 103. It has a region that is the other of the source electrode or drain electrode of transistor 104. Furthermore, the conductive layer 403F is connected to the semiconductor layer 402C and to the semiconductor layer 402D. Alternatively, the conductive layer 403F has a region in contact with the semiconductor layer 402C and a region in contact with the semiconductor layer 402D. It has a region that does so. Furthermore, the conductive layer 403F is connected to the contact holes of the insulating layer 404. The conductive layer 403F is then connected to the conductive layer 401B. Alternatively, the conductive layer 403F is in contact with the conductive layer 401B. It has a domain.

[0262] The conductive layer 403G has a region that will become the wiring 111. Also, the conductive layer 403G has an insulating layer 4 It is connected to conductive layer 401D via contact hole 04. Alternatively, conductive layer 403G It has a region that is in contact with the conductive layer 401D.

[0263] The conductive layer 403H has a region that will become the wiring 114. Also, the conductive layer 403H has an insulating layer 4 It is connected to conductive layer 401C via contact hole 04. Alternatively, conductive layer 403H It has a region that is in contact with the conductive layer 401C.

[0264] The conductive layer 403I has a region that will become wiring 115 and a source electrode or drain of transistor 104. It has a region that forms one of the in electrodes. Furthermore, the conductive layer 403I is connected to the semiconductor layer 402D. Alternatively, the conductive layer 403I has a region that is in contact with the semiconductor layer 402D.

[0265] Furthermore, the area of ​​opening 403B3 is larger than the area of ​​opening 401A1, and opening 403B The area of ​​4 is larger than the area of ​​opening 401A2. Also, opening 401A1 is larger than opening 40 It is located inside 3B3, and the opening 401A2 is located inside the opening 403B4. This eliminates the step in the conductive layer 403B caused by the conductive layer 401A, thereby preventing defects. It can be suppressed.

[0266] Furthermore, the area of ​​opening 403D3 is larger than the area of ​​opening 401B1. 404A1 is located inside the opening 403D3. This allows the conductive layer 401B to be formed. This eliminates the step in the conductive layer 403D caused by the above, thereby suppressing the occurrence of defects.

[0267] Furthermore, region 403A2 of the conductive layer 403A overlaps with the conductive layer 401A and the semiconductor layer 402A. In contrast, region 403B2 of the conductive layer 403B bypasses the semiconductor layer 402A. It overlaps with 01A. However, region 403B2 of the conductive layer 403B is via semiconductor layer 402A. It may overlap with conductive layer 401A. Also, the surface where conductive layer 403A and conductive layer 401A overlap. The product is smaller than the overlapping area of ​​conductive layer 403B and conductive layer 401A. As a result, conductivity The parasitic capacitance between layer 403A and conductive layer 401A is reduced, and the conductive layer 403B and conductive The parasitic capacitance with layer 401A can be increased. Therefore, the potential of wiring 111 can be increased. To reduce the influence of the zistor 101 on the gate and to reduce the capacitance value of the capacitive element 105 This makes it possible to reduce the layout area.

[0268] Furthermore, region 403C2 of the conductive layer 403C overlaps with the conductive layer 401B and the semiconductor layer 402B. In contrast, region 403D2 of the conductive layer 403D bypasses the semiconductor layer 402B. It overlaps with 01B. However, region 403D2 of the conductive layer 403D is via semiconductor layer 402B. It may overlap with conductive layer 401B. Also, the surface where conductive layer 403C and conductive layer 401B overlap. The product is smaller than the overlapping area of ​​conductive layer 403D and conductive layer 401B. As a result, conductivity The parasitic capacitance between layer 403C and conductive layer 401B is reduced, and the conductive layer 403D and conductive The parasitic capacitance with layer 401B can be increased. Therefore, the potential of wiring 113 can be increased. To reduce the influence of the zistor 102 on the gate and to reduce the capacitance value of the capacitive element 106 This makes it possible to reduce the layout area.

[0269] Furthermore, conductive layers 401A to 401D, semiconductor layers 402A to 402D, conductive layer 403A There are no major restrictions on the material of the substrate on which the 403I and insulating layer 404 are formed, however At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. For example, glass substrate Plates, ceramic substrates, quartz substrates, sapphire substrates, etc., may be used as substrates. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, and silicon carbide are made from silicon and silicon carbide. It is also possible to apply compound semiconductor substrates such as germanium, SOI substrates, etc. A substrate on which semiconductor elements are provided may be used as the substrate. When using a glass substrate, the 6th generation (1500mm x 1850mm), the 7th generation (1 870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2 Large-area bases such as 400mm x 2800mm, 10th generation (2950mm x 3400mm), etc. By using plates, large-scale display devices can be manufactured.

[0270] Furthermore, even if a flexible substrate is used as the substrate and transistors are formed directly on the flexible substrate, That's fine. Alternatively, a release layer may be provided between the substrate and the transistor. The release layer is half a layer on top of it. After completing a conductive device, either partially or entirely, it is used to separate it from the circuit board and transfer it to another circuit board. It is possible to do so. In that case, transistors can be transferred to substrates with poor heat resistance or flexible substrates. Cut.

[0271] For example, in this specification, it is possible to form transistors using various substrates. It will come. The type of circuit board is not limited to a specific one. One example of such a circuit board is a semi-circular one. Conductive substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foil Substrates containing tungsten, tungsten substrates, substrates containing tungsten foil, flexible substrates, adhesive Examples include laminated films, paper containing fibrous materials, or base films. One example is a glass substrate. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples include glass. Flexible substrates, laminated films, and base films are examples of such materials. The following are examples: For example, polyethylene terephthalate (PET), polyethylene Lennaphthalate (PEN), polyethersulfone (PES), polytetrafluoro There are plastics such as ethylene (PTFE). Or, as an example, acrylic Examples include synthetic resins such as polypropylene, polyester, and porcelain. Examples include refractory vinyl or polyvinyl chloride. Alternatively, polyester is one example. Polyamide, polyimide, aramid, epoxy, inorganic vapor-deposited film, or paper, etc. In particular, transistors are manufactured using semiconductor substrates, single-crystal substrates, or SOI substrates. By doing so, variations in characteristics, size, or shape are reduced, and current capacity is high. It is possible to manufacture transistors with small size. By configuring the circuit, it is possible to reduce the power consumption of the circuit or increase its integration.

[0272] Furthermore, a flexible substrate is used as the substrate, and transistors are formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After partially or completely completing a semiconductor device, it is separated from the circuit board and transferred to another circuit board. It can be used in this way. In this case, the transistor can be used on substrates with poor heat resistance or flexible substrates. It can be mounted. Furthermore, the aforementioned release layer may include, for example, an inorganic tungsten film and a silicon oxide film. This method utilizes a layered film structure or a configuration in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0273] In other words, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates on which the transistor is transposed. Examples include, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or (This includes regenerated fibers (acetate, cupro, rayon, recycled polyester, etc.), leather These include leather substrates and rubber substrates. By using these substrates, good characteristics can be achieved. Formation of zistas, formation of low-power transistors, manufacturing of durable devices, heat resistance It can be made lighter, thinner, or more compact.

[0274] Furthermore, this embodiment can be appropriately combined with the descriptions of other embodiments. Therefore, The contents described in this embodiment (or even just some of the contents) may differ from the contents described in that embodiment. The content (even partial content) and / or the description in one or more other embodiments. Applying, combining, or replacing content (even partial content) This is possible. Furthermore, the contents described in each embodiment refer to various aspects in each embodiment. This refers to content described using diagrams or content described using text in the specification. Furthermore, a diagram (even a part of it) described in one embodiment may be a different part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more figures. In another embodiment, the diagram (or even just a part of it) described above can be combined by Furthermore, many more figures can be constructed. This is also true in the following embodiments. That is the case.

[0275] (Embodiment 5) In this embodiment, a display module and electronic device having a semiconductor device according to one aspect of the present invention This will be explained using Figures 24 and 25.

[0276] The display module 8000 shown in Figure 24 consists of an upper cover 8001 and a lower cover 8002. In between, the touch panel 8004 is connected to the FPC8003, and the FPC8005 is connected to the touch panel 8004. Display panel 8006, backlight 8007, frame 8009, printed circuit board 8010 It has a battery 8011.

[0277] One embodiment of the present invention is a semiconductor device or display device used, for example, in a display panel 8006. It is possible.

[0278] The upper cover 8001 and the lower cover 8002 are the touch panel 8004 and the display panel 8 The shape and dimensions can be appropriately modified to match the size of 006.

[0279] The touch panel 8004 is a resistive or capacitive touch panel. It can be used superimposed on 006. Also, the opposing substrate (encapsulation substrate) of the display panel 8006. It is also possible to give the display panel 80 a touch panel function. It is also possible to install a light sensor in each of the 06 pixels to create an optical touch panel.

[0280] The backlight 8007 has a light source 8008. Note that in Figure 24, the backlight The example given is one in which light source 8008 is placed on 8007, but this is not the only example. In this configuration, a light source 8008 is placed at the edge of the backlight 8007, and a light diffuser plate is also used. This may also be done. Furthermore, when using self-emissive light-emitting elements such as organic EL elements, or reflective type In the case of panels, etc., a configuration without a backlight 8007 is also acceptable.

[0281] Frame 8009 provides protection for the display panel 8006, as well as the operation of the printed circuit board 8010. It has the function of an electromagnetic shield to block electromagnetic waves generated by [unclear]. The Mu8009 may also function as a heat sink.

[0282] Printed circuit board 8010 contains power supply circuits and signal outputs for video signals and clock signals. It has a processing circuit. The power supply that provides power to the power supply circuit may be an external commercial power supply. That's fine, or it could be powered by a separately provided battery 8011. Battery 8011 is, This can be omitted when using commercial power.

[0283] Furthermore, the display module 8000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may be provided as such.

[0284] Figures 25(A) to 25(G) show electronic devices. These electronic devices are enclosed in a housing. 9000, display unit 9001, speaker 9003, operation key 9005 (power switch, or (including operating switch), connection terminal 9006, sensor 9007 (force, displacement, position, velocity, acceleration) Speed, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field A device that measures electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation. It may have a microphone (including a 9008), etc.

[0285] The electronic devices shown in Figures 25(A) to 25(G) can have various functions. Example For example, a function to display various information (still images, videos, text images, etc.) on the display unit, touch Panel functions, calendar, date or time display functions, various software ( A function that controls processing by program, wireless communication function, and various functions using wireless communication. It has the ability to connect to a computer network, and to transmit various types of data using wireless communication. It has the function of receiving data, reading programs or data recorded on a recording medium and displaying them. It may have functions such as displaying information in the section. The functions that electronic devices can have are not limited to these, and they can have a variety of functions. Yes, it is possible. Also, although not shown in Figures 25(A) to 25(G), electronic devices have multiple The device may also be configured to have a numerical display unit. Furthermore, a camera or the like may be provided to the electronic device to capture still images. Shadow recording function, video recording function, and recording medium for captured images (external or built into the camera). It may also have functions such as saving to a storage device and displaying the captured image on a display unit.

[0286] Details of the electronic equipment shown in Figures 25(A) to 25(G) will be explained below.

[0287] Figure 25(A) is a perspective view showing the personal digital assistant 9100. The display unit 9001 is flexible. Therefore, it conforms to the curved surface of the curved housing 9000. It is possible to incorporate the display unit 9001. Furthermore, the display unit 9001 is a touch sensor. It is equipped with a mechanism that allows operation by touching the screen with a finger or stylus. For example, display You can launch the application by touching the icon displayed in section 9001. Cut.

[0288] Figure 25(B) is a perspective view showing the personal digital assistant (PDA) 9101. The PDA 9101 is a personal digital assistant (PDA). For example, it has one or more functions selected from a telephone, a notebook, or an information viewing device. In terms of functionality, it can be used as a smartphone. Note that the mobile information terminal 9101 is a smartphone. The speaker 9003, connection terminal 9006, sensor 9007, etc. are omitted from the diagram, but Figure 2 It can be installed in the same position as the portable information terminal 9100 shown in 5(A). The information terminal 9101 can display text and image information on multiple sides. For example, 3 Two operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 9001 It can be displayed on one side. Also, the information 9051 shown by the dashed rectangle is displayed on the display unit 900. It can be displayed on other sides of 1. For example, information 9051 can be sent via email or A display that notifies you of incoming calls from social networking services (SNS) or phone calls. Subject of emails and social media posts, sender's name, date, time, and timestamp. This includes things like remaining battery power and antenna reception strength. Or, information 9051 is displayed. Instead of displaying information 9051, you may also display operation button 9050 or the like.

[0289] Figure 25(C) is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is, The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where Report 9053 and Information 9054 are displayed on different sides. For example, mobile The user of the information terminal 9102 has the portable information terminal 9102 stored in the breast pocket of their clothing. Then you can check that display (information 9053 in this case). Specifically, the incoming call A position from which the caller's phone number or name can be observed from above the mobile information terminal 9102. The information is displayed on the device. The user can view the information without taking the portable information terminal 9102 out of their pocket. You can check and decide whether or not to answer the call.

[0290] Figure 25(D) is a perspective view showing the wristwatch-type personal information terminal 9200. Personal information terminal 9 200 includes mobile phone, email, document viewing and creation, music playback, and internet communication. It can run various applications such as computer games. The display surface of part 9001 is curved, and the display is made along the curved display surface. Yes, it is possible. Furthermore, the personal digital information terminal 9200 can perform standardized short-range wireless communication. This is possible. For example, by communicating with a wireless headset, hands It is also possible to make free calls. In addition, the mobile information terminal 9200 has a connection terminal 9006. Furthermore, it can directly exchange data with other information terminals via connectors. Charging can also be performed via connection terminal 9006. Note that the charging operation is performed via connection terminal 9006. This may also be done by wireless power transfer without the need for an intermediary.

[0291] Figure 25(E),(F),(G) is a perspective view showing a foldable portable information terminal 9201. Furthermore, Figure 25(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and Figure 25( F) The mobile information terminal 9201 changes from one state to the other, either unfolded or folded. This is a perspective view of the process, with Figure 25(G) showing the folded state of the mobile information terminal 9201. This is a perspective view. The 9201 personal digital information terminal offers excellent portability when folded, and when unfolded... In this state, the seamless, wide display area provides excellent readability. (Portable Information Terminal 920) The display unit 9001 of unit 1 is connected to three housings 9000 by a hinge 9055. It is supported by bending the two housings 9000 via the hinge 9055. The ability to reversibly transform the mobile information terminal 9201 from an unfolded state to a folded state. This is possible. For example, the mobile information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It is possible.

[0292] The electronic device described in this embodiment has a display unit for displaying some kind of information. The present invention is characterized by the following: However, one embodiment of the present invention is an electronic device that does not have a display unit. It can also be applied to the display unit of the electronic device described in this embodiment. In other words, a configuration that is flexible and can display along a curved display surface, or a folding While examples of foldable display unit configurations have been given, the system is not limited to these, and may also include non-flexible, planar displays. The display may also be configured to appear in the section.

[0293] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can. [Explanation of Symbols]

[0294] CK1 signal CK2 signal CK3 signal ND1 Node ND2 node ND3 node OUT signal SP signal T0 period T1 period T2 period T3 period T4 period 100 circuits 101 Transistors 102 transistors 103 Transistors 104 transistors 105 Capacitive element 106 Capacitive elements 107 transistors 108 transistors 109 transistors 110 transistors 101pF transistor 102pF transistor 103pF transistor 104pF transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 115B Wiring 115C wiring 116 Wiring 117 Wiring 121 transistors 122 transistors 123 Transistors 124 transistors 200 circuits 201 Circuit 211 Wiring 212 Wiring 213 Wiring 214 Wiring 215 Wiring 216 Wiring 301 pixel section 302 Scan line drive circuit 303 Signal Line Drive Circuit 304 Circuit 310 pixels 401A conductive layer 401A1 opening 401A2 opening 401B Conductive layer 401B1 opening 401C conductive layer 401D conductive layer 402A Semiconductor layer 402B semiconductor layer 402C semiconductor layer 402D semiconductor layer 403A conductive layer 403A1 area 403A2 area 403B Conductive layer 403B1 area 403B2 area 403B3 opening 403B4 opening 403C conductive layer 403C1 area 403C2 area 403D conductive layer 403D1 area 403D2 area 403D3 opening 403E conductive layer 403F conductive layer 403G conductive layer 403H conductive layer 403I conductive layer 404 Insulating layer 404A1 opening 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 cabinets 9001 Display section 9003 Speaker 9005 Operation Keys 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation Buttons 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Mobile Information Terminal 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal

Claims

1. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in conductivity with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. A semiconductor device having a third conductive layer that functions as either the source electrode or the drain electrode of the first transistor, and having a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor.

2. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. A semiconductor device in which the first conductive layer is provided in the entire region between the first opening and the semiconductor layer in a plan view.

3. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. A semiconductor device in which, in a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer.

4. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. A semiconductor device in which, in a plan view, the first aperture has a longitudinal direction along the first direction, and the channel width direction of the fourth transistor is along the first direction.

5. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. A semiconductor device in which, in a plan view, the second aperture has a longitudinal direction along the first direction, and the channel length direction of the third transistor is along the first direction.

6. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the first conductive layer is provided in the entire region between the first opening and the semiconductor layer. A semiconductor device in which, in a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer.

7. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the first conductive layer is provided in the entire region between the first opening and the semiconductor layer. A semiconductor device in which, in a plan view, the first aperture has a longitudinal direction along the first direction, and the channel width direction of the fourth transistor is along the first direction.

8. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the first conductive layer is provided in the entire region between the first opening and the semiconductor layer. A semiconductor device in which, in a plan view, the second aperture has a longitudinal direction along the first direction, and the channel length direction of the third transistor is along the first direction.

9. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer. A semiconductor device in which, in a plan view, the first aperture has a longitudinal direction along the first direction, and the channel width direction of the fourth transistor is along the first direction.

10. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer. A semiconductor device in which, in a plan view, the second aperture has a longitudinal direction along the first direction, and the channel length direction of the third transistor is along the first direction.

11. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the first conductive layer is provided in the entire region between the first opening and the semiconductor layer. In a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer. A semiconductor device in which, in a plan view, the first aperture has a longitudinal direction along the first direction, and the channel width direction of the fourth transistor is along the first direction.

12. Having first to fourth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate electrode of the first transistor. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in conductivity with the signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the power line. The first conductive layer, which functions as the gate electrode of the first transistor, has a first opening, The second conductive layer, which functions as the gate electrode of the second transistor, has a second opening. The third conductive layer, which functions as either the source electrode or the drain electrode of the first transistor, has a region that overlaps with the first conductive layer in a region that does not overlap with the semiconductor layer that functions as the channel formation region of the first transistor. In a plan view, the first conductive layer is provided in the entire region between the first opening and the semiconductor layer. In a plan view, the area in which the third conductive layer overlaps with the first conductive layer is greater than the area in which the fourth conductive layer, which functions as the other of the source electrode or drain electrode of the first transistor, overlaps with the first conductive layer. A semiconductor device in which, in a plan view, the second aperture has a longitudinal direction along the first direction, and the channel length direction of the third transistor is along the first direction.

13. In any one of claims 1 to 12, The gate electrode of the third transistor is a semiconductor device electrically connected to the signal line.

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