Clock distribution with clock offset
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- TESLA INC
- Filing Date
- 2023-08-16
- Publication Date
- 2026-08-05
Smart Images
Figure 0007901241000001 
Figure 0007901241000002 
Figure 0007901241000003
Abstract
Description
Technical Field
[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 373,024, filed on August 19, 2022, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
[0002] This disclosure generally relates to clock distribution for electronic circuits, as well as related systems and methods.
Background Art
[0003] High - density processing systems can be constructed using an array of processing nodes. The nodes can communicate with neighboring nodes to execute processing tasks. Communication between nodes can use synchronous and / or asynchronous methods. A clock signal can be provided to each node so that the nodes can be synchronized, which can enable communication between the nodes.
Summary of the Invention
Means for Solving the Problems
[0004] The technical innovations described in the claims each have several aspects, and no single one of them alone bears the desirable attributes. Without limiting the claims, some prominent features of this disclosure are briefly described here.
[0005] In one embodiment, an integrated circuit is provided having a clock distribution network for a computing node array, the integrated circuit comprising a node array including a plurality of nodes, wherein the plurality of nodes include a first node and a second node adjacent to the first node, the first node including a clock distribution circuit configuration configured to receive a clock signal, provide a clock signal to the computing circuit configuration of the first node, and provide a clock signal to the second node, wherein the clock signal is provided to the second node with a delay unit relative to the first node.
[0006] In a particular embodiment, the first node is configured to receive clock signals from two upstream nodes and to provide clock signals with delay units to two downstream nodes.
[0007] In certain embodiments, the nodes are arranged in rows and columns, and the node array is configured to propagate a clock signal through the node array such that nodes along the diagonal of the node array have substantially the same timing delay with respect to the clock signal.
[0008] In certain embodiments, the first node includes a first input clock wiring configured to receive a clock signal from a first upstream node, a second input clock wiring configured to receive a clock signal from a second upstream node, a first output clock wiring configured to provide a clock signal with a delay unit to a first downstream node, and a second output clock wiring configured to provide a clock signal with a delay unit to a second downstream node.
[0009] In a particular embodiment, the first node further comprises a first inverter coupled between a first input clock wiring and a computing circuit configuration, the first inventor also coupled a first inverter between a second input clock wiring and a computing circuit configuration, a second inverter, and a third inverter, the second and third inventors coupled between a first input clock wiring and a first output clock wiring, the second and third inverters also coupled between a second input clock wiring and a first output clock wiring.
[0010] In a particular embodiment, the first upstream node is located north of the first node, the second upstream node is located west of the first node, the first downstream node is located east of the first node, and the second downstream node is located south of the first node.
[0011] In certain embodiments, the node array includes multiple compute nodes and multiple global nodes.
[0012] In certain embodiments, the integrated circuit further comprises a clock management circuit including a clock generation circuit configured to receive a system clock signal and generate a function clock signal; a first multiplexer configured to receive a function clock signal and an alternate clock signal and to selectively output one of the function clock signal and the alternate clock signal; and a second multiplexer configured to receive the output from the first multiplexer and a test clock signal and to output one of the output from the first multiplexer and the test clock signal to the root node of the node array.
[0013] In certain embodiments, the integrated circuit further includes a multiplexer configured to receive a functional clock signal and a test clock signal from a clock generation circuit and output one of the functional clock signal and the test clock signal as a clock signal to the root node of the node array.
[0014] In certain embodiments, the node array has a strapped H-tree clock distribution topology.
[0015] In another embodiment, a node array having a mesochronous clock distribution is provided, comprising a plurality of nodes arranged in rows and columns, wherein the node array includes a root node at a corner of the node array, and the root node is configured to receive a clock signal from outside the node array, provide the clock signal with delay units to a first neighbor node in the same column of the node array, and provide the clock signal with delay units to a second neighbor node in the same row of the node array, and nodes along the diagonals of the node array receive the clock signal with the same number of unit clock delays.
[0016] In certain embodiments, the root node includes a computing circuit configuration, and the root node is further configured to provide a clock signal to the computing circuit configuration.
[0017] In a particular embodiment, the plurality of nodes include a first node configured to receive clock signals from two upstream nodes and to provide clock signals to two downstream nodes with a unit clock delay of one.
[0018] In a particular embodiment, the plurality of nodes include a first node which includes a first input clock wiring configured to receive a clock signal from a first upstream node, a second input clock wiring configured to receive a clock signal from a second upstream node, a first output clock wiring configured to provide a clock signal to a first downstream node, and a second output clock wiring configured to provide a clock signal to a second downstream node.
[0019] In certain embodiments, the first node further comprises a first inverter coupled between a first input wiring and the computing circuit configuration of the first node, and the first inventor is also coupled between a second input wiring and the computing circuit configuration.
[0020] In a particular embodiment, the first upstream node is located north of the first node, the second upstream node is located west of the first node, the first downstream node is located east of the first node, and the second downstream node is located south of the first node.
[0021] In certain embodiments, the node array further includes a multiplexer configured to receive a functional clock signal and a test clock from a clock generation circuit and output one of the functional clock signal and the test clock as a clock signal to the root node.
[0022] In certain embodiments, the node array has a strapped H-tree clock distribution topology.
[0023] In yet another embodiment, a method for clock distribution in a node array is provided, which includes receiving a clock signal at a first node of the node array, providing the clock signal to a computing circuit configuration of the first node, and providing the clock signal to neighboring nodes of the node array such that the neighboring nodes are in contact with the first node and the clock signal has a delay unit at the neighboring node with respect to the first node.
[0024] In a particular embodiment, the method further includes, at a first node, receiving a clock signal from two upstream nodes with a delay unit to the two upstream nodes, wherein one of the two upstream nodes is in the same row of the node array as the first node and the other of the two upstream nodes is in the same column of the node array as the first node, and providing the clock signal to the two downstream nodes with a delay unit to the first node.
[0025] For purposes of summarizing the present disclosure, certain aspects of the innovation, advantages, and novel features are described herein. It should be understood that not all such advantages may necessarily be achieved in accordance with any particular embodiment. Thus, the innovation may be embodied or implemented to achieve or optimize one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.
Brief Description of the Drawings
[0026] [Figure 1] FIG. 1 is a schematic block diagram of an exemplary chip according to an aspect of the present disclosure.
[0027] [Figure 2A] FIG. 2 is a schematic diagram of a clock distribution network according to one embodiment.
[0028] [Figure 2B] FIG. 3 is a schematic diagram of a clock management unit (CMU) according to an aspect of the present disclosure.
[0029] [Figure 2C] FIG. 4A shows an exemplary implementation of a clock distribution circuit configuration within an exemplary node of the node array of FIG. 2A.
[0030] [Figure 2D] FIG. 4B shows an alternative exemplary implementation of a clock distribution circuit configuration within an exemplary node of the node array of FIG. 2A.
[0031] [Figure 3] FIG. � is a node clock level map associated with an exemplary node array such as the node array of FIG. 2A.
[0032] [Figure 4A]This is a schematic diagram of a clock distribution network having a node array having a 2D distributed, strapped H-tree clock distribution topology according to one embodiment of the present disclosure.
[0033] [Figure 4B] Figure 2A shows an example implementation of a clock distribution circuit configuration within an exemplary node in the node array.
[0034] [Figure 4C] This figure shows the node array of Figure 4A rearranged to illustrate the strapped H-tree topology of the node array. [Modes for carrying out the invention]
[0035] The following descriptions of some embodiments present various descriptions of a particular embodiment. However, the innovations described herein can be embodied in numerous different ways, for example, as defined and encompassed by the claims. In this description, similar reference numbers refer to drawings where identical or functionally similar elements may be shown. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements and / or subsets of elements shown in the drawings than those shown. In addition, in some embodiments, any suitable combination of features from two or more drawings can be integrated.
[0036] This disclosure provides a novel method for distributing a clock signal across a chip, enabling the modularization of the clock circuit configuration by assembling identical subpieces of the entire clock distribution circuit configuration. The clock distribution circuit configuration disclosed herein can save area, simplify the design, and reduce power consumption. Noise can be reduced compared to clock distribution of a synchronous clock signal. Embodiments disclosed herein can also significantly reduce supply rail noise in a specific frequency range, which can improve the electrical robustness of the chip and further reduce power dissipation.
[0037] Traditionally, clock signals are built and routed at the top level of the chip, which adds effort, area, and power costs to the design. In such cases, clock distribution is a custom design at the top level of the chip. One way to do this is to route the clock signal through channels between subblocks. This can divide the design and consume area. Another way is to push the top-level clock down to the subblocks. This can slow down the design process and cause forks in identical parts of the design, each with its own copy. Traditional methods can bring the clock signal to reach all receivers almost simultaneously. The circuit can then operate in lockstep.
[0038] In the clock distribution network disclosed herein, a clock arrives at various receivers at different times. The clock signal can be distributed through a two-dimensional (2D) array of nodes so that the clock signal arrives at different nodes with different timing offsets. For the clock distribution structure, the arrival times can be grouped into a curve or wave across the dies. At a local level, the circuit configurations of the nodes can operate in lockstep. More globally, the circuit configurations within different nodes of the node array can operate with timing offsets relative to each other. Peak current from the power grid can be reduced by having different nodes perform computing with timing offsets relative to each other. Such computing can also improve the quality of the power signal. The computing circuit configurations can be designed to handle the arrival time differences of the clock signal.
[0039] The clock distribution networks disclosed herein can simplify the design of the top level of the chip and the configuration of the clock circuitry. Clocking with a fixed offset may be referred to as mesochronous clocking. Embodiments disclosed herein enable mesochronous clock networks to be constructed modularly as instances of common subsection designs. The clock signals of such networks may be locally low-skew and mesochronous at a coarser level.
[0040] The clock distribution disclosed herein can be applied to any suitable chip. In a particular application, the clock distribution disclosed herein can be applied to a chip containing an array of smaller compute nodes, each of which may be referred to as a processor or core. In this way, the clock signal can form an arrival time wave across the array. Each compute node can receive a low-skew clock signal. The compute nodes in the array can be designed using only interfaces to neighboring compute nodes, taking into account the arrival time difference (skew) of the mesochronous clock phases. A chip having the clock distribution network disclosed herein may have, for example, a 35-phase mesochronous clock or a 41-phase mesochronous clock. The clock distribution described herein can be used in a square node array (equal rows and columns) or in a rectangular node array having a different number of rows than columns.
[0041] Figure 1 is a schematic block diagram of an exemplary chip 100 according to an aspect of the present disclosure. Chip 100 may be an integrated circuit die. Chip 100 may include a node array 102 (also referred to as a compute node array) with distribution clocking, one or more serializer / deserializer (SerDes) clock blocks 104, a clock generator 106, and a clock controller 108. The SerDes clock blocks 104 can interface with other chips 100 to form an array of chips 100. In certain application examples, the node array 102 may be included in a system-on-wafer system, an array of chips 100 on a printed circuit board, etc. In certain applications, the node array 102 of Figure 1 may be implemented on a system on a wafer that is packaged in a wafer-level packaging structure. As shown in the embodiment of Figure 1, the clock generator 106 may be implemented outside the node array 102. In some embodiments, the clock generator 106 may include a phase-locked loop (PLL). The clock generator 106 can be positioned to provide clock signals to the compute nodes located at the corners of the node array 102. The clock controller 108 can also be implemented outside the node array 102. Nodes within the node array 102 may include inter-node interfaces that can be configured to communicate synchronously. The core-serializer / deserializer (SerDes) interface may be asynchronous.
[0042] In the node array 102 with distribution clocking shown in Figure 1, each node may be an instance of a computing circuit (also referred to as a processing core or compute node). In certain applications, the majority of nodes may be implemented as instances of computing circuits, and one or more nodes may be implemented as instances of different circuits. Each node in the node array 102 may contain an instance of substantially the same clock distribution circuit configuration, even if at least some of the other circuit configurations of the node differ from those of the other nodes. In the node array 102, nodes can be tiled and touching. For example, each node in the node array 102 can be self-contained and interconnected with adjacent nodes. At the same time, the node array 102 can be implemented without using top-level wiring or gates. Thus, nodes can be configured to communicate with neighboring nodes using low-level wiring via short connections. In some embodiments, the nodes of the node array 102 can be stepped without mirroring or rotation. In certain implementation forms, nodes may be connected to power lines (V DD / V SS The nodes can be aligned to the grid pitch. For example, the height and width of each node can be a multiple of the power grid pitch. The power grid pitch can then be further aligned to the bump pitch.
[0043] Each node in node array 102 may include substantially the same instance of the clock distribution circuit configuration. Nodes can be designed so that their output clock wiring aligns with the input clock wiring of their neighboring nodes. Nodes can be arranged in a stepped and tiled configuration within the node array so that their clock output wiring aligns with and is electrically connected to the clock input wiring of neighboring nodes located downstream to receive the clock signal. Such electrical connections allow the node array to be implemented without channels or top-level wiring for clock distribution. In certain embodiments, the fan-out of the clock distribution circuit configuration can be balanced relative to the inverter.
[0044] As described herein, a clock signal received at a root node may propagate from the root node to two neighboring nodes with a delay unit. The root node may be located at a corner of the node array 102. The delay unit may be a fixed offset of a given node array. The delay unit may correspond to the delay from buffering the clock signal (e.g., using an inverter) and the wiring delay associated with the propagation of the clock signal to its neighboring nodes.
[0045] One of the two neighboring nodes may be located in the same row as the root node, and the other of the two neighboring nodes may be located in the same column as the root node. The neighboring nodes are adjacent to the root node. As an example, the neighboring nodes are located south and east of the root node in Figure 2A. In this example, the clock signal continues to propagate from the two neighboring nodes of the root node in the node array to the south and east neighboring nodes with one additional delay unit. Such clock signal propagation continues through the clock distribution network in node array 102 until the clock signal reaches a node in node array 102 at the opposite corner from the root node. In this example, a signal routed from the originating node that generates the signal to a neighboring node north or west of the originating node travels upstream and may lose one unit delay in node array 102, while a signal routed from the originating node to a neighboring node south or east travels downstream and may gain one unit delay in node array 102. A signal traveling upstream can be routed faster than a signal traveling downstream to account for the unit delay and meet the setup and hold time specifications.
[0046] Figure 2A is a schematic diagram of a clock distribution network 200 according to one embodiment. The clock distribution network 200 includes a clock management unit (CMU) 202 and a clock distribution circuit configuration of a node array 204 (also referred to as a clock distribution node array) of nodes 206. Each node 206 includes an instance of the clock distribution circuit configuration for clock distribution within the node array 204. In the embodiment of Figure 2A, the clock distribution network 200 has a 2D distributed, strapped H-tree topology. The CMU 202 is configured to output a clock signal, which is received by the root node 206 of the node array 204.
[0047] Figure 2B is a schematic diagram of a CMU 202 according to an embodiment of the present disclosure. The CMU 202 includes a PLL 212, a first multiplexer 214, and a second multiplexer 216. The PLL 212 is configured to receive a system clock signal sysclk and generate a function clock signal funcclk. The first multiplexer 214 is configured to receive the function clock signal funcclk at a first input and an alternate clock signal at a second input, and to selectively output one of the function clock signal funcclk and the alternate clock signal at the output of the first multiplexer 214. Depending on the embodiment, the alternate clock signal may include one or more of a bypass clock signal, a reference clock signal generated on-chip or off-chip 100, a split clock signal, or any other suitable clock signals. The second multiplexer 216 receives the clock output signal from the first multiplexer 214 at the first input and the test clock signal testclk at the second input, and is configured to selectively output either the clock output signal from the first multiplexer 214 or the test clock signal testclk at the output of the second multiplexer 216. Thus, the CMU 202 can be configured to selectively output one of the function clock signal funcclk, the test clock signal, or an alternate clock signal to the root node of the node array 204. The CMU 202 can provide clock signals to the clock distribution network 200 to operate and / or test the chip 100. For example, the CMU 202 can provide the test clock signal testclk to the clock distribution to test the chip 100. As another example, the CMU 202 can provide the function clock signal funcclk for typical operation of the chip 100.
[0048] Referring to Figure 2A, the root may be located at the input to node 206 at a corner of node array 204. For example, the root may be located at the input to node 206 at the northwest or upper left corner of node array 204 as shown in Figure 2A. In other embodiments, the root may be at the input to another corner node 206 of node array 204 when the clock signal propagates in different directions along the rows and / or columns of the nodes. A node 206 that receives the clock signal from outside node array 204 may be referred to as the root node 206.
[0049] Referring again to Figure 2A, the clock distribution network 200 can be implemented using a node array 204. The node array 204 shown in Figure 2A is an example of the node array 102 with distribution clocking in Figure 1. In certain embodiments, each node 206 may be an instance of computing circuitry. In certain applications, most of the nodes 206 may contain instances of computing circuitry, and one or more of the remaining nodes 206 may contain instances of different circuitry, such as a global node. A global node may refer to a node 206 that does not contain circuitry configuration for performing processing tasks. In some implementations, both computing nodes and global nodes may include a communication interface that enables communication with neighboring nodes 206. In some implementations, the communication interface for the computing nodes may be the same as the communication interface for the global nodes.
[0050] In certain embodiments, each node 206 in the node array 204 may include instances of the same clock distribution circuit configuration, even if one or more other circuit configurations of the node 206 differ from those of other nodes 206. In the node array 204, the nodes 206 can be tiled and abutted. Simultaneously, the node array 204 can be implemented without top-level wiring or gates. Thus, a node 206 can communicate with a neighboring node 206 using low-level wiring via short connections. The nodes 206 in the node array 204 can be stepped without mirroring or rotation. The nodes 206 can also be aligned to the grid pitch of the power (VDD / VSS) lines. For example, the height and width of each node 206 can be multiples of the power grid pitch. In some embodiments, the power grid pitch can be further aligned to the bump pitch.
[0051] As shown in Figure 2A, each node 206 may contain an instance of substantially the same clock distribution circuit configuration. Figure 2C shows an exemplary implementation of the clock distribution circuit configuration in an exemplary node 206 of the node array 204 in Figure 2A. Referring to Figures 2A and 2C, the clock distribution circuit configuration includes a first input clock wire 222, a second input clock wire 224, a first inverter 226, a second inverter 228, a third inverter 230, a fourth inverter 232, a clock tap point 234, a first output clock wire 236, and a second output clock wire 238.
[0052] The clock distribution circuit configuration for each node 206 is designed such that the output clock traces 236 and 238 of node 206 align with the input clock traces 222 and 224 of neighboring node 206. Node 206 can be stepped and tiled within the node array 204 so that its output clock traces 236 and 238 align with and are electrically connected to the two input clock traces 222 and 224 of neighboring node 206. These electrical connections allow the node array 204 to be implemented without using channels or top-level traces for clock distribution.
[0053] Returning to Figure 2C, input wires 222 and 224 can receive input clock signals from two of the neighboring nodes 206. For example, the first input clock wire 222 receives the input clock signal from a neighboring node 206 above the current node 206, while the second input clock wire 224 receives the input clock signal from a neighboring node 206 to the left of the current node 206. The first input clock wire 222 and the second input clock wire 224 provide the clock signals to the first inverter 226 and the second inverter 228. The first inverter 226 inverts the clock signal and provides the inverted clock signal to the clock tap point 234, which then provides the clock signal to the primary circuit configuration of the corresponding node in the compute node array 102 (e.g., the compute circuit or global circuit in a particular embodiment).
[0054] The second inverter 228 inverts the clock signal and provides the inverted clock signal to the third inverter 230 and the fourth inverter 232. Each of the third inverter 230 and the fourth inverter 232 inverts the inverted clock signal and outputs the resulting clock signal to the first output clock wire 236 and the second output clock wire 238. The first output clock wire 236 and the second output clock wire 238 output the clock signal to the neighboring nodes 206 to the right and below the current node 206.
[0055] Referring back to Figure 2A, the clock signal received at the root node 206 propagates from the root node 206 to its two neighboring nodes, one downstream and one to the right, with a delay unit of one. The delay unit can be a fixed offset across the entire node array 204. In some implementations, the delay unit may correspond to the delay from buffering the clock signal (e.g., via inverters 228-232), combined with the wiring delay associated with the clock signal propagating to the downstream neighboring nodes 206. In Figure 2A, one of the downstream neighboring nodes 206 is to the right in the same row as the root node 206, and the other downstream neighboring node 206 is below in the same column as the root node 206. In other words, the neighboring nodes 206 can be located south and east of the root node 206.
[0056] The clock signal continues to propagate, with an additional delay unit, to the neighboring node 206 to the south as the clock signal traverses the entire node array 204 in Figure 2A. Such clock signal propagation continues through the clock distribution network until the clock signal reaches node 206 in node array 204 at the opposite corner from the root node 206 (for example, the lower right corner of the figure).
[0057] As a clock signal propagates through the node array 204, a node 206 within the node array 204 can receive clock signals from two other neighboring nodes 206 with substantially the same delay. A recombinant mesh topology can combine two clock signals received from two neighboring nodes 206 at a given node 206 in the node array 204. For example, in Figure 2C, clock signals received via the first input clock wire 222 and the second input clock wire 224 can be combined and received at the first inverter 226 and the second inverter 228, respectively. In some embodiments, the clock signals are combined by directly connecting the first input clock wire 222 and the second input clock wire 224 together. Other implementations for providing a recombinant mesh topology are also possible.
[0058] The clock distribution circuit configuration disclosed herein enables a flexible array structure that supports a wide range of array designs. For example, node array 204 may be a square with substantially the same number of rows and columns. Alternatively, node array 204 may be a rectangle with substantially different numbers of rows and columns. The clock distribution circuit configuration disclosed herein also provides a relatively simple reconstruction of the array with respect to the clock, which can also allow for design decisions regarding node array shape at a relatively late schedule. In contrast, array size and shape with other clock distribution networks are typically costly decisions to postpone, due to the amount of clock design time involved. However, in certain cases, such late decisions may result in an optimization of the overall chip design and therefore may be desirable.
[0059] Figure 2D shows an alternative exemplary implementation of the clock distribution circuit configuration within exemplary node 206 of node array 204 in Figure 2A. Node 206 in Figure 2D is similar to node 206 shown in Figure 2C, except that the outputs of the third inverter 230 and the fourth inverter 232 are not coupled to each other. Thus, the third inverter 230 independently provides an output clock signal to the first output clock wiring 238, while the fourth inverter 232 independently provides an output clock signal to the second output clock wiring 236.
[0060] In summary, the clock distribution network 200 can be implemented such that each node 206 receives a clock signal from at least one neighbor node (or CMU 202 in the case of the root node 206), provides the clock signal to the corresponding node in the compute node array (e.g., via a clock tap point 234), and provides the clock signal to a neighbor clock distribution node 206 when it is located adjacent to a downstream clock distribution node 206. For example, in the case of a node 206 located adjacent to four neighbor nodes 206, node 206 can receive clock signals from two upstream clock distribution nodes and provide the clock signals to two downstream clock distribution nodes with a unit delay.
[0061] Figure 3 is a node clock level map associated with an exemplary node array, such as node array 204 in Figure 2A. The exemplary node array 204 has 18 rows and 18 columns. In 18 rows and 18 columns, there may be 324 nodes. As another example, node array 204 could include 360 nodes arranged in rows and columns. Node 206 of node array 204 may have a clock distribution circuit configuration corresponding to, for example, the clock distribution circuit configuration in Figure 2C or Figure 2D. This clock map shows the number of unit delays for the clock signal output for node 206 of node array 204. For example, the root node 206 has a unit delay of 1. Two neighboring nodes 206 of the root node 206 have a unit delay of 2. Nodes 206 on a diagonal from southwest to northeast may have the same unit delay. Using the clock distribution circuit configurations described herein, the unit delay can be a fixed offset. Nodes 206 along these diagonals can receive clock signals with substantially the same timing delay. These diagonals may be referred to as phases or waves. The phases correspond to different clock signal arrival times at node 206. The clock signal distribution corresponding to the map in Figure 3 can implement a 35-phase mesochronous clock. The number of phases of the mesochronous clock signal for a node array having the clock distribution circuit configuration described herein may be the number of rows + the number of columns - 1.
[0062] In certain embodiments, instead of the clock signal traversing the node array 204 in waves formed along the diagonals of the node array 204, the clock distribution network 200 may be configured to generate waves that traverse the node array 204 in the row or column direction. For example, each node 206 may output a clock signal either south or east, rather than outputting a clock signal south and east. In this way, the clock signal may propagate in waves moving south or east. However, aspects of the present disclosure are not limited to specific directions of movement for the clock signal, and the clock signal may propagate along other diagonals and / or north or west.
[0063] The offset in Figure 3 can be considered when routing signals between nodes 206. Signals routed from the originating node to a node located north or west will travel upstream and may lose one unit delay in the node array 204 corresponding to Figure 3. Signals routed from the originating node to a node located south or east will travel downstream and may gain one unit delay in the node array 204 corresponding to Figure 3. Signals traveling upstream can be routed faster than signals traveling downstream to account for the unit delay and meet the setup and hold time specifications.
[0064] Figure 4A is a schematic diagram of a clock distribution network 400 having a node array 404 having a 2D distributed, strapped H-tree clock distribution topology according to one embodiment of the present disclosure. Figure 4B shows an exemplary implementation of the clock distribution circuit configuration within an exemplary node 406 of the node array 404 of Figure 2A. Figure 4C shows the clock distribution circuit configuration of the node array 404 of Figure 4A rearranged to illustrate the strapped H-tree topology of the node array 404.
[0065] The clock distribution network 400 includes a CMU 402 and a node array 404. The CMU 402 includes a PLL 412 and a multiplexer 416. The PLL 412 is configured to receive a system clock signal and generate a function clock signal. The multiplexer 416 is configured to receive a function clock signal and a scan clock signal and to selectively provide one of the function clock signal and the scan clock signal to the root node 406 of the node array 404. The node array 404 includes a plurality of nodes 406. Each node 406 includes a first input clock wire 422, a second input clock wire 424, a first inverter 426, a second inverter 428, a clock tap point 434, a first output clock wire 438, and a second output clock wire 436, as shown in Figure 4B.
[0066] Input wires 422 and 424 can receive input clock signals from two of the neighboring nodes 406. For example, the first input clock wire 422 receives the input clock signal from a neighboring node 406 above the current node 406, while the second input clock wire 424 receives the input clock signal from a neighboring node 406 to the left of the current node 406. If node 406 is the root node, the clock signal is received from the CMU 402. The first input clock wires 422 and 424 provide the clock signal to the first inverter 426 and the second inverter 428. The first inverter 426 inverts the clock signal and provides the inverted clock signal to the clock tap point 434, which then provides the clock signal to the primary circuitry of node 406 (e.g., computing circuitry or global circuitry in a particular embodiment).
[0067] The second inverter 428 inverts the clock signal and provides the inverted clock signal to the first output clock wiring 436 and the second output clock wiring 438. The first output clock wiring 436 and the second output clock wiring 438 output the clock signal to the neighboring nodes 406 to the right and below the current node 406.
[0068] As shown in Figures 4A to 4C, each node 406 along the diagonal of node array 404 can receive a clock signal with the same number of unit delays in a 2D-distributed, strapped H-tree clock distribution network. For example, there are four nodes 406 along the diagonal of node array 404 that receive a clock signal from the clock root with a 3-unit delay. Another example is three nodes 406 along another diagonal of node array 404 that receive a clock signal from the root node 406 with a 4-unit delay. These diagonal nodes 406 can receive clock signals from two neighboring nodes 406 with the same number of unit delays and combine the two received clock signals 406.
[0069] The node arrays disclosed herein can be implemented in a variety of processing systems. Such processing systems can be used in and / or specifically configured for high-performance computing and / or computationally intensive applications such as neural network training, neural network inference, machine learning, artificial intelligence, and complex simulations. In some applications, the processing systems can be used to perform neural network training. For example, such neural network training can generate data for an autopilot system in a vehicle (e.g., an automobile), other autonomous vehicle functions, or advanced driver-assistance systems (ADAS) functions. conclusion
[0070] The foregoing disclosure is not intended to limit this disclosure to the exact form or specific field of use disclosed. Therefore, it is intended that various alternative embodiments and / or modifications to this disclosure are possible in light of this disclosure, whether expressly described or implied herein. While embodiments of this disclosure have been described in this manner, those skilled in the art will recognize that modifications in form and detail can be made without departing from the scope of this disclosure. Therefore, this disclosure is limited only by the claims.
[0071] In the above specification, the disclosure is described with reference to specific embodiments. However, as those skilled in the art will understand, the various embodiments disclosed herein can be modified or otherwise implemented in various other ways without departing from the spirit and scope of the disclosure. Therefore, this description should be considered illustrative and is intended to teach those skilled in the art how to make and use various embodiments of the disclosed ventilation assemblies. It should be understood that the forms of disclosure shown and described herein should be construed as representative embodiments. Equivalent elements, materials, processes, or steps may be substituted with those representatively shown and described herein. Furthermore, certain features of the disclosure can be utilized independently of the use of other features, so that all will become apparent to those skilled in the art after benefiting from this description of the disclosure. Expressions such as “includes,” “equips,” “incorporates,” “consists of,” “has,” and “is” used to describe and claim the disclosure are intended to be interpreted in a non-exclusive manner, that is, to allow for the existence of items, components, or elements not expressly described. References to the singular should also be construed as relating to the plural.
[0072] Furthermore, the various embodiments disclosed herein should be interpreted in an illustrative and descriptive sense and not in any way as limiting the disclosure. All references to connections (e.g., attached, fixed, coupled, connected, etc.) are used solely to aid the reader's understanding of the disclosure and do not imply any limitation with respect to the location, orientation, or use of the systems and / or methods disclosed herein. Accordingly, references to connections should be interpreted broadly, where present. Furthermore, such references to connections do not necessarily mean that the two elements are directly connected to each other. Furthermore, without limitation, all numerical terms such as “first,” “second,” “third,” “primary,” “secondary,” “main,” or any other ordinary and / or numerical terms should also be interpreted solely as identifiers to aid the reader's understanding of the various elements, embodiments, variations, and / or modifications of the disclosure and, in particular, do not imply any limitation with respect to the order or preference of any element, embodiment, variation, and / or modification of another element, embodiment, variation, and / or modification of another or beyond.
[0073] It should be understood that, depending on the specific application, one or more of the elements shown in the drawings / figures may also be implemented in a more separated or integrated manner, or in certain cases may be removed or rendered as non-functional.
Claims
1. An integrated circuit having a clock distribution network for a computing node array, A node array comprising a plurality of nodes, wherein the plurality of nodes include a first node and a second node that abuts the first node, The first node, Receiving a clock signal, The clock signal is provided to the computing circuit configuration of the first node via the first inverter, An integrated circuit comprising a clock distribution circuit configuration configured to provide the clock signal to the second node via a second inverter and a third inverter, wherein the clock signal is delayed at the second node by a delay unit relative to the first node, and the delay unit is introduced via the second inverter and the third inverter.
2. The first node, Receiving the clock signal from two upstream nodes, The integrated circuit according to claim 1, configured to provide the clock signal with the delay unit to two downstream nodes.
3. The aforementioned nodes are arranged in rows and columns, The integrated circuit according to claim 1, wherein the node array is configured to propagate the clock signal through the node array such that nodes along the diagonal of the node array have substantially the same timing delay with respect to the clock signal.
4. The first node, A first input clock wiring configured to receive the clock signal from a first upstream node, A second input clock wiring configured to receive the clock signal from a second upstream node, A first output clock wiring configured to provide the clock signal with the delay unit to a first downstream node, The integrated circuit according to claim 1, comprising: a second output clock wiring configured to provide the clock signal with the delay unit to a second downstream node.
5. The first inverter is coupled between the first input clock wiring and the computing circuit configuration, and the first inverter is also coupled between the second input clock wiring and the computing circuit configuration. The integrated circuit according to claim 4, wherein the second inverter and the third inverter are coupled between the first input clock wiring and the first output clock wiring, and the second inverter and the third inverter are also coupled between the second input clock wiring and the first output clock wiring.
6. The first upstream node is located north of the first node, The second upstream node is located west of the first node. The first downstream node is located east of the first node, The integrated circuit according to claim 4, wherein the second downstream node is located south of the first node.
7. The integrated circuit according to claim 1, wherein the node array includes a plurality of computing nodes and a plurality of global nodes.
8. An integrated circuit having a clock distribution network for a computing node array, A node array comprising a plurality of nodes, wherein the plurality of nodes include a first node and a second node that abuts the first node, The first node, Receiving a clock signal, The first node's computing circuit configuration is provided with the clock signal, The clock distribution circuit configuration includes providing the clock signal to the second node such that the clock signal is delayed by a delay unit at the second node relative to the first node, The aforementioned integrated circuit further comprises a clock management circuit, The aforementioned clock management circuit is A clock generation circuit configured to receive a system clock signal and generate a functional clock signal, A first multiplexer configured to receive the function clock signal and the alternate clock signal, and to selectively output one of the function clock signal and the alternate clock signal, An integrated circuit comprising: a second multiplexer configured to receive the output and test clock signal from the first multiplexer and to output one of the output and test clock signal from the first multiplexer to the root node of the node array.
9. The integrated circuit according to claim 1, further comprising a multiplexer configured to receive a functional clock signal and a test clock signal from a clock generation circuit, and to output one of the functional clock signal and the test clock signal as the clock signal to the root node of the node array.
10. The integrated circuit according to claim 1, wherein the node array has a strapped H-tree clock distribution topology.
11. A node array having mesochronous clock distribution, Includes a node array containing multiple nodes arranged in rows and columns, The node array includes a root node at a corner of the node array, The root node is configured to receive a clock signal from outside the node array, provide the clock signal with a delay unit to a first neighbor node in the same column of the node array, and provide the clock signal with a delay unit to a second neighbor node in the same row of the node array. The nodes along the diagonal of the node array receive the clock signal with the same number of unit clock delays. The plurality of nodes include a first node, and the first node is Receiving the aforementioned clock signal, The clock signal is provided to the computing circuit configuration of the first node via the first inverter, A node array configured to provide the clock signal to a second node via a second inverter and a third inverter, wherein the clock signal is delayed by a delay unit at the second node relative to the first node, and the delay unit is introduced via the second inverter and the third inverter.
12. The node array according to claim 11, wherein the root node includes a computing circuit configuration, and the root node is further configured to provide the clock signal to the computing circuit configuration.
13. The first node, Receiving the clock signal from two upstream nodes, The node array according to claim 11, further configured to provide the clock signal with the delay unit to two downstream nodes.
14. The first node, A first input clock wiring configured to receive the clock signal from a first upstream node, A second input clock wiring configured to receive the clock signal from a second upstream node, A first output clock wiring configured to provide the clock signal to the second node, The node array according to claim 11, further comprising a second output clock wiring configured to provide the clock signal to a third node.
15. The node array according to claim 14, wherein the first inverter is coupled between the first input wiring and the computing circuit configuration of the first node, and the first inverter is also coupled between the second input wiring and the computing circuit configuration.
16. The first upstream node is located north of the first node, The second upstream node is located west of the first node. The second node is located east of the first node, The node array according to claim 14, wherein the third node is located south of the first node.
17. The node array, The node array according to claim 11, further comprising a multiplexer configured to receive a functional clock signal and a test clock from a clock generation circuit, and to output one of the functional clock signal and the test clock as the clock signal to the root node.
18. The node array according to claim 11, wherein the node array has a strapped H-tree clock distribution topology.
19. A method for distributing clocks in a node array, The steps include receiving a clock signal at the first node of the node array, The steps include providing the clock signal to the computing circuit configuration of the first node via the first inverter, A step of providing the clock signal to neighboring nodes of the node array via a second inverter and a third inverter, wherein the neighboring node is in contact with the first node, the clock signal has a delay unit at the neighboring node with respect to the first node, and the delay unit is introduced via the second inverter and the third inverter. Methods that include...
20. The first node receives the clock signal from two upstream nodes with the delay unit, wherein one of the two upstream nodes is in the same row as the first node in the node array, and the other of the two upstream nodes is in the same column as the first node in the node array. The method according to claim 19, further comprising the step of providing the clock signal to two downstream nodes with the delay unit to the first node.
21. The node array further includes a third node that abuts the first node, The integrated circuit according to claim 1, wherein the clock distribution circuit configuration of the first node is further configured to provide the clock signal to the third node via the second inverter and the fourth inverter, the fourth inverter being arranged in parallel with the third inverter.