Magnetoresistive element and magnetic memory device

Abstract

To provide a magnetoresistance effect element consuming low power and enabling high-speed reading.SOLUTION: A magnetoresistance effect element 100 comprises: a reference layer 14, a barrier layer 13, a recording layer 12, and a channel layer 11 that are laminated; a first terminal T1 connected to the reference layer 14; and second and third terminals T2 and T3 connected to the channel layer 11. The channel layer 11 has a first channel layer 11A and a second channel layer 11B. An electric resistance RA of the first channel layer 11A is larger than an electric resistance RB of the second channel layer 11B. The second terminal T2 is connected to the first channel layer 11A, and the third terminal T3 is connected to the second channel layer 11B. A writing current flows between the second terminal T2 and the third terminal T3 via the first channel layer 11A and the second channel layer 11B. A reading current flows between the first terminal T1 and the third terminal T3 via the reference layer 14, the barrier layer 13, the recording layer 12, and the channel layer 11.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to a magnetoresistive element and a magnetic memory device. [Background technology]

[0002] Non-volatile memory devices (MRAM) utilizing magnetoresistive elements are attracting attention as next-generation logic integrated circuits. Among MRAMs, three-terminal SOT-MRAM (Spin Orbit Torque Magnetic Memory) is known to be suitable for non-volatile memory where high-speed writing is required. For example, Patent Document 1 discloses a three-terminal SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory) composed of a stack of a channel layer, a recording layer, a barrier layer, and a reference layer.

[0003] Figure 19 shows the basic configuration of the SOT-MRAM disclosed in Patent Document 1. As shown in the figure, the SOT-MRAM 1000 is composed of a stack of channel layer 1111, recording layer 1112, barrier layer 1113, and reference layer 1114, and has three terminals T11, T12, and T13.

[0004] The channel layer 1111 is a conductive layer composed of heavy metals, etc., and is a region that generates spin-start torque when a write current flows through it. The recording layer 1112 is composed of a magnetic material, and its magnetization M1112 is variable between the +X axis and the -X axis due to the spin-start torque generated by the writing current flowing through the channel layer 1111.

[0005] The barrier layer 1113 is a non-magnetic layer composed of a tunnel insulating layer.

[0006] The reference layer 1114 is made of a magnetic material, and the direction of its magnetization M1114 is fixed.

[0007] When writing data to the SOT-MRAM1000, a voltage corresponding to the data to be written is applied between terminals T12 and T13, and a write current flows through the channel layer 1111. This causes a spin-orbit torque to act, and the direction of the magnetization M1112 of the recording layer 1112 changes according to the direction of the write current.

[0008] When the magnetization M1112 of the recording layer 1112 and the magnetization M1114 of the reference layer 1114 are aligned (parallel state), the resistance between the reference layer 1114 and the recording layer 1112 becomes small. On the other hand, when the magnetization M1112 of the recording layer 1112 and the magnetization M1114 of the reference layer 1114 are aligned in opposite directions (antiparallel state), the resistance between the reference layer 1114 and the recording layer 1112 becomes relatively larger. Data is assigned to the changing resistance values.

[0009] When reading data from the SOT-MRAM1000, a read voltage is applied between terminals T11 and T12 or T13 (here, T13), and the read current I flows. R Outputs data corresponding to the size. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2018-157108 [Overview of the project] [Problems that the invention aims to solve]

[0011] The channel layer 1111 is made of a heavy metal that acts as a conductor. Therefore, when writing data, the write current flowing through the channel layer 1111 is large, resulting in high power consumption.

[0012] To reduce the write current, it is possible to increase the resistance of channel layer 1111. However, when reading, the read current I RSince it flows through a partial region of the channel layer 1111, increasing the resistance value of the channel layer 1111 causes the resistance component of the partial region to become the load resistance, resulting in a decrease in the read current. For this reason, the TMR ratio (tunnel magnetoresistance ratio) decreases and the read speed slows down. This problem becomes prominent as the integration degree of the SOT-MRAM increases.

[0013] Let the resistance from the reference layer 1114 to the recording layer 1112 in the parallel state be R P and the resistance from the reference layer 1114 to the recording layer 1112 in the antiparallel state be R AP Also, let the load resistance from the contact surface between the recording layer 1112 and the channel layer 11 to the terminal T13 be R L Then, the TMR ratio is expressed by the following equation. TMR = [(R AP + R L ) - (R P + R L )] / (R P + R L ) = (R AP - R P ) / (R P + R L )

[0014] As is clear from this equation, as the load resistance R L increases, the TMR ratio decreases. Also, as the TMR ratio decreases, the read time (the time required for reading) becomes longer. For this reason, a high-speed read operation becomes difficult.

[0015] The present invention has been made in view of the above circumstances, and an object thereof is to provide a magnetoresistive element capable of high-speed reading with low power consumption and a magnetic memory device using the same.

Means for Solving the Problems

[0016] To achieve the above object, the Regarding the first point of view magnetoresistive element of the present invention includes a stacked reference layer, barrier layer, recording layer, and channel layer, a first terminal connected to the reference layer, Ta and A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. Equipped with, The electrical resistance of the first channel layer is greater than the electrical resistance of the second channel layer. calligraphy The incoming current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current is between the first terminal and the third terminal. It flows through the second channel layer and does not flow through the first channel layer. The resistance of the first channel layer is 2 to 12 times greater than the resistance of the second channel layer. Furthermore, the present invention Regarding the second perspective A magnetoresistive element is, A stacked reference layer, barrier layer, recording layer, and channel layer, A first terminal connected to the reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The electrical resistance of the first channel layer is greater than the electrical resistance of the second channel layer. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. The resistance value of the first channel layer is greater than the resistance value of the second channel layer. The resistance of the first channel layer is 150 to 460 Ω, and the resistance of the second channel layer is 20 to 200 Ω.

[0017] For example, the reference layer is composed of a ferromagnetic layer with a fixed magnetization direction, the barrier layer is composed of a tunnel insulating film, the recording layer is composed of a ferromagnetic layer whose magnetization direction is variable by the spin-orbit torque generated by the writing current flowing through the channel layer, and the channel layer contains heavy metals. nothing.

[0018] The channel layer includes, for example, W, Ta, Pt, Pd, WOx, TaOx, PtOx, or PdOx.

[0019] The first channel layer, for example, has a thinner film thickness than the second channel layer.

[0020] The first channel layer is, for example, longer than the second channel layer. The first channel layer may be formed in a helical pattern.

[0021] The first channel layer is, for example, narrower than the second channel layer.

[0022] The first channel layer, for example, has a higher resistivity than the second channel layer.

[0023] This invention 3 A magnetoresistive element relating to this viewpoint is, A stacked reference layer, barrier layer, recording layer, and channel layer, The first terminal is connected to the aforementioned reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. In a state where current flows between the circuit element connected to the second terminal and the circuit element connected to the third terminal, Circuit element connected to the second terminal resistance The resistor is a circuit element connected to the third terminal. resistance It's higher than resistance. For example, the circuit element includes a transistor, and the on-resistance of the transistor constituting the circuit element connected to the second terminal is higher than the on-resistance of the transistor constituting the circuit element connected to the third terminal.

[0024] The first magnetic memory device of the present invention comprises a storage cell composed of the magnetoresistive element described above, A read circuit is connected to the first and third terminals of the memory cell, applies a read voltage between the first and third terminals of the memory cell, and determines the read data based on the magnitude of the read current flowing through the third terminal. It is equipped with. The read circuit, for example, compares the magnitude of the read current flowing through the third terminal with the magnitude of the reference current, and determines the read data based on the comparison result. This invention The second The magnetic memory device is a magnetoresistive element as described above. Composed of Memory cell A memory cell array is constructed by arranging these cells in an array-like manner. , A selection circuit connected to each memory cell selects the memory cell to be read, applies a voltage between the first and third terminals of the selected memory cell, and reads the stored data based on the magnitude of the read current flowing through the third terminal. It is equipped with. [Effects of the Invention]

[0025] According to the present invention, the channel layer has a first channel layer and a second channel layer with different resistance values. As a result, the overall resistance value of the channel layer can be set to an appropriate value that suppresses power consumption by the combined resistance of the first and second channel layers. On the other hand, the resistance value of the current path of the read current flowing between the first terminal and the third terminal can be suppressed by the resistance of the second channel layer, making it possible to relatively increase the read current and enable high-speed readout. [Brief explanation of the drawing]

[0026] [Figure 1] This figure shows the structure of a magnetoresistive element according to an embodiment of the present invention, where (a) is a front view and (b) is a top view. [Figure 2] This is a perspective view of a magnetoresistive element according to an embodiment. [Figure 3] This figure illustrates the configuration of the channel layer of a magnetoresistive element according to an embodiment. [Figure 4] This diagram illustrates the operation of writing data "1" to a magnetoresistive element according to an embodiment that stores "0", where (a) is a diagram illustrating the writing operation, (b) is a waveform diagram of the writing current, and (c) is an equivalent circuit. [Figure 5]This diagram illustrates the operation of writing data "0" to a magnetoresistive element according to an embodiment that stores "1", where (a) is a diagram illustrating the writing operation, (b) is a waveform diagram of the writing current, and (c) is an equivalent circuit. [Figure 6] This figure shows the relationship between the magnetoresistance and the writing current of a magnetoresistive element according to the embodiment. [Figure 7] This diagram illustrates the operation of reading data from a magnetoresistive element according to an embodiment, where (a) is a diagram illustrating the operation of reading data from a magnetoresistive element that has stored the data "0", and (b) is an equivalent circuit. [Figure 8] This diagram illustrates the operation of reading data from a magnetoresistive element according to an embodiment, where (a) is a diagram illustrating the operation of reading data from a magnetoresistive element that has stored the data "1", and (b) is an equivalent circuit. [Figure 9] (a) and (b) are diagrams illustrating the magnetoresistive effect elements related to Comparative Examples 1 and 2. [Figure 10] (a) and (b) are circuit diagrams of a memory cell circuit that uses a magnetoresistive element according to the embodiment as a memory cell. [Figure 11] Figure 10 is a block diagram of a magnetic memory device with multiple memory cell circuits arranged in it. [Figure 12] This diagram illustrates the wiring drive time of the memory cell circuit shown in Figure 11. [Figure 13] (a) and (b) are diagrams illustrating a first example configuration of the first channel layer and the second channel layer shown in Figure 3. [Figure 14] (a) and (b) are diagrams showing a second example configuration of the first channel layer and the second channel layer shown in Figure 3. [Figure 15] This figure shows a third example configuration of the first channel layer and the second channel layer shown in Figure 3. [Figure 16] This figure shows a fourth example configuration of the first channel layer and the second channel layer shown in Figure 3. [Figure 17] This figure shows a fifth example configuration of the first channel layer and the second channel layer shown in Figure 3. [Figure 18] (a) and (b) are diagrams showing the structures of modified examples of the magnetoresistive element according to an embodiment of the present invention. [Figure 19] This is a structural diagram of a conventional 3-terminal SOT-MRAM. [Modes for carrying out the invention]

[0027] A magnetoresistive element according to an embodiment of the present invention and a magnetic memory using the magnetoresistive element as a storage cell will be described with reference to the drawings.

[0028] The magnetoresistive element 100 according to this embodiment is a 3-terminal SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory), and as shown in Figure 1(a) as a front view, (b) as a top view, and Figure 2 as a perspective view, it has a configuration in which the channel layer 11, recording layer 12, barrier layer 13, and reference layer 14 are stacked in this order or in the reverse order. Note that this is a basic configuration, and other layers may be added between the layers, and one layer may be composed of multiple layers. Furthermore, other components may be included.

[0029] In the following explanation, an XYZ Cartesian coordinate system is defined where the longitudinal direction (extension) of the channel layer 11 is the X-axis direction, the short direction of the channel layer 11 is the Y-axis direction, and the height direction in which each layer is stacked is the Z-axis direction, and will be referenced as appropriate.

[0030] The channel layer 11 contains heavy metals and has a long, flat plate shape in the X-axis direction. The channel layer 11 is, for example, a layer formed with a thickness of 0.5 nm to 40 nm, a length of 50 nm to 300 nm in the X-axis direction, and a width of approximately 20 to 150 nm in the Y-axis direction.

[0031] The spin-orbit torque generated by passing a writing current in the longitudinal direction (±X axis direction) of the channel layer 11 rewrites the direction of the magnetization M12 of the recording layer 12. For this reason, the channel layer 11 contains heavy metals or heavy metal oxides with strong spin-orbit interaction, such as W, Ta, Pt, Pd, WOx, TaOx, PtOx, or PdOx. It may also contain Hf, Re, Os, Ir, Pb, or alloys thereof. Alternatively, other materials doped with these heavy metals or alloys may be used. The other materials may be conductive or nonconductive. The channel layer 11 as a whole is conductive. Furthermore, materials such as B, C, N, O, Al, Si, P, Ga, and Ge may be added as appropriate to obtain desired electrical properties and structure.

[0032] The recording layer 12 is a ferromagnetic layer formed from a ferromagnetic material stacked on top of the channel layer 11, and is made from ferromagnetic materials such as CoFeB, FeB, Fe, Co, Ni, and Mn. The magnetization M12 of the recording layer 12 is variable between the +X axis and the -X axis due to the spin-orbit torque generated by the writing current flowing through the channel layer 11.

[0033] In this embodiment, the recording layer 12 is formed in an elliptical shape in plan view, for example, with its major axis tilted θ with respect to the X-axis. θ is, for example, approximately ±2° to ±35°. Therefore, an external magnetic field is not required in this embodiment. However, it is also possible to set θ=0° and arrange an external magnetic field.

[0034] The recording layer 12 is formed, for example, with an aspect ratio of 2.5 to 5.0 and a thickness of approximately 1.30 nm to 1.60 nm. The aspect ratio refers to the long axis La / short axis Lb of the layer plane of the recording layer 12, as shown in Figure 1(b). The recording layer 12 is formed with a width of approximately 10 to 60 nm in the short axis direction and approximately 40 to 300 nm in the long axis direction in order to obtain this aspect ratio. Due to having an aspect ratio of this magnitude, the recording layer 12, on its own, has shape magnetic anisotropy in which the magnetization M12 is oriented along the long axis direction of the recording layer 12.

[0035] The barrier layer 13 is a tunnel insulating film composed of a tunnel insulating material, such as a material containing Mg and O, particularly MgO. The barrier layer 13 has, for example, the same planar shape as the recording layer 12 and is formed to a thickness of 0.1 nm to 5 nm.

[0036] The reference layer 14 is a ferromagnetic layer formed from a ferromagnetic material and laminated on top of the barrier layer 13. The magnetization direction M14 of the reference layer 14 is set in the +X axis direction. The reference layer 14 is made of the same material as, for example, the recording layer 12. The reference layer 14 and the barrier layer 13 are formed to have the same external shape.

[0037] A first terminal (electrode) T1 is positioned and connected to the reference layer 14. A second terminal (electrode) T2 is positioned and connected to one end of the channel layer 11 in the direction of extension, and a third terminal (electrode) T3 is positioned and connected to the other end of the channel layer 11 in the direction of extension.

[0038] In this embodiment, the second terminal T2 and the third terminal T3 are used for writing operations, a write voltage is applied between the second terminal T2 and the third terminal T3, and a write current flows between the second terminal T2 and the third terminal T3 via the channel layer 11. The first terminal T1 and the third terminal T3 are used for reading operations, a read voltage is applied between the first terminal T1 and the third terminal T3, and a read current flows between the first terminal T1 and the third terminal T3 via the reference layer 14, barrier layer 13, recording layer 12, and channel layer 11.

[0039] As shown in Figure 3, the channel layer 11 is the first channel layer 11 with respect to the centroid CG of the elliptical junction surface with the recording layer 12. A and the second channel layer 11 B It is logically or physically partitioned. First channel layer 11 A This is a region within the channel layer 11 where write current flows but read current does not. Second channel layer 11 B This is the region in the channel layer 11 where both write current and read current flow.

[0040] First channel layer 11 A The electrical resistance value of, more precisely, the first channel layer 11 A and the second channel layer 11 B The boundary region between and the second terminal T2 and the first channel layer 11 A The resistance value between the connection point and R A This is the case. Also, the second channel layer 11 B The electrical resistance value of, more precisely, the first channel layer 11 A and the second channel layer 11 B The boundary region between and the third terminal T3 and the second channel layer 11 B The resistance value between the connection point and R B The first channel layer 11 A Resistance value R A is the second channel layer 11 B Resistor R B It is adjusted to a multiple of α, which is a real number greater than 1, for example, around 2 to 12 times.

[0041] Generally, the resistance between the second terminal T2 and the third terminal T3 is approximately 200 to 500 Ω, for example, 400 Ω. Therefore, the resistance value R A The resistance value R is 150-460Ω. B It is set to approximately 20-200Ω. However, it is not limited to that range.

[0042] Note that the first channel layer 11 A Resistance value R A and the second channel layer 11 B Resistance value R B The methods for making them different will be discussed later.

[0043] Next, the operation of the magnetoresistive element 100 having the above configuration will be described. First, the writing operation will be explained with reference to Figures 4 and 5.

[0044] First, the second terminal T2 and the third terminal T3 of the magnetoresistive element 100 are connected to the programming circuit 110.

[0045] Here, as shown in Figure 4(a), we assume that the direction of the magnetization M12 of the recording layer 12 and the direction of the magnetization M14 of the reference layer 14 are in the same parallel state. In this case, the magnetoresistive element 100 is in a state of storing data "0".

[0046] When the writing circuit 110 writes the data "1" to the magnetoresistive element 100, it applies a writing voltage +V between the second terminal T2 and the third terminal T3, as shown in Figure 4(a). W pulse width T W Only this is applied. This results in a pulse width T in the -X axis direction of the channel layer 11, as shown in Figure 4(b). W The writing current I W A current flows. As shown in the equivalent circuit in Figure 4(c), the writing current I W This is the resistor R A and R B It flows through a series circuit, and its magnitude is I W =V W / (R A +R B ) becomes. Writing current I W This is the writing current I in the -X axis direction, as shown in Figure 6. W The threshold IC is greater than or equal to T, and the pulse width is T W This is set to a time longer than the time required for rewriting.

[0047] As shown in Figure 4(a), the writing current I W When it flows, the spin Hall effect causes a spin current (flow of spin angular motion) J in the ±Z axis direction. S This occurs. As a result, the spins become unevenly distributed, a spin-orbit torque acts, and the direction of the magnetization M12 of the recording layer 12 becomes antiparallel to the magnetization M14 of the reference layer 14, facing in the opposite direction of the -X axis, as shown in Figure 5(a). Consequently, the resistance value of the circuit from the reference layer 14 to the recording layer 12 becomes high resistance R AP This means that the data "1" is written to the magnetoresistive element 100.

[0048] As shown in Figure 5(a), when writing data "0" to the magnetoresistive element 100, which is in an antiparallel state and storing data "1", a write voltage +V is applied between the third terminal T3 and the second terminal T2.W pulse width T W Only this is applied. As a result, the pulse width T in the +X axis direction of the channel layer 11 is applied, as shown in Figure 5(b). W The writing current I W A current flows. As shown in the equivalent circuit in Figure 5(c), the writing current I W This is the resistor R A and R B It flows through a series circuit, and its magnitude is I W =V W / (R A +R B ) becomes. Writing current I W This is the writing current I in the +X axis direction, as shown in Figure 6. W The threshold IC is greater than or equal to 0, and the pulse width T W This is set to a time longer than the time required for rewriting.

[0049] Writing current I W When it flows, the spin current J is produced due to the spin Hall effect, etc. S This occurs, causing the magnetization M12 of the recording layer 12 to reverse direction, and as shown in Figure 4(a), it aligns with the magnetization M14 of the reference layer 14 in the same +X axis direction. As a result, the resistance value of the circuit from the reference layer 14 to the recording layer 12 becomes low resistance R P This means that the data "0" is written to the magnetoresistive element 100.

[0050] Next, we will explain the operation of reading data from the magnetoresistive element 100. First, as shown in Figures 7(a) and 8(a), the first terminal T1 and the third terminal T3 of the magnetoresistive element 100 are connected to the readout circuit 120.

[0051] First, as shown in Figure 7(a), assume that the magnetization M12 of the recording layer 12 and the magnetization M14 of the reference layer 14 are both oriented in the +X direction (parallel state). In this case, the resistance of the circuit (current path) from the recording layer 12 to the reference layer 14 is low resistance R. P Therefore, the magnetoresistive element 100 is in a state where it has stored "0".

[0052] The readout circuit 120 has a readout voltage V between the third terminal T3 and the first terminal T1.R is applied to obtain the flowing read current I R As is clear from the equivalent circuit of FIG. 7(b), the read current I R is expressed by the following equation. I R =V R / (R P +R B )

[0053] On the other hand, in the state of FIG. 8(a), the magnetization M12 of the recording layer 12 is oriented in the -X axis direction, and the magnetization M14 of the reference layer 14 is oriented in the +X axis direction (anti-parallel state). Therefore, the resistance of the current path from the recording layer 12 to the reference layer 14 is the high resistance R AP and the magnetoresistive effect element 100 is in the state of storing "1".

[0054] The read circuit 120 applies a read voltage V R between the third terminal T3 and the first terminal T1 to obtain the flowing read current I R As is clear from the equivalent circuit of FIG. 8(b), the read current I R is expressed by the following equation. F I R =V R / (R AP +R B )

[0055] The read circuit 120 compares the read current I R with a preset reference current I S and if the read current I R > reference current I S then the read data = 0, if the read current I R < reference current I S then the read data = 1, and makes a determination.

[0056] Here, for comparison, as shown in FIGS. 9(a) and (b), the first channel layer 11 A and the second channel layer 11 B are both the MRAM191 of Comparative Example 1 with the high resistance R A and the first channel layer 11 A and the second channel layer 11B Both have low resistance R B Let's assume the MRAM192 in Comparative Example 2. Note that resistor R A =α·R B Therefore, α is a real number greater than 1.

[0057] Writing current I W We will compare and examine these. In this embodiment, the writing current I W This is expressed by equation (1). I W =V W / (R A +R B )=V W / [(α+1)R B ]···(1) In Comparative Example 1, the writing current I W This is expressed by equation (2). I W =V W / (R A +R A )=V W / (2·α·R B ) ···(2) In Comparative Example 2, the writing current I W This is expressed by equation (3). I W =V W / (R B +R B )=V W / (2·R B ) ···(3)

[0058] From equation (1), the magnetoresistive element 100 according to the embodiment can be configured by appropriately setting α to write current I W It can be seen that it can be set to an appropriate size, neither too large nor too small. Therefore, the write time T W This also helps avoid situations where the processing time becomes excessively long. Therefore, high-speed writing is possible while keeping power consumption low.

[0059] On the other hand, in Comparative Example 1, from equation (2), the writing current I W Although it can be suppressed, the writing current I WIt can be seen that if the size becomes too small, there is a risk of data writing failing or the time required for writing becoming longer. In Comparative Example 2, from equation (3), the writing current I W It is clear that this cannot be suppressed, making energy-saving modifications difficult.

[0060] Next, the readout current I R We will compare and examine these points.

[0061] In this embodiment, the readout current I R This is expressed by equations (4) and (5). When the data is "1": I R =V R / (R AP +R B )···(4) When the data is "0": R =V R / (R P +R B )···(5)

[0062] In Comparative Example 1, the readout current I R This is expressed by equations (6) and (7). When the data is "1": I R =V R / (R AP +R A )=V R / (R AP +α·R B )···(6) When the data is "0": R =V R / (R P +R A )=V R / (R P +α·R B )···(7)

[0063] In Comparative Example 2, the readout current I R This is expressed by equations (8) and (9). When the data is "1": I R =V R / (R AP +R B )···(8) When the data is "0": R =V R / (R P +R B )···(9)

[0064] From equations (4) to (9), in the embodiment and comparative example 2, the read current I R It can be seen that the reading current I is relatively large, enabling high-speed reading. In contrast, in Comparative Example 1, the reading current I R It is clear that the size is small, and therefore, the reading time may be long.

[0065] Next, we will compare and examine the TMR ratio. The TMR ratio of this embodiment is expressed by equation (10). TMR=[(R AP +R B )-(R P +R B )] / (R P +R B ) =(R AP -R P ) / (R P +R B )···(10)

[0066] The TMR ratio for Comparative Example 1 is expressed by equation (11). TMR=[(R AP +R A )-(R AP +R A )] / (R P +R A ) =(R AP -R P ) / (R P +R A )=(R AP -R P ) / (R P +α·R B )···(11)

[0067] The TMR ratio for Comparative Example 2 is expressed by equation (12). TMR=[(R AP +R B )-(R P +RB )] / (R P +R B ) =(R AP -R P ) / (R P +R B )···(12) From equations (10) to (12), it can be seen that in the embodiment and comparative example 2, the TMR ratio is relatively large, data discrimination is easy, and high-speed reading is possible. In contrast, in comparative example 1, the TMR ratio is relatively small, data discrimination is difficult, and reading may take a long time.

[0068] From these considerations, the magnetoresistive element 100 according to the embodiment has a first channel layer 11 A Resistor R A and the second channel layer 11 B Resistor R B By setting it appropriately, the writing current I W This demonstrates that high-speed writing is possible while suppressing performance, and high-speed reading is also possible.

[0069] Furthermore, the magnetoresistive memory element of this invention is not limited to the above-described embodiment, and various modifications and applications are possible. For example, in the above embodiment, the first channel layer 11 is based on the centroid CG of the junction region between the recording layer 12 and the channel layer 11. A and the second channel layer 11 B The area was divided into sections, but the division positions are arbitrary. The key point is that the write current I for the entire channel layer 11 W ii) Of the channel layer 11, the read current I R Read the resistance value in the region where current I flows. R The goal is to set the resistance value to be smaller than the resistance value in the region where current does not flow.

[0070] Appropriate writing current I W The resistance value (R) of the channel layer 11 required to obtain this value A +R B) can be determined by experiment or simulation. Also, among the channel layer 11, the readout current I R Regarding the resistance value in the region through which current flows, the appropriate read current I R And an appropriate resistance value R to obtain the TMR ratio. B This can be determined through experimentation or simulation.

[0071] In the above embodiment, the first terminal T1 and the third terminal T3 were used for reading data, but it is also possible to use the second terminal T2 for reading. Furthermore, it is possible to make it possible to perform reading from the second terminal T2 and reading from the third terminal T3 in parallel, thus creating a dual-port memory. However, in this case, the reading from the second terminal T2 has a lower read current I compared to reading from the third terminal T3. R Because the signal becomes smaller, appropriate signal processing is required.

[0072] Next, an example of a memory circuit configuration using the magnetoresistive element 100 having the above configuration as a memory cell will be described with reference to Figure 10(a). Figure 10(a) shows the configuration of a 1-bit memory cell circuit 200. The memory cell circuit 200 includes a magnetoresistive element 100 that constitutes a memory cell for one bit, a pair of bit lines BL1 and BL2, a word line WL, a source line SL, a first selection transistor Tr1, and a second selection transistor Tr2.

[0073] The first terminal T1 of the magnetoresistive element 100 is connected to the source line SL. The second terminal T2 is connected to the drain of the first selection transistor Tr1, and the third terminal T3 is connected to the drain of the second selection transistor Tr2. The gate electrodes of the first selection transistor Tr1 and the second selection transistor Tr2 are commonly connected to the word line WL. In addition, the source of the first selection transistor Tr1 is connected to the first bit line BL1, and the source of the second selection transistor Tr2 is connected to the second bit line BL2.

[0074] When writing data to the magnetoresistive element 100, first, an active-level signal is applied to the word line WL to turn on the selection transistors Tr1 and Tr2 in order to select the magnetoresistive element 100. Here, it is assumed that the selection transistors Tr1 and Tr2 are composed of N-channel MOS transistors, and the word line WL is set to a high level. This turns on the first selection transistor Tr1 and the second selection transistor Tr2. Meanwhile, depending on the data to be written, one of the first bit line BL1 and the second bit line BL2 is set to a high level, and the other is set to ground level.

[0075] Specifically, when writing data "1", the first bit line BL1 is set to a low level and the second bit line BL2 is set to a high level. As a result, the write current I is as shown in Figure 4(a). W The data flows in the -X direction, and the data "1" is written.

[0076] On the other hand, when writing data "0", the first bit line BL1 is set to High level and the second bit line BL2 is set to Low level. As a result, as shown in Figure 5(a), the write current I W The signal flows, and the data "0" is written. In this way, bit data is written to the magnetoresistive element 100.

[0077] On the other hand, when reading information stored in the magnetoresistive element 100, the word line WL is set to the active level, and the first selection transistor Tr1 and the second selection transistor Tr2 are turned on. Also, the bit line BL1 is left open and the bit line BL2 is set to the low (ground) level. In addition, the read voltage V is set on the source line SL. R Apply the current. This connects the source line SL → first terminal T1 → reference layer 14 to channel layer 11 → third terminal T3 → second selection transistor Tr2 → second bit line BL2 and read current I R A current flows. A readout current I is generated by an operational amplifier (not shown). R and reference current I SBy comparing these, the memory data can be obtained.

[0078] Please note that the above circuit configuration and operation are merely examples and may be modified as appropriate. For example, when using the magnetoresistive element 100 as a dual-port memory, the gate of the first selection transistor Tr1 may be connected to the first word line WL1, and the gate of the second selection transistor Tr2 may be connected to the second word line WL2, as shown in Figure 10(b). With this configuration, by independently driving the first word line WL1 and the second word line WL2, data reading via the second terminal T2 and data reading via the third terminal T3 can be performed individually and in parallel. In this case, for reading via the third terminal T3, a large read current I is used, as described above. R This allows for a large TMR ratio to be obtained.

[0079] On the other hand, for reading through the second terminal T2, the load resistance R is relatively large. A Readout will be performed via this method. However, in the case of dual-port memory, it is common for the load resistance to differ for each port, and it is desirable to adopt a circuit configuration that corresponds to the load resistance.

[0080] Next, the configuration of a magnetic memory device 300, which includes multiple memory cell circuits 200 as shown in Figures 10(a) and (b), will be described with reference to Figure 11. The magnetic memory device 300 comprises a memory cell array 311, an X driver 312, a Y driver 313, and a controller 314, as shown in the figure. The memory cell array 311 has memory cell circuits 200 arranged in an array of N rows and M columns. Each memory cell circuit 200 in a column is connected to a pair of first bit lines BL1 and second bit lines BL2 of the corresponding column. Also, each memory cell circuit 200 in a row is connected to the word line WL and source line SL of the corresponding row. The X driver 312 and the Y driver 313 are selection circuits that select memory cells.

[0081] The X driver 312 is connected to multiple word lines WL and source lines SL. It decodes the low address and drives the word line WL of the row to be accessed to the active level. It also sets the voltage of the source line SL according to the operation. For the sake of clarity in the diagram, the word line WL is represented as a single line, but in the configuration shown in Figure 10(b), two word lines are arranged.

[0082] The Y driver 313 is connected to multiple first bit lines BL1 and second bit lines BL2. It decodes the column address and sets the first bit lines BL1 and second bit lines BL2 connected to the memory cell circuit 200 to be accessed to a write or read state for the desired data. Furthermore, when reading data stored in the memory cell circuit 200, the Y driver 313 opens the first bit line BL1 and sets the second bit line BL2 to a LOW level. It then compares the read current flowing through bit lines BL1 and BL2 with a reference current to determine the resistance of each column of the memory cell circuit 200, thereby reading the stored data.

[0083] The controller 314 controls the X driver 312 and the Y driver 313 respectively, depending on whether data is being written or read.

[0084] The bit line driving capability of each individual magnetoresistive element 100 during readout is small. Therefore, as shown in Figure 11, when multiple magnetoresistive elements 100 are connected to a single bit line BL, the time required for one magnetoresistive element 100 to drive the bit line BL (wiring drive time) t cir This can increase in length and potentially affect access speed. This becomes more pronounced as the number of magnetoresistive elements 100 connected to a single bit line BL increases.

[0085] Figure 12 shows the number of magnetoresistive elements 100 connected to a single bit line, their total capacitance, and the wiring drive time t. cir And the current I flowing through the magnetoresistive element 100 cell This shows a typical relationship. This graph is based on the following equation. t cir =C × V cell / I cell Here, C represents the capacitance (wiring capacitance) of a single bit line. Wiring capacitance C can be calculated from the wiring capacitance per unit length of the bit line × the length required to connect the magnetoresistive element 100. Here, as an example, the wiring capacitance per unit length of the bit line is 208aF (= 208 × 10⁻¹⁰). -18 The value is set to F) / μm. This value is based on the "International Roadmap for Devices and Systems (IRDS) 2018 Update". Also, the cell size of the magnetoresistive element 100 is 4F × 4F = 16F. 2 We assume F = 40 nm. This indicates a circuit where two wires can be passed through each memory cell in the X-axis and Y-axis directions, which matches the configuration shown in Figure 10. The length of the bit line can be calculated as 4F × the number of connected memory cells.

[0086] V cell V is the voltage of the bit line BL set by the antiparallel magnetoresistive element 100, cell Let's assume it's 0.8V. cell This is the value of the readout current flowing through the magnetoresistive element 100.

[0087] As can be seen from Figure 12, the readout current I cell If we can achieve =14μA, the number of memory cells per bit line will be approximately 500, and even with a bit size of 1Gbit, the wiring drive time will be around 0.5ns. cir It becomes clear that this can be achieved.

[0088] Resistance R of magnetoresistive element in a recent parallel state P The resistance R of the magnetoresistive element in an antiparallel state is approximately 14,000 Ω. AP The resistance is approximately 34,000Ω. Therefore, the readout current I is 0.8 / 34,000 = 23.5μA. cell Therefore, according to the embodiment, the wiring drive time t cirThis demonstrates that high-speed readout of 0.5 ns or less and low power consumption can be achieved.

[0089] Next, the first channel layer 11 A Resistance value R A and the second channel layer 11 B Resistance value R B Examples of specific structures to differentiate them will be explained with reference to Figures 13 to 17. In Figures 13 to 17, recording layer 12 to reference layer 14 are simply referred to as MTJ.

[0090] Configuration Example 1: The length L, thickness t, and width W of the thin film are defined as shown in Figure 13(a). In this case, the resistance R of the thin film is expressed as R = ρ·L / (t·W). ρ: resistivity (Ω·m), L: length of the thin film (m), t: thickness of the thin film (m), W: width of the thin film (m) This is also true for other configuration examples.

[0091] As shown in Figure 13(b), the first channel layer 11 A Thin, the second channel layer 11 B By forming a thick layer, it is possible to create a channel layer 11 having regions with different resistance values ​​by varying the thickness t. First channel layer 11 A and the second channel layer 11 B To form layers of varying thickness, for example, a base layer with steps can be formed, heavy metals can be deposited on this base layer by sputtering, the surface of the deposited layer can be flattened, and then patterned.

[0092] Configuration Example 2: As shown in Figure 14(a), the first channel layer 11 A For a longer duration, the second channel layer 11 B By shortening the length L, a channel layer 11 having regions with different resistance values ​​can be realized. First channel layer 11 A and the second channel layer 11 BIt is not necessary to form it in a straight line; any pattern shape can be adopted as long as the required length L can be secured, such as forming it in a spiral shape as shown in Figure 14(b).

[0093] Configuration Example 3: As shown in Figure 15, the first channel layer 11 A Narrow the second channel layer 11 B By forming a wide area, W can be varied, and the channel layer 11 can be realized.

[0094] Configuration Example 4: As schematically shown in Figure 16, the first channel layer 11 A and the second channel layer 11 B Even if the external shape is the same, the first channel layer 11 A The materials that make up the second channel layer 11 B By varying the materials that make up the channel layer 11, the resistivity ρ can be varied to realize the channel layer 11. In this case, the appropriate resistivity can be determined by adjusting the blending of the various heavy metals and additives mentioned above. As a manufacturing method, for example, i) a first heavy metal layer with resistivity ρ1 is formed, and this is patterned to form the first channel layer 11 A ii) Next, the first channel layer 11 A iii) Mask the first layer, deposit a second heavy metal with resistivity ρ2 to form a heavy metal layer, and pattern it to form a second channel layer 11 B By forming the mask and removing the mask, the channel layer 11 can be formed.

[0095] Configuration Example 5: The same first channel layer 11 A and the second channel layer 11 BEven when forming such a configuration, the channel layer 11 can be realized by making the resistance of the circuit element connected to the second terminal T2 large and the resistance of the circuit element connected to the third terminal T3 small. Figure 17 shows an example of circuit elements in which the on-resistances of the selection transistors Tr1 and Tr2 shown in Figures 10(a) and (b) are made different. Any method can be used to make the on-resistances different, such as making the size (channel width or channel length) of the transistors different from each other, or doping the channel region with impurities.

[0096] Note that configuration examples 1 through 5 can be used in combination.

[0097] In the above description, the present invention has been explained using as an example a magnetoresistive element 100 in which the orientation of the magnetization M12 of the recording layer 12 and the orientation of the magnetization M14 of the reference layer 14 are substantially parallel to the stretching direction (X-axis direction) of the channel layer 11 (for example, θ = 0 to ±35°). However, the present invention is not limited to this. For example, as shown in Figure 18(a), the present invention can also be applied to a magnetoresistive element 100A in which the orientation of the magnetization M12A of the recording layer 12 and the orientation of the magnetization M14A of the reference layer 14 are substantially parallel to the planes of the recording layer 12 and the reference layer 14 and are oriented in a direction (±Y-axis direction) substantially perpendicular to the stretching direction (X-axis direction) of the channel layer 11. Furthermore, as shown in Figure 18(b), this invention can also be applied to magnetoresistive element 100B configured such that the orientation of the magnetization M12B of the recording layer 12 and the orientation of the magnetization M14B of the reference layer 14 are oriented in a direction (±Z axis direction) that is substantially perpendicular to the planes of the recording layer 12 and the reference layer 14.

[0098] As described above, according to the embodiment, the writing current I W This invention provides a magnetoresistive element and a magnetic memory device using it that enable high-speed writing and reading while reducing power consumption. [Explanation of Symbols]

[0099] 11 channel layers 11 A First channel layer 11 B Second channel layer 12 recording layers 13 Barrier Layer 14 Reference layer 100 Magnetoresistive element 200 memory cell circuit 300 Magnetic Memory Devices 311 memory cell array 312 X Driver 313 Y Driver 314 Controller

Claims

1. A stacked reference layer, barrier layer, recording layer, and channel layer, A first terminal connected to the reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The electrical resistance of the first channel layer is greater than the electrical resistance of the second channel layer. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. The resistance value of the first channel layer is 2 to 12 times greater than the resistance value of the second channel layer. Magnetoresistive element.

2. A stacked reference layer, barrier layer, recording layer, and channel layer, A first terminal connected to the reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The electrical resistance of the first channel layer is greater than the electrical resistance of the second channel layer. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. The resistance value of the first channel layer is greater than the resistance value of the second channel layer. The resistance value of the first channel layer is 150 to 460 Ω, and the resistance value of the second channel layer is 20 to 200 Ω. Magnetoresistive element.

3. The aforementioned reference layer is composed of a ferromagnetic layer with a fixed magnetization direction. The barrier layer is composed of a tunnel insulating film. The recording layer is composed of a ferromagnetic layer whose magnetization direction is variable by the spin-orbit torque generated by the writing current flowing through the channel layer. The channel layer contains heavy metals, The magnetoresistive element according to claim 1 or 2.

4. The channel layer includes W, Ta, Pt, Pd, WOx, TaOx, PtOx, or PdOx. The magnetoresistive element according to claim 1, 2, or 3.

5. The first channel layer has a thinner film thickness than the second channel layer. A magnetoresistive element according to any one of claims 1 to 4.

6. The first channel layer is longer than the second channel layer. A magnetoresistive element according to any one of claims 1 to 5.

7. The first channel layer is formed in a helical pattern. The magnetoresistive element according to claim 6.

8. The first channel layer is narrower than the second channel layer. A magnetoresistive element according to any one of claims 1 to 7.

9. The first channel layer has a higher resistivity than the second channel layer. A magnetoresistive element according to any one of claims 1 to 8.

10. A stacked reference layer, barrier layer, recording layer, and channel layer, A first terminal connected to the reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. In a state where current flows through the circuit element connected to the second terminal and the circuit element connected to the third terminal, the resistance of the circuit element connected to the second terminal is higher than the resistance of the circuit element connected to the third terminal. Magnetoresistive element.

11. A stacked reference layer, barrier layer, recording layer, and channel layer, A first terminal connected to the reference layer, A second terminal connected to one end of the channel layer, A third terminal connected to the other end of the channel layer, Equipped with, The channel layer comprises a first channel layer extending from the bonding surface with the recording layer to the connection point with the second terminal, and a second channel layer extending from the bonding surface to the connection point with the third terminal. The write current flows between the second terminal and the third terminal through the first channel layer and the second channel layer. The read current flows between the first terminal and the third terminal through the second channel layer, but does not flow through the first channel layer. The circuit element includes a transistor, and the on-resistance of the transistor constituting the circuit element connected to the second terminal is higher than the on-resistance of the transistor constituting the circuit element connected to the third terminal. Magnetoresistive element.

12. A storage cell comprising a magnetoresistive element according to any one of claims 1 to 11, A read circuit connected to the first and third terminals of the memory cell, which applies a read voltage between the first and third terminals of the memory cell and determines the read data based on the magnitude of the read current flowing through the third terminal, A magnetic memory device equipped with the following features.

13. The aforementioned readout circuit is The magnitude of the read current flowing through the third terminal is compared with the reference current, and the read data is identified based on the comparison result. The magnetic memory device according to claim 12.

14. A memory cell array is configured in which memory cells composed of magnetoresistive elements according to any one of claims 1 to 13 are arranged in an array, A selection circuit connected to each memory cell selects the memory cell to be read, applies a voltage between the first and third terminals of the selected memory cell, and reads the stored data based on the magnitude of the read current flowing through the third terminal. A magnetic memory device equipped with the following features.

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