Semiconductor device, method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device whose reliability is ensured and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device 1 includes a plurality of base layers 4 formed of second conductivity type silicon carbide, a plurality of source layers 5 each formed of first conductivity type silicon carbide, a plurality of contact layers 6 each formed of second conductivity type silicon carbide, a plurality of gate insulating layers 7 formed to be in contact with respective source layers of adjacent base layers, a plurality of gate electrode layers 8 formed respectively on the plurality of gate insulating layers, a plurality of source electrode layers 10 formed across the source layer and the contact layer on each of the plurality of base layers, a drain electrode layer 12 formed on a substrate 2, and a resistive layer 13 formed at a position overlapping the source layer, the contact layer, and the source electrode layer in a region where a dislocation defect C exists in the epitaxial layer 3 when viewed from above.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In a semiconductor device, when there are dislocation defects in its base material, it is known that stacking defects expand during current conduction depending on the type of dislocation, and techniques for preventing the expansion of dislocations are disclosed. Patent Document 1 discloses a method for manufacturing a semiconductor device for this purpose. According to this manufacturing method, by removing the gate electrode layer in the region where dislocation defects exist, the influence of the dislocation defects on the semiconductor device can be suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when the gate electrode layer in the region where dislocation defects exist is removed, the electric field distribution in the semiconductor device changes significantly. For this reason, deterioration of the breakdown voltage of the semiconductor device, fluctuations in the threshold voltage, etc. occur, and it is difficult to ensure the reliability of the semiconductor device.

[0005] The present disclosure has been made to solve the above problems. An object of the present disclosure is to provide a semiconductor device with ensured reliability and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure is a substrate formed of silicon carbide of a first conductivity type, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. Multiple base layers formed of silicon carbide of the second conductivity type are provided on the epitaxial layer, A plurality of source layers are formed on each of the plurality of base layers, each of which is made of silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, a resistive layer is formed in a region where dislocation defects exist in the epitaxial layer, overlapping the source layer, contact layer, and source electrode layer. Equipped with picture, The resistive layer is formed directly above the source electrode layer. .

[0007] One embodiment of this disclosure is that the resistive layer is formed directly above the source layer and the contact layer and directly below the source electrode layer.

[0009] One embodiment of this disclosure is that the resistive layer is formed such that, when viewed from above, the current flowing through the region where dislocation defects exist in the epitaxial layer is at least 1 / 1,000,000 and at least 1 / 10 of the current flowing through the region without dislocation defects.

[0010] In one embodiment of the present invention, the resistive layer is formed such that its resistivity is 10 Ωcm or more and 100,000 Ωcm or less.

[0011] Other aspects of the semiconductor device relating to this disclosure are: A substrate formed of first-conductivity silicon carbide, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. Multiple base layers formed of silicon carbide of the second conductivity type are provided on the epitaxial layer, A plurality of source layers are formed on each of the plurality of base layers, each of which is made of silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, a resistive layer is formed in a region where dislocation defects exist in the epitaxial layer, overlapping the source layer, contact layer, and source electrode layer. Equipped with 、 The resistance layer is formed such that its area is larger than the area of the source electrode layer. It was formed.

[0012] The method for manufacturing a semiconductor device according to the present disclosure includes: an epitaxial layer forming step of forming an epitaxial layer of silicon carbide of a first conductivity type having a lower impurity concentration than the substrate on a first surface of a substrate formed of silicon carbide of the first conductivity type; a dislocation defect detecting step of detecting dislocation defects in the epitaxial layer; a base layer forming step of forming a plurality of base layers of silicon carbide of a second conductivity type on the epitaxial layer; a source layer forming step of forming a plurality of source layers of silicon carbide of the first conductivity type having a higher impurity concentration than the epitaxial layer on each of the plurality of base layers; a contact layer forming step of forming a plurality of contact layers of silicon carbide of the second conductivity type having a higher impurity concentration than the base layer so as to be surrounded by the source layer on each of the plurality of base layers; a gate insulating layer forming step of forming a plurality of gate insulating layers so as each contact the source layer of an adjacent base layer; a gate electrode layer forming step of forming a plurality of gate electrode layers on the plurality of gate insulating layers; A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Equipped with, The source electrode layer formation step includes a resistance layer formation step in which a resistance layer is formed in a region of the epitaxial layer where dislocation defects exist when viewed from above, at a position overlapping the source layer, the contact layer, and the source electrode layer. fruit, The resistive layer formation step includes the step of forming a resistive layer directly above the source electrode layer. is.

[0013] One embodiment of this disclosure is that the resistive layer formation step includes a step of forming a resistive layer directly above the source layer and the contact layer and directly below the source electrode layer.

[0015] One embodiment of this disclosure is that the resistive layer formation step includes a step of forming a resistive layer such that, in a top view, the current value flowing through the region of the epitaxial layer where dislocation defects exist is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through the region without dislocation defects.

[0016] One embodiment of this disclosure is that the resistive layer formation step includes a step of forming a resistive layer such that the resistivity is 10 Ωcm or more and 100,000 Ωcm or less.

[0017] Another aspect of the method for manufacturing a semiconductor device according to this disclosure is an epitaxial layer formation step of forming an epitaxial layer of silicon carbide of a first conductivity type having a lower impurity concentration than that of the substrate on a first surface of a substrate formed of silicon carbide of a first conductivity type, A dislocation defect detection step for detecting dislocation defects in the epitaxial layer, A base layer formation step in which multiple base layers are formed on the epitaxial layer using silicon carbide of the second conductivity type, A source layer formation step is to form a plurality of source layers on each of the plurality of base layers using silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, A contact layer formation step is performed in which multiple contact layers are formed on each of the multiple base layers, surrounded by a source layer, using a second conductive type of silicon carbide with a higher impurity concentration than the base layer, A gate insulating layer formation step in which multiple gate insulating layers are formed so as to be in contact with the respective source layers of adjacent base layers, A gate electrode layer formation step in which a plurality of gate electrode layers are formed on the plurality of gate insulating layers, A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Equipped with, The source electrode layer formation step includes a resistance layer formation step in which a resistance layer is formed in a region of the epitaxial layer where dislocation defects exist when viewed from above, at a position overlapping the source layer, the contact layer, and the source electrode layer. The resistive layer formation step is a step of forming a resistive layer such that its area is larger than the area of ​​the source electrode layer. It included. [Effects of the Invention]

[0018] According to this disclosure, it is possible to provide a reliable semiconductor device and a method for manufacturing the semiconductor device. [Brief explanation of the drawing]

[0019] [Figure 1] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 1. [Figure 2] This is a top view of the main part of the semiconductor device in Embodiment 1. [Figure 3] This is a flowchart illustrating the manufacturing method of the semiconductor device in Embodiment 1. [Figure 4] This is a diagram illustrating the flow of forward current in the semiconductor device in Embodiment 1. [Figure 5] This is a diagram illustrating the flow of body diode current in the semiconductor device in Embodiment 1. [Figure 6] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 2. [Figure 7] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 3. [Figure 8] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 4. [Figure 9] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 5. [Figure 10] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 6. [Figure 11] This is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 7. [Modes for carrying out the invention]

[0020] Embodiments will be described with reference to the attached drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals. The explanation of such parts will be simplified or omitted as appropriate.

[0021] Embodiment 1. Figure 1 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 1.

[0022] In Figure 1, the semiconductor device 1 is a silicon carbide MOSFET. The semiconductor device 1 comprises a substrate 2, an epitaxial layer 3, a plurality of base layers 4, a plurality of source layers 5, a contact layer 6, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, a drain electrode layer 12, and a resistive layer 13.

[0023] The substrate 2 is formed of silicon carbide of the first conductivity type. For example, the substrate 2 is n + This is a type of substrate. For example, substrate 2 is formed with nitrogen as an impurity. The epitaxial layer 3 is formed on the first surface (top surface in Figure 1) of substrate 2. The epitaxial layer 3 is formed of silicon carbide of the first conductivity type with a lower impurity concentration than substrate 2. For example, the epitaxial layer 3 is n - This is a type of layer. For example, epitaxial layer 3 is formed on substrate 2 by epitaxial growth. Epitaxial layer 3 contains dislocation defects. For example, region A is a region that does not contain dislocation defects in the unit structure. For example, region B is a region that contains dislocation defects in the unit structure. In Figure 1, dislocation defects are indicated by C.

[0024] Multiple base layers 4 are formed on the epitaxial layer 3. Multiple base layers 4 are formed of second-conductivity silicon carbide. For example, multiple base layers 4 are p - It is a type of layer. For example, multiple base layers 4 are formed by ion implantation with aluminum as an impurity. Multiple source layers 5 are formed on each of the multiple base layers 4. Multiple source layers 5 are formed of silicon carbide of the first conductivity type with a higher impurity concentration than epitaxial layer 3. For example, multiple source layers 5 are n+ It is a type of layer. For example, multiple source layers 5 are formed by ion implantation with nitrogen as an impurity. Multiple contact layers 6 are formed on each of the multiple base layers 4. In each of the multiple base layers 4, the contact layer 6 is surrounded by the source layer 5. The multiple contact layers 6 are formed of silicon carbide of the second conductivity type with a higher impurity concentration than the multiple base layers 4. For example, the multiple contact layers 6 are p + These are molded layers. For example, multiple contact layers 6 are formed by ion implantation with aluminum as an impurity.

[0025] Multiple gate insulating layers 7 are formed to be in contact with the respective source layers 5 of adjacent base layers 4. Specifically, the multiple gate insulating layers 7 are formed to span the base layer 4 adjacent to the epitaxial layer 3 and the respective source layers 5 located inside it. For example, the multiple gate insulating layers 7 are formed by thermal oxidation. Multiple gate electrode layers 8 are each formed on top of the multiple gate insulating layers 7. For example, the multiple gate electrode layers 8 are formed from polysilicon by CVD.

[0026] Multiple interlayer insulating layers 9 are formed to cover each of the multiple gate electrode layers 8. For example, the multiple interlayer insulating layers 9 are formed by the CVD method. Multiple source electrode layers 10 are formed corresponding to each of the multiple base layers 4. The source electrode layers 10 are formed to span the source layer 5 and the contact layer 6. For example, the multiple source electrode layers 10 are formed by depositing Ni or the like by sputtering and then heat-treating them. The wiring electrode layer 11 is formed to cover the multiple source electrode layers 10. For example, the wiring electrode layer 11 is formed of an aluminum alloy by sputtering.

[0027] The drain electrode layer 12 is formed on the second surface (bottom surface in Figure 1) of the substrate 2. For example, the drain electrode layer 12 is formed by depositing Ni or the like by sputtering and then heat-treating it.

[0028] In this embodiment, a resistive layer 13 is added. For example, the resistive layer 13 is a thin insulator. The resistive layer 13 is formed from undoped silicon by the CVD method. The resistive layer 13 is not formed in region A where dislocation defects C of the epitaxial layer 3 do not exist when viewed from above. The resistive layer 13 is formed in region B where dislocation defects C of the epitaxial layer 3 exist when viewed from above. The resistive layer 13 is formed in a position that overlaps the source layer 5, the contact layer 6, and the source electrode layer 10 when viewed from above. Specifically, the resistive layer 13 is formed directly above the source layer 5 and the contact layer 6 and directly below the source electrode layer 10.

[0029] Next, we will explain the details of the resistive layer 13 using Figure 2. Figure 2 is a top view of the main part of the semiconductor device in Embodiment 1. In Figure 2, the substrate 2, epitaxial layer 3, multiple base layers 4, multiple gate insulating layers 7, and multiple gate electrode layers 8 are shown. Multiple source electrode layers 10 The wiring electrode layer 11 and the drain electrode layer 12 are not shown in the diagram.

[0030] In Figure 2, the dislocation defect C spans three unit structures. In these three unit structures, the region B containing the dislocation defect C is indicated by the dashed line. To avoid complexity, it is not shown, but in each unit structure, the region A that does not contain the dislocation defect is the region other than the shown region B. Note that in the cross-section along the DD line, the cross-section corresponding to region E corresponds to the cross-section in Figure 1.

[0031] In the example shown in Figure 2, three resistive layers 13 are formed corresponding to the three regions B. For example, in three unit structures where regions B exist, the resistive layers 13 are formed not only within region B but also extending into region A by a predetermined amount. The amount by which the resistive layers 13 extend into region A may be set to increase in proportion to the depth of the dislocation defect C. For example, the amount of extension may be increased in proportion to the depth of the dislocation defect C.

[0032] Next, the manufacturing method of the semiconductor device 1 will be explained using Figure 3. Figure 3 is a flowchart illustrating the manufacturing method of a semiconductor device in Embodiment 1.

[0033] As shown in Figure 3, the semiconductor device 1 is manufactured through a substrate formation process, an epitaxial layer formation process, a dislocation defect detection process, a base layer formation process, a source layer formation process, a contact layer formation process, an annealing process, a gate insulating layer formation process, a gate electrode layer formation process, an interlayer insulating layer formation process, a source electrode layer formation process, a wiring electrode layer formation process, and a drain electrode layer formation process.

[0034] In step S1, a substrate formation process is performed. In the substrate formation process, substrate 2 is formed. Subsequently, in step S2, an epitaxial layer formation process is performed. In the epitaxial layer formation process, epitaxial layer 3 is formed. Subsequently, in step S3, a dislocation defect detection process is performed. In the dislocation defect detection process, dislocation defects C in epitaxial layer 3 are detected by photoluminescence, X-ray topography, etc. Information on the locations where dislocation defects C are detected is stored in a computer (not shown).

[0035] Subsequently, in step S4, a base layer formation process is performed. In the base layer formation process, multiple base layers 4 are formed. Then, in step S5, a source layer formation process is performed. In the source layer formation process, multiple source layers 5 are formed. Then, in step S6, a contact layer formation process is performed. In the contact layer formation process, multiple contact layers 6 are formed. Then, in step S7, an annealing process is performed. In the annealing process, an annealing treatment is performed to activate the ion-implanted impurities.

[0036] Subsequently, in step S8, a gate insulating layer formation process is performed. In the gate insulating layer formation process, multiple gate insulating layers 7 are formed. Subsequently, in step S9, a gate electrode layer formation process is performed. In the gate electrode layer formation process, multiple gate electrode layers 8 are formed. Subsequently, in step S10, an interlayer insulating layer formation process is performed. In the interlayer insulating layer formation process, an interlayer insulating layer 9 is formed.

[0037] Subsequently, in step S11, a source electrode layer formation process is performed. The source electrode layer formation process includes a resistance layer formation process and a metal layer formation process. First, in the resistance layer formation process, a resistance layer 13 is formed. At that time, in step S3, the region B where dislocation defects C exist is identified from the information of the locations detected in the dislocation defect detection process and stored in the computer, and the resistance layer 13 is formed there. Subsequently, in the metal layer formation process, a source electrode layer 10 is formed.

[0038] Subsequently, in step S12, a wiring electrode layer formation process is carried out. In the wiring electrode layer formation process, a wiring electrode layer 11 is formed.

[0039] Subsequently, in step S13, a drain electrode layer formation process is carried out. In the drain electrode layer formation process, a drain electrode layer 12 is formed.

[0040] Next, we will explain the flow of forward current using Figure 4. Figure 4 is a diagram illustrating the flow of forward current in the semiconductor device in Embodiment 1.

[0041] As shown in Figure 4, the forward current reaches the substrate 2 from the drain electrode layer 12. Then, the forward current reaches the epitaxial layer 3. Next, the forward current flows toward the gate electrode layer 8. Then, the forward current reaches the base layers 4 on both sides of the gate electrode layer 8. Next, the forward current reaches the source layers 5 on both sides of the gate electrode layer 8. Finally, the forward current reaches the source electrode 10.

[0042] In this case, the forward current does not pass through the resistive layer 13 in region B. Therefore, the resistive layer 13 does not affect the forward current.

[0043] Next, we will explain the flow of current in the body diode using Figure 5. Figure 5 is a diagram illustrating the flow of body diode current in the semiconductor device in Embodiment 1.

[0044] As shown in Figure 5, the body diode current flows from the source electrode layer 10 towards the contact layer 6. The body diode current then reaches the base layer 4. Finally, the body diode current reaches the epitaxial layer 3.

[0045] In this case, in region A, the body diode current flows directly from the source electrode layer 10 to the contact layer 6. In contrast, in region B, the body diode current flows from the source electrode layer 10 to the contact layer 6 via the resistive layer 13. Therefore, the value of the body diode current in region B is significantly smaller than the value of the body diode current in region A.

[0046] According to Embodiment 1 described above, the resistive layer 13 is formed in a region B where dislocation defects C of the epitaxial layer 3 exist when viewed from above, and is positioned to overlap the source layer 5, the contact layer 6, and the source electrode layer 10. Specifically, the resistive layer 13 is formed directly above the source layer 5 and the contact layer 6 and directly below the source electrode layer 10. This ensures the reliability of the semiconductor device 1.

[0047] In particular, in silicon carbide MOSFETs, many additional field relaxation layers are provided to avoid field concentration as high-voltage elements exceeding 1000V. In contrast, according to this disclosure, the gate electrode layer 8 and the source electrode layer 10 are not removed. Therefore, the precisely designed field distribution is not disturbed. As a result, the reliability of the semiconductor device 1 can be ensured without causing degradation of the breakdown voltage or fluctuations in the threshold voltage.

[0048] In Figure 2, in the three unit structures where region B exists, the resistive layer 13 does not have to extend into region A. For example, the resistive layer 13 may be formed such that its end is positioned at the boundary between region B and region A. For example, the resistive layer 13 may be formed such that its end is positioned a predetermined amount closer to region B than the boundary between region B and region A.

[0049] Furthermore, in Figure 3, the dislocation defect detection step may be performed immediately after the annealing step in step S7, rather than immediately after the epitaxial layer formation step in step S2.

[0050] Embodiment 2. Figure 6 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 2. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0051] In Figure 6, the resistive layer 14 is a thin layer with a specific resistivity. For example, the resistive layer 14 is formed from undoped silicon by the CVD method. The resistive layer 14 is set considering the size of the semiconductor device 1 and the current value during the actual operation of the semiconductor device 1. For example, the resistive layer 14 is set considering the size of each layer, the thickness of each layer, the value of the body diode current, capacitance, switching speed, etc. For example, the resistive layer 14 is formed such that, when viewed from above, the current value flowing through region B where dislocation defects C of the epitaxial layer 3 exist is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through region A that does not contain dislocation defects C. Preferably, the resistive layer 14 is formed such that the current value flowing through region B where dislocation defects C of the epitaxial layer 3 exist is at least 1 / 100 of the current value flowing through region A that does not contain dislocation defects C. For example, the resistive layer 14 is formed so that its resistivity is at least 10 Ωcm and at least 100,000 Ωcm.

[0052] According to Embodiment 2 described above, the resistive layer 14 is formed such that, when viewed from above, the current flowing through region B where dislocation defects C of the epitaxial layer 3 exist is at least 1 / 1,000,000 and at least 1 / 10 of the current flowing through region A that does not contain dislocation defects C. Therefore, even during the actual operation of the semiconductor device 1, the electric field distribution remains almost undisturbed. As a result, the reliability of the semiconductor device 1 can be more reliably ensured.

[0053] Furthermore, the resistive layer 14 is formed such that its resistivity is between 10 Ωcm and 100,000 Ωcm. Therefore, the electric field distribution remains almost completely undisturbed even during actual operation of the semiconductor device 1. As a result, the reliability of the semiconductor device 1 can be more reliably ensured.

[0054] Embodiment 3. Figure 7 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 3. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0055] In Figure 7, the resistive layer 15 is a thin insulator. The resistive layer 15 is formed such that its area is larger than the area of ​​the source electrode layer 10.

[0056] According to Embodiment 3 described above, the resistive layer 15 is formed such that its area is larger than the area of ​​the source electrode layer 10. Therefore, the reliability of the semiconductor device 1 can be more reliably ensured.

[0057] Embodiment 4. Figure 8 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 4. Note that the same or equivalent parts as in Embodiment 2 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0058] In Figure 8, the resistive layer 16 is a thin layer with a specific resistivity. The resistive layer 16 is formed such that its area is larger than the area of ​​the source electrode layer 10.

[0059] According to Embodiment 4 described above, the resistive layer 16 is formed such that its area is larger than the area of ​​the source electrode layer 10. Therefore, the reliability of the semiconductor device 1 can be more reliably ensured.

[0060] Embodiment 5. Figure 9 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 5. Note that the same or equivalent parts as in Embodiment 3 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0061] In Figure 9, the resistive layer 17 is a thin insulator. The resistive layer 17 is formed directly above the source electrode layer 10.

[0062] According to Embodiment 5 described above, the resistive layer 17 is formed directly above the source electrode layer 10. Therefore, the reliability of the semiconductor device 1 can be more reliably ensured.

[0063] Embodiment 6. Figure 10 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 6. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0064] In Figure 10, the resistive layer 18 is a thin layer with a specific resistivity. It is formed directly above the source electrode layer 10.

[0065] According to Embodiment 6 described above, the resistive layer 18 is formed directly above the source electrode layer 10. Therefore, the reliability of the semiconductor device 1 can be more reliably ensured.

[0066] Embodiment 7. Figure 11 is a longitudinal cross-sectional view of the main part of the semiconductor device in Embodiment 7. Note that the same or equivalent parts as in Embodiment 1 are denoted by the same reference numerals. Descriptions of these parts are omitted.

[0067] As shown in Figure 11, the semiconductor device 1 is of the trench type. A resistive layer 13 is also added to the semiconductor device 1.

[0068] According to Embodiment 7 described above, even if the semiconductor device 1 is of the trench type, a resistive layer 13 is added. Therefore, the reliability of the semiconductor device 1 can be ensured.

[0069] In Embodiments 1 to 7, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case as well, the reliability of the semiconductor device 1 can be ensured.

[0070] While several aspects of at least one embodiment have been described, it should be understood that various modifications, alterations, and improvements will be readily conceivable to those skilled in the art. Such modifications, alterations, and improvements are intended to be part of and within the scope of this disclosure.

[0071] It should be understood that the embodiments of the methods and apparatus described herein are not limited to their application to the structural and arrangement details of the components described above or illustrated in the accompanying drawings. The methods and apparatus can be implemented in other embodiments and carried out or performed in various ways.

[0072] Specific implementation examples are provided here for illustrative purposes only and are not intended to be limiting.

[0073] The expressions and terms used in this disclosure are for illustrative purposes only and should not be considered limiting. The use herein of “includes,” “equips,” “possesses,” “contains,” and variations thereof means the inclusion of the items listed herein and their equivalents, as well as the supplementary items.

[0074] The use of "or" can be interpreted as meaning that any term used with "or" refers to one, more than one, or all of the terms described.

[0075] References to front / back, left / right, top / bottom / top / bottom, width / height, and front / back are all intended for convenience of description. Such references do not mean that the components of this disclosure are limited to any single positional or spatial orientation. Accordingly, the above description and drawings are illustrative only. [Explanation of symbols]

[0076] 1. Semiconductor layer, 2. Substrate, 3. Epitaxial layer, 4. Base layer, 5. Source layer, 6. Contact layer, 7. Gate insulating layer, 8. Gate electrode layer, 9. Interlayer insulating layer, 10. Source electrode layer, 11. Wiring electrode layer, 12. Drain electrode layer, 13-18. Resistive layer

Claims

1. A substrate formed of first-conductivity silicon carbide, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. A plurality of base layers formed of second-conductivity silicon carbide are provided on the epitaxial layer, Each of the above-mentioned multiple base layers is formed on each of the above-mentioned multiple source layers with silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, a resistive layer is formed in a region where dislocation defects exist in the epitaxial layer, overlapping the source layer, contact layer, and source electrode layer. Equipped with, The resistive layer is formed directly above the source electrode layer in the semiconductor device.

2. The semiconductor device according to claim 1, wherein the resistive layer is formed directly above the source layer and the contact layer and directly below the source electrode layer.

3. The semiconductor device according to claim 1 or claim 2, wherein the resistive layer is formed such that, in a top view, the current flowing through the region where dislocation defects exist in the epitaxial layer is at least 1 / 1,000,000 and at least 1 / 10 of the current flowing through the region without dislocation defects.

4. The semiconductor device according to claim 1 or claim 2, wherein the resistive layer is formed such that its resistivity is 10 Ωcm or more and 100,000 Ωcm or less.

5. A substrate formed of silicon carbide of a first conductivity type, On the first surface of the substrate, an epitaxial layer is formed of silicon carbide of a first conductivity type with a lower impurity concentration than the substrate, and contains dislocation defects. A plurality of base layers formed of second-conductivity silicon carbide are provided on the epitaxial layer, Each of the above-mentioned multiple base layers is formed on each of the above-mentioned multiple source layers with silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, Each of the aforementioned multiple base layers is surrounded by a source layer, and each of the multiple contact layers is formed of a second-conductivity silicon carbide with a higher impurity concentration than the base layer, Multiple gate insulating layers formed to contact each source layer of an adjacent base layer, A plurality of gate electrode layers formed on each of the plurality of gate insulating layers, On each of the aforementioned multiple base layers, a plurality of source electrode layers are formed spanning the source layer and the contact layer, A drain electrode layer formed on the second surface of the substrate, In a top view, a resistive layer is formed in a region where dislocation defects exist in the epitaxial layer, overlapping the source layer, contact layer, and source electrode layer. Equipped with, The resistive layer is formed such that its area is larger than that of the source electrode layer in the semiconductor device.

6. An epitaxial layer formation step of forming an epitaxial layer of first conductivity type silicon carbide having a lower impurity concentration than the substrate on the first surface of a substrate formed of first conductivity type silicon carbide, A dislocation defect detection step for detecting dislocation defects in the epitaxial layer, A base layer formation step in which multiple base layers are formed on the epitaxial layer using silicon carbide of the second conductivity type, A source layer formation step is to form a plurality of source layers on each of the plurality of base layers using silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, A contact layer formation step is performed in which multiple contact layers are formed on each of the aforementioned multiple base layers, surrounded by a source layer, using a second conductive type of silicon carbide with a higher impurity concentration than the base layer, A gate insulating layer formation step in which multiple gate insulating layers are formed so as to be in contact with the respective source layers of adjacent base layers, A gate electrode layer formation step in which a plurality of gate electrode layers are formed on the plurality of gate insulating layers, A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Equipped with, The source electrode layer formation step includes a resistance layer formation step in which a resistance layer is formed in a region of the epitaxial layer where dislocation defects exist when viewed from above, at a position overlapping the source layer, the contact layer, and the source electrode layer. The resistive layer formation step is a method for manufacturing a semiconductor device, which includes a step of forming a resistive layer directly on top of a source electrode layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the resistive layer formation step includes a step of forming a resistive layer directly above the source layer and the contact layer and directly below the source electrode layer.

8. The method for manufacturing a semiconductor device according to claim 6 or claim 7, further comprising the step of forming a resistive layer such that the current value flowing through a region of the epitaxial layer where dislocation defects exist, as viewed from above, is at least 1 / 1,000,000 and at least 1 / 10 of the current value flowing through a region without dislocation defects.

9. The method for manufacturing a semiconductor device according to claim 6 or claim 7, wherein the resistive layer formation step includes a step of forming a resistive layer such that the resistivity is 10 Ωcm or more and 100,000 Ωcm or less.

10. An epitaxial layer formation step of forming an epitaxial layer of silicon carbide of a first conductivity type having a lower impurity concentration than the substrate on the first surface of a substrate formed of silicon carbide of a first conductivity type, A dislocation defect detection step for detecting dislocation defects in the epitaxial layer, A base layer formation step in which multiple base layers are formed on the epitaxial layer using silicon carbide of the second conductivity type, A source layer formation step is to form a plurality of source layers on each of the plurality of base layers using silicon carbide of a first conductivity type having a higher impurity concentration than the epitaxial layer, A contact layer formation step is performed in which multiple contact layers are formed on each of the aforementioned multiple base layers, surrounded by a source layer, using a second conductive type of silicon carbide with a higher impurity concentration than the base layer, A gate insulating layer formation step in which multiple gate insulating layers are formed so as to be in contact with the respective source layers of adjacent base layers, A gate electrode layer formation step in which a plurality of gate electrode layers are formed on the plurality of gate insulating layers, A source electrode layer formation step is performed in which multiple source electrode layers are formed on each of the multiple base layers so as to span the source layer and the contact layer, A drain electrode layer formation step in which a drain electrode layer is formed on the second surface of the substrate, Equipped with, The source electrode layer formation step includes a resistance layer formation step in which a resistance layer is formed in a region of the epitaxial layer where dislocation defects exist when viewed from above, at a position overlapping the source layer, the contact layer, and the source electrode layer. The method for manufacturing a semiconductor device includes a step of forming a resistive layer such that its area is larger than the area of ​​the source electrode layer.

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