Flash memory array, and method for writing and erasing the same.

Abstract

The present disclosure provides a flash memory array and a write method and an erase method thereof. The flash memory array according to the present disclosure includes a plurality of flash memory cells arranged along a row direction and a column direction perpendicular to the row direction, a plurality of word line sets extending along the row direction, and a plurality of bit line sets extending along the column direction. A flash memory cell pair is provided at the intersection of the word line set and the bit line set. The flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line set. The flash memory array according to the present disclosure can increase the arrangement density of the bit line and reduce the parasitic resistance of the bit line without increasing the size of the array. In addition, compared with the flash memory array of the prior art, the flash memory array according to the present disclosure also has better process compatibility and shrinkage characteristics. The write method of the flash memory array according to the present disclosure has the advantages of low operation power consumption and high programming speed, which is helpful to increase the number of flash memory cells for parallel writing, thereby increasing the memory data write throughput rate. The erase method of the flash memory array disclosed herein can improve the threshold voltage window and enhance the reliability of storage, while having the advantages of low operating power consumption and fast erase speed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology. Specifically, the present disclosure relates to a flash memory array and a writing method and an erasing method for the flash memory array.

Background Art

[0002] JPEG0007901916000001.jpg22170

[0003] Conventional flash memories adopt a floating gate cell structure. The floating gate type non-volatile memory is derived from the MIMIS (Metal-Insulator -Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. Based on the conventional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), this structure adds a metal floating gate and an ultra-thin tunneling oxide layer, and thereby uses the metal floating gate to accumulate charges. Based on this, in 1984, Masuoka et al. proposed the concept of flash memory for the first time, which realized a high-speed erasing function by erasing in sector units and writing in bit units, eliminated the selection transistors required for EEPROM (Erasable Programmable Read Only Memory), and reduced the size of the memory cells. Since its appearance, flash memory has rapidly developed due to its fast writing speed, high integration degree, and excellent performance. Intel proposed a flash memory cell with an ETOX structure (ETOX: Electron Tunneling Oxide device) in 1988, which has become the basis for the development of most of the current floating gate type flash memory cell structures.

[0004] However, floating-gate flash memory has the following drawbacks: The process is relatively complex. The presence of floating gate structures in flash memory cells increases the vertical height of the gate structures, making it difficult to scale down the process size and cell area. At the same time, the conductivity of the floating gates allows the stored charge to move freely within the floating gates, which is detrimental to improving the reliability of the memory. To solve the problems of the complex process and low reliability of floating-gate flash memory, researchers proposed charge-trapping memory (CTM), which uses silicon nitride dielectric to store charge, and is also called SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory. Based on this, B. Eitan et al. proposed a 2-bit memory cell structure called NROM (Nitride-Read-Only-Memory) in 2000. This cell structure utilizes the non-conductive properties of an insulating silicon nitride memory medium to implement two memory bits at the source and drain ends of a single memory transistor. However, this cell structure has drawbacks, such as interference between the two memory bits and the inability to reduce device size.

[0005] On the other hand, existing floating-gate ETOX flash memory and SONOS NROM flash memory all suffer from problems such as the inability to reduce process size, large cell area, high power consumption during writing, and large array area overhead, making it impossible to achieve high-density integration of gigabit (Gb) capacity or higher.

[0006] Furthermore, existing flash memory arrays require the configuration of bit lines, word lines, and source lines to enable the selection and operation of flash memory cells. However, the source lines in existing flash arrays are formed in the active region, and the square resistance of the active region is much higher than that of metal. Therefore, in order to reduce the series resistance of the source lines, the source lines in the active region must be short-circuited every few rows or columns in the row or column direction by a common metal source line, which results in an increase in the area overhead of the flash array.

[0007] With the rapid development of applications such as mobile intelligent terminals, wearable devices, and intelligent sensor networks, higher demands are being placed on flash memory in terms of power consumption, storage capacity, and cost. Therefore, there is a need for flash memory technology that has advantages such as low power consumption, small cell area, reduced process size, high array integration density, and large capacity. [Overview of the Initiative]

[0008] The information disclosed above in this background section is intended solely to provide an understanding of the background of the idea of ​​the present invention and therefore may include information that does not constitute prior art.

[0009] To solve the problems described above in the prior art, this disclosure provides a flash memory array, as well as a method for writing to and erasing the same.

[0010] According to one aspect of the present disclosure, a flash memory array is provided. This flash memory array includes a plurality of flash memory cells arranged along row directions and column directions orthogonal to the row directions, a plurality of word line sets extending along row directions, and a plurality of bit line sets extending along column directions. Flash memory cell pairs are provided at the intersections of the word line sets and bit line sets. A flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row directions and share the same bit line set.

[0011] The flash memory array according to this disclosure can increase the bit line arrangement density and reduce bit line parasitic resistance without increasing the array size. Furthermore, compared to conventional flash memory arrays, the flash memory array according to this disclosure also has better process compatibility and miniaturization characteristics.

[0012] According to one aspect of the present disclosure, a method for writing to a flash memory array according to the above aspect of the present disclosure is provided. This writing method includes the steps of: performing a write operation on a first memory transistor of a first flash memory cell by applying a first write voltage to a first bit line, a second write voltage to an intermediate bit line and a second bit line, a third write voltage to a first control line, a fourth write voltage to a word line, and a fifth write voltage to a second control line; and performing a write operation on a second memory transistor of a first flash memory cell by applying a second write voltage to a first bit line, a first write voltage to an intermediate bit line and a second bit line, a fifth write voltage to a first control line, a fourth write voltage to a word line, and a third write voltage to a second control line. The procedure includes the steps of: performing a write operation on the first memory transistor of the second flash memory cell by applying a first write voltage to the first bit line and the intermediate bit line, applying a second write voltage to the second bit line, applying a third write voltage to the first control line, applying a fourth write voltage to the word line, and applying a fifth write voltage to the second control line; and performing a write operation on the second memory transistor of the second flash memory cell by applying a second write voltage to the first bit line and the intermediate bit line, applying a first write voltage to the second bit line, applying a fifth write voltage to the first control line, applying a fourth write voltage to the word line, and applying a third write voltage to the second control line. The fourth write voltage is less than or equal to the first power supply voltage, the second write voltage is greater than or equal to the second power supply voltage, the first write voltage is higher than a preset voltage, and the third write voltage is higher than the first write voltage. The first power supply voltage is higher than the second power supply voltage. The preset voltages are determined based on the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors. The first, fourth, and fifth write voltages are higher than the second write voltage. The second write voltage is connected to the second power supply voltage by a constant current load.During a flash memory cell write operation, the first, second, third, fourth, and fifth write voltages cause all of the flash memory cell's first memory transistor, second memory transistor, and gating transistor to conduct.

[0013] As can be seen from this, the flash memory array writing method according to the present disclosure requires charging at most two bit lines to a high write voltage in a selected row of flash memory cells, thereby significantly reducing power consumption due to charging of bit line parasitic capacitance, and thus offering the advantage of lower power consumption compared to existing flash memory array writing methods. Furthermore, the low power consumption advantage of the flash memory array writing method according to the present disclosure helps to increase the number of flash memory cells that can be written in parallel, thereby improving the data write throughput rate of the flash memory array and overcoming the disadvantage of slow data writing for existing NOR flash memory.

[0014] Another aspect of the present disclosure provides a method for erasing a flash memory array according to the above aspect of the present disclosure. The erasing method includes the following first erasing step: In the first erasing step, an erasing operation is performed on the first memory cell and the first memory transistor of the second flash memory cell by applying a first erasing voltage to the first bit line, the intermediate bit line and the second bit line, applying a second erasing voltage to the first control line, and applying a second power supply voltage to the word line and the second control line or leaving the word line and the second control line floating; and an erasing operation is performed on the first memory cell and the second memory transistor of the second flash memory cell by applying a first erasing voltage to the first bit line, the intermediate bit line and the second bit line, applying a second power supply voltage to the word line and the first control line or leaving the word line and the first control line floating, and applying a second erasing voltage to the second control line. The first erasing voltage is higher than a preset voltage, and the second erasing voltage is less than or equal to the second power supply voltage. The preset voltage is determined based on the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors.

[0015] The disclosed method for erasing a flash memory array has the advantages of improving the threshold voltage window of the erasing operation, enhancing the reliability of the memory, and having low operating power consumption and a fast erasing speed.

[0016] However, the effects of this disclosure are not limited to those described above, and various developments are possible without departing from the spirit and scope of this disclosure. It should be understood that both the above general description and the following detailed description are illustrative and explanatory, and are intended to provide a further explanation of the invention as described in the claims. [Brief explanation of the drawing]

[0017] The accompanying drawings, included to provide a further understanding of the present invention and incorporated herein and constituting part thereof, illustrate exemplary embodiments of the present invention and, together with the specification, help to illustrate the idea of ​​the present invention. [Figure 1] A cross-sectional view of a flash memory cell according to an embodiment of the present disclosure is shown. [Figure 2] An equivalent circuit diagram of a flash memory cell according to an embodiment of this disclosure is shown. [Figure 3] A schematic circuit diagram of a flash memory cell pair according to the first embodiment of this disclosure is shown. [Figure 4] A schematic circuit diagram of a flash memory array according to the first embodiment of this disclosure is shown. [Figure 5] A schematic diagram of an example layout of a bit line set according to the first embodiment of this disclosure is shown. [Figure 6] A schematic diagram of another example of a bit line set layout according to the first embodiment of this disclosure is shown. [Figure 7] A schematic circuit diagram of a flash memory cell pair according to a second embodiment of this disclosure is shown. [Figure 8] A schematic circuit diagram of a flash memory array according to a second embodiment of this disclosure is shown. [Figure 9] A schematic diagram of an example layout of a bit line set according to a second embodiment of this disclosure is shown. [Figure 10] A schematic diagram of an example of the control line layout of a flash memory array according to an embodiment of this disclosure is shown. [Figure 11] An equivalent circuit diagram is shown for performing a write operation on the first memory transistor in a flash memory cell according to an embodiment of the present disclosure. [Figure 12] This diagram shows a schematic representation of performing a write operation on the first memory transistor of the first flash memory cell according to an embodiment of the present disclosure. [Figure 13] This diagram shows a schematic representation of performing a write operation on the second memory transistor of the first flash memory cell according to an embodiment of the present disclosure. [Figure 14] This diagram shows a schematic representation of performing a write operation on the first memory transistor of the second flash memory cell according to an embodiment of the present disclosure. [Figure 15]A schematic diagram showing an operation of performing a write operation on a second memory transistor of a second flash memory cell according to an embodiment of the present disclosure is shown. [Figure 16] A schematic diagram showing a principle of performing an erase operation on a first memory transistor through a first erase step according to an embodiment of the present disclosure is shown. [Figure 17] A schematic diagram showing a principle of simultaneously performing an erase operation on a first memory transistor and a second memory transistor through a second erase step according to an embodiment of the present disclosure is shown. [Figure 18] A schematic diagram showing a principle of simultaneously performing an erase operation on a first memory transistor and a second memory transistor through a third erase step according to an embodiment of the present disclosure is shown. [Figure 19] A schematic diagram showing an operation of performing an erase operation on a first memory transistor of a first flash memory cell and a second flash memory cell through a first erase step according to an embodiment of the present disclosure is shown. [Figure 20] A schematic diagram showing an operation of performing an erase operation on a second memory transistor of a first flash memory cell and a second flash memory cell through a first erase step according to an embodiment of the present disclosure is shown. [Figure 21] A schematic diagram showing an operation of performing an erase operation on a first flash memory cell and a second flash memory cell through a second erase step according to an embodiment of the present disclosure is shown. [Figure 22] A schematic diagram showing an operation of performing an erase operation on a first flash memory cell and a second flash memory cell through a third erase step according to an embodiment of the present disclosure is shown. [Figure 23] A flowchart of an erase method for a flash memory array according to an embodiment of the present disclosure is shown.

Embodiments for Carrying Out the Invention

[0018] In the following description, numerous specific details are provided to give a complete understanding of various exemplary embodiments or implementations of the invention for illustrative purposes. As used herein, “embodiments” and “implementations” are interchangeable terms and are non-limiting examples of devices or methods using one or more of the ideas of the invention disclosed herein. However, it is clear that exemplary embodiments can be implemented without these specific details, or with one or more equivalent configurations. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessarily confusing the various exemplary embodiments. Furthermore, each exemplary embodiment may differ but is not necessarily exclusive. For example, certain shapes, arrangements, and characteristics of an exemplary embodiment may be used or implemented in other exemplary embodiments without departing from the ideas of the invention.

[0019] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features that provide details of several ways in which the idea of ​​the present invention can be put into practice. Accordingly, unless otherwise stated, features, members, modules, layers, films, panels, regions and / or aspects (hereinafter referred to individually or collectively as “elements”) of various embodiments can be additionally combined, separated, replaced and / or rearranged without departing from the idea of ​​the present invention.

[0020] The use of crosshatching and / or shadowing in drawings is typically provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshatching or shadowing cannot convey or indicate any preference or requirement for specific materials, material properties, sizes, proportions, commonalities between shown elements, and / or any other properties, attributes, or shapes of elements. Furthermore, drawings may exaggerate the size and relative sizes of elements for clarity and / or explanatory purposes. Where exemplary embodiments can be realized in different ways, specific processing sequences may be performed in a different order than described. For example, two processes described consecutively may be performed substantially simultaneously or in the reverse order of description. Similarly, the same reference number represents the same element.

[0021] When an element such as a layer is said to be "located on top of," "connected to," or "joined" another element or layer, it may be directly located on top of the other element or layer, directly connected to or joined to the other element or layer, or there may be an intervening element or layer. Naturally, when an element or layer is said to be "directly located on top of," "directly connected to," or "directly joined" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical, and / or fluid connection, regardless of the presence or absence of an intervening element. Also, the D1, D2, and D3 axes may be interpreted more broadly than being limited to three axes like the x, y, and z axes of a Cartesian coordinate system. For example, the D1, D2, and D3 axes may be perpendicular to each other, or they may point in different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as X only, Y only, Z only, and any combination of two or more of X, Y, and Z, e.g., XYZ, XYY, YZ, and ZZ. Where used herein, the term “and / or” includes any and all combinations of one or more of the listed items relating to the disclosure.

[0022] In this specification, terms such as “first,” “second,” etc., may be used to describe various types of elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, the first element described below may be called the second element without departing from the teachings of this disclosure.

[0023] Spatial relation terms such as “below,” “downward,” “bottom,” “below,” “upward,” “up,” “higher,” and “side” (e.g., “side wall”) may be used herein to describe the relationship between one element and another, as shown in the figures. Spatial relation terms are intended to encompass different orientations in the use, operation, and / or manufacture of the apparatus other than the orientation shown in the drawings. For example, if the apparatus in the drawings is inverted, the element described as “below” or “below” the other element or feature will be oriented towards the other element or feature “upward.” Thus, the exemplary term “below” may encompass both upward and downward orientations. The apparatus may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relation descriptions used herein should be interpreted accordingly.

[0024] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit them. Where used herein, the singular forms “one,” “one,” and “the” also include the plural form unless the context clearly indicates otherwise. Furthermore, where used herein, the terms “include” and / or “contain” indicate the presence of a described feature, integer, step, operation, element, component, and / or group thereof, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, where used herein, “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that would be recognized by those skilled in the art.

[0025] Several exemplary embodiments are described and shown in the drawings in terms of functional blocks, units, and / or modules, in accordance with the conventions of the art. Those skilled in the art will know that these blocks, units, and / or modules can be physically realized by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardware circuits, memory elements, and wiring connections. When blocks, units, and / or modules are realized by microprocessors or other similar hardware that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques, software (e.g., microcode) may be used to write to and control them to perform the various functions described herein, and they may optionally be driven by firmware and / or software. Each block, unit, and / or module may be realized by dedicated hardware, or as a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) performing other operations. Furthermore, without departing from the scope of the idea of ​​the present invention, each block, unit, and / or module in some exemplary embodiments can be physically divided into two or more interactive discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the idea of ​​the present invention, some exemplary embodiments of blocks, units, and / or modules can be physically combined into more complex blocks, units, and / or modules.

[0026] Herein, each embodiment will be described with reference to cross-sectional and / or exploded views. The cross-sectional and / or exploded views are schematic diagrams of idealized embodiments and / or intermediate structures. As such, variations in the illustrated shape due to manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to specific illustrated shapes of areas, including, for example, variations in shape due to manufacturing. Thus, the areas shown in the drawings may be essentially schematic, and the shapes of these areas may not reflect the actual shapes of areas in the apparatus, and this is not necessarily intended as a limitation.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art of the field to which this disclosure belongs. Terms as defined in commonly used dictionaries shall be construed to have the meaning consistent with their meaning in the context of the relevant art, and not to be construed in an idealized or overly formal sense unless expressly limited herein.

[0028] Figure 1 shows a cross-sectional view of the flash memory cell MC 100 according to an embodiment of the present disclosure.

[0029] As shown in Figure 1, the flash memory cell MC 100 according to the embodiment of the present disclosure may include a substrate 101, the substrate 101 including a second doped deep well region DNW 103 and a first doped well region PW 102 placed on the deep well region DNW 103.

[0030] In Figure 1, the first doping type is defined as type P and the second doping type as type N as an example. However, as those skilled in the art will understand, the disclosure is not limited thereto, and the first doping type may be type N, in which case the second doping type may be type P.

[0031] According to embodiments of this disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0032] Furthermore, the flash memory cell MC 100 includes a first storage transistor MS 110, a gating transistor MG 120, and a second storage transistor MD 130, connected in series in order. The first storage transistor MS 110 is located on the well area PW 102 and can store the first data DATA1. The second storage transistor MD 130 is located on the well area PW 102 and can store the second data DATA2. The gating transistor MG 120 is located on the well area PW 102 along the horizontal direction DR1 between the first storage transistor MS 110 and the second storage transistor MD 130 and is used to isolate the first storage transistor MS 110 and the second storage transistor MD 130 and to perform a gating operation on the first storage transistor MS 110 and the second storage transistor MD 130.

[0033] According to embodiments of this disclosure, since the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, the flash memory cell MC 100 can realize 2-bit storage functionality, that is, it can simultaneously store first data DATA1 and second data DATA2.

[0034] Furthermore, as shown in Figure 1, the source region of the first memory transistor MS 110 is connected to the first electrode S of the flash memory cell MC 100, which may also be called the source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which may also be called the drain D of the flash memory cell MC 100.

[0035] Those skilled in the art will recognize that, for the sake of ease of explanation, the sources and drains of flash memory cells are limited herein, but that these limitations are relative and the terms “source” and “drain” can be used interchangeably under different operating conditions.

[0036] Furthermore, as shown in Figure 1, the first memory transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask lock portion 117, which are sequentially arranged along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage medium layer 114, and a second oxide layer 115, which are sequentially stacked along the vertical direction. Similarly, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask lock portion 137, which are sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage medium layer 134, and a second oxide layer 135, which are sequentially stacked along the vertical direction.

[0037] According to embodiments of this disclosure, the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, thereby enabling 2-bit storage functionality.

[0038] According to embodiments of the present disclosure, as shown in Figure 1, the flash memory cell MC 100 for 2-bit storage may consist of three closely spaced transistors: a gating transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS 110 located at the first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at the second end of the flash memory cell MC 100.

[0039] As shown in Figure 1, the flash memory cell MC 100 may be formed on a well region PW 102 within a semiconductor substrate 101. Alternatively, to isolate the well region PW 102 from the substrate 101 and apply a voltage to the well region PW 102 under specific operating conditions, the well region PW 102 may be formed within a deep well region DNW 103, as shown in Figure 1.

[0040] As shown in Figure 1, a source region 140 formed by N-type doping is installed at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is installed at the second end of the flash memory cell MC 100. The source region 140 is connected to a metal source 142 located in the upper layer, i.e., the first electrode S, via a contact hole 141, and the drain region 150 is connected to a metal drain 152 located in the upper layer, i.e., the second electrode D, via a contact hole 151.

[0041] According to embodiments of the present disclosure, the first electrode S and the second electrode D may contain metal or highly doped polycrystalline silicon. If the first electrode S and the second electrode D are formed of metal, they may contain at least one of aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0042] As described above, as shown in Figure 1, the gate structure of the first memory transistor MS 110 may have, in order from bottom to top, a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask lock portion 117 for sidewall self-alignment. According to embodiments of this disclosure, the gate electrode 116 may include, for example, polycrystalline silicon, a metal gate, a metal silicide material, or a combination of the above materials. According to embodiments of this disclosure, the hard mask lock portion 117 may include, for example, silicon oxide, silicon nitride, silica glass material, or a combination of the above materials.

[0043] Furthermore, as shown in Figure 1, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a memory medium layer (charge storage layer) 114, and a second oxide layer (barrier oxide layer) 115 stacked in order along the vertical direction. According to embodiments of this disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide.

[0044] According to embodiments of the present disclosure, the storage medium layer 114 may include a single-layer or multi-layer storage medium. Furthermore, according to embodiments of the present disclosure, the storage medium forming the storage medium layer 114 may include a single- or multi-component oxide such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; a single- or multi-component nitride such as silicon nitride; a single- or multi-component nitrogen oxide such as silicon oxynitride; polycrystalline silicon or nanocrystalline material; or a combination of the above materials.

[0045] According to embodiments of this disclosure, if the storage medium layer 114 is formed from, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may be formed as a gate dielectric stack 112 of an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS 110 may be a SONOS type storage transistor.

[0046] Furthermore, according to embodiments of this disclosure, the first memory transistor MS 110 may be another trap charge trapping memory transistor having an operating mechanism similar to that of a SONOS-type memory transistor. This type of memory transistor uses a charge trap-rich High-K material such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide as the memory medium layer 114, instead of the silicon nitride material used in SONOS memory.

[0047] Furthermore, according to embodiments of this disclosure, the first memory transistor MS 110 may be a floating-gate type memory transistor. This type of memory transistor uses a polycrystalline silicon material instead of the silicon nitride material in SONOS memory to form a floating gate for storing charge as a memory medium layer 114.

[0048] Furthermore, according to embodiments of this disclosure, the first memory transistor MS 110 may be a nano-crystal memory transistor. This type of memory transistor uses a nano-crystal material having quantum dots as the memory medium layer 114 instead of the silicon nitride material in SONOS memory.

[0049] According to embodiments of this disclosure, the length of the gate electrode 116 of the first memory transistor MS 110 may be limited by the length of a hard mask lock portion 117 placed on the gate electrode 116 by a self-alignment process. Those skilled in the art should note that “length” as used herein means the size in the horizontal direction DR1 of the object being described.

[0050] According to embodiments of this disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS 110, except that it is located on the opposite side of the gating transistor MG 120, and can be manufactured using the same process as the first memory transistor MS 110. For the sake of simplicity, a detailed description of the structure of the second memory transistor MD 130 is omitted.

[0051] The gate structure of the gating transistor MG 120 may include, in order from bottom to top, a channel region 121, a gate dielectric layer 122, and a gate electrode 123. According to embodiments of this disclosure, the gate electrode 123 of the gating transistor MG 120 is connected to a word line, and the length of the gate electrode 123 is limited by the process size of the photolithography process. According to embodiments of this disclosure, the gate dielectric layer 122 may include, for example, silicon oxide, silicon oxynitride, or hafnium oxide. Also according to embodiments of this disclosure, the gate electrode 123 may include, for example, polycrystalline silicon, a metal gate, a metal silicide material, or a combination of the above materials.

[0052] According to embodiments of the present disclosure, the channel regions 111, 131, and 121 of the first memory transistor MS 110, the second memory transistor MD 130, and the gating transistor MG 120 may all have a first doping type, and the doping concentrations of the channel regions 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gating transistor MG 120.

[0053] Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gating transistor MG 120 may have a first doping type different from the second doping type.

[0054] For example, as shown in Figure 1, when the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gating transistor MG 120. Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 may be undoped intrinsic channels or N-type doped channel regions.

[0055] According to embodiments of the present disclosure, the flash memory cell MC 100 further includes a first isolation section 124 and a second isolation section 125. The first isolation section 124 is located between the first storage transistor MS 110 and the gating transistor MG 120 along the horizontal direction DR1 and is used to isolate the gate electrode 116 of the first storage transistor MS 110 from the gate electrode 123 of the gating transistor MG 120. The second isolation section 125 is located between the gating transistor MG 120 and the second storage transistor MD 130 along the horizontal direction DR1 and is used to isolate the gate electrode 123 of the gating transistor MG 120 from the gate electrode 136 of the second storage transistor MD 130.

[0056] Specifically, as shown in Figure 1, a first isolation portion 124 and a second isolation portion 125 in the form of side walls are provided on both sides of the gate electrode 123 of the gating transistor MG 120, and they are used to electrically isolate the gate electrode 116 of the first memory transistor MS 110 and the gate electrode 136 of the second memory transistor MD 130 by a specific isolation gap length. According to embodiments of this disclosure, the first isolation portion 124 and the second isolation portion 125 may contain the same material as the gate dielectric layer 122.

[0057] The flash memory cell according to the embodiments of this disclosure can realize two memory transistors in a single flash memory cell, thereby significantly reducing the equivalent area of ​​each memory bit, and consequently achieving lower costs and higher integration density.

[0058] Furthermore, the memory transistor in the flash memory cell according to the embodiments of this disclosure can employ a simple SONOS-type device structure, has the advantages of a simple process, a low gate electrode operating voltage, and good data retention reliability.

[0059] Furthermore, in the flash memory cell according to the embodiments of this disclosure, the mutual influence of the two memory bits is isolated by a gating transistor, and the distribution width of the stored charge and lateral diffusion are suppressed, thereby enabling a higher stored charge density in the silicon nitride memory layer. This avoids problems such as a wide charge distribution, large mutual interference, and inability to shorten the gate length that exist in existing NROM memory cells employing 2-bit storage, and significantly improves the storage window and data reliability.

[0060] In particular, the equivalent channel length of the flash memory cell according to the embodiments of this disclosure is the sum of the lengths of the gate electrodes of the first memory transistor, the gating transistor, and the second memory transistor. As described above, the gate electrode length of the gating transistor is limited by the process feature size of the photolithography process, and is usually approximately equal to or slightly larger than the critical feature size of the photolithography process, and is usually expressed as F (or CF). Also, the gate electrode lengths of the first and second memory transistors are limited by the length of the self-aligning sidewall hard mask stop, and their sizes may be smaller than F. Therefore, according to the embodiments of this disclosure, a shorter channel length of the flash memory cell can be obtained with the same process feature size, thereby achieving the objective of reducing the area and manufacturing cost of the flash memory cell.

[0061] Furthermore, in a flash memory array composed of flash memory cells according to embodiments of this disclosure, the gate electrodes of the gating transistor and the first and second memory transistors are both grounded for flash memory cells that are not selected for operation. As a result, the entire series channel of the flash memory cells is completely turned off, and the equivalent channel length is increased. Therefore, source-drain punch-through of the flash memory cells under high operating voltages can be avoided with a smaller process feature size, thereby overcoming the problem that the gate electrode length of existing flash memory cells cannot be reduced in conjunction with the reduction in process feature size. Consequently, the flash memory cells according to embodiments of this disclosure have better process miniaturization capabilities, thereby enabling smaller unit area and manufacturing costs by reducing the process feature size.

[0062] Furthermore, in the flash memory cell according to the embodiments of this disclosure, the threshold voltage of the memory transistors and the gate electrode operating voltage during erase and write operations can be lowered by reducing the doping concentration of the P-type channel regions of the first and second memory transistors, or by designing them as N-type doped channel regions, thereby improving the reliability of the memory transistors. At the same time, by increasing the doping concentration of the P-type channel region of the gating transistor, the punch-through voltage tolerance of the flash memory cell can be improved, and the leakage current between the source region and drain region of the unselected flash memory cell can be reduced.

[0063] Figure 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to an embodiment of the present disclosure.

[0064] Specifically, as shown in Figure 2, the flash memory cell MC 100 includes a first memory transistor MS 110, a gating transistor MG 120, and a second memory transistor MD 130, connected in series in order. The gating transistor MG 120 isolates the first memory transistor MS 110 and the second memory transistor MD 130, and can perform gating operations on the first memory transistor MS 110 and the second memory transistor MD 130.

[0065] Figure 3 shows a schematic circuit diagram of a flash memory cell pair 200 according to a first embodiment of the present disclosure. Figure 4 shows a schematic circuit diagram of a flash memory array according to a first embodiment of the present disclosure.

[0066] According to embodiments of the present disclosure, a flash memory array may include a plurality of flash memory cells arranged along row directions and column directions orthogonal to the row directions, a plurality of word line sets extending along row directions, and a plurality of bit line sets extending along column directions. Flash memory cell pairs are provided at the intersections of the word line sets and bit line sets. A flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row direction and share the same bit line set.

[0067] As shown in Figures 3 and 4, according to embodiments of the present disclosure, a flash memory array may include a plurality of flash memory cells as shown in Figure 2. These flash memory cells are arranged in an m × 2n array along the row direction and the column direction orthogonal to the row direction, where m and n are natural numbers greater than 1. Thus, the plurality of flash memory cells form an m row × 2n column flash memory array.

[0068] As shown in Figure 3, according to embodiments of the present disclosure, two adjacent flash memory cells in the row direction may form a flash memory cell pair 200 including a first flash memory cell 210 and a second flash memory cell 220. For example, the first flash memory cell 210 may be a flash memory cell located in the 0th row and 0th column of the flash memory array, and the second flash memory cell 220 may be a flash memory cell located in the 0th row and 1st column of the flash memory array. Therefore, according to embodiments of the present disclosure, the flash memory array may include flash memory cell pairs arranged in an m-row × n-column configuration.

[0069] The first flash memory cell 210 includes a first memory transistor 211, a gating transistor 212, and a second memory transistor 213 connected in series in the column direction. The second flash memory cell 220 includes a first memory transistor 221, a gating transistor 222, and a second memory transistor 223 connected in series in the column direction.

[0070] According to embodiments of this disclosure, in the first flash memory cell 210, the source region of the first memory transistor 211 is connected to the first electrode S1 of the first flash memory cell 210, and the drain region of the second memory transistor 213 is connected to the second electrode D1 of the first flash memory cell 210.

[0071] Furthermore, according to the embodiments of this disclosure, in the second flash memory cell 220, the source region of the first memory transistor 221 is connected to the first electrode S2 of the second flash memory cell 220, and the drain region of the second memory transistor 223 is connected to the second electrode D2 of the second flash memory cell 220.

[0072] Furthermore, according to embodiments of the present disclosure, a flash memory cell pair 200, i.e., a pair of a first flash memory cell 210 and a second flash memory cell 220, shares a set of bit lines extending along the column direction. This set of bit lines includes a first bit line BSL0, an intermediate bit line BLM0, and a second bit line BLD0. According to a first embodiment of the present disclosure, the first bit line BSL0 may be connected to a first electrode S1 of the first flash memory cell 210, the second bit line BLD0 may be connected to a second electrode D2 of the second flash memory cell 220, and the intermediate bit line BLM0 may be connected to a second electrode D1 of the first flash memory cell 210 and a first electrode S2 of the second flash memory cell 220.

[0073] As described above, according to embodiments of the present disclosure, the row-adjacent first flash memory cell 210 and the second flash memory cell 220 are connected to the same first bit line BSL0, intermediate bit line BLM0, and second bit line BLD0. In other words, according to embodiments of the present disclosure, in a flash memory array, flash memory cell pairs share the same set of bit lines. For example, the flash memory cell in the 0th column and the flash memory cell in the 1st column share a set of bit lines including the first bit line BLS0, intermediate bit line BLM0, and second bit line BLD0, the flash memory cell in the 2nd column and the flash memory cell in the 3rd column share a set of bit lines including the first bit line BLS1, intermediate bit line BLM1, and second bit line BLD1, and so on, the flash memory cell in the 2n-2nd column and the flash memory cell in the 2n-1st column share the same set of bit lines <n-1>, intermediate bit line BLM <n-1>and the second bit line BLD <n-1>They end up sharing a set of bit lines that includes this.

[0074] Furthermore, according to embodiments of the present disclosure, the flash memory array further includes a plurality of word line sets extending along the row direction. Each word line set includes a first control line, a word line, and a second control line, where the first control line is connected to the gate electrode of a first memory transistor of a flash memory cell pair, the word line is connected to the gate electrode of a gating transistor of a flash memory cell pair, and the second control line is connected to the gate electrode of a second memory transistor of a flash memory cell pair.

[0075] According to embodiments of the present disclosure, in a flash memory array, flash memory cells (pairs) in the same row share the same set of word lines, namely the first control line, word line, and second control line.

[0076] As shown in Figures 3 and 4, taking flash memory cell pair 200 as an example, the flash memory cell pair 200, i.e., the first flash memory cell 210 and the second flash memory cell 220, is located in row 0 and shares the same set of word lines, i.e., the first control line MS0, the word line WL0, and the second control line MD0, as other flash memory cells (pairs) in row 0. The first control line MS0 is connected to the gate electrodes of the first memory transistors 211 and 221 of the first flash memory cell 210 and the second flash memory cell 220, the word line WL0 is connected to the gate electrodes of the gating transistors 212 and 222 of the first flash memory cell 210 and the second flash memory cell 220, and the second control line MD0 is connected to the gate electrodes of the second memory transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220.

[0077] Similarly, the gate electrodes of the first memory transistors in the first row of flash memory cells (pairs) are both connected to the first control line MS1, the gate electrodes of the gating transistors in the first row of flash memory cells are both connected to the word line WL1, and the gate electrodes of the second memory transistors in the first row of flash memory cells are both connected to the second control line MD1. Similarly, the gate electrodes of the first memory transistors in the (m-2) row of flash memory cells are both connected to the first control line MS <m-2>The gate electrodes of the gating transistors in the m-2 row of flash memory cells are connected to the word line WL. <m-2>The gate electrodes of the second memory transistor in the m-2 row flash memory cell are connected to the second control line MD. <m-2>It is connected to the first control line MS. Similarly, the gate electrode of the first memory transistor in the (m-1)th row of flash memory cells is connected to the first control line MS. <m-1>The gate electrodes of the gating transistors in the m-1 row of flash memory cells are connected to the word line WL. <m-1>The gate electrodes of the second memory transistor in the (m-1)-th row of the flash memory cell are connected to the second control line MD. <m-1>It connects to the network.

[0078] Those skilled in the art will understand the following: Because the flash memory cells according to the embodiments of this disclosure have a symmetric structure, adjacent flash memory cells in the column direction are arranged opposite each other based on the connection relationships of the first control line, word line, second control line, first bit line, intermediate bit line, and second bit line described above. That is, the first storage transistor of the flash memory cell in the current row is adjacent in the column direction to the first storage transistor of the flash memory cell in the previous row, and the second storage transistor of the flash memory cell in the current row is adjacent in the column direction to the second storage transistor of the flash memory cell in the next row. Alternatively, the second storage transistor of the flash memory cell in the current row is adjacent in the column direction to the second storage transistor of the flash memory cell in the previous row, and the first storage transistor of the flash memory cell in the current row is adjacent in the column direction to the first storage transistor of the flash memory cell in the next row.

[0079] Figure 5 shows a schematic diagram of an example layout of a bit line set according to the first embodiment of this disclosure.

[0080] According to embodiments of the present disclosure, the first control line, word line, and second control line may be formed from at least one of polycrystalline silicon, silicide, and metal gate. Furthermore, according to embodiments of the present disclosure, the intermediate bit line may be formed from a first metal layer, and the first and second bit lines may be formed from a second metal layer different from the first metal layer. In other words, the metal layer used to form the intermediate bit line is different from the metal layer used to form the first and second bit lines. Alternatively, the first and second bit lines may be formed from the same metal layer.

[0081] According to embodiments of the present disclosure, the first metal layer and the second metal layer may contain at least one of aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0082] According to embodiments of the present disclosure, the intermediate bit line may include a first portion extending in the column direction and a second portion extending in the row direction, wherein the first bit line and the second bit line extend in the column direction.

[0083] As shown in Figure 5(a), taking the flash memory cell pair 200 as an example, the first electrodes S1 and S2 and the second electrodes D1 and D2 of the first flash memory cell 210 and the second flash memory cell 220 may be formed of a first metal layer M1 positioned above, for example, a first control line MS0, a word line WL0, and a second control line MD0 of polycrystalline silicon. As shown in Figure 5, the first control line MS0, the word line WL0, and the second control line MD0 extend parallel to each other in the row direction.

[0084] Furthermore, as shown in Figure 5(a), the intermediate bit line BLM0 is formed in a continuous "Z" shape in the column direction by the first metal layer M1, and includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction. According to the embodiments of this disclosure, the second portion P2 of the intermediate bit line BLM0 can overlap with the word line WL0 below it.

[0085] Furthermore, as shown in Figure 5(b), the first bit line BLS0 and the second bit line BLD0 are formed in the column direction by the second metal layer M2 and can overlap with the first portion P1 of the intermediate bit line BLM0.

[0086] According to embodiments of the present disclosure, the electrical connection between the first bit line BLS0 and the first electrode S1 of the first flash memory cell 210 can be achieved through a through-hole V1 between the first metal layer M1 and the second metal layer M2, and the electrical connection between the second bit line BLD0 and the second electrode D2 of the second flash memory cell 220 can be achieved through a through-hole V1 between the first metal layer M1 and the second metal layer M2.

[0087] According to embodiments of this disclosure, the first portion P1 of the intermediate bit line can overlap with the first and second bit lines, and the second portion P2 of the intermediate bit line can overlap with the row-direction polycrystalline silicon word line. This eliminates the need for additional area to provide the intermediate bit line, resulting in a more compact flash memory array. Furthermore, since both the first and second bit lines are formed from metal, there is no need for a common source line as in the prior art, thereby further reducing the area of ​​the flash memory array.

[0088] In the embodiment shown in Figure 5, two metal layers are used to arrange the first bit line, intermediate bit line, and second bit line. However, the disclosure is not limited thereto. According to embodiments of the disclosure, depending on the application of the flash memory array, more metal layers can be used to arrange the first bit line, intermediate bit line, and second bit line.

[0089] Figure 6 shows a schematic diagram of another example of a bit line set layout according to the first embodiment of the present disclosure.

[0090] Specifically, as shown in Figure 6(a), the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 positioned above, for example, the first control line, word line, and second control line of polycrystalline silicon. Unlike in Figure 5, as shown in Figure 6(c), the intermediate bit line may be formed in a continuous "Z" shape in the column direction by a third metal layer M3. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

[0091] Furthermore, as shown in Figure 6(d), the first and second bit lines are formed in the column direction by the fourth metal layer M4 and overlap with the first portion P1 of the intermediate bit line along the column direction. As shown in Figure 6(b), the electrical connection between the intermediate bit line and the first and second electrodes can be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3, and through holes V1 and V2 between each metal layer M1 to M3. Also, as shown in Figures 6(b) and (c), the electrical connection between the first bit line and the first electrode can be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4, and through holes V1 to V3 between each metal layer M1 to M4. Furthermore, as shown in Figures 6(b) and 6(c), the electrical connection between the second bit line and the second electrode can also be realized through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4, as well as through holes V1 to V3 between each metal layer M1 to M4.

[0092] Compared to the bit line layout of the two metal layers shown in Figure 5, the bit line layout of the four metal layers shown in Figure 6 allows for greater flexibility in the layout of the first bit line, intermediate bit line, and second bit line.

[0093] Furthermore, those skilled in the art will understand that the bit line arrangement of the flash memory array according to this disclosure requires at least two metal layers, and therefore, although Figure 6 shows an embodiment in which four metal layers are used to realize the bit line arrangement of the flash memory array according to this disclosure, the disclosure is not limited thereto. Those skilled in the art can, based on the teachings of this disclosure, realize the bit line arrangement of the flash memory array according to this disclosure using three or five or more metal layers.

[0094] Figure 7 shows a schematic circuit diagram of a flash memory cell pair 300 according to a second embodiment of the present disclosure. Figure 8 shows a schematic circuit diagram of a flash memory array according to a second embodiment of the present disclosure.

[0095] As shown in Figure 7, according to embodiments of the present disclosure, two adjacent flash memory cells in the row direction may form a flash memory cell pair 300 including a first flash memory cell 310 and a second flash memory cell 320. For example, the first flash memory cell 310 may be a flash memory cell located in the 0th row and 0th column of the flash memory array, and the second flash memory cell 320 may be a flash memory cell located in the 0th row and 1st column of the flash memory array. Therefore, according to embodiments of the present disclosure, the flash memory array may include flash memory cell pairs arranged in an m-row × n-column configuration.

[0096] The first flash memory cell 310 includes a first memory transistor 311, a gating transistor 312, and a second memory transistor 313 connected in series in the column direction. The second flash memory cell 320 includes a first memory transistor 321, a gating transistor 322, and a second memory transistor 323 connected in series in the column direction.

[0097] According to embodiments of this disclosure, in the first flash memory cell 310, the source region of the first memory transistor 311 is connected to the first electrode S1 of the first flash memory cell 310, and the drain region of the second memory transistor 313 is connected to the second electrode D1 of the first flash memory cell 310.

[0098] Furthermore, according to the embodiments of this disclosure, in the second flash memory cell 320, the source region of the first memory transistor 321 is connected to the first electrode S2 of the second flash memory cell 320, and the drain region of the second memory transistor 323 is connected to the second electrode D2 of the second flash memory cell 320.

[0099] The flash memory cell pairs and flash memory arrays of the second embodiment of the present disclosure shown in Figures 7 and 8 are essentially the same as the flash memory cell pairs and flash memory arrays of the first embodiment of the present disclosure shown in Figures 3 and 4, except that the connection method of the bit line sets of the flash memory cell pairs is different.

[0100] Specifically, as shown in Figures 7 and 8, according to the second embodiment of the present disclosure, the first bit line BSL0 may be connected to the second electrode D1 of the first flash memory cell 310, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 320, and the intermediate bit line BLM0 may be connected to the first electrode S1 of the first flash memory cell 310 and the first electrode S2 of the second flash memory cell 320.

[0101] Figure 9 shows a schematic diagram of an example layout of a bit line set according to a second embodiment of the present disclosure.

[0102] Specifically, as shown in Figure 9(a), the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 positioned above, for example, the first control line, word line, and second control line of polycrystalline silicon. As shown in Figure 9(c), the intermediate bit line may be formed in a continuous "Z" shape in the column direction by a third metal layer M3. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

[0103] Furthermore, as shown in Figure 9(d), the first and second bit lines are formed in the column direction by the fourth metal layer M4 and overlap with the first portion P1 of the intermediate bit line along the column direction. As shown in Figure 9(b), the electrical connection between the intermediate bit line and the first electrode can be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3, and through holes V1 and V2 between each metal layer M1 to M3. Also, as shown in Figures 9(b) and (c), the electrical connection between the first bit line and the second electrode can be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4, and through holes V1 to V3 between each metal layer M1 to M4. Furthermore, as shown in Figures 9(b) and (c), the electrical connection between the second bit line and the second electrode can also be realized through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4, as well as through holes V1 to V3 between each metal layer M1 to M4.

[0104] The flash memory array according to the above embodiments of this disclosure can increase the bit line arrangement density and reduce bit line parasitic resistance without increasing the size of the array. Furthermore, compared to conventional flash memory arrays, the flash memory array according to this disclosure also has better process compatibility and miniaturization characteristics.

[0105] Furthermore, according to embodiments of this disclosure, adjacent first or second control lines in the column direction may be connected to each other via a metal layer. Figure 10 shows a schematic diagram of an example of a control line layout for a flash memory array according to embodiments of this disclosure.

[0106] As shown in Figure 10, for example, based on the flash memory array shown in Figure 4, adjacent first control lines can be connected together in the column direction using a first metal control line MCS<0:m / 2-1> formed by a metal layer. Furthermore, adjacent second control lines in the column direction can be connected together using a second metal control line MCD<1:m / 2> formed by the same metal layer.

[0107] According to embodiments of the present disclosure, the metal layer used to form the first metal control line MCS<0:m / 2-1> and the second metal control line MCD<1:m / 2> may be different from the metal layer used to form the bit lines (including the first bit line, the intermediate bit line, and the second bit line). According to embodiments of the present disclosure, the metal layer used to form the first metal control line MCS<0:m / 2-1> and the second metal control line MCD<1:m / 2> may be located above the metal layer used to form the bit lines (including the first bit line, the intermediate bit line, and the second bit line).

[0108] According to embodiments of this disclosure, two adjacent flash memory cells in the column direction can share a control line (first or second control line) via a metal control line (first or second metal control line). By connecting the first and second control lines using the first and second metal control lines, the parasitic resistance of the first and second control lines, for example, polycrystalline silicon, can be effectively reduced, thereby effectively improving the operating speed of the flash memory array. Furthermore, by connecting the first and second control lines using the first and second metal control lines, the wiring density and process complexity of the metal control lines can be reduced. In addition, such a flash memory array that shares control lines can also reduce the number of peripheral circuits of the flash memory array for controlling the control lines, thereby reducing the area overhead of the peripheral circuits and the manufacturing cost of the memory chip.

[0109] Those skilled in the art will understand that, although the flash memory array of the present disclosure has been described above in relation to the flash memory cell MC 100 shown in Figure 1, the flash memory array of the present disclosure is not limited to the flash memory cell MC 100 shown in Figure 1. Those skilled in the art may, based on the teachings of the present disclosure, envision applying the flash memory array of the present disclosure to other types of flash memory cells, such as a flash memory cell containing only one storage transistor, or a flash memory cell using one storage transistor to store 2 bits of data, and all such variations are included within the scope of the present disclosure.

[0110] Figure 11 shows an equivalent circuit diagram of an embodiment of the present disclosure in which a write operation is performed on the first memory transistor in a flash memory cell.

[0111] As shown in Figure 11, a write operation to the first memory transistor MS 110 can be achieved by controlling the voltage applied to the source region (i.e., the first electrode S) of the first memory transistor MS 110, the gate electrode 116 of the first memory transistor MS 110, the gate electrode 123 of the gating transistor MG 120, the gate electrode 136 of the second memory transistor MD 130, and the drain region (i.e., the second electrode D) of the second memory transistor MD 130.

[0112] According to embodiments of this disclosure, when a write operation is performed on the flash memory cell MC 100, the well area PW 102 of the flash memory cell MC 100 may be grounded.

[0113] Specifically, according to the embodiment of the present disclosure, as shown in Figure 11, when performing a write operation on the first memory transistor MS 110 of the flash memory cell MC 100, a first write voltage VW1 is applied to the first electrode S, a second write voltage VW2 is applied to the second electrode D, a third write voltage VW3 is applied to the gate electrode 116 of the first memory transistor MS 110, a fourth write voltage VW4 is applied to the gate electrode 123 of the gating transistor MG 120, and a fifth write voltage VW5 is applied to the gate electrode 136 of the second memory transistor MD 130.

[0114] According to embodiments of the present disclosure, the first write voltage VW1 is higher than a preset voltage, which is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS 100. For example, in the flash memory cell MC 100 shown in Figure 11, the preset voltage allows electrons to cross the electron barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 contains silicon and the first oxide layer 113 contains silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 may be in the range of 3V to 6V. According to embodiments of the present disclosure, the first write voltage VW1 may be supplied by an external constant voltage source.

[0115] According to embodiments of this disclosure, the second write voltage VW2 is greater than or equal to the second power supply voltage VSS, and the second power supply voltage VSS may be the grounding voltage GND. Furthermore, according to embodiments of this disclosure, the second write voltage VW2 is connected to the second power supply voltage VSS by a constant current load. According to embodiments of this disclosure, the second power supply voltage VSS may be the grounding voltage.

[0116] According to embodiments of this disclosure, the third writing voltage VW3 is higher than the first writing voltage VW1. For example, the third writing voltage VW3 may be in the range of 4V to 12V.

[0117] According to embodiments of this disclosure, the fourth writing voltage VW4 is less than or equal to the first power supply voltage VDD, and the first power supply voltage VDD may be higher than the second power supply voltage VSS and within the range of 0.8V to 5V.

[0118] According to embodiments of this disclosure, the first write voltage VW1, the fourth write voltage VW4, and the fifth write voltage VW5 are higher than the second write voltage VW2. For example, the fifth write voltage VW5 may be in the range of 3V to 8V.

[0119] Furthermore, according to the embodiments of this disclosure, during a write operation of the flash memory cell MC 100, the first memory transistor MS 110, the second memory transistor MD 130, and the gating transistor MG 120 all become conductive due to the first to fifth write voltages VW1 to VW5.

[0120] Due to the symmetrical structure of the flash memory cell MC 100, there is also a symmetrical relationship between the write voltages VW1 to VW5 applied during the write operation of the first memory transistor MS 110 and the second memory transistor MD 130. Therefore, for the sake of brevity, the write voltage applied during the write operation of the second memory transistor MD 130 will not be explained again here.

[0121] As shown in Figure 11, by adjusting the constant current IWR of an externally connected constant current load, the conduction current IDS of the flash memory cell during writing (i.e., the current flowing between the first electrode S and the second electrode D of the flash memory cell MC 100) can be precisely controlled, thereby achieving the objective of adjusting the programming threshold voltage and improving the distribution accuracy of the write (programming) threshold voltage of the flash memory array.

[0122] According to embodiments of this disclosure, the write operation to the first memory transistor MS 110 and the second memory transistor MD 130 described above employs a channel hot electron injection mechanism with a low gate voltage.

[0123] According to embodiments of this disclosure, a constant current load can be realized by a current mirror circuit.

[0124] Specifically, as shown in Figure 11, a constant voltage VWR (i.e., first write voltage VW1) of approximately 4V is applied to the first electrode S, and a constant current load with a pull-down function (having a constant current IWR) is connected to the second electrode D to pull down the voltage at the second electrode D (i.e., second write voltage VW2) to between 0V and 1V, for example, to approximately 0.3V. Furthermore, a third write voltage VW3 of approximately 6V is applied to the gate electrode 116 of the first memory transistor MS 110, a fourth write voltage VW4 of approximately 1.2V is applied to the gate electrode 123 of the gating transistor MG 120, and a fifth write voltage VW5 of approximately 5V is applied to the gate electrode 136 of the second memory transistor MD 130, thereby making the first memory transistor MS 110, the second memory transistor MD 130, and the gating transistor MG 120 of the flash memory cell MC 100 all conduct.

[0125] Furthermore, since the gate voltage VW4 of the gating transistor MG 120 is low, the gating transistor MG 120 enters a low gate voltage saturation conduction state, and the conduction current of the gating transistor MG 120 determines the overall conduction current IDS of the flash memory cell MC 100. If the conduction current IDS of the flash memory cell MC 100 is greater than the constant current IWR of a constant current load, the gate conduction voltage (VGS = VW4 - VW2) of the gating transistor MG 120 can be reduced by charging the second electrode D of the flash memory cell MC 100 and increasing its voltage VW2, thereby reducing the conduction current IDS and allowing it to self-adaptively change to the constant current IWR of a constant current load. Conversely, if the conduction current IDS of the flash memory cell MC 100 is smaller than the constant current IWR of the constant current load, the second electrode D of the flash memory cell MC 100 discharges, causing its voltage VW2 to decrease. This increases the gate conduction voltage (VGS = VW4 - VW2) of the gating transistor MG 120, causing the conduction current IDS to increase and self-adaptively change to the constant current IWR of the constant current load.

[0126] Due to this self-adaptive effect, during programming of the flash memory cell MC 100, the conduction current IDS is always equal to the constant current IWR of a constant current load and is not affected by factors such as the threshold voltage and process deviation of the flash memory cell MC 100. Furthermore, according to the lucky electron model of the channel hot electron injection mechanism, the conduction current IDS during the write operation of the flash memory cell MC 100 according to this disclosure is constant and can be precisely controlled. Therefore, the gate programming (write) current is the conduction current IDS (equal to the constant current IWR) multiplied by the injection probability coefficient PINJ, which can be treated as a constant, thereby significantly improving the accuracy of the programming threshold voltage.

[0127] Figure 12 shows a schematic diagram illustrating a write operation performed on the first memory transistor 211 of the first flash memory cell 210 according to an embodiment of the present disclosure.

[0128] According to an embodiment of the present disclosure, as shown in Figure 12, when performing a write operation on the first memory transistor 211 of the first flash memory cell 210, for example, a first write voltage VW1 of 4V is applied to the first bit line BLS0, for example, a second write voltage VW2 of 0.2V is applied to the intermediate bit line BLM0 and the second bit line BLD0, for example, a third write voltage VW3 of 6V is applied to the first control line MS0 connected to the gate electrode of the first memory transistor 211, for example, a fourth write voltage VW4 of 1.2V is applied to the word line WL0 connected to the gate electrode of the gating transistor 212, and for example, a fifth write voltage VW5 of 5V is applied to the second control line MD0 connected to the gate electrode of the second memory transistor 213.

[0129] Figure 13 shows a schematic diagram illustrating a write operation performed on the second memory transistor 213 of the first flash memory cell 210 according to an embodiment of the present disclosure.

[0130] According to an embodiment of the present disclosure, as shown in Figure 13, when performing a write operation on the second memory transistor 213 of the first flash memory cell 210, for example, a second write voltage VW2 of 0.2V is applied to the first bit line BLS0, for example, a first write voltage VW1 of 4V is applied to the intermediate bit line BLM0 and the second bit line BLD0, for example, a fifth write voltage VW5 of 5V is applied to the first control line MS0 connected to the gate electrode of the first memory transistor 211, for example, a fourth write voltage VW4 of 1.2V is applied to the word line WL0 connected to the gate electrode of the gating transistor 212, and for example, a third write voltage VW3 of 6V is applied to the second control line MD0 connected to the gate electrode of the second memory transistor 213.

[0131] Figure 14 shows a schematic diagram illustrating a write operation performed on the first memory transistor 221 of the second flash memory cell 220 according to an embodiment of the present disclosure.

[0132] According to an embodiment of the present disclosure, as shown in Figure 14, when performing a write operation on the first memory transistor 221 of the second flash memory cell 220, for example, a first write voltage VW1 of 4V is applied to the first bit line BLS0 and the intermediate bit line BLM0, for example, a second write voltage VW2 of 0.2V is applied to the second bit line BLD0, for example, a third write voltage VW3 of 6V is applied to the first control line MS0 connected to the gate electrode of the first memory transistor 221, for example, a fourth write voltage VW4 of 1.2V is applied to the word line WL0 connected to the gate electrode of the gating transistor 222, and for example, a fifth write voltage VW5 of 5V is applied to the second control line MD0 connected to the gate electrode of the second memory transistor 223.

[0133] Figure 15 shows a schematic diagram illustrating a write operation performed on the second memory transistor 223 of the second flash memory cell 220 according to an embodiment of the present disclosure.

[0134] According to an embodiment of the present disclosure, as shown in Figure 15, when performing a write operation on the second memory transistor 223 of the second flash memory cell 210, for example, a second write voltage VW2 of 0.2V is applied to the first bit line BLS0 and the intermediate bit line BLM0, for example, a first write voltage VW1 of 4V is applied to the second bit line BLD0, for example, a fifth write voltage VW5 of 5V is applied to the first control line MS0 connected to the gate electrode of the first memory transistor 221, for example, a fourth write voltage VW4 of 1.2V is applied to the word line WL0 connected to the gate electrode of the gating transistor 222, and for example, a third write voltage VW3 of 6V is applied to the second control line MD0 connected to the gate electrode of the second memory transistor 223.

[0135] According to embodiments of the present disclosure, as shown in Figures 12 to 15, in the flash memory array writing method according to the present disclosure, when a write operation is performed on a flash memory cell pair 200, in addition to the bit line sets BLS0, BLM0, and BLD0 and word line sets MS0, WL0, and MD0 connected to the flash memory cell pair 200, other word line sets and bit line sets may be connected to a ground voltage such as 0V.

[0136] As can be seen from this, the flash memory array writing method according to the present disclosure requires charging at most two bit lines to a high write voltage in the bit line set connected to the row of selected flash memory cell pairs. This significantly reduces power consumption due to charging of bit line parasitic capacitance, resulting in a lower power consumption compared to existing flash memory array writing methods. Furthermore, the low power consumption advantage of the flash memory array writing method according to the present disclosure helps to increase the number of flash memory cells that can be written in parallel, thereby improving the data write throughput of the flash memory array and overcoming the drawback of slow data writing for existing NOR flash memory.

[0137] Those skilled in the art will understand that, although the flash memory array writing method of the present disclosure has been described above in relation to the flash memory cell MC 100 shown in Figure 1, the flash memory array writing method of the present disclosure is not limited to the flash memory cell MC 100 shown in Figure 1. Those skilled in the art may, based on the teachings of the present disclosure, envision applying the flash memory array writing method of the present disclosure to other types of flash memory cells, such as a flash memory cell containing only one storage transistor, or a flash memory cell that uses one storage transistor to store 2-bit data, and all such variations are included within the scope of the present disclosure.

[0138] Figure 16 shows a schematic diagram illustrating the principle of performing an erase operation on a first memory transistor through a first erase step according to an embodiment of the present disclosure.

[0139] According to embodiments of this disclosure, when an erase operation is performed on the flash memory cell MC 100, the well area PW 102 of the flash memory cell MC 100 may be grounded.

[0140] Specifically, according to embodiments of the present disclosure, as shown in Figure 16, when performing an erase operation on the first storage transistor MS 110 of the flash memory cell MC 100 through a first erase step, a second power supply voltage VSS is applied to the well area PW 102, a first erase voltage VE1 is applied to the first electrode S and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gating transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130, or the gate electrode 123 of the gating transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130 are left floating (in the figure, floating is represented by FLT), and a second erase voltage VE2 is applied to the gate electrode 116 of the first storage transistor MS 110. For example, the second power supply voltage VSS may be the ground voltage, for example, 0V.

[0141] According to embodiments of this disclosure, the first erase voltage VE1 is higher than a preset voltage VP, which is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS 100. For example, in the flash memory cell MC 100 shown in Figure 16, the preset voltage VP allows holes to cross the hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 contains silicon and the first oxide layer 113 contains silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 may be in the range of 3V to 6V. For example, the first erase voltage VE1 may be 4V.

[0142] According to embodiments of this disclosure, the second erasure voltage VE2 is less than or equal to the second power supply voltage VSS, and the second power supply voltage VSS may be the ground voltage GND. Also, according to embodiments of this disclosure, the second erasure voltage VE2 may be in the range of -8V to 0V. For example, the second erasure voltage VE2 may be -6V.

[0143] Similarly, according to embodiments of the present disclosure, when performing an erase operation on the second storage transistor MD 130 of the flash memory cell MC 100 through a first erase step, a first erase voltage VE1 is applied to the first electrode S and the second electrode D, a second power supply voltage VSS is applied to the gate electrode 123 of the gating transistor MG 120 and the gate electrode 116 of the first storage transistor MS 110, or the gate electrode 123 of the gating transistor MG 120 and the gate electrode 116 of the first storage transistor MS 110 are left floating, and a second erase voltage VE2 is applied to the gate electrode 116 of the second storage transistor MD 130.

[0144] As can be seen from this, due to the symmetrical structure of the flash memory cell MC 100, there is also a symmetrical relationship between the erase voltages VE1 and VE2 applied when erasing the first memory transistor MS 110 and the second memory transistor MD 130 in the first erase step. Therefore, for the sake of brevity, the erase voltage applied during the erasure operation of the second memory transistor MD 130 will not be explained again here.

[0145] Furthermore, according to embodiments of this disclosure, it is also possible to perform erase operations simultaneously on the first memory transistor MS 110 and the second memory transistor MD 130 of the flash memory cell MC 100 through a second erase step. Figure 17 shows a schematic diagram illustrating the principle of performing erase operations simultaneously on the first and second memory transistors through a second erase step according to embodiments of this disclosure.

[0146] According to an embodiment of the present disclosure, as shown in Figure 17, when an erase operation is performed simultaneously on the first memory transistor MS 110 and the second memory transistor MD 130 through a second erase step, a first erase voltage VE1 is applied to the first electrode S and the second electrode D, a second power supply voltage VSS is applied to the gate electrode 123 of the gating transistor MG 120 or the gate electrode 123 of the gating transistor MG 120 is left floating, and a second erase voltage VE2 is applied to the gate electrode 116 of the first memory transistor MS 110 and the gate electrode 136 of the second memory transistor MD 130.

[0147] According to embodiments of this disclosure, the erase operation performed on the first memory transistor MS 110 and the second memory transistor MD 130 through the first and second erase steps described above employs an interband tunneling hot carrier injection mechanism. Taking the erasure operation on the first memory transistor MS 110 as an example, the junction at the first electrode S of the flash memory cell MC 100 is in a high-voltage reverse-biased state, and under the action of the second erasure voltage VE2 (negative gate voltage) applied to the gate electrode 116, a physical effect of interband tunneling occurs in the depletion region of the junction. Hot holes generated by interband tunneling are injected, for example, into the silicon nitride memory medium layer 114. These hot holes can neutralize electrons accumulated during the write (programming) operation of the flash memory cell MC 100, lowering the threshold voltage of the first memory transistor MS 110. Furthermore, since the flash memory cell MC 100 is in an off state at this time, no conduction current is generated by the erasure operation, which has the advantage of low power consumption.

[0148] Figure 18 shows a schematic diagram illustrating the principle of performing erase operations simultaneously on the first and second memory transistors through a third erase step, according to an embodiment of the present disclosure.

[0149] According to embodiments of the present disclosure, an erase operation can also be performed simultaneously on the first storage transistor MS 110 and the second storage transistor MD 130 of the flash memory cell MC 100 through a fourth erase step. According to embodiments of the present disclosure, when an erase operation is performed simultaneously on the first storage transistor MS 110 and the second storage transistor MD 130, a third erase voltage VE3 is applied to the well region PW 102, the first electrode S and the second electrode D, a second power supply voltage VSS is applied to the gate electrode 123 of the gating transistor MG 120, and a fourth erase voltage VE4 is applied to the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130.

[0150] According to embodiments of the present disclosure, the third erasure voltage VE3 may be in the range of 0V to 20V. For example, the third erasure voltage VE3 may be 6V. According to embodiments of the present disclosure, the fourth erasure voltage VE4 may be in the range of -10V to 0V. For example, the fourth erasure voltage VE4 may be -6V.

[0151] Furthermore, according to embodiments of this disclosure, the third erasure voltage VE3 used in the third erasure step may be the same as or different from the first erasure voltage VE1 used in the first and second erasure steps described above, and the fourth erasure voltage VE4 used in the third erasure step may be the same as or different from the second erasure voltage VE2 used in the first and second erasure steps described above.

[0152] According to embodiments of this disclosure, the erase operation performed on the first memory transistor MS 110 and the second memory transistor MD 130 through the third erase step described above employs an FN (Fowler-Nordheim) tunneling mechanism. Taking the erasure operation on the first memory transistor MS 110 as an example, a relatively high third erase voltage VE3 is applied to the first electrode S and well area PW 102 (substrate) of the flash memory cell MC 100, and a negative voltage or ground voltage fourth erase voltage VE4 is applied to the gate electrode 116 (control gate) of the first memory transistor MS 110. Under the action of the gate inverse electric field, the electron charge accumulated and written (programmed) in the memory medium layer 114 is drawn out by the substrate through the FN tunneling mechanism, thereby lowering the threshold voltage of the first memory transistor MS 110. Furthermore, since the flash memory cell MC 100 is in an off state at this time and there is no voltage difference between its first electrode S and second electrode D, no conduction current is generated by the erase operation. Therefore, the method for erasing a flash memory cell according to this disclosure has the advantage of low power consumption.

[0153] Furthermore, the erasure operation of the third erasure step based on the FN tunneling mechanism according to this disclosure has a lower operating current compared to the first and second erasure steps based on the interband tunneling hot hole injection mechanism. Therefore, it can be applied to more rows of flash memory cells to perform erasure operations simultaneously, thus supporting erasure operations of larger capacity flash memory arrays. However, due to the trapping effect of the written (programmed) electron charge in the storage medium layer, for example, silicon nitride, it is difficult for the trapped electrons to be excited by the longitudinal reverse electric field and tunneled away from the electron trap to the substrate. Thus, the erasure operation of the third erasure step based on the FN tunneling mechanism has a higher erasure voltage, a slower operating speed, and a smaller erasure window compared to the erasure operations of the first and second erasure steps based on the interband tunneling hot carrier injection mechanism.

[0154] Figure 19 shows a schematic diagram illustrating an embodiment of the present disclosure in which an erase operation is performed on the first memory transistors 211 and 221 of the first flash memory cell 210 and the second flash memory cell 220 through a first erase step.

[0155] According to embodiments of the present disclosure, as shown in Figure 19, when performing an erase operation on the first memory transistors 211 and 221 of the first flash memory cell 210 and the second flash memory cell 220, for example, a first erase voltage VE1 of 4V is applied to the first bit line BLS0, the intermediate bit line BLM0, and the second bit line BLD0, for example, a second erase voltage VE2 of -6V is applied to the first control line MS0 connected to the gate electrodes of the first memory transistors 211 and 221, and a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gating transistors 212 and 222 and the second control line MD0 connected to the gate electrodes of the second memory transistors 213 and 223, or the word line WL0 and the second control line MD0 are left floating.

[0156] Figure 20 shows a schematic diagram illustrating an embodiment of the present disclosure in which an erase operation is performed on the second memory transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220 through a first erase step.

[0157] According to embodiments of the present disclosure, as shown in Figure 20, when performing an erase operation on the second storage transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220 through a first erase step, for example, a first erase voltage VE1 of 4V is applied to the first bit line BLS0, the intermediate bit line BLM0 and the second bit line BLD0, for example, a second erase voltage VE2 of -6V is applied to the second control line MD0 connected to the gate electrodes of the second storage transistors 213 and 223, and a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gating transistors 212 and 222 and the first control line MS0 connected to the gate electrodes of the first storage transistors 211 and 221, or the word line WL0 and the first control line MS0 are left floating.

[0158] According to embodiments of the present disclosure, as shown in Figures 19 and 20, the first erase step can be used to simultaneously erase the first or second memory transistors in one or more rows of flash memory cells. Also according to embodiments of the present disclosure, when performing an erase operation through the first erase step, all bit line sets of the flash memory array may be connected to the first erase voltage VE1. For rows of flash memory cells that are not being erased, their word line sets may be connected to the second power supply voltage VSS or left floating.

[0159] Figure 21 shows a schematic diagram illustrating an erasure operation performed on the first flash memory cell 210 and the second flash memory cell 220 through a second erasure step according to an embodiment of the present disclosure.

[0160] According to embodiments of the present disclosure, as shown in Figure 21, when an erase operation is performed simultaneously on the first storage transistors 211 and 221 and the second storage transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220 through a second erase step, for example, a first erase voltage VE1 of 4V is applied to the first bit line BLS0, the intermediate bit line BLM0 and the second bit line BLD0, for example, a second erase voltage VE2 of -6V is applied to the first control line MS0 connected to the gate electrodes of the first storage transistors 211 and 221 and the second control line MD0 connected to the gate electrodes of the second storage transistors 213 and 223, and a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gating transistors 212 and 222 or the word line WL0 is left floating.

[0161] According to embodiments of the present disclosure, as shown in Figure 21, the first and second memory transistors in one or more rows of flash memory cells can be erased using the second erase step. Also according to embodiments of the present disclosure, when performing an erase operation through the second erase step, all bit line sets of the flash memory array may be connected to the first erase voltage VE1. For rows of flash memory cells that have not undergone an erase operation, their word line sets may be connected to the second power supply voltage VSS or left floating.

[0162] According to embodiments of the present disclosure, as shown in Figures 19 to 21, an erase operation can be performed simultaneously on memory cells of one or more selected rows, or on a first storage transistor or a second storage transistor in a flash memory cell of a selected row, through a first erase step or a second erase step.

[0163] According to embodiments of the present disclosure, as shown in Figures 19 to 21, when performing an erase operation of a flash memory array through a first erase step or a second erase step, a first erase voltage VE1 is applied to the first bit line BLS<0:n-1>, the intermediate bit line BLM<0:n-1>, and the second bit line BLD<0:n-1> of the flash memory array.

[0164] According to embodiments of the present disclosure, as shown in Figures 19 to 21, for flash memory cells that have not undergone an erase operation, a second power supply voltage VSS is applied to their first control line, word line, and second control line, or the first control line, word line, and second control line are left floating.

[0165] Figure 22 shows a schematic diagram illustrating an embodiment of the present disclosure in which an erase operation is performed on the first flash memory cell and the second flash memory cell through a third erase step.

[0166] According to embodiments of the present disclosure, as shown in Figure 22, when an erase operation is performed simultaneously on the first storage transistors 211 and 221 and the second storage transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220 through a third erase step, for example, a third erase voltage VE3 of 6V is applied to the well area PW 102, the first bit line BLS0, the intermediate bit line BLM0 and the second bit line BLD0 of the flash memory array, for example, a fourth erase voltage VE4 of -6V is applied to the first control line MS0 connected to the gate electrodes of the first storage transistors 211 and 221 and the second control line MD0 connected to the gate electrodes of the second storage transistors 213 and 223, and a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gating transistors 212 and 222, or the word line WL0 is left floating.

[0167] According to embodiments of this disclosure, as shown in Figure 22, the erase operation can be performed simultaneously on the entire flash memory array through a third erase step.

[0168] Furthermore, as described above, according to the embodiments of this disclosure, the third erasure voltage VE3 used in the third erasure step may be the same as or different from the first erasure voltage VE1 used in the first and second erasure steps, and the fourth erasure voltage VE4 used in the third erasure step may be the same as or different from the second erasure voltage VE2 used in the first and second erasure steps.

[0169] According to embodiments of the present disclosure, as shown in Figure 22, when performing an erase operation on the entire flash memory array, a third erase voltage VE3 is applied to the well area PW 102, the first bit line BLS<0:n-1>, the intermediate bit line BLM<0:n-1>, and the second bit line BLD<0:n-1> of the flash memory array, a fourth erase voltage VE4 is applied to the first control line MS<0:m-1> and the second control line MD<0:m-1>, and a second power supply voltage VSS is applied to the word line WL<0:m-1> or the word line WL<0:m-1> is left floating.

[0170] As described above, the erase operation of the third erase step based on the FN tunneling mechanism is suitable for simultaneously performing erase operations on more rows or the entire flash memory array compared to the erase operations of the first and second erase steps based on the interband tunneling hot carrier injection mechanism, but the erase voltage is higher, the operation speed is slower, and the erase window is smaller. Therefore, according to embodiments of this disclosure, by using the first (second) erase step and the third erase step in combination, an optimal trade-off between erase speed and erase effect can be achieved. Specifically, by first performing an erase operation on the entire flash memory cell or a relatively large number of rows of flash memory cells using the third erase step based on the FN tunneling mechanism, the characteristic of the FN tunneling effect, which is a small operation current, can be utilized to simultaneously select and perform erase operations on a relatively large number of rows of flash memory cells, thereby erasing the threshold voltage of the selected flash memory cells to be erased to a relatively low state. Subsequently, by performing an erase operation on one or a relatively small number of flash memory cells using a first or second erase step based on an interband tunneling hot carrier injection mechanism, the neutralization effect of the injected holes can be utilized to erase the selected flash memory cells to an even lower threshold voltage state.

[0171] Figure 23 shows a flowchart of a flash memory array erasure method according to an embodiment of the present disclosure.

[0172] The erasure method 1200 begins at step S1201. Subsequently, in step S1202, an erasure operation is performed on all rows of the flash memory array through a third erasure step. Then, in step S2103, one or more flash memory cells of the flash memory array are selected, and an erasure operation is performed on the flash memory cells of the selected rows through a first erasure step or a second erasure step. In step S1203, the row addresses of the flash memory cell rows on which the first erasure step or second erasure step has been performed may also be stored. Then, in step S1204, it is determined whether the first erasure step or second erasure step has been performed on all rows of the flash memory array. If "yes", the erasure method 1200 ends at step S1205. Otherwise, the erasure method 1200 returns to step S1203 and performs an erasure operation on the flash memory cells of the rows on which the first and second erasure steps have not been performed, according to the previously stored row addresses.

[0173] According to the flash memory array erasure method combining multiple steps according to the embodiments of this disclosure, by combining the first erasure step and / or the second erasure step with the third erasure step, the erasure voltage can be reduced, the erasure time can be shortened, and a lower erasure threshold voltage can be obtained, thereby improving the erasure operation speed and improving the threshold voltage window of the flash memory cell erasure operation and the reliability of the memory.

[0174] Those skilled in the art will understand that, although the flash memory array erasure method of the present disclosure has been described above in relation to the flash memory cell MC 100 shown in Figure 1, the flash memory array erasure method of the present disclosure is not limited to the flash memory cell MC 100 shown in Figure 1. Those skilled in the art can envision, based on the teachings of the present disclosure, applying the flash memory array erasure method of the present disclosure to other types of flash memory cells, such as a flash memory cell containing only one storage transistor, or a flash memory cell using one storage transistor to store 2 bits of data, and all such variations are included within the scope of the present disclosure.

[0175] While this disclosure has been described with reference to embodiments of this disclosure, those skilled in the art will understand that various modifications and changes are possible without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. It is a flash memory array, A plurality of flash memory cells arranged along the row direction and the column direction perpendicular to the row direction, A plurality of word line sets extending along the row direction, each of the word line sets comprising a first control line, a word line, and a second control line extending along the row direction, A plurality of bit line sets extending along the column direction, each bit line set comprising a first bit line, an intermediate bit line, and a second bit line, wherein the intermediate bit line is formed of a first metal layer, and the first bit line and the second bit line are formed of a second metal layer different from the first metal layer, A pair of flash memory cells is provided at the intersection of the word line set and the bit line set, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row direction and share the same bit line set. The flash memory array is characterized in that the intermediate bit line includes a first portion extending in the column direction and a second portion extending in the row direction, the first bit line and the second bit line extend in the column direction, the first portion of the intermediate bit line overlaps with the first bit line and the second bit line, and the second portion of the intermediate bit line overlaps with the word line below.

2. Each of the first flash memory cell and the second flash memory cell includes a first memory transistor, a gating transistor, and a second memory transistor connected in series in the column direction, The flash memory array according to claim 1, characterized in that in each of the first flash memory cell and the second flash memory cell, the source region of the first memory transistor is connected to the first electrode of the flash memory cell, and the drain region of the second memory transistor is connected to the second electrode of the flash memory cell.

3. The flash memory array according to claim 2, characterized in that the first bit line is connected to the first electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the intermediate bit line is connected to the second electrode of the first flash memory cell and the first electrode of the second flash memory cell.

4. The flash memory array according to claim 2, characterized in that the first bit line is connected to the second electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the intermediate bit line is connected to the first electrode of the first flash memory cell and the first electrode of the second flash memory cell.

5. The flash memory array according to claim 3, characterized in that the first control line is connected to the gate electrode of the first memory transistor, the word line is connected to the gate electrode of the gating transistor, and the second control line is connected to the gate electrode of the second memory transistor.

6. Two first control lines adjacent in the column direction are connected to each other via a first common control line. The flash memory array according to claim 5, characterized in that two adjacent second control lines in the column direction are connected to each other via a second common control line.

7. The flash memory array according to claim 5, characterized in that the first control line, the word line, and the second control line are formed of at least one of polycrystalline silicon, silicide, and metal gate.

8. The flash memory array according to claim 6, characterized in that the first common control line and the second common control line are formed of a metal layer.

9. It is a flash memory array, A plurality of flash memory cells arranged along the row direction and the column direction perpendicular to the row direction, Multiple sets of word lines extending along the aforementioned row direction, Includes a plurality of bit line sets extending along the column direction, A pair of flash memory cells is provided at the intersection of the word line set and the bit line set, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row direction and share the same bit line set. Each set of bit lines includes a first bit line, an intermediate bit line, and a second bit line extending sequentially along the row direction, wherein none of the first bit line, the intermediate bit line, and the second bit line are connected to an adjacent pair of flash memory cells along the row direction. Each of the first flash memory cell and the second flash memory cell includes a first memory transistor, a gating transistor, and a second memory transistor connected in series in order in each of the column directions. In the first flash memory cell, the source region of the first memory transistor is connected to the first bit line, and the drain region of the second memory transistor is connected to the intermediate bit line. In the second flash memory cell, the source region of the first memory transistor is connected to the intermediate bit line, and the drain region of the second memory transistor is connected to the second bit line. Each word line set includes a first control line, a word line, and a second control line that extend sequentially along the column direction. A flash memory array characterized in that the first control line is connected to the gate electrode of the first memory transistor of the first flash memory cell and the second flash memory cell, the word line is connected to the gate electrode of the gating transistor of the first flash memory cell and the second flash memory cell, and the second control line is connected to the gate electrode of the second memory transistor of the first flash memory cell and the second flash memory cell.

10. A method for writing to a flash memory array according to any one of claims 1 to 9, The steps of performing a write operation on the first memory transistor of the first flash memory cell by applying a first write voltage to the first bit line, applying a second write voltage to the intermediate bit line and the second bit line, applying a third write voltage to the first control line, applying a fourth write voltage to the word line, and applying a fifth write voltage to the second control line, The steps of performing a write operation on the second memory transistor of the first flash memory cell by applying the second write voltage to the first bit line, applying the first write voltage to the intermediate bit line and the second bit line, applying the fifth write voltage to the first control line, applying the fourth write voltage to the word line, and applying the third write voltage to the second control line, The steps of performing a write operation on the first memory transistor of the second flash memory cell by applying a first write voltage to the first bit line and the intermediate bit line, applying a second write voltage to the second bit line, applying a third write voltage to the first control line, applying a fourth write voltage to the word line, and applying a fifth write voltage to the second control line, The process includes the step of performing a write operation on the second memory transistor of the second flash memory cell by applying the second write voltage to the first bit line and the intermediate bit line, applying the first write voltage to the second bit line, applying the fifth write voltage to the first control line, applying the fourth write voltage to the word line, and applying the third write voltage to the second control line. The fourth writing voltage is less than or equal to the first power supply voltage, the second writing voltage is greater than or equal to the second power supply voltage, the first writing voltage is higher than a preset voltage, and the third writing voltage is higher than the first writing voltage. The first power supply voltage is higher than the second power supply voltage. The aforementioned preset voltage is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors. The first write voltage, the fourth write voltage, and the fifth write voltage are higher than the second write voltage. The second writing voltage is connected to the second power supply voltage by a constant current load. A writing method characterized in that, during a write operation of a flash memory cell, the first storage transistor, the second storage transistor, the third writing voltage, the fourth writing voltage, and the fifth writing voltage all conduct to the first storage transistor, the second storage transistor, and the gating transistor of the flash memory cell.

11. The first power supply voltage is in the range of 0.8V to 5V. The aforementioned second power supply voltage is the ground voltage, The first writing voltage is in the range of 3V to 6V. The third writing voltage is in the range of 4V to 12V. The writing method according to claim 10, characterized in that the fifth writing voltage is in the range of 3V to 8V.

12. The writing method according to claim 10, characterized in that, during the writing operation of the flash memory cell, the current flowing between the first electrode and the second electrode of the flash memory cell is controlled by controlling the current of the constant current load.

13. The writing method according to claim 11, characterized in that, during the writing operation of the flash memory cell, the current flowing between the first electrode and the second electrode of the flash memory cell is controlled by controlling the current of the constant current load.

14. The writing method according to claim 10, characterized in that, during a write operation of the flash memory cell, a write operation is performed on the first memory transistor or the second memory transistor of the flash memory cell by a channel hot carrier injection mechanism.

15. The writing method according to claim 11, characterized in that, during a write operation of the flash memory cell, a write operation is performed on the first memory transistor or the second memory transistor of the flash memory cell by a channel hot carrier injection mechanism.

16. A method for erasing a flash memory array according to any one of claims 1 to 9, comprising a first erasure step, wherein the first erasure step includes: By applying a first erase voltage to the first bit line, the intermediate bit line, and the second bit line, applying a second erase voltage to the first control line, and applying a second power supply voltage to the word line and the second control line, or by floating the word line and the second control line, an erase operation is performed on the first memory cell and the first memory transistor of the second flash memory cell. By applying the first erase voltage to the first bit line, the intermediate bit line, and the second bit line, and applying the second power supply voltage to the word line and the first control line, or by floating the word line and the first control line, and applying the second erase voltage to the second control line, an erase operation is performed on the second memory transistor of the first flash memory cell and the second memory transistor of the second flash memory cell. The first erase voltage is higher than a preset voltage, and the second erase voltage is lower than or equal to the second power supply voltage. The erasure method is characterized in that the preset voltage is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stacks of the first and second memory transistors.

17. The aforementioned second power supply voltage is the ground voltage, The first erasure voltage is in the range of 3V to 6V. The erasure method according to claim 16, characterized in that the second erasure voltage is in the range of -8V to 0V.

18. The process further includes a second erasure step, in which the second erasure step, The erasure method according to claim 16, characterized in that an erasure operation is performed simultaneously on the first flash memory cell and the second flash memory cell by applying the first erasure voltage to the first bit line, the intermediate bit line and the second bit line, applying the second erasure voltage to the first control line and the second control line, and applying the second power supply voltage to the word line or by floating the word line.

19. The erasure method according to claim 16, characterized in that, during the erasure operation of the flash memory cell, the erasure operation is performed on the first memory transistor or the second memory transistor by an interband tunneling hot carrier injection mechanism.

20. The erasure method according to claim 18, characterized in that, during the erasure operation of the flash memory cell, the erasure operation is performed on the first memory transistor or the second memory transistor by an interband tunneling hot carrier injection mechanism.

21. The process further includes a third erasure step, in which the above third erasure step, By applying a third erase voltage to the substrate of the flash memory array, the first bit line, the intermediate bit line, and the second bit line, applying a fourth erase voltage to the first control line and the second control line, and applying the second power supply voltage to the word line or making the word line float, an erase operation is performed simultaneously on the first flash memory cell and the second flash memory cell. The erasure method according to claim 16, characterized in that the third erasure voltage is in the range of 0V to 20V, and the fourth erasure voltage is in the range of -10V to 0V.

22. The process further includes a third erasure step, in which the above third erasure step, By applying a third erase voltage to the substrate of the flash memory array, the first bit line, the intermediate bit line, and the second bit line, applying a fourth erase voltage to the first control line and the second control line, and applying the second power supply voltage to the word line or making the word line float, an erase operation is performed simultaneously on the first flash memory cell and the second flash memory cell. The erasure method according to claim 18, characterized in that the third erasure voltage is in the range of 0V to 20V, and the fourth erasure voltage is in the range of -10V to 0V.

23. The erasure method according to claim 21, characterized in that, during the erasure operation of the flash memory cell, the erasure operation is performed on the first memory transistor or the second memory transistor by a Fowler-Nordheim tunneling mechanism.

24. The erasure method according to claim 22, characterized in that, during the erasure operation of the flash memory cell, the erasure operation is performed on the first memory transistor or the second memory transistor by a Fowler-Nordheim tunneling mechanism.

25. The erasure method according to claim 21, further comprising the steps of first performing an erasure operation on the entire flash memory array through the third erasure step, and then performing an erasure operation on a portion of the flash memory cells of the flash memory array through the first erasure step.

26. The erasure method according to claim 22, further comprising the steps of first performing an erasure operation on the entire flash memory array through the third erasure step, and then performing an erasure operation on a portion of the flash memory cells of the flash memory array through the first erasure step or the second erasure step.

27. The third erase voltage is the same as or different from the first erase voltage. The erasure method according to claim 21, characterized in that the fourth erasure voltage is the same as or different from the second erasure voltage.

28. The third erase voltage is the same as or different from the first erase voltage. The erasure method according to claim 22, characterized in that the fourth erasure voltage is the same as or different from the second erasure voltage.

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