Electronic components and communication equipment

Abstract

To provide an electronic component and a communication device available in a wide frequency band.SOLUTION: An electronic component 1 has a first input-output port 11, a second input-output port 12, a third input-output port 13, a first circuit 21, a second circuit 22, a third circuit 23, and a matching circuit 24. The first circuit 21 is a characteristic impedance conversion circuit provided between the first input-output port 11 and the second input-output port 12. The second circuit 22 is a characteristic impedance conversion circuit provided between the first input-output port 11 and the third input-output port 13. The third circuit 23 is provided between the second input-output port 12 and the third input-output port 13, having a circuit configuration that has a complex conjugate relation with each of the first circuit 21 and the second circuit 22.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an electronic component used in a communication device and a communication device.

Background Art

[0002] In recent years, not only portable wireless communication devices such as mobile phones, portable information terminals, and body-worn terminals, but also various devices such as automobiles, aircraft, and other transportation devices, as well as traffic signal devices, household electrical appliances, industrial devices, and measuring devices, have come to have a wireless communication function. With the spread of such devices, various things such as devices, apparatuses, and sensors are connected via wireless communication. Also, some of such devices have a broadcast reception function.

[0003] Some communication devices having a wireless communication function and a broadcast reception function include a plurality of antennas for stabilizing wireless communication and broadcast reception. One of the electronic components used in a communication device having a plurality of antennas is a distributor and combiner. The distributor and combiner is used to distribute a signal to a plurality of antennas or to combine a plurality of signals received by a plurality of antennas.

[0004] Patent Documents 1 to 3 describe a distributor and combiner that distributes and combines high-frequency signals. Patent Document 4 describes a high-power distributor / combiner that distributes and combines high-frequency signals of high power. Also, Patent Document 4 describes that a high-power distributor / combiner is broadened in bandwidth by connecting eight stages of Wilkinson circuits each including two distributed constant lines and a resistor in series.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

[0006] Communication equipment with wireless communication and broadcast reception capabilities is in high demand for miniaturization, thinning, and high performance, and the electronic components used in communication equipment are also required to be miniaturized, thinning, and high performance. On the other hand, in order to increase the speed and functionality of wireless communication, and broadcasting, development of wireless communication and broadcasting methods with expanded signal bandwidths is progressing. Therefore, communication equipment and the electronic components used in communication equipment are required to support multiple wireless communication and broadcasting methods, and to have broad bandwidth.

[0007] Conventional distributors and synthesizers can achieve broadband bandwidth by using multiple stages, as described in Patent Document 4, for example. However, this results in a large distributor and synthesizer.

[0008] This invention has been made in view of the above problems, and its objective is to provide electronic components and communication equipment that can be used in a wide frequency band. [Means for solving the problem]

[0009] The electronic component of the present invention comprises a first input / output port, a second input / output port, a third input / output port, a first circuit which is a characteristic impedance conversion circuit provided between the first input / output port and the second input / output port, a second circuit which is a characteristic impedance conversion circuit provided between the first input / output port and the third input / output port, and a third circuit provided between the second input / output port and the third input / output port, having a circuit configuration that is complex conjugate to each of the first and second circuits.

[0010] In the electronic component of the present invention, each of the first to third circuits may include at least one inductor and at least one capacitor. In this case, at least one inductor of the third circuit may be provided in the third circuit such that it is complex conjugate to at least one capacitor of each of the first and second circuits. Also, at least one capacitor of the third circuit may be provided in the third circuit such that it is complex conjugate to at least one inductor of each of the first and second circuits.

[0011] If each of the first to third circuits includes at least one inductor and at least one capacitor, the first circuit may include, as at least one inductor and at least one capacitor, a first inductor provided in a first path connecting a first input / output port and a second input / output port, and a first capacitor provided between the first path and ground. The second circuit may include, as at least one inductor and at least one capacitor, a second inductor provided in a second path connecting a first input / output port and a third input / output port, and a second capacitor provided between the second path and ground. The third circuit may include, as at least one inductor and at least one capacitor, a third capacitor connected in series with the first inductor, a fourth capacitor connected in series with the second inductor, and a third inductor. The third circuit may further include a resistive element. The third inductor and resistive element may be provided in parallel between the third capacitor and the fourth capacitor.

[0012] Furthermore, if each of the first to third circuits includes at least one inductor and at least one capacitor, the first circuit may include, as at least one inductor and at least one capacitor, a first inductor provided in a first path connecting a first input / output port and a second input / output port, and a first capacitor. The second circuit may include, as at least one inductor and at least one capacitor, a second inductor provided in a second path connecting a first input / output port and a third input / output port, and a second capacitor. The first capacitor and the second capacitor may be connected to each other. The third circuit may include, as at least one inductor and at least one capacitor, a third capacitor connected in series with the first inductor, a fourth capacitor connected in series with the second inductor, and a third inductor. The third circuit may further include a resistive element. The third inductor and the resistive element may be provided in parallel between the third capacitor and the fourth capacitor.

[0013] If the third circuit includes a third capacitor, a fourth capacitor, a third inductor, and a resistor, the circuit configuration of the third circuit may be symmetrical with respect to the third inductor and resistor.

[0014] Furthermore, in the electronic component of the present invention, the first circuit may include, as at least one inductor and at least one capacitor, a first capacitor provided in a first path connecting a first input / output port and a second input / output port, and a first inductor provided between the first path and ground. Furthermore, the second circuit may include, as at least one inductor and at least one capacitor, a second capacitor provided in a second path connecting a first input / output port and a third input / output port, and a second inductor provided between the second path and ground. Furthermore, the third circuit may include, as at least one inductor and at least one capacitor, a third inductor connected in series with the first capacitor, a fourth inductor connected in series with the second capacitor, and a third capacitor. Furthermore, the third circuit may further include a resistive element. The third capacitor and the resistive element may be provided in parallel between the third inductor and the fourth inductor. In this case, the circuit configuration of the third circuit may be symmetrical with respect to the third capacitor and resistor element.

[0015] Furthermore, in the electronic component of the present invention, the first circuit and the second circuit may each be connected to ground.

[0016] Furthermore, in the electronic component of the present invention, the first circuit and the second circuit may be connected by multiple paths that do not go through the third circuit. In this case, neither the first circuit nor the second circuit needs to be connected to ground.

[0017] Furthermore, the electronic component of the present invention may further include a fourth input / output port, a fourth circuit that is a characteristic impedance conversion circuit provided between the first input / output port and the fourth input / output port, and a fifth circuit provided between the third input / output port and the fourth input / output port and having a circuit configuration that is in a complex conjugate relationship with each of the second and fourth circuits. In this case, the second circuit may be connected to the first circuit by a plurality of paths that do not pass through the third circuit and may be connected to the fourth circuit by a plurality of paths that do not pass through the fifth circuit.

[0018] Furthermore, the electronic component of the present invention may further include a matching circuit provided between the first input / output port and the first and second circuits. In this case, the first circuit, the second circuit, and the matching circuit may branch from one node. Also, the matching circuit may include at least one matching circuit capacitor provided on a third path connecting the first input / output port and the node, and at least one matching circuit inductor provided between the third path and the ground.

[0019] Furthermore, the electronic component of the present invention may be a distributor and combiner.

[0020] The communication device of the present invention includes the electronic component of the present invention and at least one antenna connected to the electronic component.

Advantages of the Invention

[0021] In the electronic component of the present invention, a first circuit is provided between the first input / output port and the second input / output port, a second circuit is provided between the first input / output port and the third input / output port, and a third circuit having a circuit configuration that is in a complex conjugate relationship with each of the first and second circuits is provided between the second input / output port and the third input / output port. Thus, according to the present invention, there is an effect that an electronic component and a communication device that can be used in a wide frequency band can be realized.

Brief Description of the Drawings

[0022] [Figure 1] It is a block diagram showing the configuration of an electronic component according to the first embodiment of the present invention. [Figure 2] It is a circuit diagram showing the circuit configuration of an electronic component according to the first embodiment of the present invention. [Figure 3] It is a block diagram showing a first example of a communication device according to the first embodiment of the present invention. [Figure 4] It is a block diagram showing a second example of a communication device according to the first embodiment of the present invention. [Figure 5] It is a perspective view showing an electronic component according to the first embodiment of the present invention. [Figure 6] It is a perspective view showing the inside of the main body of the electronic component shown in FIG. 5. [Figure 7] It is a perspective view showing the dielectric layer, conductor layer, and through hole of the main body of the electronic component shown in FIG. 5. [Figure 8] It is a plan view showing the pattern formation surface of the first dielectric layer of the main body of the electronic component shown in FIG. 5. [Figure 9] It is a plan view showing the pattern formation surface of the second dielectric layer of the main body of the electronic component shown in FIG. 5. [Figure 10] It is a plan view showing the pattern formation surface of the third dielectric layer of the main body of the electronic component shown in FIG. 5. [Figure 11] It is a plan view showing the terminal formation surface of the third dielectric layer of the main body of the electronic component shown in FIG. 5. [Figure 12] It is a circuit diagram showing the circuit configuration of an electronic component of a comparative example. [Figure 13] It is a characteristic diagram showing the frequency characteristics of the isolation of a model of a comparative example. [Figure 14] It is a characteristic diagram showing the frequency characteristics of the insertion loss of a model of a comparative example. [Figure 15] It is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output terminal of a model of a comparative example. [Figure 16] It is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output terminal of a model of a comparative example. [Figure 17]This is a characteristic diagram showing the frequency characteristics of the isolation model in the first embodiment. [Figure 18] This is a characteristic diagram showing the frequency characteristics of the insertion loss of the model in the first embodiment. [Figure 19] This is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output terminal of the model of the first embodiment. [Figure 20] This is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output terminal of the model of the first embodiment. [Figure 21] This is a block diagram showing the configuration of an electronic component according to a second embodiment of the present invention. [Figure 22] This is a circuit diagram showing the circuit configuration of an electronic component according to a second embodiment of the present invention. [Figure 23] This is a characteristic diagram showing the frequency characteristics of the isolation model in the second embodiment. [Figure 24] This is a characteristic diagram showing the frequency characteristics of the insertion loss of the model in the second embodiment. [Figure 25] This is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output terminal of the model in the second embodiment. [Figure 26] This is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output terminal of the model in the second embodiment. [Figure 27] This is a circuit diagram showing the circuit configuration of an electronic component according to a third embodiment of the present invention. [Figure 28] This is a block diagram showing the configuration of an electronic component according to a fourth embodiment of the present invention. [Figure 29] This is a circuit diagram showing the circuit configuration of an electronic component according to a fourth embodiment of the present invention. [Figure 30] This is a characteristic diagram showing the frequency characteristics of the isolation model in the third embodiment. [Figure 31] This is a characteristic diagram showing the frequency characteristics of the insertion loss of the model in the third embodiment. [Figure 32] This is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output terminal of the model of the third embodiment. [Figure 33]This is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output terminal of the model of the third embodiment. [Figure 34] This is a block diagram showing the configuration of an electronic component according to a fifth embodiment of the present invention. [Figure 35] This is a circuit diagram showing the circuit configuration of an electronic component according to a fifth embodiment of the present invention. [Modes for carrying out the invention]

[0023] [First Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the configuration of an electronic component according to the first embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a block diagram showing the configuration of an electronic component according to this embodiment. Figure 2 is a circuit diagram showing the circuit configuration of an electronic component according to this embodiment. The electronic component 1 according to this embodiment includes a first input / output port 11, a second input / output port 12, a third input / output port 13, a first circuit 21, a second circuit 22, and a third circuit 23.

[0024] The first circuit 21 is located between the first input / output port 11 and the second input / output port 12 in the circuit configuration. The second circuit 22 is located between the first input / output port 11 and the third input / output port 13 in the circuit configuration. The third circuit 23 is located between the second input / output port 12 and the third input / output port 13 in the circuit configuration. The first and second circuits 21 and 22 are each connected to ground. In this application, the expression "in the circuit configuration" refers to the arrangement on the circuit diagram, not the arrangement in the physical configuration.

[0025] In this embodiment, in particular, electronic component 1 is a distributor and combiner that distributes or combines multiple signals. The first and second circuits 21 and 22 are characteristic impedance conversion circuits used to adjust the impedance of each of the first to third input / output ports 11 to 13 to a predetermined value (e.g., 50Ω).

[0026] The third circuit 23 is a signal absorption circuit that absorbs the signal that flows to the other input / output port 13 when a signal is input to either the second input / output port 12 or the third input / output port 13. In this embodiment, the third circuit 23 has a circuit configuration that is complex conjugate to each of the first and second circuits 21 and 22. A circuit configuration that is complex conjugate to each of the first and second circuits 21 and 22 is a circuit configuration in which the sign of the imaginary part of the impedance is opposite to that of each of the first and second circuits 21 and 22.

[0027] Here, the path connecting the first input / output port 11 and the second input / output port 12 is called the first path P1, and the path connecting the first input / output port 11 and the third input / output port 13 is called the second path P2. Furthermore, the elements of the first circuit 21 provided on the first path P1 are called the series elements of the first circuit 21, and the elements of the first circuit 21 provided between the first path P1 and ground are called the parallel elements of the first circuit 21. Furthermore, the elements of the second circuit 22 provided on the second path P2 are called the series elements of the second circuit 22, and the elements of the second circuit 22 provided between the second path P2 and ground are called the parallel elements of the second circuit 22.

[0028] In this embodiment, the elements constituting the third circuit 23 are provided in the third circuit 23 in such a complex conjugate relationship with respect to the elements constituting the first and second circuits 21 and 22, respectively, as described below. In the third circuit 23, elements whose impedance has the opposite sign of the imaginary part to that of the series elements of the first circuit 21 are connected in series with respect to the series elements of the first circuit 21. Also, elements whose impedance has the opposite sign of the imaginary part to that of the series elements of the second circuit 22 are connected in series with respect to the series elements of the second circuit 22. Furthermore, elements whose impedance has the opposite sign of the imaginary part to that of the parallel elements of the first and second circuits 21 and 22 are provided between the elements whose impedance has the opposite sign of the imaginary part to that of the series elements of the first circuit 21 and the elements whose impedance has the opposite sign to that of the series elements of the second circuit 22.

[0029] Inductors and capacitors are elements whose impedances have opposite signs in the imaginary part. Each of the first to third circuits 21 to 23 includes at least one inductor and at least one capacitor. At least one inductor in the third circuit 23 is provided in the third circuit 23 such that it is complex conjugate to at least one capacitor in each of the first and second circuits 21 and 22. At least one capacitor in the third circuit 23 is provided in the third circuit 23 such that it is complex conjugate to at least one inductor in each of the first and second circuits 21 and 22.

[0030] In this embodiment, the first circuit 21 includes at least one first inductor provided in the first path P1 and at least one first capacitor provided between the first path P1 and ground. The second circuit 22 includes at least one second inductor provided in the second path P2 and at least one second capacitor provided between the second path P2 and ground.

[0031] The third circuit 23 includes at least one third capacitor connected in series with at least one first inductor, at least one fourth capacitor connected in series with at least one second inductor, and at least one third inductor. The third circuit 23 further includes a resistor R31. At least one third inductor and the resistor R31 are provided in parallel between at least one third capacitor and at least one fourth capacitor. The circuit configuration of the third circuit 23 is symmetrical with respect to at least one third inductor and the resistor R31.

[0032] Electronic component 1 further includes a matching circuit 24. In terms of circuit configuration, the matching circuit 24 is provided between the first input / output port 11 and the first and second circuits 21 and 22. The matching circuit 24 is connected to ground. The first circuit 21, the second circuit 22, and the matching circuit 24 branch from a single node ND.

[0033] The matching circuit 24 includes at least one matching circuit capacitor provided in the third path P3 connecting the first input / output port 11 and node ND, and at least one matching circuit inductor provided between the third path P3 and ground. The first path P1 connects the first input / output port 11 and the second input / output port 12 via the third path P3. The second path P2 connects the first input / output port 11 and the third input / output port 13 via the third path P3.

[0034] The specific circuit configuration of the electronic component 1 according to this embodiment will be described below with reference to Figure 2. As shown in Figure 2, the first circuit 21 includes two first inductors L11 and L12 and one first capacitor C11. One end of the first inductor L11 is connected to node ND. The other end of the first inductor L11 is connected to one end of the first inductor L12 and one end of the first capacitor C11. The other end of the first inductor L12 is connected to the second input / output port 12. The other end of the first capacitor C11 is connected to ground.

[0035] The configuration of the second circuit 22 is the same as that of the first circuit 21. That is, the second circuit 22 includes two second inductors L21 and L22 and one second capacitor C21. One end of the second inductor L21 is connected to node ND. The other end of the second inductor L21 is connected to one end of the second inductor L22 and one end of the second capacitor C21. The other end of the second inductor L22 is connected to the third input / output port 13. The other end of the second capacitor C21 is connected to ground.

[0036] The third circuit 23 includes two third capacitors C31 and C32 connected in series with the first inductors L11 and L12, two fourth capacitors C33 and C34 connected in series with the second inductors L21 and L22, and one third inductor L31. One end of the third capacitor C31 is connected to the other end of the first inductor L12 and to the second input / output port 12. The other end of the third capacitor C31 is connected to one end of the third capacitor C32 and to one end of the third inductor L31. One end of the fourth capacitor C33 is connected to the other end of the second inductor L22 and to the third input / output port 13. The other end of the fourth capacitor C33 is connected to one end of the fourth capacitor C34 and to the other end of the third inductor L31.

[0037] The other end of the third capacitor C32 is connected to one end of the resistor R31. The other end of the fourth capacitor C34 is connected to the other end of the resistor R31. The impedance of the third circuit 23 is adjusted to match the characteristic impedance of the second input / output port 12 or the third input / output port 13. Specifically, the resistance value of the resistor R31 is adjusted so that the third circuit 23 matches the second input / output port 12 or the third input / output port 13.

[0038] The matching circuit 24 includes one matching circuit capacitor C41 and two matching circuit inductors L41 and L42. One end of the matching circuit capacitor C41 is connected to the first input / output port 11 and one end of the matching circuit inductor L41. The other end of the matching circuit capacitor C41 is connected to node ND and one end of the matching circuit inductor L42. The other ends of each of the matching circuit inductors L41 and L42 are connected to ground.

[0039] Next, a communication device according to this embodiment will be described. The communication device 100 according to this embodiment comprises an electronic component 1 according to this embodiment and at least one antenna connected to the electronic component 1.

[0040] First, with reference to Figure 3, a first example of the communication device 100 will be described. In the first example, the communication device 100 comprises an electronic component 1, one antenna 2, and a signal processing circuit 3. The antenna 2 is connected to the first input / output port 11 of the electronic component 1. The signal processing circuit 3 is connected to the second and third input / output ports 12 and 13 of the electronic component 1.

[0041] The signal processing circuit 3 is a circuit for realizing a predetermined function of the communication device 100. The signal processing circuit 3 may include at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), and a microcomputer. The signal processing circuit 3 may further include an analog circuit.

[0042] In the first example, electronic component 1 can distribute the received signal received by antenna 2 to a second input / output port 12 and a third input / output port 13. The two distributed received signals are input to signal processing circuit 3 via the second and third input / output ports 12 and 13 for predetermined processing. Also in the first example, electronic component 1 can combine the two transmitted signals output from signal processing circuit 3. The combined signal is supplied to antenna 2 via the first input / output port 11.

[0043] Next, with reference to Figure 4, a second example of the communication device 100 will be described. In the second example, the communication device 100 comprises an electronic component 1, two antennas 2A and 2B, and a signal processing circuit 3. Antenna 2A is connected to the second input / output port 12 of the electronic component 1. Antenna 2B is connected to the third input / output port 13 of the electronic component 1. The signal processing circuit 3 is connected to the first input / output port 11 of the electronic component 1.

[0044] In the second example, electronic component 1 can combine two received signals received by antennas 2A and 2B. The combined signal is input to the signal processing circuit 3 via the first input / output port 11 and subjected to predetermined processing. Also in the second example, electronic component 1 can distribute the transmitted signal output from the signal processing circuit 3 to the second input / output port 12 and the third input / output port 13. The two distributed transmitted signals are supplied to antennas 2A and 2B via the second and third input / output ports 12 and 13.

[0045] Next, an example of the structure of electronic component 1 will be described with reference to Figures 5 to 7. Figure 5 is a perspective view of electronic component 1. Figure 6 is a perspective view showing the interior of the main body of electronic component 1. Figure 7 is a perspective view showing the dielectric layer, conductor layer, and through-hole of the main body of electronic component 1. Electronic component 1 further includes a laminate 30 for integrating first to third input / output ports 11 to 13, first to third circuits 21 to 23, and matching circuit 24. As will be explained in detail later, the laminate 30 includes a plurality of laminated dielectric layers and a plurality of conductor layers.

[0046] The laminate 30 has a rectangular parallelepiped shape. The laminate 30 has an upper surface 30a, a lower surface 30b, and four side surfaces 30c to 30f that constitute the outer periphery of the laminate 30. The upper surface 30a and the lower surface 30b face opposite each other, as do the side surfaces 30c and 30d, and the side surfaces 30e and 30f. The side surfaces 30c to 30f are perpendicular to the upper surface 30a and the lower surface 30b. In the laminate 30, the direction perpendicular to the upper surface 30a and the lower surface 30b is the stacking direction of the multiple dielectric layers and the multiple conductive layers. In Figures 5 and 6, this stacking direction is indicated by an arrow with the symbol T. The upper surface 30a and the lower surface 30b are located at both ends of the stacking direction T.

[0047] The laminate 30 includes a main body 30A that constitutes the main part of the electronic component 1, and a support substrate 30B that supports the main body 30A. The main body 30A and the support substrate 30B are aligned in the stacking direction T. The main body 30A has a top surface, a bottom surface, and four sides that constitute the outer periphery of the main body 30A. The support substrate 30B has a top surface, a bottom surface, and four sides that constitute the outer periphery of the support substrate 30B. The top surface of the main body 30A and the bottom surface of the support substrate 30B face each other. The bottom surface of the main body 30A constitutes the bottom surface 30b of the laminate 30. The top surface of the support substrate 30B constitutes the top surface 30a of the laminate 30.

[0048] The electronic component 1 further includes first to fifth terminals 41, 42, 43, 44, and 45 provided on the main body 30A. As shown in Figure 5, the first to fifth terminals 41 to 45 are located on the bottom surface of the main body 30A, i.e., the bottom surface 30b of the laminate 30. The first terminal 41 corresponds to the first input / output port 11. The second terminal 42 corresponds to the second input / output port 12. The third terminal 43 corresponds to the third input / output port 13. The fourth and fifth terminals 44 and 45 are connected to ground, respectively.

[0049] Next, the main body 30A will be described in detail with reference to Figures 7 to 11. The main body 30A contains three stacked dielectric layers. Hereinafter, these three dielectric layers will be referred to as the first to third dielectric layers, in order from the top surface of the main body 30A. The first to third dielectric layers will also be denoted by reference numerals 31 to 33. In Figure 7, the first to third dielectric layers 31 to 33 are drawn spaced apart from each other along the stacking direction T (see Figures 5 and 6).

[0050] Each of the first to third dielectric layers 31-33 has a pattern-forming surface. The third dielectric layer 33 has a terminal-forming surface located on the opposite side of the pattern-forming surface. Figure 8 shows the pattern-forming surface of the first dielectric layer 31. Figure 9 shows the pattern-forming surface of the second dielectric layer 32. Figure 10 shows the pattern-forming surface of the third dielectric layer 33. Figure 11 shows the terminal-forming surface of the third dielectric layer 33.

[0051] As shown in Figure 8, the pattern-forming surface of the first dielectric layer 31 has the following conductor layers formed: conductor layers 101, 102, 103, 104, 105, conductor layers 111, 112, 113 for the first circuit 21, conductor layers 121, 122, 123 for the second circuit 22, conductor layers 131, 132, 135 for the third circuit 23, conductor layer 136 for the resistive element, and conductor layers 141, 142, 143 for the matching circuit 24.

[0052] Each of the conductor layers 111, 112, 121, 122, 135, 136, 141, and 142 has a first end and a second end located on opposite sides of each other. The first end of each of the conductor layers 111 and 112 is connected to conductor layer 113. The first end of each of the conductor layers 121 and 122 is connected to conductor layer 123. The first end of conductor layer 135 is connected to conductor layer 131. The first end of conductor layer 141 is connected to conductor layer 104. The first end of conductor layer 142 is connected to conductor layer 143.

[0053] Furthermore, through-holes T101, T102, T103, T104, T105, T106, T107, T109, T110, T112, T115, T118, T119, T120, T121, T122, and T123 are formed in the dielectric layer 31. Through-holes T101 to T105 are connected to the conductor layers 101 to 105, respectively.

[0054] Through-hole T106 is connected to the vicinity of the second end of conductor layer 111. Through-hole T107 is connected to the vicinity of the second end of conductor layer 112. Through-hole T109 is connected to the vicinity of the second end of conductor layer 121. Through-hole T110 is connected to the vicinity of the second end of conductor layer 122. Through-hole T112 is connected to conductor layer 131. Through-hole T115 is connected to conductor layer 132. Through-hole T118 is connected to the vicinity of the second end of conductor layer 135. Through-hole T119 is connected to the vicinity of the first end of conductor layer 136. Through-hole T120 is connected to the vicinity of the second end of conductor layer 136. Through-hole T121 is connected to the vicinity of the second end of conductor layer 141. Through-hole T122 is connected to the vicinity of the second end of conductor layer 142. The through-hole T123 is connected to the vicinity of the first end of the conductor layer 142.

[0055] As shown in Figure 9, the pattern-forming surface of the second dielectric layer 32 has a conductor layer 213 for the first circuit 21, a conductor layer 223 for the second circuit 22, conductor layers 231, 232, 233, and 234 for the third circuit 23, and a conductor layer 243 for the matching circuit 24.

[0056] Furthermore, through-holes T201, T202, T203, T204, T205, T206, T207, T208, T209, T210, T211, T212, T213, T214, T215, T216, T217, T218, T219, T220, T221, T222, T223, and T224 are formed in the dielectric layer 32. Through-holes T201~T207, T209, T210, T212, T215, T218~T223 are connected to through-holes T101~T107, T109, T110, T112, T115, T118~T123, respectively, formed in the first dielectric layer 31.

[0057] Through-hole T208 is connected to conductor layer 213. Through-hole T211 is connected to conductor layer 223. Through-hole T213 is connected to conductor layer 231. Through-hole T214 is connected to conductor layer 232. Through-hole T216 is connected to conductor layer 233. Through-hole T217 is connected to conductor layer 234. Through-hole T224 is connected to conductor layer 243.

[0058] As shown in Figure 10, the pattern-forming surface of the third dielectric layer 33 has conductor layers 301, 302, 303, 304, 305, conductor layers 311, 312, 313 for the first circuit 21, conductor layer 314, conductor layers 321, 322, 323 for the second circuit 22, conductor layers 331, 332, 333, 334, 335 for the third circuit 23, conductor layer 337, and conductor layers 341, 342, 343 for the matching circuit 24. Conductor layers 313 and 323 are connected to conductor layer 305. Conductor layer 331 is connected to conductor layer 302. Conductor layer 333 is connected to conductor layer 303. Conductor layer 343 is connected to conductor layer 301.

[0059] Each of the conductor layers 311, 312, 314, 321, 322, 335, 341, and 342 has a first end and a second end located on opposite sides of each other. The first end of conductor layer 311 is connected to the first end of conductor layer 321. The first end of conductor layer 312 is connected to conductor layer 331. The first end of conductor layer 314 is connected to conductor layer 313. The second end of conductor layer 314 is connected to the vicinity of the first end of conductor layer 342. The first end of conductor layer 322 is connected to conductor layer 333. The first end of conductor layer 341 is connected to conductor layer 301. The first end of conductor layer 342 is connected to conductor layer 304.

[0060] The through-holes T201 to T205 formed in the second dielectric layer 32 are connected to the conductor layers 301 to 305, respectively. In Figure 10, the dashed lines indicate the connection positions of the through-holes T206 to T224 formed in the second dielectric layer 32. Through-hole T206 is connected to the vicinity of the second end of the conductor layer 311. Through-hole T207 is connected to the vicinity of the second end of the conductor layer 312. Through-hole T208 is connected to the conductor layer 313. Through-hole T209 is connected to the vicinity of the second end of the conductor layer 321. Through-hole T210 is connected to the vicinity of the second end of the conductor layer 322. Through-hole T211 is connected to the conductor layer 323.

[0061] Through-hole T212 is connected to conductor layer 337. Through-hole T213 is connected to conductor layer 331. Through-holes T214 and T219 are connected to conductor layer 332 at different locations. Through-hole T215 is connected to the vicinity of the first end of conductor layer 335. Through-hole T216 is connected to conductor layer 333. Through-holes T217 and T220 are connected to conductor layer 334 at different locations. Through-hole T218 is connected to the vicinity of the second end of conductor layer 335. Through-hole T221 is connected to the vicinity of the second end of conductor layer 341. Through-hole T222 is connected to the vicinity of the second end of conductor layer 342. Through-hole T223 is connected to the vicinity of the second end of conductor layer 311. Through-hole T224 is connected to conductor layer 343.

[0062] Furthermore, through-holes T301, T302, T303, T304, and T305 are formed in the dielectric layer 33. Through-holes T301 to T305 are connected to the conductor layers 301 to 305, respectively.

[0063] As shown in Figure 11, the terminal formation surface of the third dielectric layer 33 has the first to fifth terminals 41 to 45 formed thereon. Also in Figure 11, the dashed lines indicate the connection positions of the through-holes T301 to T305. The through-holes T301 to T305 are connected to the first to fifth terminals 41 to 45, respectively.

[0064] The laminate 30 shown in Figure 5 is constructed by laminating the first to third dielectric layers 31 to 33 on the bottom surface of the support substrate 30B such that the terminal forming surface of the third dielectric layer 33 is on the bottom surface 30b of the laminate 30. The electronic component 1 may also include an insulating layer (not shown) interposed between the first dielectric layer 31 of the main body 30A and the support substrate 30B.

[0065] The following describes the correspondence between the components of electronic component 1 and the internal components of the main body 30A shown in Figures 7 to 11. First, the first circuit 21 will be described. The first inductor L11 is composed of conductor layers 111 and 311 connected to each other by through-holes T106 and T206. The first inductor L12 is composed of conductor layers 112 and 312 connected to each other by through-holes T107 and T207. The first capacitor C11 is composed of conductor layers 113 and 213 and a dielectric layer 31 between the conductor layers 113 and 213.

[0066] Next, the second circuit 22 will be described. The second inductor L21 is composed of conductor layers 121 and 321 connected to each other by through-holes T109 and T209. The second inductor L22 is composed of conductor layers 122 and 322 connected to each other by through-holes T110 and T210. The second capacitor C21 is composed of conductor layers 123 and 223 and a dielectric layer 31 between the conductor layers 123 and 223.

[0067] Next, the third circuit 23 will be described. The third capacitor C31 is composed of conductor layers 131, 231 and a dielectric layer 31 between the conductor layers 131, 231. The third capacitor C32 is composed of conductor layers 131, 232 and a dielectric layer 31 between the conductor layers 131, 232. The fourth capacitor C33 is composed of conductor layers 132, 233 and a dielectric layer 31 between the conductor layers 132, 233. The fourth capacitor C34 is composed of conductor layers 132, 234 and a dielectric layer 31 between the conductor layers 132, 234. The third inductor L31 is composed of conductor layers 135, 335 connected to each other by through-holes T118, T228. The resistive element R31 is composed of a conductor layer 136.

[0068] Next, the matching circuit 24 will be described. The matching circuit capacitor C41 is composed of conductor layers 143 and 243 and a dielectric layer 31 between the conductor layers 143 and 243. The matching circuit inductor L41 is composed of conductor layers 141 and 341 connected to each other by through-holes T121 and T221. The matching circuit inductor L42 is composed of conductor layers 142 and 342 connected to each other by through-holes T122 and T222.

[0069] Next, the operation and effects of the electronic component 1 and communication device 100 according to this embodiment will be described. The electronic component 1 according to this embodiment is a distributor and combiner. One of the main parameters that represent the characteristics of a distributor and combiner is isolation. The definition of isolation for electronic component 1 is as follows: When a high-frequency signal with power P20 is input to the second input / output port 12, the power of the signal output from the third input / output port 13 is denoted as P23. Isolation I is defined by the following equation (1).

[0070] I = 10log(P23 / P20) …(1)

[0071] The isolation I is preferably -10 dB or less. In this embodiment, a third circuit 23 is provided between the second input / output port 12 and the third input / output port 13, having a circuit configuration that is complex conjugate to each of the first and second circuits 21 and 22. As a result, according to this embodiment, the frequency bandwidth in which the isolation I is below a predetermined magnitude can be widened.

[0072] The effects of this embodiment will be explained below with reference to the simulation results. First, the models of the first embodiment and the comparative example used in the simulation will be described. The model of the first embodiment is a model of electronic component 1 according to this embodiment. The model of the comparative example is a model of comparative electronic component 51, which is a general Wilkinson-type distributor and combiner.

[0073] Figure 12 is a circuit diagram showing the circuit configuration of the comparative example electronic component 51. The comparative example electronic component 51 comprises a first input / output port 11, a second input / output port 12, a third input / output port 13, inductors L51 and L52, a capacitor C51, and a resistor R51. Inductor L51 is provided between the first input / output port 11 and the second input / output port 12. Inductor L52 is provided between the first input / output port 11 and the third input / output port 13. Resistor R51 is provided between the second input / output port 12 and the third input / output port 13. One end of capacitor C51 is connected to one end of inductor L51 and resistor R51, and the other end is connected to the other end of inductor L51 and resistor R51.

[0074] In the simulation, isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 were determined for both the model of the first embodiment and the model of the comparative example. The definitions of insertion loss and reflection loss for electronic component 1 are as follows: When power P10 is input to the first input / output port 11, P11 is the power of the signal reflected by the first input / output port 11, and P12 is the power of the signal output from the second input / output port 12. Also, when a high-frequency signal with power P20 is input to the second input / output port 12, P22 is the power of the signal reflected by the second input / output port 12, and P21 is the power of the signal output from the first input / output port 11. The insertion loss IL, the reflection loss RL1 of the first input / output port 11, and the reflection loss RL2 of the second input / output port 12 are defined by the following equations (2) to (4).

[0075] IL = 10log(P12 / P10) …(2) RL1 = 10log(P11 / P10) …(3) RL2 = 10log(P22 / P20) …(4)

[0076] The definitions of isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 for the comparative example electronic component 51 are the same as the definitions of isolation I, insertion loss IL, reflection loss RL1 of the first input / output port 11, and reflection loss RL2 of the second input / output port 12 for electronic component 1.

[0077] Figure 13 is a characteristic curve showing the frequency characteristics of isolation in the comparative example model. In Figure 13, the horizontal axis represents frequency, and the vertical axis represents isolation. In the comparative example model, isolation was -10 dB or less when the frequency was within the range of 4729 to 5304 MHz. Therefore, the bandwidth in which isolation was -10 dB or less was 575 MHz. The relative bandwidth, which is the bandwidth divided by the center frequency, was 11.5%.

[0078] Figure 14 is a characteristic curve showing the frequency characteristics of the insertion loss in the comparative example model. In Figure 14, the horizontal axis represents frequency and the vertical axis represents insertion loss. If the insertion loss is represented as -x (dB), the value of x was 3.54 at 5000 MHz.

[0079] Figure 15 is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output port 11 in the comparative example model. Figure 16 is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output port 12 in the comparative example model. In both Figure 15 and Figure 16, the horizontal axis represents frequency and the vertical axis represents reflection loss. When the reflection loss of the first input / output port 11 is expressed as -r1 (dB), the value of r1 was 9.56 at 2400 MHz, 9.52 at 5000 MHz, and 9.50 at 6000 MHz. When the reflection loss of the second input / output port 12 is expressed as -r2 (dB), the value of r2 was 9.66 at 2400 MHz, 15.28 at 5000 MHz, and 11.1 at 6000 MHz.

[0080] Figure 17 is a characteristic diagram showing the frequency characteristics of isolation in the model of the first embodiment. In Figure 17, the horizontal axis represents frequency and the vertical axis represents isolation. In the model of the first embodiment, isolation was -10 dB or less when the frequency range was 2015 to 8228 MHz. Therefore, the bandwidth in which isolation was -10 dB or less was 6213 MHz. The relative bandwidth, which is the bandwidth divided by the center frequency, was 121.3%.

[0081] Figure 18 is a characteristic diagram showing the frequency characteristics of the insertion loss in the model of the first embodiment. In Figure 18, the horizontal axis represents frequency and the vertical axis represents insertion loss. When the insertion loss is expressed as -x (dB), the value of x was 3.52 at 2400 MHz and 3.34 at 6000 MHz.

[0082] Figure 19 is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output port 11 in the model of the first embodiment. Figure 20 is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output port 12 in the model of the first embodiment. In both Figure 19 and Figure 20, the horizontal axis represents frequency and the vertical axis represents reflection loss. When the reflection loss of the first input / output port 11 is expressed as -r1 (dB), the value of r1 was 18.05 at 2400 MHz, 19.27 at 5000 MHz, and 29.86 at 6000 MHz. When the reflection loss of the second input / output port 12 is expressed as -r2 (dB), the value of r2 was 19.27 at 2400 MHz, 29.41 at 5000 MHz, and 28.93 at 6000 MHz.

[0083] From the results shown in Figures 13 and 17, it can be seen that the bandwidth in which isolation is -10 dB or less in the model of the first embodiment is 10.8 times that of the model of the comparative example. Thus, according to this embodiment, the frequency bandwidth in which isolation is below a predetermined magnitude can be widened. Furthermore, from the results shown in Figures 18 to 20, it can be seen that the model of the first embodiment has practically sufficient characteristics in a wide frequency band, for example, 2400 to 6000 MHz. Thus, according to this embodiment, the electronic component 1 can be used in a wide frequency band.

[0084] In the comparative example, for the electronic component 51, one way to make the bandwidth in which the isolation is -10 dB or less the same width as that of the electronic component 1 according to this embodiment is to connect multiple stages (for example, 10 or more stages) of circuit portions consisting of inductors L51, L52, capacitor C51, and resistor R51 in cascaded order, as described in Patent Document 4. However, this would increase the size of the electronic component 51. In contrast, according to this embodiment, it is possible to widen the frequency bandwidth in which the isolation is below a predetermined size without increasing the size of the electronic component 1.

[0085] [Second Embodiment] Next, a second embodiment of the present invention will be described. First, the configuration of the electronic component according to this embodiment will be described with reference to Figures 21 and 22. Figure 21 is a block diagram showing the configuration of the electronic component according to this embodiment. Figure 22 is a circuit diagram showing the circuit configuration of the electronic component according to this embodiment.

[0086] The configuration of the electronic component 61 according to this embodiment is the same as the configuration of the electronic component 1 according to the first embodiment, except that the matching circuit 24 is not provided. In this embodiment, the first input / output port 11 is connected to node ND.

[0087] Next, an example of the characteristics of the electronic component 61 according to this embodiment will be described by referring to the simulation results. In the simulation, isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 were determined using the model of the second embodiment, which is a model of the electronic component 61 according to this embodiment. The definitions of isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 for the electronic component 61 according to this embodiment are the same as the definitions of isolation I, insertion loss IL, reflection loss RL1 of the first input / output port 11, and reflection loss RL2 of the second input / output port 12 for the electronic component 1 according to the first embodiment.

[0088] Figure 23 is a characteristic curve showing the frequency characteristics of isolation in the model of the second embodiment. In Figure 23, the horizontal axis represents frequency and the vertical axis represents isolation. In the model of the second embodiment, isolation was -10 dB or less when the frequency was in the range of 1805 to 7983 MHz. Therefore, the bandwidth in which isolation was -10 dB or less was 6178 MHz. The relative bandwidth, which is the bandwidth divided by the center frequency, was 126.2%.

[0089] Figure 24 is a characteristic diagram showing the frequency characteristics of the insertion loss in the model of the second embodiment. In Figure 24, the horizontal axis represents frequency and the vertical axis represents insertion loss. When the insertion loss is expressed as -x (dB), the value of x was 3.57 at 2400 MHz and 3.28 at 6000 MHz.

[0090] Figure 25 is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output port 11 in the model of the second embodiment. Figure 26 is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output port 12 in the model of the second embodiment. In both Figure 25 and Figure 26, the horizontal axis represents frequency and the vertical axis represents reflection loss. When the reflection loss of the first input / output port 11 is expressed as -r1 (dB), the value of r1 was 10.66 at 2400 MHz, 17.03 at 5000 MHz, and 39.21 at 6000 MHz. When the reflection loss of the second input / output port 12 is expressed as -r2 (dB), the value of r2 was 11.62 at 2400 MHz, 22.65 at 5000 MHz, and 29.34 at 6000 MHz.

[0091] As can be seen from the results shown in Figure 25, the bandwidth in which isolation is -10 dB or less in the model of the second embodiment is approximately the same as the bandwidth in which isolation is -10 dB or less in the model of the first embodiment described in the first embodiment. Thus, according to this embodiment, the frequency bandwidth in which isolation is below a predetermined magnitude can be widened. Furthermore, as can be seen from the results shown in Figures 24 to 26, the model of the second embodiment has practically sufficient characteristics in a wide frequency band, for example, 2400 to 6000 MHz. Thus, according to this embodiment, the electronic component 61 can be used in a wide frequency band.

[0092] Other configurations, operations, and effects in this embodiment are the same as those in the first embodiment.

[0093] [Third Embodiment] Next, a third embodiment of the present invention will be described with reference to Figure 27. The electronic component 71 according to this embodiment differs from the electronic component 61 according to the second embodiment in the following respects. The electronic component 71 according to this embodiment includes a first circuit 26, a second circuit 27, and a third circuit 28 instead of the first to third circuits 21 to 23 in the second embodiment. The circuit configuration arrangement of the first to third circuits 26 to 28 in the electronic component 71 is the same as the circuit configuration arrangement of the first to third circuits 21 to 23 in the electronic component 61 according to the second embodiment. The third circuit 28 has a circuit configuration that is complex conjugate to each of the first and second circuits 26 and 27. The functions of the first to third circuits 26 to 28 are the same as the functions of the first to third circuits 21 to 23 in the second embodiment.

[0094] The first circuit 26 includes at least one first capacitor provided in the first path P1 connecting the first input / output port 11 and the second input / output port 12, and at least one first inductor provided between the first path P1 and ground. The second circuit 27 includes at least one second capacitor provided in the second path P2 connecting the first input / output port 11 and the third input / output port 13, and at least one second inductor provided between the second path P2 and ground.

[0095] Third circuit 28 The third circuit includes at least one third inductor connected in series with at least one first capacitor, at least one fourth inductor connected in series with at least one second capacitor, and at least one third capacitor. 28 It further includes a resistive element R81. At least one third capacitor and the resistive element R81 are provided in parallel between at least one third inductor and at least one fourth inductor. The circuit configuration of the third circuit 28 is symmetrical with respect to at least one third capacitor and the resistive element R81.

[0096] The specific circuit configuration of the electronic component 71 according to this embodiment will now be described with reference to Figure 27. As shown in Figure 27, the first circuit 26 includes two first capacitors C61 and C62 and one first inductor L61. One end of the first capacitor C61 is connected to node ND. The other end of the first capacitor C61 is connected to one end of the first capacitor C62 and one end of the first inductor L61. The other end of the first capacitor C62 is connected to the second input / output port 12. The other end of the first inductor L61 is connected to ground.

[0097] The configuration of the second circuit 27 is the same as that of the first circuit 26. That is, the second circuit 27 includes two second capacitors C71 and C72 and one second inductor L71. One end of the second capacitor C71 is connected to node ND. The other end of the second capacitor C71 is connected to one end of the second capacitor C72 and one end of the second inductor L71. The other end of the second capacitor C72 is connected to the third input / output port 13. The other end of the second inductor L71 is connected to ground.

[0098] The third circuit 28 includes two third inductors L81 and L82 connected in series with the first capacitors C61 and C62, two fourth inductors L83 and L84 connected in series with the second capacitors C71 and C72, and one third capacitor C81. One end of the third inductor L81 is connected to the other end of the first capacitor C62 and to the second input / output port 12. The other end of the third inductor L81 is connected to one end of the third inductor L82 and to one end of the third capacitor C81. One end of the fourth inductor L83 is connected to the other end of the second capacitor C72 and to the third input / output port 13. The other end of the fourth inductor L83 is connected to one end of the fourth inductor L84 and to the other end of the third capacitor C81.

[0099] The other end of the third inductor L82 is connected to one end of the resistor R81. The other end of the fourth inductor L84 is connected to the other end of the resistor R81.

[0100] Furthermore, the electronic component 71 may, in the same manner as the electronic component 1 in the first embodiment, include a matching circuit provided between the first input / output port 11 and the first and second circuits 26 and 27 in terms of circuit configuration. Other configurations, operations, and effects in this embodiment are the same as in the first or second embodiment.

[0101] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. First, the configuration of the electronic component according to this embodiment will be described with reference to Figures 28 and 29. Figure 28 is a block diagram showing the configuration of the electronic component according to this embodiment. Figure 29 is a circuit diagram showing the circuit configuration of the electronic component according to this embodiment.

[0102] The configuration of the electronic component 401 according to this embodiment is basically the same as that of the electronic component 1 according to the first embodiment. That is, the electronic component 401 comprises first to third input / output ports 11 to 13, first to third circuits 21 to 23, and a matching circuit 24.

[0103] The configuration of the first to third circuits 21-23 and the matching circuit 24 is the same as in the first embodiment, except as follows: In this embodiment, the first circuit 21 and the second circuit 22 are connected by multiple paths that do not go through the third circuit 23. In particular, in this embodiment, the first circuit 21 and the second circuit 22 are connected by one path that goes through node ND and another path that does not go through node ND and the third circuit 23. Neither the first circuit 21 nor the second circuit 22 is connected to ground.

[0104] As shown in Figure 29, in this embodiment, the first capacitor C11 of the first circuit 21 and the second capacitor C21 of the second circuit 22 are connected to each other. The path connecting the first capacitor C11 and the second capacitor C21 corresponds to the "other path that does not go through node ND and the third circuit 23" mentioned above.

[0105] Furthermore, the third circuit 23 includes two inductors L31A and L31B connected in series, and two resistors R31A and R31B connected in series, instead of the third inductor L31 and resistor R31 in the first embodiment. One end of inductor L31A is connected to one end each of the third capacitors C31 and C32. One end of inductor L31B is connected to one end each of the fourth capacitors C33 and C34. The other ends of inductors L31A and L31B are connected to each other.

[0106] One end of resistor R31A is connected to the other end of the third capacitor C32. One end of resistor R31B is connected to the other end of the fourth capacitor C34. The other ends of resistors R31A and R31B are connected to each other.

[0107] Next, an example of the characteristics of the electronic component 401 according to this embodiment will be described by referring to the simulation results. In the simulation, isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 were determined using the model of the third embodiment, which is a model of the electronic component 401 according to this embodiment. 401 The definitions of isolation, insertion loss, reflection loss of the first input / output port 11, and reflection loss of the second input / output port 12 are the same as the definitions of isolation I, insertion loss IL, reflection loss RL1 of the first input / output port 11, and reflection loss RL2 of the second input / output port 12 of the electronic component 1 according to the first embodiment.

[0108] Figure 30 is a characteristic diagram showing the frequency characteristics of isolation in the model of the third embodiment. In Figure 30, the horizontal axis represents frequency and the vertical axis represents isolation. In the model of the third embodiment, isolation was -10 dB or less when the frequency was in the range of 3574 to 5719 MHz. Therefore, the bandwidth in which isolation was -10 dB or less was 2145 MHz. The relative bandwidth, which is the bandwidth divided by the center frequency, was 46.2%.

[0109] Figure 31 is a characteristic diagram showing the frequency characteristics of the insertion loss in the model of the third embodiment. 31 In this graph, the horizontal axis represents frequency and the vertical axis represents insertion loss. If insertion loss is represented as -x (dB), the value of x was 3.62 at 3574MHz and 3.55 at 5179MHz.

[0110] Figure 32 is a characteristic diagram showing the frequency characteristics of the reflection loss of the first input / output port 11 in the model of the third embodiment. Figure 33 is a characteristic diagram showing the frequency characteristics of the reflection loss of the second input / output port 12 in the model of the third embodiment. In both Figure 32 and Figure 33, the horizontal axis represents frequency and the vertical axis represents reflection loss. When the reflection loss of the first input / output port 11 is expressed as -r1 (dB), the value of r1 was 13.17 at 3574 MHz and 11.13 at 5179 MHz. When the reflection loss of the second input / output port 12 is expressed as -r2 (dB), the value of r2 was 20.09 at 3574 MHz and 21.83 at 5179 MHz.

[0111] As can be seen from the results shown in Figure 30, the bandwidth over which isolation is -10 dB or less in the model of the third embodiment is wider than the bandwidth over which isolation is -10 dB or less in the comparative example model described in the first embodiment. Thus, according to this embodiment, the frequency bandwidth over which isolation is below a predetermined magnitude can be widened. Furthermore, as can be seen from the results shown in Figures 31 to 33, the model of the third embodiment has practically sufficient characteristics in a wide frequency band, for example, 3574 to 5719 MHz. Thus, according to this embodiment, the electronic component 401 can be used in a wide frequency band.

[0112] Furthermore, the electronic component 401 in this embodiment may not be provided with a matching circuit 24, similar to the electronic component 61 in the second embodiment. Other configurations, operations, and effects in this embodiment are the same as in the first or second embodiment.

[0113] [Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to Figures 34 and 35. Figure 34 is a block diagram showing the configuration of the electronic component according to this embodiment. Figure 35 is a circuit diagram showing the circuit configuration of the electronic component according to this embodiment.

[0114] The configuration of the electronic component 501 according to this embodiment differs from the configuration of the electronic component 401 according to the fourth embodiment in the following respects. In addition to the first to third input / output ports 11 to 13, the first to third circuits 21 to 23 and the matching circuit 24, the electronic component 501 includes a fourth input / output port 14, a fourth circuit 524, and a fifth circuit 525.

[0115] The fourth circuit 524 is configured to be located between the first input / output port 11 and the fourth input / output port 14. Similar to the first to third circuits 21-23, the fourth circuit 524 is a characteristic impedance conversion circuit used to adjust the impedance of the fourth circuit 524 to a predetermined value (e.g., 50Ω).

[0116] In this embodiment, the second circuit 22 is connected to the first circuit 21 by multiple paths that do not pass through the third circuit 23, and is also connected to the fourth circuit 524 by multiple paths that do not pass through the fifth circuit 525. In particular, in this embodiment, the second circuit 22 and the fourth circuit 524 are connected by one path that passes through node ND and another path that does not pass through node ND or the fifth circuit 525. None of the first, second, and fourth circuits 21, 22, and 524 are connected to ground.

[0117] As shown in Figure 35, the configuration of the fourth circuit 524 is the same as that of the first and second circuits 21 and 22. That is, the fourth circuit 524 includes two inductors L241 and L242 and one capacitor C241. One end of inductor L241 is connected to node ND. The other end of inductor L241 is connected to one end of inductor L242 and one end of capacitor C241. The other end of inductor L242 is connected to the fourth input / output port 14. The other end of capacitor C241 is connected to the connection point between the first capacitor C11 of the first circuit 21 and the second capacitor C21 of the second circuit 22.

[0118] As shown in Figure 35, the second capacitor C21 of the second circuit 22 and the capacitor C241 of the fourth circuit 524 are connected to each other. The path connecting the second capacitor C21 and the capacitor C241 corresponds to the "other path that does not go through node ND and the fifth circuit 525" mentioned above.

[0119] The fifth circuit 525 is configured to be located between the third input / output port 13 and the fourth input / output port 14. Similar to the third circuit 23, the fifth circuit 525 is a signal absorption circuit that absorbs the signal that flows to the other input / output port 14 when a signal is input to one of the third input / output port 13 or the fourth input / output port 14. The fifth circuit 525 has a circuit configuration that is complex conjugate to each of the second and fourth circuits 22 and 524. That is, the elements constituting the fifth circuit 525 are arranged in the fifth circuit 525 such that they are complex conjugate to the elements constituting each of the second and fourth circuits 22 and 524.

[0120] Electronic components 501 The circuit further comprises a first sub-circuit 511, a second sub-circuit 512, and a third sub-circuit 513. The first to third sub-circuits 511 to 513 are connected to each other. The third circuit 23 is composed of the first and second sub-circuits 511 and 512. The fifth circuit 525 is composed of the second and third sub-circuits 512 and 513. The second sub-circuit 512 is used in both the third circuit 23 and the fifth circuit 525.

[0121] The first sub-circuit 511 includes two capacitors C311 and C312 connected in series with the first inductors L11 and L12, an inductor L31A, and a resistor R31A. The second sub-circuit 512 includes two capacitors C321 and C322 connected in series with the second inductors L21 and L22, an inductor L31B, and a resistor R31B. The third sub-circuit 513 includes two capacitors C331 and C332 connected in series with inductors L241 and L242, an inductor L31C, and a resistor R31C. Capacitors C311 and C312 correspond to the third capacitors C31 and C32 in the fourth embodiment, respectively, and capacitors C321 and C322 correspond to the fourth capacitors C33 and C34 in the fourth embodiment, respectively.

[0122] One end of capacitor C311 is connected to the first inductor L12 and the second input / output port 12. The other end of capacitor C311 is connected to one end of capacitor C312 and one end of inductor L31A. One end of capacitor C321 is connected to the second inductor L22 and the third input / output port 13. The other end of capacitor C321 is connected to one end of capacitor C322 and one end of inductor L31B. One end of capacitor C331 is connected to inductor L242 and the fourth input / output port 14. The other end of capacitor C331 is connected to one end of capacitor C332 and one end of inductor L31C. The other ends of inductors L31A, L31B, and L341C are connected to each other.

[0123] The other end of capacitor C312 is connected to one end of resistor R31A. The other end of capacitor C322 is connected to one end of resistor R31B. The other end of capacitor C332 is connected to one end of resistor R31C. The other ends of resistors R31A, R31B, and R31C are connected to each other.

[0124] In this embodiment, the third circuit 23 includes capacitors C311, C312, C321, and C322, inductors L31A and L31B, and resistors R31A and R31B. The fifth circuit 525 includes capacitors C321, C322, C331, and C332, inductors L31B and L31C, and resistors R31B and R31C. Capacitors C321 and C322, inductors L31B, and resistors R31B are used in both the third circuit 23 and the fifth circuit 525.

[0125] Furthermore, in this embodiment, the electronic component 501 can be considered as having two of one of the "first circuit" and "second circuit" of the present invention, one of the "first circuit" and "second circuit" of the present invention, the fourth circuit 524 of the present invention, and the fifth circuit 525 of the present invention. In this case, the electronic component 501 can be considered as having two of one of the "first circuit" and "second circuit," one of the "first circuit" and "second circuit," and two of the "third circuit."

[0126] Other configurations, operations, and effects in this embodiment are the same as those in the fourth embodiment.

[0127] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are possible. For example, as long as the requirements of the claims are met, the number of input / output ports on the branch side and the number and arrangement of inductors and capacitors in each circuit are not limited to the examples shown in each embodiment, but are arbitrary. The number of input / output ports on the branch side is not limited to two or three, but may be four or more.

[0128] Furthermore, the electronic component of the present invention may include other circuits such as filters in addition to the configuration shown in Figure 1 or Figure 21. In this case, at least one of the first to third input / output ports 11 to 13 may be provided inside the laminate 30.

[0129] Furthermore, the first to third circuits of the present invention are not limited to distributors and combiners, but can be applied to various electronic components having functions such as branch switches, shunts, mixers, splitters, dividers, combiners, and 3dB hybrids.

[0130] Furthermore, the electronic components of the present invention are not limited to the laminate 30 described with reference to Figures 5 to 11, as long as they have a circuit configuration that satisfies the claims, but can also be constructed using a low-temperature co-fired ceramic (LTCC) multilayer substrate or discrete elements, i.e., chip capacitors, chip inductors, and chip resistors.

[0131] Furthermore, in the third embodiment, the first circuit 26 and the second circuit 27 may be connected by multiple paths that do not go through the third circuit 28, similar to the first and second circuits 21 and 22 in the fourth embodiment. Specifically, the first circuit 26 The first inductor L61 of circuit 26 and the second inductor L71 of circuit 27 may be connected to each other. Neither the first circuit 26 nor the second circuit 27 may be connected to ground.

[0132] Furthermore, in the fifth embodiment, the first, second, and fourth circuits 21, 22, and 524 may all be connected to ground, similar to the first and second circuits 21 and 22 in the first embodiment. In this case, the first capacitor C11 of the first circuit 21, the second capacitor C21 of the second circuit 22, and the capacitor C241 of the fourth circuit 524 do not need to be connected to each other. [Explanation of Symbols]

[0133] 1...Electronic component, 2,2A,2B...Antenna, 3...Signal processing circuit, 11...First input / output port, 12...Second input / output port, 13...Third input / output port, 21...First circuit, 22...Second circuit, 23...Third circuit, 24...Matching circuit, 30...Laminate, 30A...Main body, 30B...Support substrate, 31~33...Dielectric layer, 41...First terminal, 42...Second terminal, 43...Third terminal, 44...Fourth terminal, 45...Fifth terminal, 100...Communication equipment.

Claims

1. The first input / output port, The second input / output port, A third input / output port, A first circuit, which is a characteristic impedance conversion circuit, is provided between the first input / output port and the second input / output port. A second circuit, which is a characteristic impedance conversion circuit, is provided between the first input / output port and the third input / output port. The system comprises a third circuit provided between the second input / output port and the third input / output port, Each of the first to third circuits includes at least one inductor and at least one capacitor, The at least one inductor of the third circuit is provided in the third circuit such that it is complex conjugate to the at least one capacitor of each of the first and second circuits. The at least one capacitor of the third circuit is provided in the third circuit such that it is complex conjugate to the at least one inductor of each of the first and second circuits. The first circuit includes, as the at least one inductor and the at least one capacitor, a first inductor provided in a first path connecting the first input / output port and the second input / output port, and a first capacitor, The second circuit includes, as the at least one inductor and the at least one capacitor, a second inductor provided in a second path connecting the first input / output port and the third input / output port, and a second capacitor. The third circuit is an electronic component characterized by including, as the at least one inductor and the at least one capacitor, a third capacitor connected in series with the first inductor, a fourth capacitor connected in series with the second inductor, and the third inductor.

2. The third circuit further includes a resistive element, The electronic component according to claim 1, characterized in that the third inductor and the resistive element are provided in parallel between the third capacitor and the fourth capacitor.

3. The first capacitor is provided between the first path and ground. The electronic component according to claim 1 or 2, characterized in that the second capacitor is provided between the second path and the ground.

4. The electronic component according to claim 1 or 2, characterized in that the first capacitor and the second capacitor are connected to each other.

5. The electronic component according to claim 2, characterized in that the circuit configuration of the third circuit is symmetrical with respect to the third inductor and the resistive element.

6. The first input / output port, The second input / output port, A third input / output port, A first circuit, which is a characteristic impedance conversion circuit, is provided between the first input / output port and the second input / output port. A second circuit, which is a characteristic impedance conversion circuit, is provided between the first input / output port and the third input / output port. The system comprises a third circuit provided between the second input / output port and the third input / output port, Each of the first to third circuits includes at least one inductor and at least one capacitor, The at least one inductor of the third circuit is provided in the third circuit such that it is complex conjugate to the at least one capacitor of each of the first and second circuits. The at least one capacitor of the third circuit is provided in the third circuit such that it is complex conjugate to the at least one inductor of each of the first and second circuits. The first circuit includes, as the at least one inductor and the at least one capacitor, a first capacitor provided in a first path connecting the first input / output port and the second input / output port, and a first inductor provided between the first path and ground. The second circuit includes, as the at least one inductor and the at least one capacitor, a second capacitor provided in the second path connecting the first input / output port and the third input / output port, and a second inductor provided between the second path and the ground. The third circuit includes, as the at least one inductor and the at least one capacitor, a third inductor connected in series with the first capacitor, a fourth inductor connected in series with the second capacitor, and a third capacitor. The third circuit further includes a resistive element, The electronic component is characterized in that the third capacitor and the resistive element are provided in parallel between the third inductor and the fourth inductor.

7. The electronic component according to claim 6, characterized in that the circuit configuration of the third circuit is symmetrical with respect to the third capacitor and the resistor element.

8. The electronic component according to claim 1, characterized in that the first circuit and the second circuit are each connected to ground.

9. The electronic component according to claim 1, characterized in that the first circuit and the second circuit are connected by a plurality of paths that do not pass through the third circuit.

10. The electronic component according to claim 9, characterized in that neither the first circuit nor the second circuit is connected to ground.

11. Furthermore, there is a fourth input / output port, A fourth circuit, which is a characteristic impedance conversion circuit, is provided between the first input / output port and the fourth input / output port. The system includes a fifth circuit provided between the third input / output port and the fourth input / output port, Each of the fourth and fifth circuits includes at least one other inductor and at least one other capacitor, The at least one other inductor of the fifth circuit is provided in the fifth circuit such that it is complex conjugate to the at least one capacitor of the second circuit and the at least one other capacitor of the fourth circuit. The at least one other capacitor of the fifth circuit is provided in the fifth circuit such that it is complex conjugate to the at least one inductor of the second circuit and the at least one other inductor of the fourth circuit. The fourth circuit includes, as the at least one other inductor and the at least one other capacitor, a fifth inductor provided in a specific path connecting the first input / output port and the fourth input / output port, and a fifth capacitor, The electronic component according to any one of claims 1 to 5, 8 to 10, wherein the fifth circuit includes, as the at least one other inductor and the at least one other capacitor, a sixth capacitor connected in series with the second inductor, a seventh capacitor connected in series with the fifth inductor, and the sixth inductor.

12. The electronic component according to claim 11, characterized in that the second circuit is connected to the first circuit by a plurality of paths that do not pass through the third circuit, and is also connected to the fourth circuit by a plurality of paths that do not pass through the fifth circuit.

13. Furthermore, the electronic component according to any one of claims 1 to 12 is characterized by comprising a matching circuit provided between the first input / output port and the first and second circuits.

14. The first circuit, the second circuit, and the matching circuit branch from one node, The matching circuit is characterized by including a matching circuit capacitor provided in a third path connecting the first input / output port and the node, and a matching circuit inductor provided between the third path and ground, as described in claim 13.

15. The electronic component according to any one of claims 1 to 14, characterized in that the electronic component is a distributor and a combiner.

16. An electronic component according to any one of claims 1 to 15, A communication device characterized by comprising at least one antenna connected to the aforementioned electronic component.

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