Communication device

Abstract

To provide a communication device capable of high-speed, high-quality signal transmission.SOLUTION: A communication device 1 includes a first substrate SUB1, a second substrate SUB2, and an insulating element 50. The first substrate SUB1 has an oscillation circuit 20 and a modulation circuit 30. The second substrate SUB 2 is insulated from the first substrate SUB1, and has a reception circuit 60 and an output circuit 70. The oscillation circuit 20 outputs a carrier signal in a high-frequency band. The modulation circuit 30 outputs a modulated signal based upon the carrier signal, and also adjusts a period in which the modulated signal is output to a length shorter or longer length than that of a period in which an externally input signal Din has a first logical level when the input signal Din has the first logical level. The reception circuit 60 receives an electric signal based upon the modulated signal through the insulating element 50 and demodulates the electric signal. The output circuit 70 outputs an output signal Dout, based upon the electric signal demodulated by the reception circuit 60, to the outside.SELECTED DRAWING: Figure 3

Description

Technical Field

[0004] , , , , , , , ,

[0001] Embodiments relate to a communication device.

Background Art

[0002] A digital isolator is known as a communication device that transmits digital signals between galvanically isolated primary and secondary devices. In a digital isolator, magnetic coupling by an isolation transformer or electric field coupling by an isolation capacitor is used for signal transmission between the primary and secondary devices. That is, the digital isolator realizes signal transmission between the primary and secondary devices using a magnetic field or an electric field as a medium. The digital isolator is used, for example, when connecting a high-voltage device and a low-voltage device. In this case, the digital isolator can suppress the propagation of noise between the high-voltage device and the low-voltage device and the risk of electric shock to the user.

[0003] In a digital isolator, for efficient communication, an input signal modulated in a high-frequency band is input to an isolation transformer or an isolation capacitor provided at the insulation boundary between the primary and secondary devices. As a modulation method used in the digital isolator, for example, an on-off keying (OOK) method that represents digital data based on the presence or absence of a carrier wave is used. The OOK method can simplify the demodulation circuit and enables high-speed demodulation processing. It is preferable that the digital isolator has a pulse width of an input signal input to the primary device and a pulse width of an output signal output from the secondary device that are substantially the same, and can transmit signals between the primary and secondary devices at high speed and with high quality.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

[0005] To provide a communication device capable of high-speed and high-quality signal transmission. [Means for solving the problem]

[0006] The communication device of the embodiment includes a first substrate, a second substrate, and a first insulating element. The first substrate has an oscillator circuit and a first modulation circuit. The second substrate is insulated from the first substrate and has a first receiving circuit and a first output circuit. The first insulating element is connected between the first modulation circuit and the first receiving circuit. The oscillator circuit outputs a carrier signal in the high frequency band. The first modulation circuit has at least one delay circuit and outputs a first modulated signal based on the carrier signal when a first input signal input from an external source is at a first logic level, and uses at least one delay circuit to adjust the length of the period during which the first modulated signal is output to be shorter or longer than the period during which the first input signal is at a first logic level. The first receiving circuit receives a first electrical signal based on the first modulated signal via the first insulating element and demodulates the first electrical signal. The first output circuit outputs a first output signal to the outside, based on the first electrical signal demodulated by the first receiving circuit. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example of the configuration of the communication device according to the first embodiment when N=1. [Figure 2] A block diagram showing an example of the configuration of the communication device according to the first embodiment when N=2. [Figure 3] A schematic diagram showing a more detailed example of the configuration of the communication device according to the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of the input modulation section of a communication device according to the first embodiment. [Figure 5] A circuit diagram showing an example of the circuit configuration of a transmission circuit included in a communication device according to the first embodiment. [Figure 6] A circuit diagram showing an example of the circuit configuration of an amplification circuit included in a communication device according to the first embodiment. [Figure 7] A circuit diagram showing an example of the circuit configuration of a full-wave rectifier circuit included in a communication device according to the first embodiment. [Figure 8] A timing chart showing a first example of operation of a receiving circuit in a communication device according to the first embodiment. [Figure 9] A timing chart showing a second example of operation of a receiving circuit in a communication device according to the first embodiment. [Figure 10] A timing chart showing an example of the operation of a modulation circuit included in a communication device according to the first embodiment. [Figure 11] A circuit diagram showing an example of the circuit configuration of the input modulation section of a communication device according to the second embodiment. [Figure 12] A timing chart showing an example of the operation of a modulation circuit included in a communication device according to the second embodiment. [Figure 13] A circuit diagram showing an example of the circuit configuration of the input modulation section of a communication device according to the third embodiment. [Figure 14] A timing chart showing an example of the operation of a modulation circuit in a communication device according to the third embodiment. [Figure 15] A circuit diagram showing an example of the circuit configuration of the input modulation section of a communication device according to the fourth embodiment. [Figure 16]Timing chart showing an operation example of a modulation circuit included in a communication device according to the fourth embodiment. [Figure 17] Block diagram showing an example of the configuration of a communication device according to the fifth embodiment. [Figure 18] Circuit diagram showing an example of the circuit configuration of an oscillation circuit included in a communication device according to the fifth embodiment. [Figure 19] Circuit diagram showing an example of the circuit configuration of a rising delay circuit. [Figure 20] Timing chart showing an example of the characteristics of a rising delay circuit. [Figure 21] Circuit diagram showing an example of the circuit configuration of a falling delay circuit. [Figure 22] Timing chart showing an example of the characteristics of a falling delay circuit. [Figure 23] Circuit diagram showing an example of the circuit configuration of a communication device according to the first modification of the first embodiment. [Figure 24] Block diagram showing an example of the configuration of a communication device according to the second modification of the first embodiment.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus and method for embodying the technical idea of the invention. The drawings are schematic or conceptual, and dimensions, ratios, etc. in each drawing are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference numerals. In this specification, reference numerals with “hyphen + number” are used when distinguishing a plurality of components having similar functions.

[0009] In this specification, the signal input to the isolation element (isolation transformer or isolation capacitance) in a digital isolator used with an on-off keying (OOK) modulation scheme is referred to as the "OOK modulated signal." This specification describes the case where the logic level indicating no input signal is the "L (Low)" level, and the logic level indicating the presence of an input signal is the "H (High)" level. That is, the "H" level corresponds to the inverse logic level of the "L" level. Note that the correspondence between the presence or absence of an input signal and the logic level may be changed depending on the circuit configuration.

[0010] <1> First Embodiment The communication device 1 according to the first embodiment is a digital isolator that utilizes magnetic field coupling by an isolation transformer. The primary side equipment in the communication device 1 has a function to shorten the period during which it outputs an OOK modulated signal based on the pulse of the input signal to the pulse width of the input signal. Details of the first embodiment will be described below. In the following description, N is an integer of 1 or more and corresponds to the number of channels provided by the communication device 1.

[0011] <1-1> Composition <1-1-1> Configuration of communication device 1 Figure 1 is a block diagram showing an example of the configuration of a communication device 1 according to the first embodiment when N=1. That is, Figure 1 illustrates a communication device 1 configured with one channel. As shown in Figure 1, the N=1 communication device 1 includes, for example, an input circuit 10, an oscillation circuit 20, a modulation circuit 30, a transmission circuit 40, an isolation element 50, a receiving circuit 60, an output circuit 70, an input terminal T1, an output terminal T2, a first board SUB1, and a second board SUB2.

[0012] The input circuit 10, oscillator circuit 20, modulation circuit 30, transmitter circuit 40, and input terminal T1 are mounted on the first board SUB1. The receiver circuit 60, output circuit 70, and output terminal T2 are mounted on the second board SUB2. The insulating element 50 may be mounted on either the first board SUB1 or the second board SUB2, or on both the first board SUB1 and the second board SUB2. The configuration mounted on the first board SUB1 corresponds to the primary side equipment of the communication device 1. The configuration mounted on the second board SUB2 corresponds to the secondary side equipment of the communication device 1. The ground level of the first board SUB1 and the ground level of the second board SUB2 are isolated from each other.

[0013] The input circuit 10 is a receiving circuit that receives a data signal Din input to the input terminal T1 from an external device. The input terminal T1 corresponds to the input terminal of the communication device 1. The input circuit 10 generates an input signal VIN based on the data signal Din. The input circuit 10 then outputs the generated input signal VIN to the oscillation circuit 20 and the modulation circuit 30, respectively. The input circuit 10 includes, for example, a buffer. In other words, the input circuit 10 buffers the input signal input from the external device to the input terminal T1 and outputs it to the oscillation circuit 20 and the modulation circuit 30, respectively. The input signal VIN may also be called the “modulation signal”.

[0014] The oscillator circuit 20 is a signal generator that generates a high-frequency signal based on the input signal VIN. Hereinafter, the high-frequency signal generated by the oscillator circuit 20 will be referred to as the "carrier signal CS". In this specification, the high-frequency band is, for example, 500 MHz or higher. The oscillator circuit 20 generates the carrier signal CS when the input signal VIN is at a "high" level, and stops generating the carrier signal CS when the input signal VIN is at a "low" level. The oscillator circuit 20 outputs the generated carrier signal CS to the modulation circuit 30. The oscillator circuit 20 includes, for example, a ring oscillator. In the communication device 1 with N=1, the input signal VIN and the carrier signal CS operate synchronously.

[0015] The modulation circuit 30 modulates the input signal VIN input from the input circuit 10 using the carrier signal CS. For example, during the period when the input signal VIN is at a "H" level, the modulation circuit 30 outputs a positive-sequence signal and a negative-sequence signal based on the carrier signal CS to the transmission circuit 40. On the other hand, during the period when the input signal VIN is at a "L" level, the modulation circuit 30 stops outputting signals based on the carrier signal CS. In this state, the voltage levels of the positive-sequence input terminal and the negative-sequence input terminal of the transmission circuit 40 are approximately the same. The input signal VIN modulated by the modulation circuit 30 may also be called the "modulated signal". In the communication device 1, the combination of the oscillation circuit 20 and the modulation circuit 30 may also be called the "OOK modulation circuit".

[0016] The transmitting circuit 40 generates a differential signal based on the modulated signals on the positive and negative phases input from the modulation circuit 30. The transmitting circuit 40 then outputs the generated differential signal to the insulating element 50. If the insulating element 50 is an isolation transformer, the transmitting circuit 40 supplies a differential current to the insulating element 50 based on the modulated signals on the positive and negative phases. The differential signal generated by the transmitting circuit 40 corresponds to the OOK modulated signal.

[0017] The insulating element 50 is used for signal transmission using the OOK method. The insulating element 50 includes at least one isolation transformer. The insulating element 50 transmits an electrical signal (differential signal) based on the differential signal input from the transmitting circuit 40 to the receiving circuit 60 by magnetic field coupling of the isolation transformer. The insulating element 50 corresponds to the insulating boundary between the first substrate SUB1 and the second substrate SUB2. The insulating element 50 may also be called a "galvanic insulating element" because it achieves galvanic isolation between the first substrate SUB1 and the second substrate SUB2.

[0018] The receiving circuit 60 is a demodulation circuit that demodulates the electrical signal input from the insulating element 50. The receiving circuit 60 outputs the demodulated electrical signal to the output circuit 70.

[0019] The output circuit 70 generates an output signal based on the electrical signal demodulated by the receiving circuit 60. The output circuit 70 then outputs the generated output signal to the output terminal T2. The output terminal T2 corresponds to the output terminal of the communication device 1. The signal output from the output terminal T2 corresponds to the data signal Dout that the communication device 1 outputs based on the input data signal Din. The output circuit 70 includes, for example, a buffer. In other words, the output circuit 70 buffers the demodulated electrical signal and outputs it externally as an output signal via the output terminal T2.

[0020] Figure 2 is a block diagram showing an example of the configuration of the communication device 1 according to the first embodiment when N=2. That is, Figure 2 illustrates a communication device 1 configured with 2 channels. As shown in Figure 2, the N=2 communication device 1 comprises input circuits 10-1 and 10-2, oscillation circuit 20, modulation circuits 30-1 and 30-2, transmission circuits 40-1 and 40-2, isolation elements 50-1 and 50-2, receiving circuits 60-1 and 60-2, output circuits 70-1 and 70-2, input terminals T1-1 and T1-2, output terminals T2-1 and T2-2, first board SUB1, and second board SUB2.

[0021] The set of input circuit 10-1, modulation circuit 30-1, transmission circuit 40-1, isolation element 50-1, reception circuit 60-1, output circuit 70-1, input terminal T1-1, and output terminal T2-1 corresponds to the first channel of the communication device 1. The first channel receives the data signal Din input to input terminal T1-1. <1> The signal is transmitted via input circuit 10-1, modulation circuit 30-1, transmission circuit 40-1, isolation element 50-1, reception circuit 60-1, and output circuit 70-1, and a data signal Dout is output from output terminal T2-1.

[0022] The set of input circuit 10-2, modulation circuit 30-2, transmission circuit 40-2, isolation element 50-2, reception circuit 60-2, output circuit 70-2, input terminal T1-2, and output terminal T2-2 corresponds to the second channel of the communication device 1. The second channel receives the data signal Din input to input terminal T1-2. <2> The signal is transmitted via input circuit 10-2, modulation circuit 30-2, transmission circuit 40-2, isolation element 50-2, reception circuit 60-2, and output circuit 70-2, and a data signal Dout is output from output terminal T2-2.

[0023] In communication device 1 with N=2, the oscillator circuit 20 is shared among multiple channels. Specifically, the input circuit 10-1 receives the data signal Din <1> The input signal VIN generated based on <1> This is output to the oscillator circuit 20 and the modulation circuit 30-1, respectively. The input circuit 10-2 receives the data signal Din <2> The input signal VIN generated based on <2> This is output to the oscillator circuit 20 and the modulation circuit 30-2, respectively. The oscillator circuit 20 then receives the input signal VIN <1> and <2> Based on this, the carrier signal CS is generated.

[0024] In communication device 1 with N=2, the oscillation circuit 20 receives the input signal VIN. <1> and <2> The carrier signal CS is generated during the period when at least one of the input signals VIN is at an "H" level, and the input signal VIN is generated. <1> and <2> The generation of the carrier signal CS is stopped during the period when both are at the "L" level. The oscillator circuit 20 then outputs the generated carrier signal CS to the modulation circuits 30-1 and 30-2, respectively. In each channel of the communication device 1 with N=2 or more, the input signal VIN and the carrier signal CS may operate asynchronously.

[0025] The communication device 1 may be composed of N (where N is an integer of 2 or more) channels. Since it is permissible for the input signal VIN and the carrier signal CS to be asynchronous in each channel, the communication device 1 only needs to have one oscillator circuit 20 shared by the first to the Nth channels. In this case, the oscillator circuit 20 controls the input signal VIN <1> ~ <n>The carrier signal CS is generated during the period when at least one of the input signals VIN is at a "H" level, and the input signal VIN is generated. <1> ~ <n>The generation of the carrier signal CS is stopped during the period when all of the values ​​are at the "L" level. Note that the first embodiment is valid when N is a positive integer. The following describes the case where the communication device 1 has two channels (N=2).

[0026] Figure 3 is a schematic diagram showing a more detailed example of the configuration of the communication device 1 according to the first embodiment. Figure 3 extracts the configuration related to one channel input and output and shows a typical example of the circuit configuration of a digital isolator used in the OOK method. As shown in Figure 3, the transmitting circuit 40 is shown as a 2-input 2-output driver circuit (Drv.). The communication device 1 further comprises power supply circuits PW1 and PW2, and power supply terminals T3, T4, T5 and T6. Power supply circuit PW1 and power supply terminals T3 and T4 are mounted on the first board SUB1. Power supply circuit PW2 and power supply terminals T5 and T6 are mounted on the second board SUB2.

[0027] Power terminal T3 is a terminal used to supply system power to the first board SUB1. A power supply voltage VDD1 (e.g., 2.25V to 5.5V) is applied to power terminal T3 by an external device. The power supply voltage VDD1 is supplied to the power supply circuit PW1 and the input circuit 10, respectively, via power terminal T3. Power terminal T4 is a terminal used to specify the ground level (ground voltage) of the first board SUB1. A ground voltage VSS1 is applied to power terminal T4 by an external device. In this specification, the power node connected to power terminal T4 and supplying the ground voltage VSS1 is referred to as the "ground node of the first board SUB1".

[0028] The power supply circuit PW1 is a power supply for the miniature MOS transistor mounted on the first substrate SUB1. The minimum gate width of the miniature MOS transistor is, for example, 0.13 μm or 0.18 μm. The power supply circuit PW1 includes, for example, a BGR (Band Gap Reference) circuit and an LDO (Low Drop Out) circuit. The power supply circuit PW1 generates a power supply voltage (for example, 1.5V) for the miniature MOS transistor using the BGR circuit and the LDO circuit. The power supply circuit PW1 then supplies the generated power supply voltage to the input circuit 10, the oscillator circuit 20, the modulation circuit 30, and the transmitter circuit 40, respectively. In this specification, the power supply node that supplies the power supply voltage generated by the power supply circuit PW1 is referred to as the "power supply node of the first substrate SUB1". The voltage applied to the power supply node of the first substrate SUB1 is referred to as "VREF1".

[0029] Power terminal T5 is a terminal used to supply system power to the second board SUB2. An external device applies a power supply voltage VDD2 (e.g., 2.25V to 5.5V) to power terminal T5. The power supply voltage VDD2 is supplied to the power supply circuit PW2 and the output circuit 70, respectively, via power terminal T5. Power terminal T6 is a terminal used to specify the ground level (ground voltage) of the second board SUB2. An external device applies a ground voltage VSS2 to power terminal T6. In this specification, a power node connected to power terminal T6 and supplying the ground voltage VSS2 is referred to as the "ground node of the second board SUB2". For example, one of the power supply voltages VDD1 and VDD2 corresponds to the power supply voltage of high-voltage equipment, and the other corresponds to the power supply voltage of low-voltage equipment.

[0030] The power supply circuit PW2 is a power supply for the miniature MOS transistor mounted on the second substrate SUB2. The power supply circuit PW2 includes, for example, a BGR circuit and an LDO circuit. The power supply circuit PW2 generates a power supply voltage (e.g., 1.5V) for the miniature MOS transistor using the BGR circuit and the LDO circuit. The power supply circuit PW2 then supplies the generated power supply voltage to the amplifier circuit 61, the full-wave rectifier circuit 62, and the output circuit 70, respectively. In this specification, the power supply node that supplies the power supply voltage generated by the power supply circuit PW2 is referred to as the "power supply node of the second substrate SUB2". The voltage applied to the power supply node of the second substrate SUB2 is referred to as "VREF2".

[0031] Furthermore, the communication device 1 includes isolation transformers 51 and 52, which are insulating elements 50 that use a magnetic field as a transmission medium, and each has coils formed at both ends of an insulating layer. Isolation transformers 51 and 52 are mounted on a first substrate SUB1 and a second substrate SUB2, respectively. Isolation transformers 51 and 52 are electrically connected, for example, by bonding wires. Specifically, isolation transformer 51 includes coils 511 to 514 and an insulating layer 515. Isolation transformer 52 includes coils 521 to 524 and an insulating layer 525.

[0032] One end of coil 511 is connected to the negative (-) output terminal of the transmission circuit 40. The other end of coil 511 and one end of coil 512 are each connected to the power supply terminal T4 (ground node of the first substrate SUB1). The other end of coil 512 is connected to the positive (+) output terminal of the transmission circuit 40. Coils 513 and 514 are connected in series. Coils 511 and 513 are magnetically coupled via the insulating layer 515. Coils 512 and 514 are magnetically coupled via the insulating layer 515. One end of coil 521 is connected to one end of the series-connected coils 513 and 514, for example via wire bonding. The other end of coil 521 is connected to one end of coil 522. The other end of coil 522 is connected to the other ends of the series-connected coils 513 and 514, for example via wire bonding. Coils 521 and 523 are magnetically coupled via the insulating layer 525. Coils 522 and 524 are magnetically coupled via an insulating layer 525. One end of coil 523 is connected to the positive-phase input terminal (+) of the amplification circuit 61. The other end of coil 523 and one end of coil 524 are each connected to the power supply terminal T6 (ground node of the second substrate SUB2). The other end of coil 524 is connected to the negative-phase input terminal (-) of the amplification circuit 61. In this way, isolation transformers 51 and 52 each constitute a tapped transformer. The insulating layers 515 and 525 are, for example, an oxide film or polyimide.

[0033] The receiving circuit 60 also includes an amplification circuit 61 and a full-wave rectifier circuit 62. The amplification circuit 61 amplifies the high-frequency differential signal (electrical signal) input from the insulating element 50. The amplification circuit 61 then outputs the amplified differential signal to the full-wave rectifier circuit 62. The full-wave rectifier circuit 62 full-wave rectifies the differential signal input from the amplification circuit 61. The full-wave rectifier circuit 62 then performs envelope detection on the full-wave rectified differential signal and outputs it to the output circuit 70. Each of the amplification circuit 61 and the full-wave rectifier circuit 62 includes, for example, a differential circuit. Details of the circuit configurations of the amplification circuit 61 and the full-wave rectifier circuit 62 will be described later. The amplification circuit 61 may also be called an "RF (Radio Frequency) differential amplifier (RF Amp.)".

[0034] In the communication device 1 described above, the input data (Din) pulse input to the input terminal T1 of the primary device (first board SUB1) is converted into an OOK modulated signal based on the carrier signal CS and transmitted to the secondary device (second board SUB2) via an insulating boundary (insulating element 50). The secondary device then reconstructs the data based on the OOK modulated signal and outputs an output data (Dout) pulse corresponding to the input data pulse.

[0035] Furthermore, when the isolation element 50 is composed of an isolation transformer, it is preferable to use a high-frequency carrier signal CS in order to suppress the size of the isolation transformer. For this reason, the oscillation circuit 20, modulation circuit 30, transmission circuit 40, and reception circuit 60 (amplification circuit 61 and full-wave rectification circuit 62) are composed of miniature MOS transistors so that they can handle high-frequency signals. On the other hand, the system power supply of the communication device 1 is required to operate at, for example, 2.25V to 5.5V. For this reason, the circuits composed of miniature MOS transistors are driven by a power supply voltage (for example, 1.5V) lower than the system power supply, which is generated by the LDO circuits of power supply circuits PW1 and PW2.

[0036] In the first embodiment, the example shown was that the isolation transformer is provided on both the first substrate SUB1 and the second substrate SUB2, but the invention is not limited to this. The isolation transformer may be mounted on either the first substrate SUB1 or the second substrate SUB2, or on both the first substrate SUB1 and the second substrate SUB2.

[0037] <1-1-2> Configuration of the modulation circuit 30 Figure 4 is a circuit diagram showing an example of the circuit configuration of the input modulation unit IMP included in the communication device 1 according to the first embodiment. Figure 4 shows the detailed circuit configuration of the modulation circuit 30. As shown in Figure 4, the modulation circuit 30 includes, for example, a buffer 301, an inverter 302, logical AND circuits 303, 304 and 305, inverters 306 and 307, and rising edge delay circuits RDC1 and RDC2.

[0038] The input circuit 10 outputs the input signal VIN to the oscillator circuit 20, the rising edge delay circuit RDC1, the rising edge delay circuit RDC2, the AND gate 305, and the inverter 306, respectively. The oscillator circuit 20 outputs the carrier signal CS, which it generates based on the input signal VIN, to the buffer 301 and the inverter 302, respectively.

[0039] Buffer 301 delays the carrier signal CS input from the oscillator circuit 20 to adjust the signal timing and outputs it to the AND circuit 303.

[0040] The inverter 302 inverts the logic of the carrier signal CS input from the oscillator circuit 20. Then, the inverter 302 outputs the inverted carrier signal CS to the AND circuit 304.

[0041] The rise time delay circuit RDC1 is a delay circuit that delays the rising edge of the input signal VIN input from the input circuit 10 and outputs it. Hereinafter, the delay time of the signal rising edge caused by the rise time delay circuit RDC1 will be referred to as "tdr1". The input signal VIN delayed by the rise time delay circuit RDC1 will be referred to as "input signal VINdr1". The rise time delay circuit RDC1 outputs the input signal VINdr1, based on the input signal VIN, to the AND circuits 303 and 304, respectively.

[0042] The rise-time delay circuit RDC2 is a delay circuit that delays the rising edge of the input signal VIN, which is input from the input circuit 10, and outputs it. Hereinafter, the delay time of the rising edge of the signal by the rise-time delay circuit RDC2 will be referred to as "tdr2". The input signal VIN that has been delayed by the rise-time delay circuit RDC2 will be referred to as "input signal VINdr2". The rise-time delay circuit RDC2 outputs the input signal VINdr2, which is based on the input signal VIN, to the inverter 307. The inverter 307 inverts the logic of the input signal VINdr2 that has been input from the rise-time delay circuit RDC2. Then, the inverter 307 outputs the input signal VINdr2 with the logic inverted to the AND circuit 305.

[0043] The AND circuit 303 performs a logical AND operation between the carrier signal CS input from the buffer 301 and the input signal VINdr1 input from the rising edge delay circuit RDC1. The AND circuit 303 then outputs the result of the operation as the positive-phase modulated signal VINP to the transmission circuit 40. In other words, the output of the AND circuit 303 is associated with the positive-phase signal of the OOK modulated signal.

[0044] The AND circuit 304 performs a logical AND operation between the inverted carrier signal CS input from the inverter 302 and the input signal VINdr1 input from the rising-edge delay circuit RDC1. The AND circuit 304 then outputs the result of the operation as the inverse-phase modulated signal VINN to the transmission circuit 40. In other words, the output of the AND circuit 304 corresponds to the inverse-phase signal of the OOK modulated signal.

[0045] The AND circuit 305 performs a logical AND operation between the input signal VIN input from the input circuit 10 and the inverted input signal VINdr2 input from the inverter 307. If tdr2 is longer than tdr1, the AND circuit 305 performs a logical AND operation on tdr 2 and A pulse is generated and output to the transmission circuit 40 as a boost signal VBST. The boost signal VBST is a control signal used to control the boost circuit BC included in the transmission circuit 40. Details of the boost circuit BC will be described later.

[0046] The inverter 306 inverts the logic of the input signal VIN received from the input circuit 10. The inverter 306 then outputs the inverted input signal VIN as a shunt signal VSHT to the transmission circuit 40. The shunt signal VSHT is a control signal used to control the shunt circuit SC included in the transmission circuit 40. Details of the shunt circuit SC will be described later.

[0047] In communication device 1, the positive-phase modulated signal VINP, the negative-phase modulated signal VINN, the boost signal VBST, and the shunt signal VSHT, all output from the modulation circuit 30, are synchronized. In other words, the OOK modulated signal, the boost signal VBST, and the shunt signal VSHT are synchronized.

[0048] <1-1-3> Configuration of the transmission circuit 40 Figure 5 is a circuit diagram showing an example of the circuit configuration of a transmission circuit 40 provided in the communication device 1 according to the first embodiment. As shown in Figure 5, the transmission circuit 40 includes, for example, PMOS transistors MP1 and MP2, NMOS transistors MN1 to MN5, resistors RP, RN, RLP_TX and RLN_TX, capacitors CP_TX, CN_TX and CC, input terminals T10 to T13, output terminals T14 and T15, and nodes N10 to N15.

[0049] Input terminal T10 is the positive-phase input terminal of the transmitting circuit 40. The modulated signal VINP output from the modulation circuit 30 is input to input terminal T10. Input terminal T10 is connected to the gate terminals of the PMOS transistor MP2 and the NMOS transistor MN2, respectively. Input terminal T11 is the negative-phase input terminal of the transmitting circuit 40. The modulated signal VINN output from the modulation circuit 30 is input to input terminal T11. Input terminal T11 is connected to the gate terminals of the PMOS transistor MP1 and the NMOS transistor MN1, respectively.

[0050] The source terminals of PMOS transistors MP1 and MP2 are connected to the power supply node of the first board SUB1. That is, VREF1 is applied to the source terminals of PMOS transistors MP1 and MP2 by the power supply circuit PW1. The drain terminals of PMOS transistors MP1 and MP2 are connected to nodes N10 and N11, respectively. The drain terminals of NMOS transistors MN1 and MN2 are connected to nodes N10 and N11, respectively. The source terminals of NMOS transistors MN1 and MN2 are connected to the ground node of the first board SUB1. In other words, PMOS transistors MP1 and NMOS transistors MN1 constitute an inverter circuit in which the modulated signal VINN is input to the input terminal and the output terminal is connected to node N10. PMOS transistors MP2 and NMOS transistors MN2 constitute an inverter circuit in which the modulated signal VINP is input to the input terminal and the output terminal is connected to node N11. The pair of PMOS transistors MP1 and MP2 and the pair of NMOS transistors MN1 and MN2 operate as a differential inverter circuit.

[0051] The NMOS transistor MN3 and resistor RP are connected in parallel between nodes N10 and N12. The NMOS transistor MN4 and resistor RN are connected in parallel between nodes N11 and N13. The gate terminals of NMOS transistors MN3 and MN4 are connected to input terminal T12. A boost signal VBST is input to input terminal T12. The pair of NMOS transistors MN3 and MN4 corresponds to a boost circuit BC controlled by the boost signal VBST.

[0052] Capacitor CP_TX is connected between nodes N12 and N14. Specifically, one electrode of capacitor CP_TX is connected to node N12, and the other electrode is connected to node N14. Capacitor CN_TX is connected between nodes N13 and N15. Specifically, one electrode of capacitor CN_TX is connected to node N13, and the other electrode is connected to node N15.

[0053] The drain and source terminals of the NMOS transistor MN5 are connected to nodes N14 and N15, respectively. The gate terminal of the NMOS transistor MN5 is connected to input terminal T13. The shunt signal VSHT is input to input terminal T13. The NMOS transistor MN5 corresponds to the shunt circuit SC, which is controlled by the shunt signal VSHT.

[0054] Resistor RLP_TX is connected between node N14 and the ground node of the first board SUB1. Resistor RLN_TX is connected between node N15 and the ground node of the first board SUB1. Capacitor CC is connected between nodes N14 and N15.

[0055] Output terminal T14 is connected to node N14. The signal output from output terminal T14 corresponds to the positive-sequence differential signal VOP_TX output from the transmitting circuit 40. Output terminal T15 is connected to node N15. The signal output from output terminal T15 corresponds to the negative-sequence differential signal VON_TX output from the transmitting circuit 40. The differential signals VOP_TX and VON_TX are input to the isolation element 50 (isolation transformer 51).

[0056] The transmitting circuit 40 described above operates with differential inverter circuits (MP1, MN1, MP2, and MN2) and can supply differential current to the isolation element 50 (isolation transformer 51). On the other hand, if a common-mode current flows from the primary-side equipment to the secondary-side equipment, radiated EMI (Electromagnetic Interference) may worsen. Therefore, in the communication device 1, a parallel resonant circuit is formed by the resonant capacitance (CC) and the inductance of the isolation transformer 51. As a result, the transmitting circuit 40 can suppress the transmission of signals other than those based on the carrier signal CS to the secondary-side equipment, thereby improving EMI performance.

[0057] Furthermore, it is preferable that the communication device 1 has resistance to CMTI (Common Mode Transient Immunity), in which the ground level of the primary side and the ground level of the secondary side change abruptly. In contrast, in the transmitting circuit 40, the load resistors (RLP_TX and RLN_TX) are connected between a resonant circuit composed of capacitor CC and nodes N14 and N15 and the ground level of the first substrate SUB1 (the grounding node of the first substrate SUB1). Also, capacitors CP_TX and CN_TX are connected between the differential inverter circuits (MP1, MN1, MP2 and MN2) and the isolation transformer 51.

[0058] In this example, since a tapped transformer is used as the isolation element 50, most of the CMTI noise flows from the isolation transformer 51 to the ground node of the first substrate SUB1. However, some of the CMTI noise may be applied to the transmitting circuit 40. On the other hand, the CMTI noise is biased towards frequencies below 10 MHz. Therefore, the CMTI noise reaching the transmitting circuit 40 can be suppressed by the capacitance (CP_TX and CN_TX) and the impedance difference of the load resistors (RLP_TX and RLN_TX).

[0059] Furthermore, in a resonant circuit, immediate response is difficult because it requires time to charge the capacitance CC when the transmission of the carrier signal CS starts from no signal. In contrast, the boost circuit BC turns on NMOS transistors MN3 and MN4 based on the boost signal VBST when the transmission of the carrier signal CS starts from no signal. As a result, the resistance values ​​between nodes N10 and N12 and between nodes N11 and N13 decrease, and the amount of current supplied to capacitance CC increases. This shortens the charging time of capacitance CC when the transmission of the carrier signal CS starts from no signal, allowing the resonant circuit to operate quickly.

[0060] On the other hand, when the transmission of the carrier signal CS ends and there is no signal, it is preferable that the capacitance CC of the resonant circuit discharges quickly. In contrast, the shunt circuit SC turns on the NMOS transistor MN5 based on the shunt signal VSHT when the transmission of the carrier signal CS stops. Then, nodes N14 and N15 are electrically connected via the NMOS transistor MN5, and one electrode and the other electrode of the capacitance CC become at the same potential. As a result, the discharge time of the capacitance CC when the transmission of the carrier signal CS ends and there is no signal is shortened, and the resonant circuit can operate quickly.

[0061] <1-1-4> Configuration of the Amplifier Circuit 61 Figure 6 is a circuit diagram showing an example of the circuit configuration of an amplifier circuit 61 provided in the communication device 1 according to the first embodiment. As shown in Figure 6, the amplifier circuit 61 includes, for example, resistors RLP_RX and RLN_RX, diodes 611 to 614, capacitors CP_RX and CN_RX, a bias circuit 615, a constant current source 616, resistors RA1, RA2, RB1 and RB2, NMOS transistors MN6 and NM7, input terminals T20 and T21, output terminals T22 to T25, and nodes N20 to N28.

[0062] Input terminal T20 is the positive-sequence input terminal (+) of the amplification circuit 61. The differential signal VOP_TX transmitted from the transmitting circuit 40 via the isolation element 50 is input to input terminal T20. Input terminal T21 is the negative-sequence input terminal (-) of the amplification circuit 61. The differential signal VON_TX transmitted from the transmitting circuit 40 via the isolation element 50 is input to input terminal T21. Hereafter, the potential difference between input terminals T20 and T21, i.e., the differential output voltage of the isolation transformer 52, will be referred to as "VIN_RX". Input terminals T20 and T21 are connected to nodes N20 and N21, respectively.

[0063] Resistors RLP_RX and RLN_RX are load resistors connected between the receiving circuit 60 and the ground node (ground potential) of the second board SUB2. Resistor RLP_RX is connected between node N20 and the ground node of the second board SUB2. Resistor RLN_RX is connected between node N21 and the ground node of the second board SUB2.

[0064] The anode of diode 611 and the cathode of diode 612 are each connected to node N20. The cannode of diode 611 and the anode of diode 612 are each connected to the ground node of the second board SUB2. The pair of diodes 611 and 612 adjusts the voltage at node N20 to stay within a certain range. The anode of diode 613 and the cathode of diode 614 are each connected to node N21. The cannode of diode 613 and the anode of diode 614 are each connected to the ground node of the second board SUB2. The pair of diodes 613 and 614 adjusts the voltage at node N21 to stay within a certain range.

[0065] Capacitor CP_RX is connected between nodes N20 and N22. Specifically, one electrode of capacitor CP_RX is connected to node N20, and the other electrode is connected to node N22. Capacitor CN_RX is connected between nodes N21 and N23. Specifically, one electrode of capacitor CN_RX is connected to node N21, and the other electrode is connected to node N23.

[0066] The bias circuit 615 applies a bias voltage to nodes N22 and N23, respectively. As a result, the voltage at node N22 changes based on the bias voltage and the voltage at the other electrode of capacitor CP_RX (the output voltage on the positive-sequence side of the insulating element 50). The voltage at node N23 changes based on the bias voltage and the voltage at the other electrode of capacitor CN_RX (the output voltage on the negative-sequence side of the insulating element 50). The bias voltage is, for example, VREF2 / 2.

[0067] Resistor RA1 is connected between the power node of the second board SUB2 and node N24. Resistor RA2 is connected between the power node of the second board SUB2 and node N25. That is, VREF2 is applied to one end of each resistor RA1 and RA2 by the power supply circuit PW2. The resistance value of resistor RA1 is designed to be approximately equal to the resistance value of resistor RA2. Resistor RB1 is connected between nodes N24 and N26. Resistor RB2 is connected between nodes N25 and N27. The resistance value of resistor RB1 is designed to be approximately equal to the resistance value of resistor RB2. The gate terminals of NMOS transistors MN6 and MN7 are connected to nodes N22 and N23, respectively. The drain terminals of NMOS transistors MN6 and MN7 are connected to nodes N26 and N27, respectively. The source terminals of NMOS transistors MN6 and MN7 are connected to node N28. The constant current source 616 is connected between node N28 and the ground node of the second substrate SUB2. The constant current source 616 adjusts the amount of current flowing from node N28 to the ground node of the second substrate SUB2 to IBIAS1. The bias current IBIAS1 corresponds to the sum of the drain current IMN6 of the NMOS transistor MN6 and the drain current IMN7 of the NMOS transistor MN7. As a result, the set of NMOS transistors MN6 and MN7 and the constant current source 616 constitutes a differential circuit (differential amplifier circuit).

[0068] Output terminal T22 is connected to node N25. Output terminal T23 is connected to node N24. Output terminal T24 is connected to node N27. Output terminal T25 is connected to node N26. The pair of output terminals T23 and T24 corresponds to the output terminal that outputs the differential voltage on the positive-sequence side of the amplifier circuit 61. The pair of output terminals T22 and T25 corresponds to the output terminal that outputs the differential voltage on the negative-sequence side of the amplifier circuit 61. Hereafter, the potential difference between output terminals T23 and T24 will be called "VOP_RX". The potential difference between output terminals T22 and T25 will be called "VON_RX".

[0069] As explained above, the isolation element 50 and the differential circuit included in the amplification circuit 61 are connected by capacitance (CP_RX and CN_RX). In this example, since a tapped transformer is used as the isolation element 50 (isolation transformer 52), most of the CMTI noise flows from the isolation transformer 52 to the ground node of the second substrate SUB2. However, some of the CMTI noise may be applied to the amplification circuit 61. On the other hand, the CMTI noise is biased towards frequencies below 10 MHz. Therefore, the CMTI noise reaching the differential circuit can be suppressed by the capacitance (CP_RX and CN_RX) and the impedance difference of the load resistors (RLP_RX and RLN_RX).

[0070] Furthermore, the output voltage (VIN_RX) from the isolation transformer 52 is amplified by a differential circuit having NMOS transistors MN6 and MN7. In the amplification circuit 61, the size and electrical characteristics of NMOS transistors MN6 and MN7 are designed to be approximately identical. That is, the amplification circuit 61 amplifies the signal from the isolation transformer 52 using a symmetrical differential circuit. Therefore, the amplitude of CMTI noise relative to the amplitude of the signal from the isolation transformer 52 is suppressed by the CMRR (Common Mode Rejection Ratio) of the differential circuit. In other words, the differential circuit of the amplification circuit 61 can improve CMTI immunity.

[0071] Furthermore, in the OOK modulation scheme, differential transmission is desirable when considering the effects of external noise. However, if the circuit is symmetrical, there is a risk of malfunction due to circuit noise when there is no signal. For this reason, the amplifier circuit 61 has a configuration that receives a signal based on the carrier signal CS from the primary side equipment using a large offset voltage Voffset against circuit noise. Specifically, the amplifier circuit 61 applies the offset voltage Voffset to VOP_RX and VON_RX through the load resistors of the differential circuit (RA1, RA2, RB1 and RB2) and the bias current IBIAS1 from the constant current source 616.

[0072] In the amplification circuit 61, VOP_RX is expressed by the following equation (1).

[0073]

number

[0074] In the amplification circuit 61, VON_RX is expressed by the following equation (2).

[0075]

number

[0076] In equations (1) and (2), "RA" represents the resistance values ​​of resistors RA1 and RA2. In equations (1) and (2), "RB" represents the resistance values ​​of resistors RB1 and RB2. In equations (1) and (2), "gm" represents the transconductance of NMOS transistors MN6 and MN7. From equations (1) and (2), it can be seen that an offset voltage of IBIAS1 × (RB / 2) is applied to VOP_RX and VON_RX.

[0077] <1-1-5> Configuration of the full-wave rectifier circuit 62 Figure 7 is a circuit diagram showing an example of the circuit configuration of a full-wave rectifier circuit 62 provided in the communication device 1 according to the first embodiment. As shown in Figure 7, the full-wave rectifier circuit 62 includes, for example, NMOS transistors MN8 to MN13, PMOS transistors MP3 to MP6, constant current sources 621 and 622, capacitors CL, input terminals T30 to T33, output terminal T34, and nodes N30 to N35.

[0078] Input terminal T30 is connected to output terminal T22. Input terminal T31 is connected to output terminal T23. Input terminal T32 is connected to output terminal T24. Input terminal T33 is connected to output terminal T25. The pair of input terminals T31 and T32 corresponds to the input terminal of the positive-sequence differential voltage input to the full-wave rectifier circuit 62. The pair of input terminals T30 and T33 corresponds to the input terminal of the negative-sequence differential voltage input to the full-wave rectifier circuit 62. That is, the potential difference between input terminals T31 and T32 is VOP_RX. The potential difference between input terminals T30 and T33 is VON_RX.

[0079] The gate terminals of NMOS transistors MN8 and MN9 are connected to input terminals T32 and T31, respectively. The drain terminals of NMOS transistors MN8 and MN9 are connected to nodes N33 and N32, respectively. The source terminals of NMOS transistors MN8 and MN9 are connected to node N30. A constant current source 621 is connected between node N30 and the ground node of the second substrate SUB2. The constant current source 621 adjusts the amount of current flowing from node N30 to the ground node of the second substrate SUB2 to IBIAS2. The bias current IBIAS2 corresponds to the sum of the drain current IMN8 of NMOS transistor MN8 and the drain current IMN9 of NMOS transistor MN9. Thus, the combination of NMOS transistors MN8 and MN9 and the constant current source 621 constitutes a differential amplifier circuit.

[0080] The gate terminals of NMOS transistors MN10 and MN11 are connected to input terminals T30 and T33, respectively. The drain terminals of NMOS transistors MN10 and MN11 are connected to nodes N32 and N33, respectively. The source terminals of NMOS transistors MN10 and MN11 are connected to node N31. A constant current source 622 is connected between node N31 and the ground node of the second substrate SUB2. The constant current source 622 adjusts the amount of current flowing from node N31 to the ground node of the second substrate SUB2 to IBIAS3. The bias current IBIAS3 corresponds to the sum of the drain current IMN10 of NMOS transistor MN10 and the drain current IMN11 of NMOS transistor MN11. Thus, the combination of NMOS transistors MN10 and MN11 and the constant current source 622 constitutes a differential amplifier circuit.

[0081] The source terminals of PMOS transistors MP3, MP4, MP5, and MP6 are connected to the power supply nodes of the second board SUB2. That is, VREF2 is applied to the source terminals of PMOS transistors MP3, MP4, MP5, and MP6 by the power supply circuit PW2. The gate and drain terminals of PMOS transistor MP3 are connected to node N32. The gate and drain terminals of PMOS transistor MP4 are connected to node N33. The gate terminal of PMOS transistor MP5 is connected to node N32. The drain terminal of PMOS transistor MP5 is connected to node N34. The gate terminal of PMOS transistor MP6 is connected to node N33. The drain terminal of PMOS transistor MP6 is connected to node N35. In this way, each pair of PMOS transistors MP3 and MP5, and each pair of PMOS transistors MP4 and MP6, constitute a current mirror circuit. Therefore, the drain current IMP3 of PMOS transistor MP3 is mirrored to PMOS transistor MP5. Similarly, the drain current IMP4 of PMOS transistor MP4 is mirrored in PMOS transistor MP6.

[0082] The gate and drain terminals of NMOS transistor MN12 are connected to node N34. The source terminal of NMOS transistor MN12 is connected to the ground node of the second substrate SUB2. The gate terminal of NMOS transistor MN13 is connected to node N34. The drain terminal of NMOS transistor MN13 is connected to node N35. The source terminal of NMOS transistor MN13 is connected to the ground node of the second substrate SUB2. In this way, the pair of NMOS transistors MN12 and MN13 constitute a current mirror circuit. Therefore, the drain current of NMOS transistor MN12 is mirrored in NMOS transistor MN13.

[0083] Capacitor CL is connected between node N35 and the ground node of the second board SUB2. Capacitor CL represents the load capacitance of the full-wave rectifier circuit 62. Capacitor CL can also be considered as the input capacitance of the output circuit 70. Output terminal T34 is connected to node N35. Output terminal T34 corresponds to the output terminal that outputs the output signal VO of the full-wave rectifier circuit 62, i.e., the OOK modulated signal demodulated by the receiving circuit 60 (a combination of the amplifier circuit 61 and the full-wave rectifier circuit 62).

[0084] As described above, the full-wave rectifier circuit 62 performs envelope detection by full-wave rectifying VOP_RX and VON_RX using a differential circuit. In the full-wave rectifier circuit 62, the NMOS transistors MN8, MN9, MN10, and MN11 are designed to have approximately the same size and electrical characteristics. The bias currents IBIAS2 and IBIAS3 are also designed to be approximately the same.

[0085] The current flowing through node N33 corresponds to the sum of the drain currents IMN8 of NMOS transistor MN8 and IMN11 of NMOS transistor MN11. This current flowing through node N33 is then mirrored by PMOS transistors MP4 and MP6 to become the charging current ICharge that charges the capacitor CL. The current mirroring ratio of PMOS transistors MP4 and MP6 is, for example, 1:1.

[0086] The current flowing through node N32 corresponds to the sum of the drain currents IMN9 of NMOS transistor MN9 and IMN10 of NMOS transistor MN10. This current is then mirrored by PMOS transistors MP3 and MP5 and input to node N34. Furthermore, the current input to node N34 is mirrored by NMOS transistors MN12 and MN13, becoming the discharge current IDischarge that discharges capacitance CL. When the current mirror ratio of PMOS transistors MP3 and MP5 is 1:1, the current mirror ratio of NMOS transistors MN12 and MN13 is designed to be, for example, 2:1. Alternatively, the current mirror ratio of PMOS transistors MP3 and MP5 may be 2:1. In this case, the current mirror ratio of NMOS transistors MN12 and MN13 is designed to be 1:1. In the full-wave rectifier circuit 62, it is sufficient that the IDischarge is designed to be smaller than the sum of the drain currents IMN9 of the NMOS transistor MN9 and IMN10 of the NMOS transistor MN10.

[0087] The voltage value of the output signal VO of the full-wave rectifier circuit 62 is expressed by the following equation (3).

[0088]

number

[0089] As shown in equation (3), the voltage value of the output signal VO of the full-wave rectifier circuit 62 is proportional to the amount of charge stored in the capacitor CL.

[0090] <1-2> Operation An example of the operation of the communication device 1 according to the first embodiment will be described below.

[0091] <1-2-1> Example of operation of receiving circuit 60 The operation example of the differential circuit included in the receiving circuit 60 will be described below with reference to Figure 8. Figure 8 is a timing chart showing a first operation example of the receiving circuit 60 provided in the communication device 1 according to the first embodiment. Figure 8(A) shows the differential output voltage (VIN_RX) of the isolation transformer 52. Figure 8(B) shows the output voltages (VOP_RX and VON_RX) of the amplification circuit 61. Figure 8(C) shows the drain currents IMN8 and IMN9 of the NMOS transistors MN8 and MN9, respectively. Figure 8(D) shows the drain currents IMN8 and IMN9 of the NMOS transistors MN10 and MN11, respectively. Figure 8(E) shows the drain current IMP3 of the PMOS transistor MP3. Figure 8(F) shows the drain current IMP4 of the PMOS transistor MP4. Figure 8(t1) shows the timing when the input signal VIN changes from "L" level to "H" level. Figure 8(t2) shows the timing when the input signal VIN changes from "H" level to "L" level.

[0092] VIN_RX is near 0V when there is no signal (VIN=0V). On the other hand, VIN_RX is a high-frequency signal during the time intervals t1 and t2, which correspond to the period when the input signal VIN pulse is being received. This high-frequency signal is generated based on the carrier signal CS.

[0093] The amplifier circuit 61 amplifies the differential input voltage, so VOP_RX and VON_RX operate in reverse phase. However, when there is no signal, an offset voltage Voffset is added to both VON_RX and VON_RX.

[0094] In the no-signal state (VIN=0V), VOP_RX=VON_RX=VOffset>0V. Therefore, IMN9 is larger than IMN8, and IMN10 is larger than IMN11. As a result, IMP3, which is the sum of IMN9 and IMN10, is large, and IMP4, which is the sum of IMN8 and IMN11, is small.

[0095] When VIN > 0V, VOP_RX decreases and VON_RX increases. Therefore, IMN8 increases and IMN9 decreases, and IMN10 increases and IMN11 decreases. However, since IMN9 and IMN10 are large when there is no signal, the decrease in IMN9 is large, but the increase in IMN10 is small. As a result, IMP3 decreases. On the other hand, since IMN8 and IMN11 are small when there is no signal, the increase in IMN8 is large, but the decrease in IMN11 is small. As a result, IMP4 increases.

[0096] When VIN < 0V, VOP_RX increases and VON_RX decreases. Therefore, IMN8 decreases and IMN9 increases, and IMN10 decreases and IMN11 increases. However, since IMN9 and IMN10 are large when there is no signal, the increase in IMN9 is small, but the decrease in IMN10 is large. As a result, IMP3 increases. On the other hand, since IMN8 and IMN11 are small when there is no signal, the decrease in IMN8 is small, but the increase in IMN11 is large. As a result, IMP4 decreases.

[0097] As described above, the receiving circuit 60 operates based on the input signal VIN, thereby obtaining IMP3 and IMP4, which are full-wave rectified currents, from the input voltage (VIN_RX).

[0098] The relationship between the drain current IMP4 of the PMOS transistor MP4, which is a full-wave rectified current, and the output signal VO will be explained below with reference to Figure 9. Figure 9 is a timing chart showing a second example of operation of the receiving circuit 60 provided in the communication device 1 according to the first embodiment. Figure 9(A) shows the output voltage (VIN_RX) of the isolation transformer 52, similar to Figure 8(A). Figure 9(B) shows the drain currents IMP4 and IMN12 of the PMOS transistor MP4 and the NMOS transistor MN12, respectively. Figures 9(C) and (D) show the charging current ICharge and the discharging current IDischarge, respectively. Figure 9(E) shows the output signal VO. t1 in Figure 9 shows the timing when the input signal VIN changes from "L" level to "H" level. t2 in Figure 9 shows the timing when the input signal VIN changes from "H" level to "L" level.

[0099] PMOS transistors MP4 and MP6 constitute a current mirror circuit. The current mirror ratio of PMOS transistors MP4 and MP6 is, for example, 1:1. Therefore, the drain current IMP4 of PMOS transistor MP4 becomes the charging current ICharge that charges the capacitor CL.

[0100] On the other hand, the drain current IMP3 of PMOS transistor MP3 is mirrored by PMOS transistor MP5 and folded back by a current mirror circuit composed of NMOS transistors MN12 and MN13. For example, the current mirror ratio of PMOS transistors MP4 and MP6 is 2:1, and the current mirror ratio of NMOS transistors MN12 and MN13 is 1:1. In this case, the discharge current IDischarge, which discharges the capacitance CL, is half the current IMP3.

[0101] If IMN12 is set to be greater than IMP4 when there is no signal, then IDischarge > ICharge, and no charge is accumulated in the capacitance CL. In this case, the output signal VO will be 0V.

[0102] On the other hand, when an OOK modulated signal is input (time t1), IMP4 increases and IMN12 decreases in the receiving circuit 60. That is, ICharge > IDischarge, charge accumulates in the capacitor CL, and the voltage of the output signal VO rises. When the voltage of the output signal VO rises and stabilizes, ICharge ≈ IDischarge.

[0103] Then, when the OOK modulated signal disappears (time t2), ICharge becomes approximately zero and is discharged by IDischarge. At this time, IDischarge is a constant value. On the other hand, during charging, it is charged with a full-wave rectified current. Therefore, the rise time of the output signal VO voltage is slower than the fall time of the output signal VO voltage.

[0104] In the following, the response time from when the OOK modulated signal is input from no signal to when the OOK modulated signal is reflected in the output signal VO of the communication device 1 in the secondary equipment (receiving circuit 60 and output circuit 70) is called "tON_RX". The response time from when the OOK modulated signal becomes no signal to when the no signal is reflected in the output signal VO of the communication device 1 in the secondary equipment of the communication device 1 is called "tOFF_RX". The response time from when the input signal VIN changes from a "L" level to a "H" level to when the primary equipment of the communication device 1 (input circuit 10, modulation circuit 30, and transmission circuit 40, etc.) outputs the OOK modulated signal is called "tON_IO". The response time from when the input signal VIN changes from a "H" level to a "L" level to when the primary equipment of the communication device 1 stops outputting the OOK modulated signal is called "tOFF_IO".

[0105] <1-2-2> Example of operation of modulation circuit 30 The operation example of the modulation circuit 30 will be described below with reference to Figure 10. Figure 10 is a timing chart showing an operation example of the modulation circuit 30 provided in the communication device 1 according to the first embodiment. Figure 10(A) shows the input signal VIN. Figure 10(B) shows the output signal (carrier signal CS) of the oscillation circuit 20. Figure 10(C) shows the modulated signal VINP on the positive phase side of the modulation circuit 30. Figure 10(D) shows the modulated signal VINN on the negative phase side of the modulation circuit 30. Figures 10(E) and (F) show the boost signal VBST and the shunt signal VSHT, respectively. Figure 10 t1 shows the timing when the input signal VIN changes from "L" level to "H" level. Figure 10 t2 shows the timing when the input signal VIN changes from "H" level to "L" level. Note that Figure 10 illustrates the case where a high-frequency carrier signal CS is output based on the input signal VIN of another channel. In other words, we will now describe the case where the input signal VIN to the modulation circuit 30 operates asynchronously with the carrier signal CS.

[0106] When the input signal VIN is at a "L" level, both the modulated signal VINP on the positive phase side and the modulated signal VINN on the negative phase side of the modulation circuit 30 are at a "L" level. In this case, the boost signal VBST is at a "L" level, and the shunt signal VSHT is at a "H" level.

[0107] When the input signal VIN changes from a "L" level to a "H" level, the boost signal VBST becomes "H" level and the shunt signal VSHT becomes "L" level. When the shunt signal VSHT becomes "L" level, the capacitor CC becomes ready for charging. When the boost signal VBST becomes "H" level, the charging speed of the capacitor CC for supplying the differential signal to the isolation element 50 increases compared to when the NMOS transistors MN3 and MN4 are off (when the boost signal VBST is "L" level).

[0108] Furthermore, input signals VINdr1 and VINdr2 are delayed by tdr1 and tdr2 respectively, changing from a "L" level to a "H" level. Based on the fact that input signal VINdr1 has reached a "H" level, the modulation circuit 30 outputs high-frequency signals (VINP and VINN) based on the carrier signal CS. This causes the transmission circuit 40 to start outputting the OOK modulated signal. The boost circuit BC increases the charging speed of the capacitor CC during the period (boost period) when the boost signal VBST is at a "H" level and VINP and VINN based on the carrier signal CS are being output. Then, based on the fact that input signal VINdr2 has reached a "H" level, the boost signal VBST returns to a "L" level. In other words, the increase in the charging speed of the capacitor CC by the boost circuit BC stops.

[0109] When the input signal VIN changes from a high level to a low level, the shunt signal VSHT also changes to a high level. Based on the fact that the input signal VIN has changed to a low level, the modulation circuit 30 stops outputting the high-frequency signals (VINP and VINN) based on the carrier signal CS. As a result, the output of the OOK modulated signal by the transmitting circuit 40 stops, resulting in a no-signal state. In addition, when the shunt signal VSHT changes to a high level, the charge accumulated in the capacitor CC is discharged by the shunt circuit SC.

[0110] In the first embodiment, the length of the boost period is "tdr2-tdr1". That is, in the first embodiment, the delay time tdr2 of the rise delay circuit RDC2 is longer than the delay time tdr of the rise delay circuit RDC1. The shunt signal VSHT should be at an "L" level when there is a carrier (high-frequency signal) in the OOK modulated signal. For this reason, the shunt signal VSHT is set to the inverse logic of the input signal VIN.

[0111] <1-3> Effects of the First Embodiment According to the communication device 1 of the first embodiment described above, signals can be transmitted at high speed and with high quality between primary-side equipment and secondary-side equipment. The effects of the first embodiment will be described in detail below.

[0112] Generally, when an OOK modulated signal is received by a comparator and output through an output buffer, tON_RX is longer than tOFF_RX. When "tON_RX + tON_IO" is greater than "tOFF_RX + tOFF_IO", the pulse width of the output signal VO of communication device 1 is narrower than the pulse width of the input signal VIN to communication device 1. On the other hand, when "tON_RX + tON_IO" is less than "tOFF_RX + tOFF_IO", the pulse width of the output signal VO of communication device 1 is wider than the pulse width of the input signal VIN to communication device 1. In other words, when "tON_RX + tON_IO" and "tOFF_RX + tOFF_IO" are different, the pulse width of the output signal VO changes with respect to the pulse width of the input signal VIN. In this case, the upper limit of the signal transmission speed of the digital isolator may be limited by the change in the pulse widths of the input and output signals. Therefore, there is a need for a digital isolator in which the pulse width of the input signal and the pulse width of the output signal are approximately the same, enabling high-speed and high-quality signal transmission.

[0113] Therefore, the communication device 1 according to the first embodiment includes a modulation circuit 30 suitable for a digital isolator such that "tON_RX+tON_IO" is greater than "tOFF_RX+tOFF_IO" (the pulse width is narrowed by signal transmission). Specifically, the modulation circuit 30 includes a delay circuit (rising edge delay circuit RDC1) that delays the timing at which the modulated signals on the positive and negative phase sides of the OOK modulation signal become signals based on the carrier signal CS when the input signal VIN changes from a "L" level to a "H" level. On the other hand, the rising edge delay circuit RDC1 immediately cuts off the output of the signal based on the carrier signal CS when the input signal VIN changes from a "H" level to a "L" level.

[0114] As a result, in the communication device 1 according to the first embodiment, the response time from when the input signal VIN changes from a "L" level to a "H" level until the modulation circuit 30 outputs a signal based on the carrier signal CS becomes longer than the response time from when the input signal VIN changes from a "H" level to a "L" level until the modulation circuit 30 stops outputting a signal based on the carrier signal CS. This difference in response time can be adjusted by the delay time tdr1 of the rise time delay circuit RDC1.

[0115] As a result, in the communication device 1 according to the first embodiment, the pulse width of the input signal VIN and the pulse width of the output signal VO can be adjusted to be approximately the same. Therefore, the communication device 1 according to the first embodiment can eliminate the limitation on the upper limit of the signal transmission speed due to changes in the pulse width of the input signal and the output signal, and can realize high-speed and high-quality signal transmission.

[0116] In the communication device 1 according to the first embodiment, the size and electrical characteristics of the pair of MOS transistors used as inputs to the differential circuit included in the receiving circuit 60 are designed to be substantially identical; that is, the two transistors used in the differential circuit are arranged symmetrically. Therefore, the receiving circuit 60 can have improved CMTI immunity. Furthermore, since the size and electrical characteristics of the pair of MOS transistors are designed to be substantially identical, significant changes in the characteristics of the pair of MOS transistors in the differential circuit due to process causes are suppressed, and a stable receiving circuit 60 can be realized.

[0117] Furthermore, the communication device 1 according to the first embodiment is configured with multiple channels and allows the input signal VIN and the carrier signal CS to operate asynchronously. In addition, the communication device 1 according to the first embodiment shares one oscillator circuit 20 among multiple channels. As a result, the communication device 1 according to the first embodiment can reduce power consumption and manufacturing costs compared to the case where multiple oscillator circuits 20 are provided.

[0118] <2> Second Embodiment The communication device 1A according to the second embodiment has a configuration in which the circuit configuration of the input modulation unit IMP has been changed from that of the communication device 1 according to the first embodiment. Furthermore, the primary side equipment in the communication device 1A has a function to make the period for outputting an OOK modulated signal based on the pulse of the input signal longer than the pulse width of the input signal. The details of the second embodiment and the differences from the first embodiment will be described below.

[0119] <2-1> Composition Figure 11 is a circuit diagram showing an example of the circuit configuration of the input modulation unit IMP included in the communication device 1A according to the second embodiment. As shown in Figure 11, the communication device 1A includes a modulation circuit 30A instead of the modulation circuit 30. The modulation circuit 30A has a configuration in which the rising edge delay circuit RDC1 is replaced with a falling edge delay circuit FDC1 in the modulation circuit 30 of the first embodiment.

[0120] In the second embodiment, the input circuit 10 outputs the input signal VIN to the falling-fall delay circuit FDC1, the rising-fall delay circuit RDC2, and the AND circuit 305, respectively.

[0121] The falling-fall delay circuit FDC1 is a delay circuit that delays the falling edge of the input signal VIN input from the input circuit 10 and outputs it. Hereinafter, the delay time of the falling edge of the signal by the falling-fall delay circuit FDC1 will be referred to as "tdf1". The input signal VIN delayed by the falling-fall delay circuit FDC1 will be referred to as "input signal VINdf1". The falling-fall delay circuit FDC1 outputs the input signal VINdf1, based on the input signal VIN, to the oscillator circuit 20, the AND circuit 303, the AND circuit 304, and the inverter 306, respectively. In the second embodiment, the oscillator circuit 20 outputs the carrier signal CS, generated based on the input signal VINdf1 input from the falling-fall delay circuit FDC1, to the buffer 301 and the inverter 302, respectively.

[0122] In the second embodiment, the AND circuit 303 performs a logical AND operation between the carrier signal CS input from the buffer 301 and the input signal VINdf1 input from the falling-fall delay circuit FDC1. The AND circuit 303 then outputs the result of the operation as the modulated signal VINP on the positive phase to the transmission circuit 40.

[0123] In the second embodiment, the AND circuit 304 performs a logical AND operation between the inverted carrier signal CS input from the inverter 302 and the input signal VINdf1 input from the falling-fall delay circuit FDC1. The AND circuit 304 then outputs the result of the operation as the modulated signal VINN on the inverse side to the transmission circuit 40.

[0124] In the second embodiment, the inverter 306 inverts the logic of the input signal VINdf1 received from the falling-fall delay circuit FDC1. The inverter 306 then outputs the inverted input signal VINdf1 as a shunt signal VSHT to the transmission circuit 40.

[0125] The other configurations of the communication device 1A according to the second embodiment are the same as those of the communication device 1 according to the first embodiment.

[0126] <2-2> Operation The operation example of the modulation circuit 30A will be described below with reference to Figure 12. Figure 12 is a timing chart showing an operation example of the modulation circuit 30A provided in the communication device 1A according to the second embodiment. (A) to (F) in Figure 12 represent the input signal VIN, the carrier signal CS, the modulated signal on the positive phase side VINP, the modulated signal on the negative phase side VINN, the boost signal VBST, and the shunt signal VSHT, respectively. t1 in Figure 12 indicates the timing when the input signal VIN changes from the "L" level to the "H" level. t2 in Figure 12 indicates the timing when the input signal VIN changes from the "H" level to the "L" level. Note that Figure 12 illustrates the case where a high-frequency carrier signal CS is output based on the input signal VIN of another channel. That is, the case where the input signal VIN to the modulation circuit 30A operates asynchronously with the carrier signal CS will be described.

[0127] When the input signal VIN is at a "L" level, both the modulated signal VINP on the positive phase side and the modulated signal VINN on the negative phase side of the modulation circuit 30A are at a "L" level.

[0128] When the input signal VIN changes from a "L" level to a "H" level, the boost signal VBST becomes "H" level and the shunt signal VSHT becomes "L" level. Based on the fact that the input signal VIN has become "H" level, the modulation circuit 30A outputs high-frequency signals (VINP and VINN) based on the carrier signal CS.

[0129] Additionally, the input signal VINdr2 becomes high ("H") after a delay of tdr2. The boost signal VBST becomes low ("L") based on the input signal VINdr2 becoming high ("H").

[0130] When the input signal VIN changes from a high level to a low level, the input signal VINdf1 also changes to a low level with a delay of tdf1. Based on the fact that the input signal VINdf1 has changed to a low level, the modulation circuit 30A stops outputting the high-frequency signals (VINP and VINN) based on the carrier signal CS. Also, the shunt signal VSHT changes to a high level based on the fact that the input signal VINdf1 has changed to a low level.

[0131] In the second embodiment, the length of the boost period is "tdr2". That is, in the second embodiment, the boost period is determined by the delay time of the rise delay circuit RDC2.

[0132] Other operations of the communication device 1A according to the second embodiment are the same as those of the communication device 1 according to the first embodiment.

[0133] <2-3> Effects of the second embodiment The communication device 1A according to the second embodiment includes a modulation circuit 30A suitable for a digital isolator such that "tON_RX+tON_IO" is smaller than "tOFF_RX+tOFF_IO" (i.e., the pulse width widens due to signal transmission). Specifically, the modulation circuit 30A includes a delay circuit (falling edge delay circuit FDC1) that delays the timing at which the modulated signals on the positive and negative phases of the OOK modulated signal stop outputting signals based on the carrier signal CS when the input signal VIN changes from a "H" level to a "L" level. On the other hand, the falling edge delay circuit FDC1 immediately outputs the modulated signals on the positive and negative phases based on the carrier signal CS when the input signal VIN changes from a "L" level to a "H" level.

[0134] As a result, in the communication device 1A according to the second embodiment, the response time from when the input signal VIN changes from a "L" level to a "H" level until the modulation circuit 30 outputs a signal based on the carrier signal CS is shorter than the response time from when the input signal VIN changes from a "H" level to a "L" level until the modulation circuit 30 stops outputting a signal based on the carrier signal CS. This difference in response time can be adjusted by the delay time tdf1 of the falling-fall delay circuit FDC1.

[0135] As a result, the communication device 1A according to the second embodiment can be adjusted so that the pulse width of the input signal VIN and the pulse width of the output signal VO are approximately the same. Therefore, the communication device 1A according to the second embodiment can eliminate the limitation on the upper limit of the signal transmission speed due to changes in the pulse width of the input signal and the output signal, and can realize high-speed and high-quality signal transmission.

[0136] <3> Third Embodiment The communication device 1B according to the third embodiment has the same functions as the communication device 1 according to the first embodiment. Furthermore, the primary-side equipment in the communication device 1B has the function of generating the leading pulse of the OOK modulated signal regardless of the phase of the carrier signal CS when it detects a pulse of the input signal. The details of the third embodiment, and the differences from the first and second embodiments, will be described below.

[0137] <3-1> Composition Figure 13 is a circuit diagram showing an example of the circuit configuration of the input modulation unit IMP included in the communication device 1B according to the third embodiment. As shown in Figure 13, the communication device 1B includes a modulation circuit 30B instead of the modulation circuit 30. The modulation circuit 30B has a configuration in which the buffer 301, inverter 302, and rising edge delay circuit RDC1 of the modulation circuit 30 of the first embodiment are omitted, and rising edge delay circuits RDC3 and RDC4, a negative OR (NOR) circuit 310, an inverter 311, a logical AND (AND) circuit 312, a logical OR (OR) circuit 313, and a negative OR (NOR) circuit 314 are added.

[0138] In the third embodiment, the input circuit 10 outputs the input signal VIN to the oscillator circuit 20, the rising edge delay circuits RDC2, RDC3, and RDC4, the AND circuits 303, 304, and 305, and the inverter 306, respectively. In the third embodiment, the oscillator circuit 20 outputs the carrier signal CS, which is generated based on the input signal VIN, to the NOR circuit 310.

[0139] The rise time delay circuit RDC3 is a delay circuit that delays the rising edge of the input signal VIN input from the input circuit 10 and outputs it. Hereafter, the delay time of the signal rising edge caused by the rise time delay circuit RDC3 will be referred to as "tdr3". The input signal VIN delayed by the rise time delay circuit RDC3 will be referred to as "input signal VINdr3". The rise time delay circuit RDC3 outputs the input signal VINdr3, based on the input signal VIN, to the AND circuit 312.

[0140] The rise-time delay circuit RDC4 is a delay circuit that delays the rising edge of the input signal VIN, which is input from the input circuit 10, and outputs it. Hereinafter, the delay time of the signal rising edge caused by the rise-time delay circuit RDC4 will be referred to as "tdr4". The input signal VIN delayed by the rise-time delay circuit RDC4 will be referred to as "input signal VINdr4". The rise-time delay circuit RDC4 outputs the input signal VINdr4, based on the input signal VIN, to the inverter 311. The inverter 311 inverts the logic of the input signal VINdr4 input from the rise-time delay circuit RDC4. Then, the inverter 311 outputs the inverted input signal VINdr4 as a gate signal GS to the NOR circuit 310, the AND circuit 312, and the NOR circuit 314, respectively.

[0141] The NOR gate 310 performs a negative OR operation between the carrier signal CS input from the oscillator 20 and the gate signal GS input from the inverter 311. The NOR gate 310 then outputs the operation result to the OR gate 313 and the NOR gate 314, respectively.

[0142] The AND circuit 312 performs a logical AND operation between the input signal VINdr3, which is input from the rising edge delay circuit RDC3, and the gate signal GS, which is input from the inverter 311. The AND circuit 312 then outputs the result of the operation as a bit signal BS to the OR circuit 313.

[0143] The OR circuit 313 performs a logical OR operation between the output signal (calculation result) of the NOR circuit 310 and the bit signal BS input from the AND circuit 312. The OR circuit 313 then outputs the calculation result to the AND circuit 303.

[0144] The NOR gate 314 performs a negative OR operation between the output signal (calculation result) of the NOR gate 310 and the gate signal GS input from the inverter 311. The NOR gate 314 then outputs the calculation result to the AND gate 304.

[0145] In the third embodiment, the AND circuit 303 performs a logical AND operation between the output signal (calculation result) of the OR circuit 313 and the input signal VIN input from the input circuit 10. The AND circuit 303 then outputs the calculation result as the modulated signal VINP on the positive phase to the transmission circuit 40.

[0146] In the third embodiment, the AND circuit 304 performs a logical AND operation between the output signal (calculation result) of the NOR circuit 314 and the input signal VIN input from the input circuit 10. The AND circuit 304 then outputs the calculation result as the modulated signal VINN on the opposite phase to the transmission circuit 40.

[0147] The other configurations of the communication device 1B according to the third embodiment are the same as those of the communication device 1 according to the first embodiment.

[0148] <3-2> Operation The operation example of the modulation circuit 30B will be described below with reference to Figure 14. Figure 14 is a timing chart showing an operation example of the modulation circuit 30B provided in the communication device 1B according to the third embodiment. Figures (A) to (F) of Figure 14 show the input signal VIN, carrier signal CS, gate signal GS, bit signal BS, modulated signal VINP on the positive phase, modulated signal VINN on the negative phase, boost signal VBST, and shunt signal VSHT, respectively. t1 in Figure 14 shows the timing when the input signal VIN changes from "L" level to "H" level. t2 in Figure 14 shows the timing when the input signal VIN changes from "H" level to "L" level. Note that Figure 14 illustrates the case where a high-frequency carrier signal CS is output based on the input signal VIN of another channel. That is, the case where the input signal VIN to the modulation circuit 30B operates asynchronously with the carrier signal CS will be described.

[0149] When the input signal VIN is at a "L" level, both the modulated signal VINP on the positive phase side and the modulated signal VINN on the negative phase side of the modulation circuit 30B are at a "L" level. Also, the gate signal GS is at a "H" level, and the bit signal BS is at a "L" level.

[0150] When the input signal VIN changes from a "L" level to a "H" level, the boost signal VBST also changes to a "H" level, and the shunt signal VSHT changes to a "L" level. Furthermore, input signals VINdr3 and VINdr4 change to a "H" level after a delay of tdr3 and tdr4, respectively. The bit signal BS is at a "H" level during the period when input signal VINdr3 is at a "H" level and input signal VINdr4 is at a "L" level. That is, the period during which the bit signal BS is at a "H" level corresponds to the difference between the delay time tdr3 of the rise delay circuit RDC3 and the delay time tdr4 of the rise delay circuit RDC4. Finally, the modulated signal VINP on the positive phase side is at a "H" level during the period when the bit signal BS is at a "H" level. That is, the leading pulse width of the modulated signal VINP on the positive phase side is "tdr4-tdr3".

[0151] When the input signal VINdr4 changes from a "L" level to a "H" level, the gate signal GS changes from a "H" level to a "L" level. The modulation circuit 30 then outputs high-frequency signals (VINP and VINN) based on the carrier signal CS. Specifically, from the positive-phase modulated signal VINP, the carrier signal CS, masked by the gate signal GS, is output relative to the bit signal BS. For the negative-phase modulated signal VINN, the carrier signal CS, masked by the gate signal GS and inverted, is output. The phases of the positive-phase modulated signal VINP and the negative-phase modulated signal VINN are inverse, except for the leading pulse signal.

[0152] When the input signal VIN changes from a high level to a low level, the oscillator circuit 20 stops outputting the high-frequency carrier signal CS, and the shunt signal VSHT becomes high. Based on the fact that the input signal VIN has become low, the modulation circuit 30 stops outputting the high-frequency signals (VINP and VINN) based on the carrier signal CS.

[0153] In the third embodiment, the delay time tdr2 of the rise delay circuit RDC2 is longer than the delay time tdr4 of the rise delay circuit RDC4. Also, in the third embodiment, the length of the boost period is "tdr4-tdr3". In the third embodiment, the boost period is determined by the delay times of the rise delay circuits RDC3 and RDC4.

[0154] Other operations of the communication device 1B according to the third embodiment are the same as those of the communication device 1 according to the first embodiment.

[0155] <3-3> Effects of the Third Embodiment When multiple channels share a single oscillator circuit 20, each modulation circuit 30 may operate asynchronously with the carrier signal CS. In a modulation circuit 30 operating asynchronously with the carrier signal CS, the transition timing of the input signal VIN and the transition timing of the carrier signal CS will be mismatched. In this case, the waveform of the first pulse of the OOK modulated signal may change depending on the phase of the carrier signal CS at the time the pulse of the input signal VIN is input. Similarly, the waveform of the last pulse of the OOK modulated signal may change depending on the phase of the carrier signal CS at the time the pulse of the input signal VIN stops. In other words, when the input signal VIN and the oscillator circuit 20 operate asynchronously, the first and last pulses of the OOK modulated signal will each have random pulse widths.

[0156] As described in the first embodiment, the full-wave rectifier circuit 62 has, in principle, a slow rising edge response and a fast falling edge response. Therefore, even if the final pulse of the OOK modulated signal has a random pulse width, the effect on the falling edge response of the full-wave rectifier circuit 62 is small. On the other hand, the fact that the leading pulse of the OOK modulated signal has a random pulse width can affect the falling edge response of the full-wave rectifier circuit 62, causing a change in the waveform of the output voltage of the receiving circuit 60, which can be a cause of random jitter.

[0157] Therefore, the communication device 1B according to the third embodiment is equipped with a function to stabilize the leading pulse of the OOK modulated signal using a delay circuit. Specifically, the modulation circuit 30B in the third embodiment generates a bit signal BS by utilizing the difference in delay times between the rising edge delay circuits RDC3 and RDC4. Then, the modulation circuit 30B generates the leading pulse of the OOK modulated signal based on the bit signal BS. Subsequently, the modulation circuit 30B generates a high-frequency pulse based on the carrier signal CS based on the gate signal GS.

[0158] As a result, in the communication device 1B according to the third embodiment, the modulation circuit 30B can output a stable leading pulse regardless of the phase difference between the carrier signal CS and the input signal VIN. Therefore, the communication device 1B according to the third embodiment can suppress the generation of jitter at the output of the receiving circuit 60.

[0159] Furthermore, in the communication device 1B according to the third embodiment, the output time of the OOK modulated signal is shortened by the delay time tdr3 of the rising edge delay circuit RDC3. Therefore, in the communication device 1B according to the third embodiment, when the pulse width widens due to signal transmission, the pulse width of the input signal and the pulse width of the output signal can be adjusted to be approximately the same by adjusting the delay time tdr3 of the rising edge delay circuit RDC3. Therefore, the communication device 1B according to the third embodiment can eliminate the limitation on the upper limit of the signal transmission speed due to changes in the pulse width of the input signal and the output signal, and can realize high-speed and high-quality signal transmission.

[0160] <4> Fourth Embodiment The communication device 1C according to the fourth embodiment has the same functions as the communication device 1A according to the second embodiment. Furthermore, the primary-side equipment in the communication device 1C has the function of generating the leading pulse of the OOK modulated signal regardless of the phase of the carrier signal CS when it detects a pulse of the input signal, similar to the third embodiment. The details of the fourth embodiment, and the differences from the first to third embodiments, will be described below.

[0161] <4-1> Composition Figure 15 is a circuit diagram showing an example of the circuit configuration of the input modulation unit IMP included in the communication device 1C according to the fourth embodiment. As shown in Figure 15, the communication device 1C includes a modulation circuit 30C instead of the modulation circuit 30. The modulation circuit 30C has a configuration in which the rising edge delay circuit RDC3 is omitted and a falling edge delay circuit FDC2 is added, compared to the modulation circuit 30B of the fourth embodiment.

[0162] In the fourth embodiment, the input circuit 10 outputs the input signal VIN to the rising edge delay circuits RDC2 and RDC4, the falling edge delay circuit FDC2, and the AND gates 305 and 312, respectively.

[0163] The falling-fall delay circuit FDC2 is a delay circuit that delays the falling edge of the input signal VIN input from the input circuit 10 and outputs it. Hereinafter, the delay time of the falling edge of the signal by the falling-fall delay circuit FDC2 will be referred to as "tdf2". The input signal VIN delayed by the falling-fall delay circuit FDC2 will be referred to as "input signal VINdf2". The falling-fall delay circuit FDC2 outputs the input signal VINdf2, based on the input signal VIN, to the oscillator circuit 20, the AND circuit 303, the AND circuit 304, and the inverter 306, respectively. In the fourth embodiment, the oscillator circuit 20 outputs the carrier signal CS, which is generated based on the input signal VINdf2 input from the falling-fall delay circuit FDC2, to the NOR circuit 310.

[0164] In the fourth embodiment, the AND circuit 312 performs a logical AND operation between the input signal VIN input from the input circuit 10 and the gate signal GS input from the inverter 311. The AND circuit 312 then outputs the result of the operation as a bit signal BS to the OR circuit 313.

[0165] In the fourth embodiment, the AND circuit 303 performs a logical AND operation between the output signal (calculation result) of the OR circuit 313 and the input signal VINdf2 input from the falling-fall delay circuit FDC2. The AND circuit 303 then outputs the calculation result as the modulated signal VINP on the positive phase to the transmission circuit 40.

[0166] In the fourth embodiment, the AND circuit 304 performs a logical AND operation between the output signal (calculation result) of the NOR circuit 314 and the input signal VINdf2 input from the falling-fall delay circuit FDC2. The AND circuit 304 then outputs the calculation result as the modulated signal VINN on the inverse side to the transmitting circuit 40.

[0167] In the fourth embodiment, the inverter 306 inverts the logic of the input signal VINdf2 received from the falling-fall delay circuit FDC2. The inverter 306 then outputs the inverted input signal VINdf2 as a shunt signal VSHT to the transmission circuit 40.

[0168] The other configurations of the communication device 1C according to the fourth embodiment are the same as those of the communication device 1B according to the third embodiment.

[0169] <4-2> Operation The operation example of the modulation circuit 30C will be described below with reference to Figure 16. Figure 16 is a timing chart showing an operation example of the modulation circuit 30C provided in the communication device 1C according to the fourth embodiment. Figures (A) to (F) of Figure 16 show the input signal VIN, carrier signal CS, gate signal GS, bit signal BS, modulated signal VINP on the positive phase, modulated signal VINN on the negative phase, boost signal VBST, and shunt signal VSHT, respectively. t1 in Figure 16 shows the timing when the input signal VIN changes from "L" level to "H" level. t2 in Figure 16 shows the timing when the input signal VIN changes from "H" level to "L" level. Note that Figure 16 illustrates the case where a high-frequency carrier signal CS is output based on the input signal VIN of another channel. That is, the case where the input signal VIN to the modulation circuit 30C operates asynchronously with the carrier signal CS will be described.

[0170] When the input signal VIN is at a "L" level, both the modulated signal VINP on the positive phase side and the modulated signal VINN on the negative phase side of the modulation circuit 30C are at a "L" level. Also, the gate signal GS is at a "H" level, and the bit signal BS is at a "L" level.

[0171] When the input signal VIN changes from a "L" level to a "H" level, the boost signal VBST becomes "H" and the shunt signal VSHT becomes "L". Also, the input signal VINdr4 becomes "H" after a delay of tdr4. The bit signal BS is "H" during the period when the input signal VIN is "H" and the input signal VINdr4 is "L". In other words, the period during which the bit signal BS is "H" corresponds to the delay time tdr4 of the rising edge delay circuit RDC4. The modulated signal VINP on the positive phase side is "H" during the period when the bit signal BS is "H". In other words, the leading pulse width of the modulated signal VINP on the positive phase side is "tdr4".

[0172] When the input signal VINdr4 changes from a "L" level to a "H" level, the gate signal GS changes from a "H" level to a "L" level. The modulation circuit 30 then outputs high-frequency signals (VINP and VINN) based on the carrier signal CS.

[0173] When the input signal VIN changes from a high level to a low level, the input signal VINdf2 also changes to a low level with a delay of tdf2. Based on the fact that the input signal VINdf2 has reached a low level, the modulation circuit 30C stops outputting the high-frequency signals (VINP and VINN) based on the carrier signal CS. Also, the shunt signal VSHT changes to a high level based on the fact that the input signal VINdf2 has reached a low level. In this example, the high-frequency carrier signal CS is maintained even when the input signal VINdf2 is at a low level, but the output of the carrier signal CS is stopped when all other input signals VIN are at a low level.

[0174] In the fourth embodiment, the length of the boost period is "tdr2". That is, in the fourth embodiment, the boost period is determined by the delay time of the rise delay circuit RDC2.

[0175] Other operations of the communication device 1C according to the fourth embodiment are the same as those of the communication device 1B according to the third embodiment.

[0176] <4-3> Effects of the fourth embodiment The communication device 1C according to the fourth embodiment has a function to stabilize the leading pulse of the OOK modulated signal using a delay circuit different from that of the third embodiment. Specifically, the modulation circuit 30C in the fourth embodiment generates a bit signal BS using the delay time tdr4 of the rising edge delay circuit RDC4. Then, the modulation circuit 30C generates the leading pulse of the OOK modulated signal based on the bit signal BS. Subsequently, the modulation circuit 30C generates a high-frequency pulse based on the carrier signal CS based on the gate signal GS.

[0177] As a result, in the communication device 1C according to the fourth embodiment, the modulation circuit 30C can output a stable leading pulse regardless of the phase difference between the carrier signal CS and the input signal VIN. Therefore, the communication device 1C according to the fourth embodiment can suppress the generation of jitter at the output of the receiving circuit 60.

[0178] Furthermore, in the communication device 1C according to the fourth embodiment, the output time of the OOK modulated signal is extended by the delay time tdf2 of the falling-fall delay circuit FDC2. Therefore, in the communication device 1C according to the fourth embodiment, when the pulse width narrows due to signal transmission, the pulse width of the input signal and the pulse width of the output signal can be adjusted to be approximately the same by adjusting the delay time tdf2 of the falling-fall delay circuit FDC2. Consequently, the communication device 1C according to the fourth embodiment can eliminate the limitation on the upper limit of the signal transmission speed due to changes in the pulse width of the input signal and the output signal, and can realize high-speed and high-quality signal transmission.

[0179] <5> Fifth Embodiment The fifth embodiment of the communication device 1D relates to a communication device 1 configured with multiple channels, in which a different carrier signal CS is used for each channel. The details of the fifth embodiment are described below, and the differences from the first to fourth embodiments are explained below.

[0180] <5-1> Composition Figure 17 is a block diagram showing an example of the configuration of a communication device 1D according to the fifth embodiment. Figure 17 illustrates a communication device 1D configured with two channels. As shown in Figure 17, the communication device 1D has a configuration in which the oscillation circuit 20 is replaced with an oscillation circuit 20A in the communication device 1 according to the first embodiment. The oscillation circuit 20A receives the input signal VIN <1> and <2> During the period when at least one of the signals is at the "H" level, carrier signals CS1 and CS2 with different phases are generated, and the input signal VIN <1> and <2> During the period when both are at the "L" level, the generation of carrier signals CS1 and CS2 is stopped. The oscillator circuit 20A then outputs the generated carrier signals CS1 and CS2 to the modulation circuits 30-1 and 30-2, respectively. In this case, the modulation circuit 30 for each channel generates an OOK modulated signal using carrier signals CS with different phases.

[0181] (Configuration of oscillator circuit 20A) Figure 18 is a circuit diagram showing an example of the circuit configuration of the oscillation circuit 20A provided in the communication device 1D according to the fifth embodiment. As shown in Figure 18, the oscillation circuit 20A includes, for example, an OR circuit 80, a NAND gate 81, inverters 82 to 84, a buffer 85, an inverter 86, and nodes N40 to 42.

[0182] The OR gate 80 receives the input signal VIN from the input circuit 10-1. <1> The input signal VIN is input from input circuit 10-2. <2> A logical OR operation is performed with the OR circuit 80. The OR circuit 80 then outputs the operation result to the NAND circuit 81. The NAND circuit 81 performs a negative logical AND operation between the output signal (operation result) of the NAND circuit 81 and the voltage at node N42 (output signal of inverter 83). The NAND circuit 81 then outputs the operation result to inverter 82 via node N40. Inverter 82 inverts the logic of the output signal (operation result) of the NAND circuit 81 and outputs it to inverter 83 via node N41. Inverter 83 inverts the logic of the output signal (operation result) of the NAND circuit 81 and outputs it to inverter 84 and NAND circuit 81 respectively via node N42. Inverter 84 outputs a signal with the logic of the signal input to node N42 inverted. Buffer 85 delays the signal input to node N41 to adjust the timing of the signal and outputs it. Inverter 86 outputs a signal with the logic of the signal input to node N40 inverted. The outputs of inverter 84, buffer 85, and inverter 86 correspond to carrier signals CS1, CS2, and CS3, respectively. While Figure 17 illustrates the case where carrier signals CS1 and CS2 are supplied to modulation circuits 30-1 and 30-2, respectively, carrier signal CS3 may be used instead of carrier signal CS1 or CS2. Furthermore, if the communication device 1D consists of three or more channels, each of the carrier signals CS1 to CS3 may be supplied to the corresponding modulation circuit 30.

[0183] In the oscillation circuit 20A, the set of NAND gate 81, inverter 82, and inverter 83 corresponds to a ring oscillator. Input signal VIN <1> and <2> If all of these are at the "L" level, the ring oscillator of the oscillation circuit 20A will not oscillate. Therefore, the outputs of inverter 84, buffer 85, and inverter 86 will each be at the "L" level. Input signal VIN <1> and <2> If at least one of these is at the "H" level, the ring oscillator of the oscillation circuit 20A oscillates. At this time, high-frequency carrier signals CS1, CS2, and CS3 are output from inverter 84, buffer 85, and inverter 86, respectively. The phases of the carrier signals CS1 to CS3 are different because the nodes from which the signals are extracted are different from each other.

[0184] Note that while Figure 17 illustrates the case where carrier signals CS1 and CS2 are output to modulation circuits 30-1 and 30-2 respectively, the device is not limited to this. In communication device 1D, it is sufficient that carrier signals CS with different phases are used across multiple channels.

[0185] Furthermore, the communication device 1D may consist of N (where N is an integer greater than or equal to 2) channels. Since it is permissible for the input signal VIN and the carrier signal CS to be asynchronous in each channel, the communication device 1D only needs to have one oscillator circuit 20A shared by the first to the Nth channels. In this case, the oscillator circuit 20A controls the input signal VIN <1> ~ <n>Generate multiple carrier signals CS with different phases during the period when at least one of them is at the "H" level, and input signal VIN <1> ~ <n>The generation of the carrier signal CS is stopped during the period when all of them are at the "L" level. The assignment of each of the modulation circuits 30-1 to 30-N to a carrier signal CS with a different phase does not have to be one-to-one. In the fifth embodiment, a carrier signal CS having the same phase may be input to multiple modulation circuits 30.

[0186] <5-2> Effects of the Fifth Embodiment In a communication device capable of receiving N-bit signals, N modulation circuits 30 operate synchronously, and a synchronized carrier signal flows through N insulating elements 50. As a result, the EMI radiated from the modulation circuits 30 and insulating elements 50 is also multiplied by N. In the first to fourth embodiments, the signals (pulses) output by each modulation circuit 30 are perfectly synchronized with the carrier signal CS. One way to improve EMI performance is to change the driving phase between multiple insulating elements 50.

[0187] Therefore, the communication device 1D according to the fifth embodiment includes an oscillation circuit 20A capable of generating multiple types of carrier signals CS. This allows the communication device 1D according to the fifth embodiment to supply carrier signals CS with different phases to each modulation circuit 30. As a result, the communication device 1D according to the fifth embodiment can improve the harmonic EMI performance. In the fifth embodiment, the case in which the oscillation circuit 20A generates three types of carrier signals CS with different phases was illustrated, but the invention is not limited to this. The oscillation circuit 20A only needs to be configured to generate two or more types of carrier signals CS with different phases.

[0188] <6> others (A typical example of a rise-off delay circuit (RDC)) The following describes a typical example of a rise-off delay circuit (RDC).

[0189] Figure 19 is a circuit diagram showing an example of the circuit configuration of a rise-time delay circuit (RDC). As shown in Figure 19, the RDC rise-time delay circuit includes, for example, an inverter 90, a buffer 91, and a (negative OR) NOR circuit 92. The inverter 90 inverts the input signal to the RDC rise-time delay circuit and outputs it to the buffer 91 and the NOR circuit 92, respectively. The buffer 91 delays the output signal of the inverter 90 and outputs it to the NOR circuit 92. The NOR circuit 92 performs a negative OR operation between the output signal of the inverter 90 and the output signal of the inverter 90 delayed by the buffer 91. The NOR circuit 92 then outputs the result of the operation as the output signal of the RDC rise-time delay circuit. The buffer 91 is, for example, an inverter chain or a current-limiting inverter chain. Alternatively, the RDC rise-time delay circuit may include a capacitor and a constant current source as the buffer 91, and the delay determined by charging and discharging the capacitor by the constant current source may be utilized.

[0190] Figure 20 is a timing chart showing an example of the characteristics of the rise-time delay circuit RDC. As shown in Figure 20, when the input signal to the rise-time delay circuit RDC remains at the "L" level, the NOR circuit 92 receives "H" level signals from both the inverter 90 and the buffer 91. Therefore, the output signal of the NOR circuit 92 (the output signal of the rise-time delay circuit RDC) becomes "L".

[0191] When the input signal transitions from a "L" level to a "H" level, the NOR circuit 92 immediately receives a "L" level signal from the inverter 90, while simultaneously receiving a delayed "L" level signal from the buffer 91. As a result, the output signal of the NOR circuit 92 (the output signal of the rising edge delay circuit RDC) maintains a "L" level for the delay time tdr caused by the buffer 91 before transitioning to a "H" level.

[0192] When the input signal transitions from a high level to a low level, the NOR circuit 92 immediately receives a high-level signal from the inverter 90. As a result, the output signal of the NOR circuit 92 (the output signal of the rising edge delay circuit RDC) immediately transitions from a high level to a low level. After the buffer 91's delay time tdr has elapsed, the NOR circuit 92 receives high-level signals from both the inverter 90 and the buffer 91.

[0193] (A typical example of a fall-fall delay circuit (FDC)) The following describes a typical example of a falling-edge delay circuit (FDC). Figure 21 is a circuit diagram showing an example of the circuit configuration of a falling-edge delay circuit (FDC). As shown in Figure 21, the falling-edge delay circuit (FDC) includes, for example, an inverter 93, a buffer 94, and a NAND gate 95. The inverter 93 inverts the input signal to the falling-edge delay circuit (FDC) and outputs it to the buffer 94 and the NAND gate 95, respectively. The buffer 94 delays the output signal of the inverter 93 and outputs it to the NAND gate 95. The NAND gate 95 performs a negative logical AND operation between the output signal of the inverter 93 and the output signal of the inverter 93 delayed by the buffer 94. The NAND gate 95 then outputs the result of the operation as the output signal of the falling-edge delay circuit (FDC). The buffer 94 is, for example, an inverter chain or a current-limiting inverter chain. In addition, the rising-edge delay circuit (RDC) may include a capacitor and a constant current source as the buffer 94, and the delay determined by charging and discharging the capacitor by the constant current source may be utilized.

[0194] Figure 22 is a timing chart showing an example of the characteristics of the falling-false delay circuit FDC. As shown in Figure 22, when the input signal to the falling-false delay circuit FDC remains at the "L" level, the NAND circuit 95 receives "H" level signals from both the inverter 93 and the buffer 94. Therefore, the output signal of the NAND circuit 95 (the output signal of the falling-false delay circuit FDC) becomes "L".

[0195] When the input signal transitions from "L" level to "H" level, the NAND circuit 95 immediately receives an "L" level signal from the inverter 93. As a result, the output signal of the NAND circuit 95 (the output signal of the falling-fall delay circuit FDC) immediately transitions from "L" level to "H" level. After the buffer 94's delay time tdf has elapsed, the NAND circuit 95 receives "L" level signals from both the inverter 93 and the buffer 94.

[0196] When the input signal transitions from a high (H) level to a low (L) level, the NAND circuit 95 immediately receives a high (H) level signal from the inverter 93, while simultaneously receiving a delayed high (H) level signal from the buffer 94. As a result, the output signal of the NAND circuit 95 (the output signal of the falling-fall delay circuit FDC) maintains a high (H) level for the delay time tdf caused by the buffer 94 before transitioning to a low (L) level.

[0197] (First modified example of insulating element 50) In the first embodiment, an example was given in which the insulating element 50 is composed of an isolation transformer that uses a magnetic field as the transmission medium, but the invention is not limited thereto. The communication device 1 may also include an insulating element 50 that uses an electric field as the transmission medium. When an electric field is used as the transmission medium, an insulating capacitance with metal plates formed on both ends of the insulating layer is used.

[0198] Figure 23 is a circuit diagram showing an example of the circuit configuration of a communication device 1E according to a first modification of the first embodiment. As shown in Figure 23, the communication device 1E is equipped with an insulating element 50A instead of the insulating element 50. The insulating element 50A includes insulating capacitance sections 53 and 54. The insulating capacitance section 53 is mounted on the first substrate SUB1 and includes insulating capacitances 531 and 532. The insulating capacitance section 54 is mounted on the second substrate SUB2 and includes insulating capacitances 541 and 542.

[0199] One electrode of the insulating capacitance 531 is connected to the negative (-) output terminal of the transmission circuit 40. One electrode of the insulating capacitance 532 is connected to the positive (+) output terminal of the transmission circuit 40. One electrode of the insulating capacitance 541 is connected to the positive (+) input terminal of the amplification circuit 61. One electrode of the insulating capacitance 542 is connected to the negative (-) input terminal of the amplification circuit 61. The other electrode of the insulating capacitance 531 and the other electrode of the insulating capacitance 541 are connected, for example, via wire bonding. The other electrode of the insulating capacitance 532 and the other electrode of the insulating capacitance 542 are connected, for example, via wire bonding. The insulating layers included in the insulating capacitances 531, 532, 541 and 542 may be an oxide film or polyimide.

[0200] When the insulating element 50A is composed of insulating capacitance, the transmitting circuit 40 supplies a differential voltage based on the modulated signal to the insulating element 50A. As a result, the insulating element 50A can transmit the signal from the transmitting circuit 40 to the amplification circuit 61 through the electric field coupling of the insulating capacitances 531, 532, 541, and 542.

[0201] In the first modification of the first embodiment, the case in which the insulating capacitance section is provided on both the first substrate SUB1 and the second substrate SUB2 is illustrated, but the invention is not limited thereto. The insulating capacitance section may be mounted on either the first substrate SUB1 or the second substrate SUB2, or on both the first substrate SUB1 and the second substrate SUB2. The configuration described in the first modification of the first embodiment may be combined with other embodiments and modifications.

[0202] (Second modified example of insulating element 50) In the first embodiment, an example was given in which the insulating element 50 is provided on both the first substrate SUB1 and the second substrate SUB2, but the invention is not limited thereto. In the communication device 1, the insulating element 50 may be provided on substrates different from the first substrate SUB1 and the second substrate SUB2.

[0203] Figure 24 is a block diagram showing an example of the configuration of a communication device 1F according to a second modification of the first embodiment. As shown in Figure 24, the communication device 1F has a configuration in which a third board SUB3 is added to the communication device 1. The third board SUB3 is electrically connected to either the first board SUB1 or the second board SUB2. An insulating element 50 is mounted on the third board SUB3. In this case, the transmitting circuit 40 mounted on the first board SUB1 and the insulating element 50 mounted on the third board SUB3 are connected, for example, by wire bonding. Similarly, the receiving circuit 60 mounted on the second board SUB2 and the insulating element 50 mounted on the third board SUB3 are connected, for example, by wire bonding.

[0204] The cost of the process for forming the insulating element 50 is high because it includes the process of forming a thick oxide film. In contrast, in the second modification of the first embodiment, the insulating element 50 is formed on the third substrate SUB3, which can reduce manufacturing costs compared to the case where the insulating element 50 is formed on both the first substrate SUB1 and the second substrate SUB2. The configuration described in the second modification of the first embodiment may be combined with other embodiments and modifications.

[0205] (Other variations, etc.) The above embodiments may be combined to the extent possible. The fifth embodiment may be combined with any of the first to fourth embodiments.

[0206] In the above embodiment, an example was given in which a signal is not transmitted to the insulating element 50 when the input signal VIN is at the "L" level, and a carrier signal CS is transmitted to the insulating element 50 when the input signal VIN is at the "H" level, but the invention is not limited to this. The communication device 1 may be configured not to transmit a signal to the insulating element 50 when the input signal VIN is at the "H" level, and to transmit a carrier signal CS to the insulating element 50 when the input signal VIN is at the "L" level. Furthermore, in the transmitting circuit 40, the boost circuit BC may be configured to increase the charging speed of the capacitor CC when the boost signal VBST is at the "L" level, and the shunt circuit SC may be configured to discharge the charge stored in the capacitor CC when the shunt signal VSHT is at the "L" level.

[0207] In the third embodiment, the modulation circuit 30B is exemplified as being composed of three inverter circuits, four AND circuits, one OR circuit, and two negated OR circuits, but it is not limited thereto. The modulation circuit 30B may have other circuit configurations as long as it is possible to produce a logic output equivalent to that described in the third embodiment. Similarly, in the fourth embodiment, the modulation circuit 30C may have other circuit configurations as long as it is possible to produce a logic output equivalent to that described in the fourth embodiment.

[0208] In this specification, a configuration in which an isolation device (isolation transformer or isolation capacitance) is provided on both the first substrate SUB1 and the second substrate SUB2 may be called a "double isolation method". In this specification, a configuration in which an isolation device (isolation transformer or isolation capacitance) is provided on either the first substrate SUB1 or the second substrate SUB2 may be called a "single isolation method". In this specification, buffers 85, 91, 94 and 301 may each be called a "delay element".

[0209] In this specification, a "H" level voltage corresponds to a voltage above a threshold when determining data in binary terms. A "L" level voltage corresponds to a voltage below a threshold when determining data in binary terms. In this specification, "connected" means electrically connected, and does not exclude, for example, another element in between. "Electrically connected" may be via an insulator, as long as it can function as if electrically connected. The input circuit 10 may be called the "input buffer circuit". The output circuit 70 may be called the "output buffer circuit".

[0210] In this specification, "conductivity type" corresponds to "N-type" or "P-type". For example, a transistor of the first conductivity type corresponds to one of an NMOS transistor and a PMOS transistor, and a transistor of the second conductivity type corresponds to the other of an NMOS transistor and a PMOS transistor. One end and the other end may be called the "first end" and the "second end". The ground node may be called the power node. One end of the constant current source corresponds to one of the input terminal and the output terminal, and the other end of the constant current source corresponds to the other of the input terminal and the output terminal. In the above embodiment, the constant current source may consist of one transistor, a plurality of transistors, or a current mirror circuit including two transistors.

[0211] In this specification, transistor sizes are compared using, for example, the gate width in the case of a planar MOSFET. In this specification, transistor sizes are compared using, for example, the number of fins in the case of a FinFET. In this specification, transistor sizes are compared using, for example, the number of stacked nanosheets, which are semiconductor layers, in the case of a nanosheet structure transistor.

[0212] Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to these descriptions.

[0213] (Note 1) A first substrate having an oscillator circuit and a first modulation circuit, A second substrate, which is insulated from the first substrate and has a first receiving circuit and a first output circuit, A first insulating element connected between the first modulation circuit and the first receiving circuit, Equipped with, The above oscillator circuit outputs a carrier signal in the high frequency band, The first modulation circuit has at least one delay circuit and outputs a first modulated signal based on the carrier signal when a first input signal input from an external source is at a first logic level, and uses the at least one delay circuit to adjust the length of the period during which the first modulated signal is output to be shorter or longer than the period during which the first input signal is at the first logic level. The first receiving circuit described above receives a first electrical signal based on the first modulated signal described above via the first insulating element described above, demodulates the first electrical signal described above, The first output circuit outputs a first output signal to the outside based on the first electrical signal demodulated by the first receiving circuit. Communication device.

[0214] (Note 2) The length of the period during which the first output signal is at the first logic level is approximately equal to the length of the period during which the first input signal is at the first logic level. The communication device described in Appendix 1.

[0215] (Note 3) The first modulation circuit has a first logic circuit, and the at least one delay circuit includes a first delay circuit to which a signal based on the first input signal is input. The output signal of the first delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it transitions from the second logic level to the first logic level after a first time delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The first logic circuit outputs the result of a logical AND operation between the output signal of the first delay circuit and the carrier signal as the first modulated signal. Communication device as described in Appendix 1 or Appendix 2.

[0216] (Note 4) The first modulation circuit has a second logic circuit, and the at least one delay circuit includes a second delay circuit and a third delay circuit to which a signal based on the first input signal is input. The output signal of the second delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it transitions from the second logic level to the first logic level after a second time delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The output signal of the third delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it transitions from the second logic level to the first logic level after a third time delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The second logic circuit outputs the result of a logical AND operation between the signal based on the first input signal and the signal based on the carrier signal as the first modulated signal. The first modulation circuit outputs a signal of the first logic level with a length based on the difference between the second time and the third time, before outputting the first modulated signal. Communication device as described in Appendix 1 or Appendix 2.

[0217] (Note 5) The length of the period during which the first modulation circuit outputs the first modulated signal is shorter than the period during which the first output signal is at the first logic level. Communication device as described in Appendix 3 or Appendix 4.

[0218] (Note 6) The first modulation circuit has a third logic circuit, and the at least one delay circuit includes a fourth delay circuit to which a signal based on the first input signal is input. The output signal of the fourth delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it immediately transitions from the second logic level to the first logic level. When the input signal transitions from the first logic level to the second logic level, it transitions from the first logic level to the second logic level after a fourth time delay. The third logic circuit outputs the result of a logical AND operation between the output signal of the fourth delay circuit and the carrier signal as the first modulated signal. Communication device as described in Appendix 1 or Appendix 2.

[0219] (Note 7) The first modulation circuit has a fourth logic circuit, and the at least one delay circuit includes a fifth delay circuit and a sixth delay circuit to which a signal based on the first input signal is input. The output signal of the fifth delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it transitions from the second logic level to the first logic level after a 5-hour delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The output signal of the sixth delay circuit described above is: When the input signal transitions from the second logic level to the first logic level, it immediately transitions from the second logic level to the first logic level. When the input signal transitions from the first logic level to the second logic level, it transitions from the first logic level to the second logic level after a 6-hour delay. The fourth logic circuit outputs the result of a logical AND operation between the output signal of the sixth delay circuit and the signal based on the carrier signal as the first modulated signal. The first modulation circuit outputs a signal of the first logic level with a length based on the fifth time, before outputting the first modulated signal. Communication device as described in Appendix 1 or Appendix 2.

[0220] (Note 8) The length of the period during which the first modulation circuit outputs the first modulated signal is longer than the period during which the first output signal is at the first logic level. Communication device as described in Appendix 6 or Appendix 7.

[0221] (Note 9) The first substrate further comprises a first transmitting circuit connected between the first modulation circuit and the first insulating element. The first transmitting circuit includes first to third capacitors, a first inverter circuit into which the first modulated signal is input, a second inverter circuit into which the inverted signal of the first modulated signal is input, a first transistor and a first resistor connected in parallel between the output terminal of the first inverter circuit and one electrode of the first capacitor, and a second transistor and a second resistor connected in parallel between the output terminal of the second inverter circuit and one electrode of the second capacitor. One electrode of the third capacitance is connected to the other electrode of the first capacitance, and the other electrode of the third capacitance is connected to the other electrode of the second capacitance. A boost signal is input to the gate terminals of the first transistor and the second transistor, respectively. The first insulating element outputs the first electrical signal based on the voltage of one electrode of the third capacitance and the voltage of the other electrode of the third capacitance. The first modulation circuit generates the boost signal of the first logic level until 7 hours have elapsed since the first input signal transitioned from the inverse logic level of the first logic level to the first logic level, and generates the boost signal of the inverse logic level of the first logic level during the period when the first modulated signal is not output. A communication device as described in any of Appendix 1 to Appendix 8.

[0222] (Note 10) The first substrate further comprises a first transmitting circuit connected between the first modulation circuit and the first insulating element. The first transmitting circuit described above includes first to third capacitors, a first inverter circuit to which the first modulated signal is input and electrically connected to one electrode of the first capacitor, a second inverter circuit to which the inverted signal of the first modulated signal is input and electrically connected to one electrode of the second capacitor, and a third transistor. One electrode of the third capacitance is connected to the other electrode of the first capacitance, and the other electrode of the third capacitance is connected to the other electrode of the second capacitance. The first insulating element outputs the first electrical signal based on the voltage of one electrode of the third capacitance and the voltage of the other electrode of the third capacitance. One end of the third transistor is connected to the other electrode of the first capacitor, the other end of the third transistor is connected to the other electrode of the second capacitor, and a shunt signal is input to the gate terminal of the third transistor. The first modulation circuit generates the shunt signal at the second logic level during the period when the first modulated signal is output, and when the output of the first modulated signal is completed, it transitions the shunt signal from the second logic level to the first logic level. A communication device as described in any of Appendix 1 to Appendix 8.

[0223] (Note 11) The first receiving circuit described above includes an amplification circuit and a full-wave rectification circuit. The above amplification circuit amplifies the first electrical signal using a differential amplifier circuit and outputs it to the above full-wave rectifier circuit. The full-wave rectifier circuit performs full-wave rectification of the output of the amplification circuit using a differential amplifier circuit and a current mirror circuit, performs envelope detection, and outputs the demodulated first electrical signal, obtained by the first receiving circuit, to the first output circuit. A communication device as described in any of Appendix 1 to Appendix 10.

[0224] (Note 12) The above amplification circuit adds an offset voltage to the output signal to the above full-wave rectifier circuit. The communication device described in Appendix 11.

[0225] (Note 13) The system further comprises N insulating elements (where N is an integer of 2 or more) including the first insulating element described above. The first substrate described above has N modulation circuits, including the first modulation circuit described above. The second substrate has N receiving circuits including the first receiving circuit and N output circuits including the first output circuit. The kth input signal (where k is an integer between 2 and N) is transmitted by the kth modulation circuit, the kth insulating element, the kth receiving circuit, and the kth output circuit, and output to the outside as the kth output signal. The oscillator circuit supplies the carrier signal to each of the first to the Nth modulation circuits when at least one of the first to the Nth input signals is at the first logic level, and stops supplying the carrier signal to each of the first to the Nth modulation circuits when all of the first to the Nth input signals are at the inverse logic level of the first logic level. A communication device as described in any of Appendix 1 to Appendix 12.

[0226] (Note 14) The phase of the carrier signal supplied to the first modulation circuit is different from the phase of the carrier signal supplied to the k modulation circuit. The communication device described in Appendix 13.

[0227] (Appendix 15) The first insulating element is an insulating capacitor or an insulating transformer. The communication device according to any one of Appendices 1 to 14.

[0228] (Appendix 16) The at least one delay circuit includes a third inverter circuit that receives an input signal, a first delay element that delays and outputs the output signal of the third inverter circuit, and a fifth logic circuit that outputs the result of a negative logical sum operation between the output signal of the third inverter circuit and the output signal of the first delay element. The communication device according to any one of Appendices 3, 4, and 7.

[0229] (Appendix 17) The at least one delay circuit includes a fourth inverter circuit that receives an input signal, a second delay element that delays and outputs the output signal of the fourth inverter circuit, and a sixth logic circuit that outputs the result of a negative logical product operation between the output signal of the fourth inverter circuit and the output signal of the second delay element. The communication device according to Appendix 6 or 7.

[0230] (Appendix 18) The oscillation circuit includes a ring oscillator. The communication device according to any one of Appendices 1 to 17.

[0231] (Appendix 19) The first insulating element is provided on one of the first substrate and the second substrate, or on both the first substrate and the second substrate. The communication device according to any one of Appendices 1 to 18.

[0232] (Appendix 20) The communication device further includes a third substrate electrically connected to either the first substrate or the second substrate. The first insulating element is provided on the third substrate. A communication device as described in any of the appendices 1 through 19.

[0233] (Note 21) The first modulation circuit outputs an inverted phase signal which is the inverse logic level of the first modulated signal, and the first electrical signal corresponds to the signal transmitted through the first insulating element, where the differential signal based on the first modulated signal and the inverted phase signal is the differential signal. A communication device as described in any of Appendix 1 to Appendix 20.

[0234] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0235] 1...Communication device, 10...Input circuit, 20...Oscillator circuit, 30...Modulation circuit, 40...Transmitting circuit, 50...Isolation element, 51,52...Isolation transformer, 53,54...Isolation capacitance section, 60...Receiver circuit, 61...Amplifier circuit, 62...Full-wave rectifier circuit, 70...Output circuit, 80...Logical OR circuit, 81...Negative AND circuit, 82~84,86,90...Inverter, 85...Buffer, 91...Buffer, 92...Negative OR circuit, 93...Inverter, 94...Buffer, 95...NAND circuit, 301...Buffer, 302...Inverter, 303,304...Logical AND circuit, 306,307...Inverter, 310...Negative OR circuit, 311... Inverter, 312... AND circuit, 313... OR circuit, 314... NOR circuit, 511~514... Coil, 515... Insulating layer, 521~524... Coil, 525... Insulating layer, 531, 532, 541, 542... Insulation capacitance, 611~614... Diode, 615... Bias circuit, 616, 621, 622... Constant current source, CS... Carrier signal, RDC... Rising-edge delay circuit, FDC... Falling-edge delay circuit, IBIAS... Bias current, MN... NMOS transistor, MP... PMOS transistor, PW... Power supply circuit, RA, RB... Resistor, SUB... Circuit board, VIN, VINdr, VINdf... Input signal< / n> < / n> < / n> < / n>

Claims

1. A first substrate having an oscillator circuit and a first modulation circuit, A second substrate, which is insulated from the first substrate and has a first receiving circuit and a first output circuit, A first insulating element connected between the first modulation circuit and the first receiving circuit, Equipped with, The aforementioned oscillator circuit outputs a carrier signal in the high-frequency band, The first modulation circuit has at least one delay circuit and outputs a first modulated signal based on the carrier signal when a first input signal input from an external source is at a first logic level, and uses the at least one delay circuit to adjust the length of the period during which the first modulated signal is output to be shorter or longer than the period during which the first input signal is at a first logic level. The first receiving circuit receives a first electrical signal based on the first modulated signal via the first insulating element, demodulates the first electrical signal, The first output circuit outputs a first output signal to the outside based on the first electrical signal demodulated by the first receiving circuit. The at least one delay circuit includes a first delay circuit and a second delay circuit to which a signal based on the first input signal is input, The output signal of the first delay circuit is When the input signal transitions from the second logic level to the first logic level, the system transitions from the second logic level to the first logic level after a first time delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The output signal of the second delay circuit is When the input signal transitions from the second logic level to the first logic level, a second time delay is performed before the transition from the second logic level to the first logic level. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The first modulation circuit is configured to start outputting the first modulated signal based on the fact that a first time has elapsed since the signal transitioned from the second logic level to the first logic level, and to set the length of the leading pulse of the first modulated signal to a length based on the difference between the first time and the second time. Communication device.

2. A first substrate having an oscillator circuit and a first modulation circuit, A second substrate, which is insulated from the first substrate and has a first receiving circuit and a first output circuit, A first insulating element connected between the first modulation circuit and the first receiving circuit, Equipped with, The aforementioned oscillator circuit outputs a carrier signal in the high-frequency band, The first modulation circuit has at least one delay circuit and outputs a first modulated signal based on the carrier signal when a first input signal input from an external source is at a first logic level, and uses the at least one delay circuit to adjust the length of the period during which the first modulated signal is output to be shorter or longer than the period during which the first input signal is at a first logic level. The first receiving circuit receives a first electrical signal based on the first modulated signal via the first insulating element, demodulates the first electrical signal, The first output circuit outputs a first output signal to the outside based on the first electrical signal demodulated by the first receiving circuit. The first substrate further includes a first transmitting circuit connected between the first modulation circuit and the first insulating element. The first transmitting circuit includes first to third capacitors, a first inverter circuit into which the first modulated signal is input, a second inverter circuit into which the inverted signal of the first modulated signal is input, a first transistor and a first resistor connected in parallel between the output terminal of the first inverter circuit and one electrode of the first capacitor, and a second transistor and a second resistor connected in parallel between the output terminal of the second inverter circuit and one electrode of the second capacitor. One electrode of the third capacitor is connected to the other electrode of the first capacitor, and the other electrode of the third capacitor is connected to the other electrode of the second capacitor, and a boost signal is input to the gate terminals of the first transistor and the second transistor, The first insulating element outputs the first electrical signal based on the voltage of one electrode of the third capacitance and the voltage of the other electrode of the third capacitance. The first modulation circuit generates the boost signal of the first logic level from the time the first input signal transitions from the inverse logic level of the first logic level to the first logic level until a predetermined time has elapsed, and generates the boost signal of the inverse logic level of the first logic level during the rest of the period. Communication device.

3. A first substrate having an oscillator circuit and a first modulation circuit, A second substrate, which is insulated from the first substrate and has a first receiving circuit and a first output circuit, A first insulating element connected between the first modulation circuit and the first receiving circuit, Equipped with, The aforementioned oscillator circuit outputs a carrier signal in the high-frequency band, The first modulation circuit has at least one delay circuit and outputs a first modulated signal based on the carrier signal when a first input signal input from an external source is at a first logic level, and uses the at least one delay circuit to adjust the length of the period during which the first modulated signal is output to be shorter or longer than the period during which the first input signal is at a first logic level. The first receiving circuit receives a first electrical signal based on the first modulated signal via the first insulating element, demodulates the first electrical signal, The first output circuit outputs a first output signal to the outside based on the first electrical signal demodulated by the first receiving circuit. The first substrate further includes a first transmitting circuit connected between the first modulation circuit and the first insulating element. The first transmitting circuit comprises first to third capacitors, a first inverter circuit to which the first modulated signal is input and electrically connected to one electrode of the first capacitor, a second inverter circuit to which the inverted signal of the first modulated signal is input and electrically connected to one electrode of the second capacitor, and a third transistor. One electrode of the third capacitance is connected to the other electrode of the first capacitance, and the other electrode of the third capacitance is connected to the other electrode of the second capacitance. The first insulating element outputs the first electrical signal based on the voltage of one electrode of the third capacitance and the voltage of the other electrode of the third capacitance. One end of the third transistor is connected to the other electrode of the first capacitor, the other end of the third transistor is connected to the other electrode of the second capacitor, and a shunt signal is input to the gate terminal of the third transistor. The first modulation circuit is configured to output a signal at the inverse logic level of the first input signal as the shunt signal. Communication device.

4. The length of the period during which the first output signal is at the first logic level is approximately equal to the length of the period during which the first input signal is at the first logic level. A communication device according to any one of claims 1 to 3.

5. The at least one delay circuit includes a first delay circuit to which a signal based on the first input signal is input, The output signal of the first delay circuit is When the input signal transitions from the second logic level to the first logic level, the system transitions from the second logic level to the first logic level after a first time delay. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The first modulation circuit is configured to start outputting the first modulated signal based on a first time elapsed since the signal transitioned from the second logic level to the first logic level, and to stop outputting the first modulated signal based on the signal transitioning from the first logic level to the second logic level. The communication device according to claim 2 or claim 3.

6. The at least one delay circuit includes a second delay circuit to which a signal based on the first input signal is input, The output signal of the second delay circuit is When the input signal transitions from the second logic level to the first logic level, a second time delay is performed before the transition from the second logic level to the first logic level. When the input signal transitions from the first logic level to the second logic level, it immediately transitions from the first logic level to the second logic level. The first modulation circuit is configured such that the length of the leading pulse of the first modulated signal is determined based on the difference between the first time and the second time. The communication device according to claim 5.

7. The at least one delay circuit includes a third delay circuit to which a signal based on the first input signal is input, The output signal of the third delay circuit is When the input signal transitions from the second logic level to the first logic level, it immediately transitions from the second logic level to the first logic level. When the input signal transitions from the first logic level to the second logic level, a third time delay is performed before the transition from the first logic level to the second logic level. The first modulation circuit is configured to start outputting the first modulated signal based on the transition of the signal from the second logic level to the first logic level, and to stop outputting the first modulated signal based on the elapsed third of time since the signal transitioned from the first logic level to the second logic level. The communication device according to claim 2 or claim 3.

8. The first receiving circuit has an amplification circuit and a full-wave rectifier circuit, The amplification circuit amplifies the first electrical signal using a differential amplifier circuit and outputs it to the full-wave rectifier circuit, and adds an offset voltage to the output signal to the full-wave rectifier circuit. The full-wave rectifier circuit performs full-wave rectification of the output of the amplifier circuit using a differential amplifier circuit and a current mirror circuit, performs envelope detection, and outputs the first electrical signal, demodulated by the first receiving circuit, to the first output circuit. A communication device according to any one of claims 1 to 3.

9. The invention further comprises N (where N is an integer of 2 or more) insulating elements, including the first insulating element, The first substrate has N modulation circuits, including the first modulation circuit. The second substrate has N receiving circuits including the first receiving circuit and N output circuits including the first output circuit. The kth input signal (where k is an integer between 2 and N) is transmitted by the kth modulation circuit, the kth insulating element, the kth receiving circuit, and the kth output circuit, and output to the outside as the kth output signal. The oscillator circuit supplies the carrier signal to each of the first to the Nth modulation circuits when at least one of the first to the Nth input signals is at the first logic level, and stops supplying the carrier signal to each of the first to the Nth modulation circuits when all of the first to the Nth input signals are at the inverse logic level of the first logic level. A communication device according to any one of claims 1 to 3.

10. The phase of the carrier signal supplied to the first modulation circuit and the phase of the carrier signal supplied to the k modulation circuit are different. The communication device according to claim 9.

11. The first insulating element is provided on either the first substrate or the second substrate, or on both the first substrate and the second substrate. A communication device according to any one of claims 1 to 3.

12. The present invention further comprises a third substrate electrically connected to the first substrate and the second substrate, The first insulating element is provided on the third substrate, A communication device according to any one of claims 1 to 3.

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