Manufacturing method for semiconductor devices

Abstract

To provide a manufacturing method of a semiconductor device which can improve the removal property of a modified resist in comparison to a conventional technique.SOLUTION: A manufacturing method of a semiconductor device according to the present invention is the manufacturing method of the semiconductor device that removes a resist film by using plasma gas and includes the steps of: executing resist film removal processing of removing the resist film in which impurity ions are injected by using only plasma gas of oxygen-based gas without containing fluorine-based gas; increasing the removal amount of the modified resist by lowering the wafer temperature of the semiconductor device by separating the semiconductor device from a heating device by using a wafer lift moving-up / down device in the resist film removal step; and removing the remaining resist film using the pure water scrub cleaning method.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, such as a MOS-type field-effect transistor. [Background technology]

[0002] Techniques for removing resist from the surface of a sample such as a semiconductor substrate using gas plasma include, for example, a technique in which oxygen gas is plasma-generated by high-frequency discharge and the resist on the sample surface is ashed and removed in the gas plasma; a technique in which active particles (radicals) are transported from an oxygen gas plasma generated by microwave discharge to a separate chamber and the resist is ashed and removed; and a technique in which a gas containing fluorine, such as carbon tetrafluoride gas, is added to oxygen gas and plasma-generated to accelerate the ashing rate of the resist hardened by ion implantation, etc., in the gas plasma, thereby removing the resist.

[0003] For example, Patent Document 1 discloses the following resist removal method. This resist removal method is (1) A step of plasmaizing a gas for removing resist from the sample surface and a gas that promotes the removal of the resist and can etch the sample under reduced pressure, (2) A step of removing the resist partially with the gas plasma, (3) A step of stopping the plasma generation of the gas for promoting resist removal and removing the remaining resist with the gas plasma of the gas for resist removal, It is characterized by having [this feature].

[0004] Furthermore, for example, Patent Document 2 discloses a method for manufacturing a semiconductor device that optimally removes scum without adversely affecting the underlying layer of the resist pattern. This method for manufacturing a semiconductor device is: (1) A step of forming an oxide film on a semiconductor substrate, coating a photoresist on the oxide film, exposing the photoresist to light, and developing the exposed photoresist to form an opening in the photoresist, (2) Using the photoresist as a mask, the oxide film is subjected to oxygen plasma treatment, and after the oxygen plasma treatment, diluted hydrofluoric acid is supplied to the oxide film and the photoresist 8. (3) After the step of supplying the diluted hydrofluoric acid, the step of ion implanting a single-conductivity impurity into the semiconductor substrate through the oxide film using the photoresist as a mask, It is characterized by having [this feature]. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Patent No. 2644758 [Patent Document 2] Japanese Patent Publication No. 2013-65594 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, in conventional resist removal techniques for forming MOS-type field-effect transistors, the "technique for removing resist by adding a fluorine-containing gas, such as carbon tetrafluoroethylene gas, to oxygen gas," which aims to remove resists that have hardened and are difficult to remove by ion implantation, had the following problems. Specifically, when the sample surface exposed to the gas plasma is silicon or silicon oxide, the corresponding silicon substrate, the polysilicon film on the gate, and the silicon oxide film on the sidewalls are also etched by the fluorine-containing gas, making it impossible to obtain the desired transistor structure.

[0007] In particular, transistors that utilize impurity diffusion near the substrate surface had a problem where, if the silicon oxide film on the source / drain region was removed, out-diffusion (diffusion outward) occurred during heat treatment, making it impossible to obtain the desired transistor characteristics. On the other hand, if process conditions were set to reduce the amount of etching on the sample surface, the resist would denature during high-concentration injection, reducing its removeability and resulting in the generation of residue.

[0008] An object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the removability of a deteriorated resist as compared with the prior art.

[0009] Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of completely removing a resist modified by high-concentration implantation without etching silicon or silicon oxide on the sample surface.

Means for Solving the Problems

[0010] A method for manufacturing a semiconductor device according to an aspect of the present invention includes: In a semiconductor device containing silicon and silicon oxide on the sample surface, removing a resist film using a plasma gas The aforementioned a method for manufacturing a semiconductor device and , performing a resist film removal process of removing a resist film implanted with impurity ions using only a plasma gas of an oxygen-based gas without including a fluorine-based gas; In order to remove a resist film altered by the injection of the oxygen-based gas without etching silicon or silicon oxide, In the resist film removal process, by using a wafer lift-up and lowering device to increase the distance between the semiconductor device and the heating device, By lowering the wafer temperature of the semiconductor device, the ability to remove the altered resist is improved, increasing the removal amount of the deteriorated resist; removing the remaining resist film using a pure water scrub cleaning method; and.

Effects of the Invention

[0011] Therefore, according to the method for manufacturing a semiconductor device according to an aspect of the present invention, the removability of the deteriorated resist can be improved. Further, even a resist modified by high-concentration implantation can be completely removed without etching silicon or silicon oxide on the sample surface.

Brief Description of the Drawings

[0012] [Figure 1A]This is a longitudinal cross-sectional view of the first step in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 1B] This is a longitudinal cross-sectional view of a second step showing a method for manufacturing a MOS-type field-effect transistor according to the embodiment. [Figure 1C] This is a longitudinal cross-sectional view of the third step in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 1D] This is a longitudinal cross-sectional view of the fourth step in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 1E] This is a longitudinal cross-sectional view of the fifth step in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 1F] This is a longitudinal cross-sectional view of the sixth step in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 1G] This is a longitudinal cross-sectional view of the seventh step showing the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 2A] This is a longitudinal cross-sectional view of the first step in the manufacturing method of a conventional MOS-type field-effect transistor. [Figure 2B] This is a longitudinal cross-sectional view of the second step in the manufacturing method of a conventional MOS-type field-effect transistor. [Figure 2C] This is a longitudinal cross-sectional view of the third step in the manufacturing method of a conventional MOS-type field-effect transistor. [Figure 2D] This is a longitudinal cross-sectional view of the fourth step in the manufacturing method of a conventional MOS-type field-effect transistor. [Figure 2E] This is a longitudinal cross-sectional view of the fifth step in the manufacturing method of a conventional MOS-type field-effect transistor. [Figure 2F] This is a longitudinal cross-sectional view of the sixth step in a conventional method for manufacturing a MOS-type field-effect transistor. [Figure 3] This is a photograph of a longitudinal cross-section of a MOS field-effect transistor manufactured using a conventional method for producing MOS field-effect transistors. [Figure 4]This is a photograph of a longitudinal cross-section of a MOS field-effect transistor when using the manufacturing method of the MOS field-effect transistor according to the embodiment. [Figure 5] This graph shows the drain voltage versus drain current characteristics, illustrating the improvement in the electrical characteristics of a MOS-type field-effect transistor when using the manufacturing method of the MOS-type field-effect transistor according to the embodiment. [Figure 6A] This graph shows the reduction in silicon oxide (OX) and silicon nitride (SiN) film thickness due to the resist film removal process, which is a conventional method for manufacturing MOS-type field-effect transistors. [Figure 6B] This table shows the amount of film reduction in silicon oxide (OX) and silicon nitride (SiN) due to the resist film removal process, which is a conventional method for manufacturing MOS-type field-effect transistors. [Figure 7] This is a photograph showing a wafer lifting device using three support pins, which is used in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 8A] Figure 7 is a graph showing the amount of resist film reduction during lift-up when using the wafer lifting device. [Figure 8B] Figure 7 is a table showing the amount of resist film reduction during lift-up when using the wafer lifting device. [Figure 9A] This is a photograph of the plane before water washing, showing the effect of water washing after resist removal when using the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Figure 9B] This is a photograph of the plan view after water washing, showing the effect of water washing after resist removal when using the manufacturing method of a MOS-type field-effect transistor according to the embodiment. [Modes for carrying out the invention]

[0013] Embodiments and modified examples of the present invention will be described below with reference to the drawings. The same or similar components are denoted by the same reference numerals.

[0014] (Inventor's insights) Figures 2A to 2F are longitudinal cross-sectional views showing a conventional method for manufacturing a MOS-type field-effect transistor, illustrating the removal of resist using a process gas that utilizes a plasma containing carbon tetrafluoride (CF4).

[0015] Before forming the sidewall (SW) shown in Figure 2A, a gate silicon oxide film 13 is formed on the semiconductor substrate 10, followed by the formation of a polysilicon electrode 14 and then a resist film 16. Next, in Figure 2B, the resist film 16 is isotropically etched from the upper side of the semiconductor substrate 10 using a process gas containing carbon tetrafluoride gas (CF4), resulting in a tapered surface 14t on the side of the polysilicon electrode 14, as shown in Figure 2C.

[0016] On the other hand, as shown in Figure 2D, after forming the sidewalls (SW) of the high-temperature silicon oxide film (HTO) 31 and silicon nitride film 32 on the side of the polysilicon electrode 14, the resist film 33 is isotropically etched from the upper side of the semiconductor substrate 10 using a process gas containing carbon tetrafluoride gas (CF4), as shown in Figure 2E. Furthermore, after etching the sidewalls (SW) and etching the semiconductor substrate 10 in a step shape, the result is as shown in Figure 2F.

[0017] In other words, as shown in Figures 2A to 2C, when the resist film 16 is removed using a process gas containing carbon tetrafluoride gas (CF4) according to a conventional example, the resist film 16 is isotropically etched. As a result, before the formation of the sidewall (SW), a portion of the upper part of the polysilicon electrode 14 is also etched, and a tapered surface 14t is formed. In contrast, when the sidewall (SW) is formed, as shown in Figures 2D to 2F, the gate silicon oxide film 13 is etched, and a portion of the exposed area 10e of the semiconductor substrate 10, which is a Si substrate, is etched. Additionally, the resist film 33 is isotropically etched, causing the upper part of the sidewall (SW) to be etched and narrowed.

[0018] Figure 3 is a photograph of a longitudinal cross-section of a MOS field-effect transistor manufactured using a conventional method. As can be seen from the cross-sectional view of a transistor with gate width W / gate length L = 10 μm / 0.18 μm in Figure 3, it is evident that the removal of the resist by a process gas containing carbon tetrafluoride (CF4) affects the transistor shape.

[0019] The inventors have found that by using a fluorine-free gas such as carbon tetrafluoride (CF4) as the process gas in resist removal, and by using a wafer lifting device to lower the wafer temperature during the resist film removal process, the removal efficiency of the altered resist can be improved. Furthermore, by performing a water washing treatment after resist removal, it is possible to completely remove even resists that have been altered by high-concentration implantation without etching the silicon or silicon oxide on the sample surface.

[0020] Based on this finding, embodiments of the present invention have the following features, for example, in the resist removal process in a predetermined semiconductor process, such as 1.8V transistor formation. Specifically, in the resist removal process of 1.8V, 3.3V, and 5V transistor formation processes, the process gas used is composed of a fluorine-free gas such as carbon tetrafluoride (CF4), and a wafer lift-up mechanism is used in the resist film removal process to lower the wafer temperature and suppress the degradation of the resist, thereby improving the resist removal performance. Subsequently, by performing a water washing process, even resists modified by high-concentration implantation can be completely removed. Furthermore, by reducing etching damage during resist removal, it is possible to prevent over-etching of the sides of the polysilicon gate electrode and to leave the silicon oxide film on the source / drain region, thereby suppressing out-diffusion during thermal diffusion.

[0021] (Embodiment) FIGS. 1A to 1G are longitudinal sectional views showing a method for manufacturing a MOS type field effect transistor according to an embodiment. In the embodiment, referring to FIGS. 1A to 1G, a manufacturing process using a plasma gas for forming a 1.8V system semiconductor transistor will be described below.

[0022] In FIG. 1A, in a semiconductor substrate 10 such as a Si substrate, for example, at the central portions of the formation positions of each of a PMOS type field effect transistor (hereinafter referred to as a PMOSFET) and an NMOS type field effect transistor (hereinafter referred to as an NMOSFET), N-type impurity ions (for example, P or As and the dose amount is, for example, 2×10 12 ~1×10 13 ions / cm 2 ) and P-type impurity ions (for example, B or Ar and the dose amount is, for example, 1×10 13 ~5×10 13 ions / cm 2 ) are implanted to form an N-type well (NW) 11 and a P-type well (PW) 12. Next, after forming a gate oxide silicon film 13 and a polysilicon film on the semiconductor substrate 10, the N-type well 11, and the P-type well 12, polysilicon electrodes 14 and 15 are formed by a predetermined etching.

[0023] Next, in FIG. 1B, in order to form a lightly doped drain (LDD) structure, after covering the polysilicon electrode with a resist film 16, P-type impurity ions 17 (for example, B and BF2, or Ar and the dose amount is, for example, 1×10 15 ~5×10 15 ions / cm 2 ) are implanted into the N-type well 11, and N-type impurity ions 19 (for example, P and As and the dose amount is, for example, 1×10 15 ~5×10 15 ions / cm 2 ) are implanted into the P-type well 12. After the implantation, the resist film 16 is removed (twice with the NLDD layer 20 and the PLDD layer 18 respectively), and then the implanted impurity ions are thermally diffused to form the NLDD layer 20 and the PLDD layer 18 respectively.

[0024] Here, the removal of the resist film 16 is performed using the wafer lifting device shown in Figure 7. Figure 7 is a photograph showing a wafer lifting device with three support pins used in the manufacturing method of a MOS-type field-effect transistor according to the embodiment. As shown in Figure 7, the semiconductor substrate 10 is placed on the upper surface of the wafer lifting device shown in Figure 7, which has a heating device on its lower surface. The wafer is lifted up by a metallic three-point support pin structure (a structure in which the three support pins can move up and down in a direction perpendicular to the wafer surface (up and down direction)), thereby moving the wafer of the semiconductor substrate 10 away from the temperature control (heating) stage of the heating device and increasing the distance between the semiconductor substrate 10 and the heating device. This makes it possible to lower the wafer temperature in a shorter time than by lowering the temperature of the temperature control stage itself. Furthermore, by lifting down the wafer, the wafer of the semiconductor substrate 10 is brought closer to the temperature control (heating) stage, shortening the distance between the semiconductor substrate 10 and the heating device, allowing it to return to its original position and raising the original wafer temperature in a shorter time. Furthermore, in this embodiment, after the removal treatment of the resist film 16, any remaining resist film 16 is removed using a pure water scrub cleaning method (see Figure 9, described later).

[0025] Next, in Figure 1C, in order to form the P-structure and N-structure, the polysilicon electrodes 14 and 15 are covered with resist films 16A, respectively. Then, the PLDD layer 18 and the N-type well 11 contain P-type impurity ions 21 (for example, BF2 or Ar, with a dose of, for example, 1 × 10⁻¹⁶). 15 ~5×10 15 ions / cm 2 ) are injected, and N-type impurity ions 19 (for example, P with a dose of, for example, 1 × 10) are injected into the NLDD layer 20 and the P-type well 12. 15 ~5×10 15 ions / cm 2 The ions are injected. After the injection, the resist film 16A is removed (twice in total on both sides), and then the injected impurity ions are thermally diffused to form P-type diffusion layers 22,22 and N-type diffusion layers 24,24, respectively.

[0026] Here, the removal process of the resist film 16A is performed using the wafer lifting device shown in Figure 7, in the same manner as in Figure 1B.

[0027] Next, in Figure 1D, after forming a high-temperature silicon oxide (HTO) film 31 and a silicon nitride (SiN) film 32, sidewalls (SW) are formed on the sides of the polysilicon electrode 14 by etching. Furthermore, in Figure 1E, in order to form N+ and P+ structures, a resist film 33 is covered outside the regions of the polysilicon electrode 14, P-type well 12, N-type well 11, P-type diffusion layers 22, 22, and N-type diffusion layers 24, 24. Then, in the P-type diffusion layers 22, 22, P-type impurity ions 34 (for example, B with a dose of, for example, 1 × 10⁻¹⁶) are present, respectively. 15 ~5×10 15 ions / cm 2 ) are injected, and N-type impurity ions 37, 37 (for example, P, As, with a dose of, for example, 1 × 10) are injected into the N-type diffusion layers 24, 24 respectively. 15 ~5×10 15 ions / cm 2 ) is injected. After the injection, the resist film 33 is removed (twice in total on both sides), and then the injected impurity ions are thermally diffused, as shown in Figure 1F. (1) A PMOSFET having a gate electrode made of a polysilicon electrode 14, a source electrode made of a P-type diffusion layer 35, and a drain electrode made of a P-type diffusion layer 36, (2) An NMOSFET having a gate electrode made of a polysilicon electrode 14, a source electrode made of an N-type diffusion layer 38, and a drain electrode made of an N-type diffusion layer 39, A formation is created.

[0028] Here, the removal of the resist film 33 is performed using the wafer lifting device shown in Figure 7, in the same manner as in Figure 1B.

[0029] Furthermore, in Figure 1G, a dielectric substrate 40 is placed on the semiconductor substrate 10 at predetermined intervals, and electrodes 42, 52, 62, and 72 are formed, for example, side by side on the back surface of the dielectric substrate 40, while electrodes 44, 54, 64, and 74 are formed, for example, side by side on the front surface of the dielectric substrate 40. Here, electrode 42 is connected to electrode 44 via a connecting conductor 43, electrode 52 is connected to electrode 54 via a connecting conductor 53, electrode 62 is connected to electrode 64 via a connecting conductor 63, and electrode 72 is connected to electrode 74 via a connecting conductor 73.

[0030] In the PMOSFET on the semiconductor substrate 10, the source electrode, which is made of a P-type diffusion layer 35, is connected to electrode 42 via a connecting conductor 41, and the drain electrode, which is made of a P-type diffusion layer 36, is connected to electrode 52 via a connecting conductor 51. In the NMOSFET on the semiconductor substrate 10, the source electrode, which is made of an N-type diffusion layer 38, is connected to electrode 62 via a connecting conductor 61, and the drain electrode, which is made of an N-type diffusion layer 39, is connected to electrode 72 via a connecting conductor 71.

[0031] In the gate formation process described above, there are a total of six steps to remove the implanted resist films 16, 16A, and 33. The resist films 16, 16A, and 33 are modified by the implantation of impurity ions. In particular, modification by impurity ions such as BF2 is significant, and in conventional examples, the ability to remove the resist was improved by using a process gas to which carbon tetrafluoride gas (CF4) was added. In contrast, in this embodiment, by using a process gas to which carbon tetrafluoride gas (CF4) is not added, the following effects are obtained. [Examples]

[0032] Below, a prototype MOSFET manufactured according to the above-described manufacturing process is shown as an example.

[0033] Figure 3 is a photograph of a longitudinal cross-section of a MOS field-effect transistor when using a conventional method for manufacturing a MOS field-effect transistor. Figure 4 is a photograph of a longitudinal cross-section of a MOS field-effect transistor when using a method for manufacturing a MOS field-effect transistor according to the embodiment.

[0034] By comparing the cross-sectional view in Figure 3 relating to a conventional example with the cross-sectional view in Figure 4 relating to the embodiment, it can be seen that in the embodiment, the transistor shape is improved compared to the conventional example, as seen in the cross-sectional view of a transistor with gate width W / gate length L = 10 μm / 0.18 μm. Specifically, in the embodiment of Figure 4, compared to the cross-sectional shape of the transistor produced by the conventional process in Figure 3, the taper of the polysilicon electrode is smaller, the sidewall (SW) width is thicker, and the recess in the semiconductor substrate is eliminated.

[0035] Figure 5 is a graph showing the drain voltage versus drain current characteristics, illustrating the improvement in the electrical characteristics of a MOS-type field-effect transistor when using the manufacturing method of the MOS-type field-effect transistor according to the embodiment.

[0036] As is clear from the transistor cross-sectional shape shown in Figure 4, the reduced taper of the sidewall (SW) increases the effective gate length of the MOSFET, which affects the saturation drain current Idsat. As shown in Figure 5, this improves the RonA characteristic (the drain current characteristic with respect to the drain voltage when the MOSFET is ON), and significantly increases the drain current.

[0037] Furthermore, by increasing the width of the sidewall (SW), the N-type diffusion layer in the N- region directly beneath the sidewall (SW) can be covered when N-type impurity ions (N+) are implanted, thereby improving breakdown voltage and reliability. In addition, by eliminating erosion in the semiconductor substrate, the occurrence of Si defects, which can become sources of leakage, can be suppressed. As a result, as can be seen from the Id-Vd characteristics of a transistor with gate width W / gate length L = 10 μm / 0.18 μm (Figure 5), the RonA characteristics are significantly improved in this embodiment.

[0038] The on-time resistance Ron of transistors fabricated using a process gas containing carbon tetrafluoride (CF4) according to a conventional example and a process gas according to this embodiment is 119.5Ω and 82.7Ω, respectively, when Vg = 1.8V and Vd = 0.1V. This embodiment achieves a reduction of approximately 31%.

[0039] Figure 6A is a graph showing the reduction in silicon oxide (OX) and silicon nitride (SiN) film thickness due to the resist film removal process in a conventional method for manufacturing a MOS-type field-effect transistor. Figure 6B is a table showing the reduction in silicon oxide (OX) and silicon nitride (SiN) film thickness due to the resist film removal process in a conventional method for manufacturing a MOS-type field-effect transistor.

[0040] As is clear from Figures 6A and 6B, increasing the processing time using the (O2+CF4) process gas from 15 seconds to 36 seconds increases the film thickness reduction of the silicon oxide (OX) film from 0.9 Å to 14.2 Å on average in the plane. This is because CF4 gas generates fluorine radicals in the plasma (CF4+e-→CF3+F), which react with silicon (Si+4F→SiF4), thus etching semiconductor substrates, such as Si substrates.

[0041] Furthermore, the film thickness of the silicon nitride (SiN) film increases from 3.5 Å to 11.7 Å on average in the plane. This is because the silicon nitride (SiN) film is etched by the reaction of Si and F due to the addition of carbon tetrafluoroethylene (CF4) gas (SiN + CF4). X ++H+→SiF X ↑+NH X ↑+HCN↑+NH X F↑). Furthermore, with oxygen gas (O2) alone, neither silicon oxide film (OX) nor silicon nitride film (SiN) showed any film loss even after 210 seconds of treatment.

[0042] Figure 8A is a graph showing the amount of resist film reduction during lift-up when using the wafer lift-up device shown in Figure 7. Figure 8B is a table showing the amount of resist film reduction during lift-up when using the wafer lift-up device shown in Figure 7. In other words, Figures 8A and 8B illustrate the dependence of the resist film reduction during wafer lift-up on processing time.

[0043] As shown in Figures 8A and 8B, when the wafer was processed for 10 seconds and 30 seconds using a wafer lifting device with a process gas consisting only of O2, the average reduction in the resist film was 412.0 Å and 571.3 Å, respectively. From these results, a linear approximation can be performed using the following equation (1).

[0044] Film reduction amount y=8.0×time x (seconds)+332.3 (1)

[0045] For 60 seconds, the calculation is y = 8 × 60 + 332.3 = 812.3 Å / min.

[0046] Furthermore, when using a wafer lifting device to pin down the wafer, the amount of resist film reduction is approximately 65,000 Å per minute, and the etching rate decreases significantly to approximately 0.4% by lifting the wafer up. In addition, by setting the wafer lift-up time according to the degree of resist modification, it becomes possible to remove the resist layer that has been altered (hardened) by ion implantation or other methods and is difficult to remove.

[0047] Figure 9A is a plan view photograph before water washing, showing the effect of water washing after resist removal when using the manufacturing method of a MOS-type field-effect transistor according to the embodiment. Figure 9B is a plan view photograph after water washing, showing the effect of water washing after resist removal when using the manufacturing method of a MOS-type field-effect transistor according to the embodiment. In other words, Figures 9A and 9B are diagrams illustrating the effect of water washing after resist film removal.

[0048] As shown in Figure 9A, after removing the resist with O2 gas alone, some compounds of impurities from ion implantation and the resist remain. Subsequently, as shown in Figure 9B, these compounds can be easily removed by simply washing with water, without the use of ozone plasma treatment or chemicals.

[0049] As described above, according to this embodiment, the driving capability of transistor characteristics such as 1.8V, 3.3V, and 5V systems can be improved in a predetermined semiconductor process. Specifically, for example, in the formation of 1.8V, 3.3V, and 5V transistors, the process gas used during resist removal is composed of a fluorine-free gas such as carbon tetrafluoroethylene (CF4), and by using a wafer lift-up mechanism or the like during the resist film removal process to lower the wafer temperature, the removal efficiency of the altered resist is improved. Subsequently, by performing a water washing process, etching damage other than resist removal is reduced, the silicon oxide film on the source / drain region can be left, out-diffusion during heat treatment can be suppressed, and even resist altered by high-concentration injection can be completely removed.

[0050] (Summary of the embodiments and their effects) A method for manufacturing a semiconductor device for a MOSFET, according to embodiments of the present invention, is: In a method for manufacturing a semiconductor device that removes a resist film using plasma gas, A process to remove a resist film in which impurity ions have been implanted, using only an oxygen-based plasma gas and no fluorine-based gases, In the resist film removal process, a wafer lifting device is used to increase the distance between the semiconductor device and the heating device, thereby lowering the wafer temperature of the semiconductor device and increasing the amount of altered resist removed. A step of removing the remaining resist film using a pure water scrubbing method, It is characterized by including.

[0051] This improves the removal of altered resists. Furthermore, it allows for the complete removal of resists altered by high-concentration injection without etching the silicon or silicon oxide on the sample surface.

[0052] Furthermore, in the method for manufacturing the semiconductor device, the resist film removal process includes removing the resist film such that an oxide film containing silicon remains on the source or drain region. This makes it possible to suppress out-diffusion during thermal diffusion after implantation of impurity ions into the NLDD layer, PLDD layer, N-structured N-type diffusion layer, and P-structured P-type diffusion layer regions.

[0053] Furthermore, in the method for manufacturing the semiconductor device, the plasma gas containing the oxygen-based gas contains only the oxygen-based gas and the nitrogen-based gas. By creating a plasma of only oxygen and nitrogen elements without including other elements, unwanted reaction products can be eliminated and residue generation can be suppressed.

[0054] Furthermore, in the method for manufacturing the semiconductor device, the step of removing the remaining resist film using the pure water scrub cleaning method includes removing the resist film using pure water to which CO2 has been added. This suppresses static charge buildup during cleaning by the pure water scrub cleaning method and prevents electrostatic discharge damage to the transistor.

[0055] Furthermore, in the method for manufacturing the semiconductor device, the impurity ions include BF2, P, B, As, or Ar. This ensures that the types of impurity ions are necessary for transistor formation and modify the resist film, thereby further improving the effectiveness of this embodiment.

[0056] Furthermore, in the method for manufacturing the semiconductor device, the step of increasing the distance between the semiconductor device and the heating device using a wafer lifting device is performed by first using the wafer lifting device to lower the wafer temperature of the semiconductor device, removing the resist using a plasma containing the oxygen-based gas, and then using the wafer lifting device to lift down, thereby shortening the distance between the semiconductor device and the heating device, raising the wafer temperature of the semiconductor device, and removing the resist film using the plasma. This allows for a decrease in the etching rate of the resist and a longer processing time when the wafer surface temperature is lowered by lifting up, and then a reduction in processing time when the wafer surface temperature is raised by lifting down, thereby increasing the etching rate and optimizing the processing time and resist removal efficiency according to the degree of resist modification.

[0057] Furthermore, in the method for manufacturing the semiconductor device, the semiconductor device is, for example, a MOS-type field-effect transistor. The preferred manufacturing conditions are as follows. The processing time when the wafer is lifted using the wafer lifting device is 120 seconds. The processing time in the lifted-down state is 90 seconds. The microwave power of the plasma generator that generates the aforementioned plasma gas is 840W. The stage temperature of the heating device is 250°C. The gas flow rate of the plasma gas containing the aforementioned oxygen-based gas is 3750 sccm. The pressure inside the processing chamber of the semiconductor device manufacturing apparatus is 1.1 Torr.

[0058] This makes it possible to obtain a good shape for the MOS field-effect transistor.

[0059] (Differences from Patent Document 1) Patent Document 1 discloses a manufacturing method characterized by comprising the steps of: plasma-forming a gas for removing the resist from the sample surface and a gas that promotes resist removal and can etch the sample under reduced pressure, for the purpose of removing only the resist without etching the silicon or silicon oxide on the sample surface; removing the resist with the gas plasma; and stopping the plasma formation of the gas for promoting resist removal at or immediately before the end of resist removal and performing over-etching with the gas plasma of the gas for resist removal.

[0060] This embodiment is indeed similar in that it removes only the resist without etching the silicon or silicon oxide on the sample surface. However, it does not resolve the problem of residue from the modified resist film generated by the high-concentration injection described above.

[0061] (Differences from Patent Document 2) Patent Document 2 discloses a manufacturing method characterized by a step of treating resist residue with oxygen plasma using the resist as a mask, for the purpose of optimally removing resist residue without adversely affecting the underlying layer of the resist pattern, and after the oxygen plasma treatment, treating silicon oxide and resist with diluted hydrofluoric acid, and then ion implanting impurities into a semiconductor substrate through silicon oxide using the resist as a mask.

[0062] This embodiment is indeed similar in that it involves irradiating a resist with a plasma of fluorine-free oxygen-based gas, followed by the removal of the resist residue by wet treatment. However, because diluted hydrofluoric acid is used for the wet treatment, the problem of silicon oxide etching remains unresolved. [Industrial applicability]

[0063] As described in detail above, the method for manufacturing a semiconductor device according to one aspect of the present invention can improve the removeability of altered resist. Furthermore, even resist altered by high-concentration injection can be completely removed without etching the silicon or silicon oxide on the sample surface. [Explanation of Symbols]

[0064] 10 Semiconductor substrates 11 N-type wells 12 P-type wells 13 Gate silicon oxide film 14,15 Polysilicon electrodes 16,16A resist film 17 P-type impurity ions 19 N-type impurity ions 18 PLDD layers 20 NLDD layers 21 P-type impurity ions 22 P-type diffusion layer 23 N-type impurity ions 24 N-type diffusion layer 31. High-temperature silicon oxide film (HTO) 32 Silicon Nitride Film 33 Resist film 34 P-type impurity ions 35,36 P-type diffusion layer 37 N-type impurity ions 38,39 N-type diffusion layer 40 Dielectric substrate 41, 51, 61, 71 Connecting conductors 42,52,62,72 electrode 43, 53, 63, 73 Connecting conductors 44,54,64,74 electrode

Claims

1. A method for manufacturing a semiconductor device in which silicon and silicon oxide are included on the sample surface, wherein a resist film is removed using a plasma gas, A process to remove a resist film in which impurity ions have been implanted, using only an oxygen-based plasma gas and no fluorine-based gases, In order to remove the resist film altered by the injection of the oxygen-based gas without etching the silicon or silicon oxide, the resist film removal process includes a step of increasing the amount of altered resist removed by increasing the distance between the semiconductor device and the heating device using a wafer lifting device, thereby lowering the wafer temperature of the semiconductor device and improving the removeability of the altered resist. A step of removing the remaining resist film using a pure water scrubbing method, A method for manufacturing a semiconductor device, including semiconductor devices.

2. The resist film removal process includes removing the resist film such that an oxide film containing silicon remains on the source or drain region. A method for manufacturing a semiconductor device according to claim 1.

3. The plasma gas containing the aforementioned oxygen-based gas contains only oxygen-based gas and nitrogen-based gas. A method for manufacturing a semiconductor device according to claim 1.

4. The step of removing the remaining resist film using the pure water scrubbing method is as follows: CO 2 This includes removing the resist film using pure water to which the additive has been added. A method for manufacturing a semiconductor device according to claim 1.

5. The aforementioned impurity ions are BF 2 , including P, B, As, or Ar A method for manufacturing a semiconductor device according to claim 1.

6. The step of using a wafer lifting device to increase the distance between the semiconductor device and the heating device is: Using the wafer lifting device, the wafer temperature of the semiconductor device is lowered, and the resist is removed using the plasma containing the oxygen-based gas. Then, the wafer lifting device is used to lift the wafer down, thereby shortening the distance between the semiconductor device and the heating device, and the wafer temperature of the semiconductor device is raised, and the resist film is removed using the plasma. The method for manufacturing a semiconductor device according to claim 3.

7. The semiconductor device is a MOS-type field-effect transistor. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. The semiconductor device is a MOS-type field-effect transistor, The processing time when the wafer is lifted using the wafer lifting device is 120 seconds. The processing time in the lifted-down state is 90 seconds. The microwave power of the plasma generator that generates the aforementioned plasma gas is 840 W. The stage temperature of the heating device is 250°C. The gas flow rate of the plasma gas containing the aforementioned oxygen-based gas is 3750 sccm. The pressure inside the processing chamber of the semiconductor device manufacturing apparatus is 1.1 Torr. A method for manufacturing a semiconductor device according to claim 6.

Images