Power circuit

Abstract

To prevent backflow between the input and output terminals of the switch circuit.SOLUTION: A power supply circuit of the embodiment includes: a first transistor having a source connected to an input terminal and a gate to which a first control voltage is supplied from a first node; a second transistor having a drain connected to a drain of the first transistor, a source connected to an output terminal, and a gate to which a second control voltage is supplied; a comparator which receives at a first input terminal a voltage supplied to the input terminal, receives at a second input terminal a voltage appearing at a second node which is a connection point between the drains of the first and second transistors, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result; and a diode connected between the first input terminal and the second input terminal of the comparator.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a power supply circuit.

Background Art

[0002] A power supply circuit inserts a switch circuit in a power supply line in order to prevent an internal circuit from being damaged when the power supply and the ground are reversely connected.

[0003] However, there is a problem that a reverse current may occur when the voltage at the output terminal of the switch circuit becomes higher than the input terminal voltage during the ON operation of the switch circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An embodiment aims to provide a power supply circuit capable of preventing a reverse current between the input and output terminals of a switch circuit.

Means for Solving the Problems

[0006] The power supply circuit of the embodiment includes a first transistor whose source is connected to an input terminal and whose gate is supplied with a first control voltage from a first node; a second transistor whose drain is connected to the drain of the first transistor, whose source is connected to an output terminal and whose gate is supplied with a second control voltage; a comparator which applies the voltage supplied to the input terminal to a first input terminal, applies the voltage appearing at a second node which is the connection point between the drains of the first and second transistors to a second input terminal, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result; and a diode connected between the first input terminal and the second input terminal of the comparator. A third transistor controls conduction and non-conductivity between the second node and the second input terminal of the comparator, and a fifth transistor whose drain is connected to the first node, whose source is connected to a reference potential point, and whose gate is supplied with the output of the comparator. Equipped with The voltage output from the cathode of the diode is input to the first input terminal of the comparator, and the voltage input to the anode of the diode is input to the second input terminal of the comparator. . [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing a power supply circuit according to the first embodiment of the present invention. [Figure 2] This is an explanatory diagram for describing the backflow prevention mechanism. [Figure 3] This is an explanatory diagram illustrating protection against negative voltage. [Figure 4] This is a circuit diagram showing a second embodiment of the present invention. [Figure 5] This is a circuit diagram illustrating the operation of the second embodiment. [Figure 6] This is a circuit diagram showing a modified example. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings.

[0009] (First Embodiment) Figure 1 is a circuit diagram showing a power supply circuit according to a first embodiment of the present invention. This embodiment includes a protection circuit to prevent reverse current flow between the input and output terminals of the switch circuit. Furthermore, in this embodiment, it is also possible to prevent the protection circuit from being destroyed when the input voltage becomes negative.

[0010] As shown in Figure 1, the power supply circuit 1 has NMOS transistors M1 and M2 that constitute a switch circuit between an input terminal 11 to which an input voltage VIN is supplied from an external source, and an output terminal 12 to which an output voltage VOUT is output to an external load circuit (not shown). The switch circuit is composed of two transistors M1 and M2 to prevent current from flowing when the transistors are off by the body diodes (parasitic diodes) of the transistors.

[0011] Furthermore, the power supply circuit 1 includes PMOS transistors M3 and M5, NMOS transistors M4 and M6, resistors R1, R2, and R3, diode D1, comparator CMP, current source I1, and ESD (Electro-Static Discharge) element I2.

[0012] Transistor M1 has its source connected to input terminal 11 and its drain connected to the drain of transistor M2. Transistor M2 has its source connected to output terminal 12 and its drain connected to the drain of transistor M1. The gates of transistors M1 and M2 are supplied with a first control voltage, VGATE1, and a second control voltage, VGATE2, respectively, from a gate controller (not shown).

[0013] The gate controller can apply a voltage to the gates of transistors M1 and M2 to conduct the switch circuit when the voltage VOUT is output. The gate controller can also apply a voltage to the gates of transistors M1 and M2 to deconduct the switch circuit when the voltage VOUT is stopped. For example, if the voltage VIN is 80V, the gate controller will conduct the switch circuit by applying 85V as voltages VGATE1 and VGATE2 to the gates of transistors M1 and M2. Alternatively, to deconduct the switch circuit, the gate controller may apply a voltage of 80V VGATE1 to the gate of transistor M1 and a voltage of 0V VGATE2 to the gate of transistor M2.

[0014] A resistor R1 is connected between the gate of transistor M1 (hereinafter referred to as node N1) and the input terminal 11.

[0015] Between node N1 and the reference potential point VSS, the current paths of transistors M3 and M4 are connected in series. The source of transistor M3 is connected to node N1, the drain is connected to the drain of M4, and the gate is supplied with voltage VIN. Also, the source of transistor M4 is connected to the reference potential point VSS, and the gate is supplied with the output of comparator CMP.

[0016] The common drain of transistors M1 and M2 (hereinafter referred to as node N2) is connected to the positive input terminal + of comparator CMP via the current path of transistor M5. Transistor M5 has its source connected to node N2, its drain connected to the positive input terminal + of comparator CMP, and its gate connected to node N2 via resistor R3.

[0017] The negative input terminal - of comparator CMP is connected to input terminal 11 via resistor R2. The anode of diode D1 is connected to the positive input terminal + of comparator CMP, and the cathode of diode D1 is connected to the negative input terminal - of comparator CMP. Note that a resistor may be connected between the positive input terminal + and the negative input terminal - of comparator CMP instead of diode D1.

[0018] The gate of transistor M5 is connected to the reference potential point VSS via the current path of transistor M6 and current source I1. Transistor M6 has its drain connected to the gate of transistor M5, its source connected to current source I1, and its gate supplied with power supply voltage VDD.

[0019] An ESD element I2, which is an electrostatic protection element, is connected between input terminal 11 and the reference potential point VSS. The ESD element I2 has a function of protecting the element from transient overvoltage due to static electricity.

[0020] Next, the operation of the embodiment configured as described above will be described with reference to FIGS. 2 and 3. FIG. 2 is an explanatory diagram for explaining the backflow prevention operation, and FIG. 3 is an explanatory diagram for explaining the protection against negative voltage. FIGS. 2 and 3 show examples of the voltages of each part.

[0021] (Backflow prevention) First, referring to FIG. 2, the backflow prevention operation will be described. Now, assume that the voltage VIN is 80V, and the gate controller has set the voltages VGATE1 and VGATE2 to 85V. In this case, the transistors M1 and M2 are on, and during normal operation, the 80V voltage VIN supplied to the input terminal 11 is supplied to the load from the output terminal 12 through the switch circuit formed by the transistors M1 and M2.

[0022] Here, assume that the voltage of the output terminal 12 rises to 81V. Then, since the channels of the transistors M1 and M2 are conducting, as shown by the arrows in FIG. 2, a backflow will occur from the output terminal 12 to the input terminal 11. As a result, the voltage of the node N2 (hereinafter referred to as voltage MID) also rises to 81V. Also, during normal operation when a positive voltage is supplied to the input terminal 11, a voltage VDD (for example, 5V) is applied to the gate of the transistor M6. Therefore, the transistor M6 is on, and a current flows from the node N2 to the reference potential point VSS through the resistor R3. This current becomes a constant current (for example, 1 μA) by the current source I1. Note that since the source of the transistor M6 is lower than the voltage VDD (5V), it has a function of preventing breakdown of the transistors constituting the current source I1.

[0023] When a current flows through the resistor R3, the transistor M5 turns on because the gate voltage becomes lower than the source voltage. As a result, the voltage MID is applied to the positive input terminal of the comparator CMP via the transistor M5. On the other hand, the voltage VIN is applied to the negative input terminal - of the comparator CMP from the input terminal 11 through the resistor R2.

[0024] Since voltage VIN is 80V and voltage MID is 81V, the output of comparator CMP is high level (hereinafter referred to as H level). The H level output of comparator CMP is supplied to the gate of transistor M4, and transistor M4 turns on. Transistor M3 is on when voltage VIN is applied to its gate and node N1 is 85V. Therefore, when transistor M4 turns on, current flows to the reference potential point VSS via the current path of transistors M3 and M4, as shown by the arrow, and the voltage at node N1 is lowered.

[0025] When the voltage at node N1 drops to approximately 80V, transistor M3 turns off, maintaining the voltage at node N1 at approximately 80V. That is, when the voltage VGATE1 becomes 80V, transistor M1 turns off. By switching transistor M1 from on to off, reverse current from output terminal 12 to input terminal 11 is prevented. By providing transistor M3, the voltage at node N1 does not become too low, and it is possible to prevent excessive voltage from being applied to the gate of transistor M1 and damaging it.

[0026] In this embodiment, the reverse current prevention protection circuit enclosed by the dashed line prevents reverse current from occurring from the output terminal 12 to the input terminal 11.

[0027] However, for some reason, a negative voltage may be applied to the input terminal 11. In this case, the difference between the voltage MID applied to the positive input terminal + of the comparator CMP and the voltage VIN applied to the negative input terminal - becomes large, and there is a risk that the comparator CMP may be destroyed. Therefore, in this embodiment, a function is provided to prevent the destruction of the comparator CMP, which constitutes the reverse current prevention protection circuit.

[0028] (Comparator protection circuit) Refer to Figure 3 to explain the operation of comparator protection.

[0029] Let's assume that voltage VIN is 0V, and voltages VOUT and MID are also 0V. Now, let's assume that the voltage VIN at input terminal 11 becomes negative, for example, voltage VIN becomes -60V. In this case, an inrush current will try to flow between input terminal 11 and output terminal 12. If an inrush current were to flow, there is a risk that transistors M1 and M2 would be destroyed. In this embodiment, a resistor R1 is provided between input terminal 11 and node N1. When voltage VIN becomes -60V, current flows from the gate of transistor M1 through resistor R1, and voltage VGATE1 also drops to approximately -60V. As a result, transistor M1 turns off, and voltages VOUT and MID remain approximately 0V. In this way, an inrush current between input terminal 11 and output terminal 12 can be prevented, and the destruction of transistors M1 and M2 can be prevented.

[0030] In the explanation of reverse current prevention described above, the voltage at node N2 and the voltage at input terminal 11 were applied to the positive polarity input terminal + and the negative polarity input terminal - of comparator CMP, respectively. When input terminal 11 has a negative voltage, transistor M1 is off, so node N2 and output terminal 12 are approximately 0V, and comparator CMP is supplied with a voltage of 0V MID and a voltage of -60V VIN. When such a relatively large voltage difference is supplied to comparator CMP, there is a risk that comparator CMP may be destroyed. Therefore, in this embodiment, a negative voltage protection circuit enclosed by a dashed line is provided.

[0031] An ESD element I2 is provided between the input terminal 11 and the reference potential point VSS. When the voltage VIN changes from 0V to -60V, the reference potential point VSS also changes from 0V to -60V due to the ESD element I2. As a result, the gate voltage of transistor M6 drops from 0V to -60V due to the influence of the reference potential point VSS, and transistor M6 turns off. Consequently, no current flows through resistor R3. Transistor M5 turns off when its gate voltage and source voltage become approximately 0V.

[0032] This results in a non-conducting current path between the positive input terminal + of comparator CMP and node N2. The positive input terminal + and negative input terminal - of comparator CMP are connected by diode D1, and the positive input terminal + of comparator CMP changes to match the voltage (-60V) of the negative input terminal -. Thus, excessive input is prevented from being applied to comparator CMP, and the comparator CMP is prevented from being destroyed. Thus, in this embodiment, in the event of an abnormal situation where a negative voltage is supplied to the input terminal 11, the conduction between node N2 and the positive input terminal + of comparator CMP is interrupted by transistor M5, and the voltages at the positive input terminal + and the negative input terminal - of comparator CMP are matched by diode D1, thereby preventing the comparator CMP from being destroyed.

[0033] (Second embodiment) Figure 4 is a circuit diagram showing a second embodiment of the present invention. In Figure 4, components identical to those in Figure 1 are denoted by the same reference numerals and their descriptions are omitted. This embodiment shows a specific example of the configuration of a comparator CMP.

[0034] In Figure 4, the comparator CMP is composed of PMOS transistors M11 and M12, NMOS transistors M13 to M15, and current sources I3 to I5. Transistor M15 is a thin-film transistor. The connection point between resistor R2 and the cathode of diode D1 (hereinafter referred to as node N3) is connected to the reference potential point VSS via the current path of transistor M11, the current path of transistor M13, and the current source I3. Transistor M11 has its source connected to node N3, its drain connected to the drain of transistor M13, and its gate connected to the gate of transistor M12. Transistor M13 has its source connected to the current source I3, and its gate is supplied with voltage VDD.

[0035] The connection point between the drain of transistor M5 and the anode of diode D1 (hereinafter referred to as node N4) is connected to the reference potential point VSS via the current path of transistor M12, the current path of transistor M14, and the current source I4. Transistor M12 has its source connected to node N4, its gate connected to the gate of transistor M11, and its drain connected to the drain of transistor M14 and the gate of transistor M11. Transistor M14 has its source connected to the reference potential point VSS, and its gate is supplied with voltage VDD.

[0036] The current path of current source I5 and transistor M15 is connected between the power line supplying voltage VDD and the reference potential point VSS. Transistor M15 has its drain connected to the gates of current source I5 and transistor M4, its source connected to the reference potential point VSS, and its gate connected to the source of transistor M13.

[0037] Furthermore, transistor M13 has the same voltage breakdown violation prevention function as transistor M6, that is, a function to prevent voltage breakdown violations of the transistors constituting current source I3. Similarly, transistor M14 has a function to prevent voltage breakdown violations of the transistors constituting current source I4.

[0038] Next, the operation of the embodiment configured in this way will be described with reference to Figure 5. Figure 5 shows an example of the voltages at each part when the input terminal 11 is 80V and the output terminal 12 is 81V, and reverse current is about to occur.

[0039] First, we will explain the operation of the comparator CMP during normal operation, that is, when input terminal 11 is 80V and 80V is supplied to the load from output terminal 12. Transistors M1 and M2 are turned on when 85V is applied to their gates from the gate controller. In this case, as mentioned above, node N2 is 80V. Transistor M5 is turned on, and node N4 is 80V. Strictly speaking, the voltage at node N4 is slightly lower than 80V. On the other hand, the voltage at node N3 is 80V.

[0040] The gates of transistors M11 and M12 are common, and the gate-source voltage of transistor M11 is greater than the gate-source voltage of transistor M12. Therefore, the current flowing through the current path of transistor M13 is greater than the current flowing through the current path of transistor M14. Assuming that the currents from current sources I3 and I4 are the same, a portion of the current flowing from the source of transistor M13 flows to the gate of transistor M15, so M15 is on. Transistor M4 is off, and a voltage of 85V VGATE1 is applied to the gate of transistor M1 from the gate controller, keeping transistor M1 on.

[0041] Next, let's assume that output terminal 12 reaches 81V and a reverse current is about to occur. Transistor M1 is on, and node N2 changes from 80V to 81V. Transistor M5 is on, and node N4 also reaches 81V. On the other hand, the voltage at node N3 is 80V. Therefore, for example, if the common gate voltage of transistors M11 and M12 is 79V, the gate-source voltage of transistor M11 will be 1V, and the gate-source voltage of transistor M12 will be 2V. That is, the gate-source voltage of transistor M11 will be smaller than the gate-source voltage of transistor M12, and the current flowing through the current path of transistor M14 will be larger than the current flowing through the current path of transistor M13.

[0042] For example, if both current sources I3 and I4 have a current of 10 μA, then the current flowing through the current path of transistor M14 will be 10 μA, and the current flowing through the current path of transistor M13 will be less than 10 μA (e.g., 5 μA). As a result, current flows from the gate of transistor M15 to the reference potential point VSS, and transistor M15 turns off. This causes the gate of transistor M4 to reach a high level, and transistor M4 turns on. As a result, as described above, node N1 drops to 80 V, and transistor M1 turns off. In this way, reverse current is prevented.

[0043] Thus, in this embodiment, the same effects as in the first embodiment can be obtained.

[0044] (modified version) Figure 6 is a circuit diagram showing a modified example. In Figure 6, components identical to those in Figure 1 are given the same reference numerals and their descriptions are omitted.

[0045] This modified version differs from Figure 1 in that the source of transistor M5 is connected to output terminal 12, and the voltage VOUT is supplied to the source of transistor M5 instead of the MID voltage. Since the voltages VOUT and MID are approximately the same, the operation of this modified version is the same as in Figure 1. Note that if the voltage VOUT rises higher than the voltage VIN, the voltage change of voltage VOUT is slightly faster than the voltage change of MID voltage, so it is conceivable that the transistor M1 can be turned off slightly earlier in this modified version than in the example in Figure 1.

[0046] Thus, in this modified example, the same effects as in the first embodiment can be obtained, and backflow prevention can be performed at a faster speed.

[0047] The present invention is not limited to the embodiments described above, and can be modified in various ways during implementation without departing from its essence. Furthermore, the embodiments described above include inventions at various stages, and various inventions can be extracted by appropriate combinations of the multiple constituent elements disclosed. For example, if some constituent elements are deleted from all the constituent elements shown in the embodiments, and the problem described in the section on the problem the invention aims to solve is solved and the effect described in the section on the effect of the invention is obtained, then the configuration with these constituent elements deleted can be extracted as an invention. [Explanation of Symbols]

[0048] 1...Power supply circuit, 11...Input terminal, 12...Output terminal, CMP...Comparator, D1...Diode, I1~I5...Current source, I2...ESD element, M1~M6, M11~M15...Transistor, N1~N4...Node, R1~R3...Resistor.

Claims

1. A first transistor whose source is connected to the input terminal and whose gate is supplied with a first control voltage from a first node, A second transistor whose drain is connected to the drain of the first transistor, whose source is connected to the output terminal, and whose gate is supplied with a second control voltage, A comparator that applies the voltage supplied to the input terminal to the first input terminal, applies the voltage appearing at the second node which is the connection point between the drains of the first and second transistors to the second input terminal, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result, A diode connected between the first input terminal and the second input terminal of the comparator, A third transistor controls the conduction and non-conduction between the second node and the second input terminal of the comparator, A fifth transistor, whose drain is connected to the first node, whose source is connected to a reference potential point, and whose gate is supplied with the output of the comparator, It is equipped with, A power supply circuit in which the voltage output from the cathode of the diode is input to the first input terminal of the comparator, and the voltage input to the anode of the diode is input to the second input terminal of the comparator.

2. A first transistor whose source is connected to the input terminal and whose gate is supplied with a first control voltage from a first node, A second transistor whose drain is connected to the drain of the first transistor, whose source is connected to the output terminal, and whose gate is supplied with a second control voltage, A comparator that applies the voltage supplied to the input terminal to the first input terminal, applies the voltage appearing at the second node which is the connection point between the drains of the first and second transistors to the second input terminal, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result, A diode connected between the first input terminal and the second input terminal of the comparator, A third transistor controls the conduction and non-conduction between the second node and the second input terminal of the comparator, A fifth transistor, whose drain is connected to the first node, whose source is connected to a reference potential point, and whose gate is supplied with the output of the comparator, It is equipped with, A power supply circuit in which the cathode of the diode is connected to the first input terminal of the comparator, and the anode of the diode is connected to the second input terminal of the comparator.

3. A fourth transistor whose drain is connected to the drain of the fifth transistor, whose source is connected to the first node, and whose gate is supplied with the voltage supplied to the input terminal, It further comprises, The power supply circuit according to claim 1 or 2, wherein the fifth transistor is connected to the first node via the fourth transistor.

4. A resistor connected between the input terminal and the first node, A sixth transistor whose drain is connected to the gate of the third transistor, whose source is connected to the reference potential point via a first current source, and whose gate is supplied with a power supply voltage, A resistor connected between the second node and the gate of the third transistor, An electrostatic protection element connected between the input terminal and the reference potential point, The power supply circuit according to claim 3, further comprising the above.

5. The aforementioned comparator, A seventh transistor whose source is connected to the first input terminal and whose drain is connected to the reference potential point via a second current source, An eighth transistor whose source is connected to the second input terminal, whose gate is connected to the gate of the seventh transistor, and whose drain is connected to the reference potential point via a third current source and also to the gate of the seventh transistor, A ninth transistor whose drain is connected to the power line supplying the power supply voltage and the gate of the fifth transistor, whose source is connected to the reference potential point and whose gate is connected to the source of the seventh transistor, The power supply circuit according to claim 4, further comprising the above.

6. The voltage appearing at the output terminal is applied to the second input terminal of the comparator, instead of the voltage at the second node. The power supply circuit according to claim 1 or 2.

7. A first transistor whose source is connected to the input terminal and whose gate is supplied with a first control voltage from a first node, A second transistor whose drain is connected to the drain of the first transistor, whose source is connected to the output terminal, and whose gate is supplied with a second control voltage, A comparator that applies the voltage supplied to the input terminal to the first input terminal, applies the voltage appearing at the second node which is the connection point between the drains of the first and second transistors to the second input terminal, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result, A diode connected between the first input terminal and the second input terminal of the comparator, A third transistor controls the conduction and non-conduction between the second node and the second input terminal of the comparator, A fourth transistor is connected to the first node as a source, and the gate is supplied with the voltage supplied to the input terminal, A fifth transistor whose drain is connected to the drain of the fourth transistor, whose source is connected to a reference potential point, and whose gate is supplied with the output of the comparator, It is equipped with, A power supply circuit in which the voltage output from the cathode of the diode is input to the first input terminal of the comparator, and the voltage input to the anode of the diode is input to the second input terminal of the comparator.

8. A first transistor whose source is connected to the input terminal and whose gate is supplied with a first control voltage from a first node, A second transistor whose drain is connected to the drain of the first transistor, whose source is connected to the output terminal, and whose gate is supplied with a second control voltage, A comparator that applies the voltage supplied to the input terminal to the first input terminal, applies the voltage appearing at the second node which is the connection point between the drains of the first and second transistors to the second input terminal, compares the voltages at the first input terminal and the second input terminal, and controls the first control voltage supplied to the first node based on the comparison result, A diode connected between the first input terminal and the second input terminal of the comparator, A third transistor controls the conduction and non-conduction between the second node and the second input terminal of the comparator, A fourth transistor is connected to the first node as a source, and the gate is supplied with the voltage supplied to the input terminal, A fifth transistor whose drain is connected to the drain of the fourth transistor, whose source is connected to a reference potential point, and whose gate is supplied with the output of the comparator, It is equipped with, A power supply circuit in which the cathode of the diode is connected to the first input terminal of the comparator, and the anode of the diode is connected to the second input terminal of the comparator.

9. A resistor connected between the input terminal and the first node, A sixth transistor whose drain is connected to the gate of the third transistor, whose source is connected to the reference potential point via a first current source, and whose gate is supplied with a power supply voltage, A resistor connected between the second node and the gate of the third transistor, An electrostatic protection element connected between the input terminal and the reference potential point, The power supply circuit according to claim 7 or 8, further comprising the above.

10. The aforementioned comparator, A seventh transistor whose source is connected to the first input terminal and whose drain is connected to the reference potential point via a second current source, An eighth transistor whose source is connected to the second input terminal, whose gate is connected to the gate of the seventh transistor, and whose drain is connected to the reference potential point via a third current source and also to the gate of the seventh transistor, A ninth transistor whose drain is connected to the power line supplying the power supply voltage and the gate of the fifth transistor, whose source is connected to the reference potential point and whose gate is connected to the source of the seventh transistor, The power supply circuit according to claim 9, further comprising the above.

11. The voltage appearing at the output terminal is applied to the second input terminal of the comparator, instead of the voltage at the second node. The power supply circuit according to claim 7 or 8.

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