Semiconductor equipment

Abstract

To provide a semiconductor device capable of reducing a switching loss.SOLUTION: A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, and a second electrode. The third semiconductor region is located on the second semiconductor region and has an impurity concentration of the second conductivity type which is greater than that of the second semiconductor region. The second electrode is located on the third semiconductor region. The second electrode includes a first portion and a second portion. The first portion is located in the second semiconductor region. The second portion is located on the first portion. The second portion is in contact with the third semiconductor region in a second direction perpendicular to a first direction which is being from the first electrode to the first semiconductor region. A length in the second direction of the first portion is longer than a length in the second direction of the second portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as diodes and reverse-conducting insulated gate bipolar transistors (RC-IGBTs) are used for applications such as power conversion. For these semiconductor devices, low switching losses are desirable. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-134149 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device capable of reducing switching losses. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, a third semiconductor region having a second conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region and has a higher impurity concentration of the second conductivity type than the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode includes a first portion and a second portion. The first portion is provided in the second semiconductor region. The second portion is located on the first portion. The second portion is in contact with the third semiconductor region in a second direction perpendicular to a first direction toward the first semiconductor region from the first electrode. The length of the first portion in the second direction is longer than the length of the second portion in the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to the first embodiment. [Figure 2] Figures 2(a) and 2(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] Figures 3(a) and 3(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 6] Figure 6 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 7] Figure 7 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 8] Figure 8 is a perspective cross-sectional view showing a part of a semiconductor device according to a modified example of the first embodiment. [Figure 9]Figure 9 is a plan view of a semiconductor device according to the second embodiment. [Figure 10] Figure 10 is an enlarged plan view of part A of Figure 9. [Figure 11] Figure 11 is a cross-sectional view of the line B1-B2 in Figure 10. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Furthermore, even when representing the same part, the dimensions and ratios may differ between drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] In the following explanation, n + , n, n - and p + The notation p represents the relative levels of impurity concentrations in each conductivity type. That is, n + The concentration of n-type impurities is relatively higher in n than in n. - This indicates that the concentration of n-type impurities is relatively lower than that of n. Also, p + The concentration of p-type impurities is relatively higher than that of p, - This indicates that the p-type impurity concentration is relatively lower than that of the p-type. Each embodiment may be carried out by reversing the p-type and n-type in each semiconductor region.

[0009] Furthermore, the XYZ Cartesian coordinate system is used in the description of the embodiments. The direction from the first electrode toward the first semiconductor region is defined as the Z direction (first direction). The two directions perpendicular to the Z direction and mutually orthogonal are defined as the X direction (second direction) and the Y direction (third direction). Also, for the sake of explanation, the direction from the first electrode toward the first semiconductor region is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first electrode and the first semiconductor region and are independent of the direction of gravity.

[0010] (First Embodiment) FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a diode. As shown in FIG. 1, the semiconductor device 100 according to the first embodiment has an n - -type cathode region 101 (an example of a first semiconductor region), a p-type anode region 102 (an example of a second semiconductor region), a p + -type anode region 103 (an example of a third semiconductor region), an n + -type cathode region 104, a cathode electrode 111 (an example of a first electrode), and an anode electrode 112 (an example of a second electrode).

[0011] The cathode electrode 111 is provided on the lower surface of the semiconductor device 100. The n + -type cathode region 104 is provided on the cathode electrode 111 and is electrically connected to the cathode electrode 111. The n - -type cathode region 101 is provided on the n + -type cathode region 104. The n-type impurity concentration of the n - -type cathode region 101 is lower than the n-type impurity concentration of the n + -type cathode region 104.

[0012] The p-type anode region 102 is provided on the n - -type cathode region 101. A pn junction is formed between the n - -type cathode region 101 and the p-type anode region 102. The p + -type anode region 103 is provided on the p-type anode region 102. The p-type impurity concentration of the p + -type anode region 103 is higher than the p-type impurity concentration of the p-type anode region 102.

[0013] The anode electrode 112 is provided on the p-type anode region 102 and the p +It is provided on the p-shaped anode region 103. The anode electrode 112 includes a portion that protrudes toward the cathode electrode 111. This protruding portion includes a first portion 112a and a second portion 112b. The first portion 112a is provided in the p-shaped anode region 102 and is in contact with the p-shaped anode region 102. The second portion 112b is provided on the p-shaped anode region 102 and is p in the X direction + It is aligned with the shape anode region 103. The length L1 of the first part 112a is longer than the length L2 of the second part 112b. Multiple first parts 112a and multiple second parts 112b are provided in the X direction. For example, each of the multiple first parts 112a and multiple second parts 112b extends in the Y direction.

[0014] An example of the materials used for each component is described below. n - p-type cathode region 101, p-type anode region 102, p + Shape anode region 103, and n + The cathode region 104 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The cathode electrode 111 and the anode electrode 112 contain metals such as titanium or aluminum.

[0015] For example, n - The n-type impurity concentration in the cathode region 101 is 1.0 × 10⁻⁶. 13 atoms / cm 3 The above 1.0 × 10 15 atoms / cm 3 The following is true: The p-type impurity concentration in the p-type anode region 102 is 1.0 × 10⁻⁶. 16 atoms / cm 3 The above 1.0 × 10 18 atoms / cm 3 The following is p + The p-type impurity concentration in the anodic region 103 is 1.0 × 10⁻⁶. 18 atoms / cm 3 Larger than 5.0 x 1021 atoms / cm 3 The following is the case: n + The n-type impurity concentration in the cathode region 104 is 1.0 × 10⁴ 18 atoms / cm 3 The above 1.0 × 10 21 atoms / cm 3 The following applies:

[0016] Figures 2(a), 2(b), 3(a), 3(b), and 4 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. First, n + Semiconductor layer 104x and n - A semiconductor substrate containing a shaped semiconductor layer 101x is prepared. - The semiconductor layer 101x is n + It is provided on top of the shaped semiconductor layer 104x. - P-type impurities are ion-implanted onto the surface of the p-type semiconductor layer 101x to form a p-type semiconductor region 102x. As shown in Figure 2(a), p-type impurities are ion-implanted onto the surface of the p-type semiconductor region 102x, + A shaped semiconductor region 103x is formed.

[0017] p-type semiconductor region 102x and p + A mask M is formed on the p-type semiconductor region 103x by photolithography. The mask M has multiple openings. Using the mask M, a portion of the p-type semiconductor region 102x and p are etched by reactive ion etching (RIE). + A portion of the shaped semiconductor region 103x is removed. As a result, as shown in Figure 2(b), p + An aperture OP1 is formed that penetrates the shaped semiconductor region 103x.

[0018] A protective film P is formed along the surface of the mask M and the inner surface of the opening OP1. The protective film P formed on the top surface of the mask M and the bottom surface of the opening OP1 is removed by anisotropic etching. As a result, the protective film P is left only on the side walls of the opening OP1, as shown in Figure 3(a).

[0019] A portion of the p-type semiconductor region 102x is removed by isotropic ion etching through the aperture OP1. As shown in Figure 3(b), the p-type semiconductor region 102x is isotropically etched from the bottom of aperture OP1. A wider aperture OP2 is formed below aperture OP1.

[0020] The mask M and protective film P are removed. Metal layers 112x and 112y are formed by chemical vapor deposition (CVD). Metal layer 112x contains titanium. Metal layer 112y contains tungsten. Openings OP1 and OP2 are filled by metal layers 112x and 112y. As shown in Figure 4(a), a metal layer 112z is formed on metal layers 112x and 112y by sputtering. Metal layer 112z contains aluminum.

[0021] n + n + The back surface of the shaped semiconductor layer 104x is ground. As shown in Figure 4(b), a metal layer 111x is formed on the ground back surface by sputtering. Thus, the semiconductor device 100 according to the first embodiment is manufactured.

[0022] The operation of the semiconductor device 100 will be explained. When a positive voltage is applied to the anode electrode 112 relative to the cathode electrode 111, n - A forward voltage is applied between the p-type cathode region 101 and the p-type anode region 102. As a result, the semiconductor device 100 turns on, and from the anode electrode 112 Cathode electrode Current flows to 111. At this time, from the anode electrode 112 n - Shape of cathode region A hole is injected into 101, and an electron is injected into 101 from the cathode electrode 111.

[0023] Subsequently, when a positive voltage is applied to the cathode electrode 111 relative to the anode electrode 112, the current from the anode electrode 112 to the cathode electrode 111 stops. The semiconductor device 100 switches from the ON state to the OFF state. At this time, n- The electrons and holes accumulated in the cathode region 101 are discharged to the cathode electrode 111 and the anode electrode 112, respectively.

[0024] The advantages of the first embodiment will be explained. When the semiconductor device 100 is ON, n - The fewer carriers accumulated in the cathode region 101, the less n when the semiconductor device 100 switches to the off state. - The number of carriers emitted from the cathode region 101 decreases. In other words, the switching of the semiconductor device 100 becomes faster, and the switching loss of the semiconductor device 100 is reduced. In the semiconductor device 100, n - To reduce the carriers accumulating in the p-type cathode region 101, the anode electrode 112 includes a first portion 112a. The first portion 112a is located within the p-type anode region 102. The p-type impurity concentration in the p-type anode region 102 is p + The concentration of p-type impurities is lower than that of the p-type anode region 103. A Schottky junction is formed between the p-type anode region 102 and the first portion 112a. When the semiconductor device 100 is ON, holes are less likely to be injected from the first portion 112a into the p-type anode region 102. On the other hand, electrons are ejected from the p-type anode region 102 into the first portion 112a. Therefore, n - This can reduce the amount of carriers accumulated in the cathode region 101.

[0025] In particular, the length L1 of the first portion 112a is longer than the length L2 of the second portion 112b. Therefore, the contact area between the p-type anode region 102 and the first portion 112a can be increased. A larger contact area allows for an increase in the amount of electrons emitted from the p-type anode region 102 to the first portion 112a. - As the electrons accumulated in the cathode region 101 decrease, n - The number of holes injected into the cathode region 101 is also reduced. According to the first embodiment, when the semiconductor device 100 is ON, n - This reduces the carriers accumulated in the cathode region 101, thereby reducing the switching loss of the semiconductor device 100.

[0026] The p-type impurity concentration in the p-type anode region 102 is 1.0 × 10⁻⁶. 16 atoms / cm 3 The above 1.0 × 10 18 atoms / cm 3 The following is preferable. Within this concentration range, a Schottky junction is well formed between the p-type anode region 102 and the first portion 112a.

[0027] In the example shown in Figure 1, the anode electrode 112 further includes a third portion 112c. The third portion 112c is located between the first portion 112a and the second portion 112b. The third portion 112c is in contact with the p-shaped anode region 102 in the X direction. The length of the third portion 112c in the X direction is the same as the length L2 of the second portion 112b in the X direction.

[0028] Alternatively, the anode electrode 112 does not have to include the third portion 112c. Of the portions protruding toward the cathode electrode 111, the wider portion is p + It may be in contact with the shaped anode region 103. However, in this case, compared to the case in which the third portion 112c is provided, p + The contact area between the shaped anode region 103 and the anode electrode 112 increases. As a result, p + The injection of holes into the anode region 103 increases. Therefore, n - To reduce the carriers accumulated in the cathode region 101, it is preferable that the anode electrode 112 includes a third portion 112c.

[0029] Figures 5 to 8 are perspective cross-sectional views showing a part of a semiconductor device according to a modified example of the first embodiment.

[0030] In the semiconductor device 100a shown in Figure 5, p + The p-shaped anode region 103 is located on a portion of the p-shaped anode region 102. Another portion of the p-shaped anode region 102 is p in the X direction. + It is aligned with the shape of the anode region 103.

[0031] p + The plurality of p-shaped anode regions 103 are provided in the X direction. One second portion 112b is provided between a pair of p + -shaped anode regions 103 and is in contact with those p + -shaped anode regions 103. For example, each p + -shaped anode region 103 extends in the Y direction along the first portion 112a and the second portion 112b.

[0032] p + When the area of the p-shaped anode region 103 in the X-Y plane is small, when the semiconductor device 100a is in the on state, the carriers flowing into the n - -shaped cathode region 101 decrease. The carriers accumulated in the n - -shaped cathode region 101 also decrease. Thereby, the switching loss of the semiconductor device 100a can be reduced. ​​​​​​​​​​​​​​​​​​​​​​​​The carriers accumulated in the cathode region 101 can be further reduced. Compared to semiconductor device 100a, semiconductor device 100b can further reduce switching losses.

[0035] The semiconductor device 100c shown in Figure 7 further comprises conductive portions 121. The conductive portion 121 faces the p-type anode region 102 in the X direction via an insulating layer 121a. The conductive portion 121 is electrically connected to the anode electrode 112. Multiple conductive portions 121 are provided in the X direction, and each conductive portion 121 extends in the Y direction.

[0036] In the semiconductor device 100d shown in Figure 8, a void V exists in the first portion 112a. For example, the void V is located approximately in the center of the XZ plane of the first portion 112a and directly beneath the second portion 112b.

[0037] Voids V may exist in each of the multiple first parts 112a. Voids V may exist in only a portion of the multiple first parts 112a. Voids V may extend along the Y direction, as shown in Figure 8. Multiple voids V may exist in the Y direction, separated from each other.

[0038] When manufacturing the semiconductor device 100d, compressive stress is generated on the upper surface. If the compressive stress is excessively strong, cracks will occur in the semiconductor region. As a result, for example, the leakage current of the semiconductor device 100d will increase. When a void V is provided, at least a portion of the void V deforms in response to the compressive stress. This reduces the compressive stress generated on the upper surface of the semiconductor device 100d. This suppresses the occurrence of cracks and reduces the leakage current of the semiconductor device 100d.

[0039] (Second Embodiment) Figure 9 is a plan view of a semiconductor device according to the second embodiment. Figure 10 is an enlarged plan view of part A of Figure 9. Figure 11 is a cross-sectional view of B1-B2 in Figure 10. Figure 10 corresponds to the C1-C2 cross-section in Figure 11. The semiconductor device according to the second embodiment is an RC-IGBT. The semiconductor device 200 according to the second embodiment is shown in Figure9~11 As shown in - an n-type (first conductivity type) base region 201 (an example of a first semiconductor region), a p-type (second conductivity type) anode region 202 (an example of a second semiconductor region), a p + -type anode region 203 (an example of a third semiconductor region), a p + -type collector region 204 (an example of a fourth semiconductor region), a p-type base region 205 (an example of a fifth semiconductor region), an n + -type emitter region 206 (an example of a sixth semiconductor region), a p + -type contact region 207, an n + -type cathode region 208, a collector electrode 211 (an example of a first electrode), an emitter electrode 212 (an example of a second electrode), a gate pad 213, a gate electrode 221, a conductive part 222, and an insulating layer 225.

[0040] As shown in FIG. 9, an emitter electrode 212 and a gate pad 213 are provided on the upper surface of the semiconductor device 200. The emitter electrode 212 and the gate pad 213 are separated from each other. For example, in the Y direction, a plurality of emitter electrodes 212 are provided. Around each emitter electrode 212, a gate wiring 213a is provided. A part of the gate wiring 213a extends in the Y direction between the emitter electrodes 212. The gate wiring 213a is electrically connected to the gate pad 213.

[0041] As shown in FIGS. 9 and 10, the semiconductor device 200 has a diode region R1 and an IGBT region R2. In the example shown in FIG. 9, a plurality of each of the diode region R1 and the IGBT region R2 are provided in the X direction and the Y direction. In the X direction, the diode region R1 and the IGBT region R2 are provided alternately.

[0042] As shown in FIG. 11, a collector electrode 211 is provided on the lower surface of the semiconductor device 200. The collector electrode 211 and the emitter electrode 212 are separated from each other, and the plurality of diode regions R1 and the plurality of IGBT regions R2 are located between the collector electrode 211 and the emitter electrode 212.

[0043] Each diode region R1 has n - Part of the base region 201, p-type anode region 202, p + Shape anode region 203, n + A cathode region 208 and a conductive portion 222 are provided.

[0044] n + The cathode region 208 is located on a portion of the collector electrode 211 and is electrically connected to the collector electrode 211. - A portion of the shape base region 201 is n + It is located on the p-type cathode region 208. The p-type anode region 202 is n - The part of the shaped base region 201 is provided, n + It is located above the cathode region 208.

[0045] The conductive portion 222 faces the p-type anode region 202 in the X direction via the insulating layer 222a. + The p-shaped anode region 203 is located on top of the p-shaped anode region 202. + The p-type impurity concentration in the p-type anode region 203 is higher than that in the p-type anode region 202. + The shaped anode region 203 and the conductive portion 222 are electrically connected to the emitter electrode 212.

[0046] The emitter electrode 212 in the semiconductor device 200, like the anode electrode 112 in the semiconductor device 100, includes a first portion 212a and a second portion 212b. The first portion 212a is provided in the p-type anode region 202. The first portion 212a is in contact with the p-type anode region 202, and a Schottky junction is formed between the p-type anode region 202 and the first portion 212a. The second portion 212b is provided on top of the first portion 212a and is p in the X direction + It is aligned with the shape anode region 203. The second part 212b is p + It is in contact with the shaped anode region 203. The length L1 of the first portion 212a in the X direction is longer than the length L2 of the second portion 212b in the X direction.

[0047] The emitter electrode 212 may further include a third portion 212c. The third portion 212c is located between the first portion 212a and the second portion 212b. The third portion 212c is in contact with the p-type anode region 202 in the X direction. The length of the third portion 212c in the X direction is the same as the length L2 of the second portion 212b in the X direction.

[0048] In one diode region R1, p-type anode region 202, p + Multiple p-shaped anode regions 203, first portion 212a, second portion 212b, and conductive portion 222 are provided in the X direction. Multiple p-shaped anode regions 202, multiple p + Each of the shaped anode region 203, the plurality of first portions 212a, the plurality of second portions 212b, and the plurality of conductive portions 222 is arranged in a stripe pattern and extends in the Y direction.

[0049] Each IGBT region R2 contains n - Another part of the shape base region 201, p + Type collector area 204, p-type base area 205, n + Shape emitter region 206, p + A contact region 207 and a gate electrode 221 are provided.

[0050] p + The collector region 204 is located on another portion of the collector electrode 211 and is electrically connected to the collector electrode 211. - Another part of the shape base region 201 is p + It is located on top of the p-shaped collector region 204. The p-shaped base region 205 is n - Provided on the other part of the shaped base region 201, p + It is located above the shape collector area 204.

[0051] The emitter electrode 212 further includes a fourth portion 212d that protrudes toward the collector electrode 211. +The p-shaped emitter region 206 is located on the p-shaped base region 205 and is in contact with the fourth portion 212d in the X direction. + The shaped contact region 207 is provided between the p-shaped base region 205 and the fourth portion 212d in the Z direction, n + It is located below the emitter region 206. + The p-type impurity concentration in the p-type contact region 207 is higher than that in the p-type base region 205.

[0052] The gate electrode 221 faces the p-type base region 205 in the X direction via the gate insulating layer 221a. In the illustrated example, the gate electrode 221 is further connected via the gate insulating layer 221a to the n - Shape base region 201 and n + It also faces the shape emitter region 206.

[0053] The emitter electrode 212 is a p-type base region 205, n + Shape emitter region 206, and p + It is electrically connected to the contact region 207. An insulating layer 225 is provided between the emitter electrode 212 and the gate electrode 221, so that the emitter electrode 212 and the gate electrode 221 are electrically isolated from each other.

[0054] In one IGBT region R2, the p-type base region 205, n + Shape emitter region 206, p + Multiple p-shaped base regions 205, multiple n-shaped base regions 205, and multiple n-shaped base regions 205 are provided in the X direction. + Shape emitter region 206, multiple p + Each of the shaped contact region 207, the plurality of fourth portions 212d, and the plurality of gate electrodes 221 are arranged in a stripe pattern and extend in the Y direction. The ends of the gate electrodes 221 in the Y direction are electrically connected to the gate wiring 213a. The gate electrodes 221 are electrically connected to the gate pad 213 via the gate wiring 213a.

[0055] The operation of the semiconductor device 200 will be explained. With a positive voltage applied to the collector electrode 211 relative to the emitter electrode 212, a voltage above a threshold is applied to the gate electrode 221. This forms a channel (inversion layer) in the p-type base region 205. Electrons pass through the channel, and + Shape emitter region 206 to n - The holes flow into the base region 201, p + From the collector area 204 to n - It flows into the shape base region 201. - The carrier density accumulated in the base region 201 increases, causing conductivity modulation. As a result, n - The electrical resistance of the p-type base region 201 decreases significantly, and the IGBT region R2 turns on. Subsequently, when the voltage applied to the gate electrode 221 falls below a threshold, the channel in the p-type base region 205 disappears, and the IGBT region R2 switches to the off state.

[0056] After the IGBT region R2 is switched to the off state, electrons accumulated in the n-type base region 201 are discharged to the collector electrode 211 through the p+-type collector region 204. Holes are discharged to the emitter electrode 212 through the p-type base region 205.

[0057] For example, in a circuit equipped with a semiconductor device 200, when an induced electromotive force is generated and a positive voltage is applied to the emitter electrode 212 relative to the collector electrode 211, the diode region R1 operates. From the p-type anode region 202 to n - Holes flow into the shaped base region 201, n + Shape cathode region 208 to n - Electrons flow into the base region 201. The diode region R1 functions as a freewheeling diode (FWD).

[0058] As shown in Figure 11, p + Shape collector area 204 and n - Between the shape base region 201 and n + Shape cathode region 208 and n -An n-type buffer region 209 may be provided between the n-type base region 201 and the n-type buffer region 209. The n-type impurity concentration in the n-type buffer region 209 is n + The n-type impurity concentration is lower than that of the cathode region 208, n - It is higher than the n-type impurity concentration in the base region 201. By providing the n-type buffer region 209, - The depletion layer in the n-type base region 201 can be more reliably suppressed by the n-type buffer region 209.

[0059] In the IGBT region R2, some of the multiple gate electrodes 221 may be replaced with conductive parts 222. By replacing some of the gate electrodes 221 with conductive parts 222, when the IGBT region R2 is ON, n - The density of carriers accumulated in the base region 201 can be increased, further reducing the electrical resistance of the semiconductor device 200. Furthermore, the conductive portion 222 in the diode region R1 can be omitted.

[0060] An example of the materials used for each component of the semiconductor device 200 is described below. n - Type base region 201, p-type anode region 202, p + Shape anode region 203, p + Type collector area 204, p-type base area 205, n + Shape emitter region 206, p + Shaped contact area 207, n + The n-type cathode region 208 and the n-type buffer region 209 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities.

[0061] The collector electrode 211, emitter electrode 212, gate pad 213, and gate wiring 213a contain a metal such as titanium, tungsten, or aluminum. The gate electrode 221 and conductive part 222 contain a conductive material such as polysilicon. The gate insulating layer 221a, insulating layer 222a, and insulating layer 225 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0062] For example, n - The n-type impurity concentration in the base region 201 is 1.0 × 10⁻⁶. 13 atoms / cm 3 The above 1.0 × 10 15 atoms / cm 3 The following is true: The p-type impurity concentrations in the p-type anode region 202 and the p-type base region 205 are 1.0 × 10⁻⁶. 16 atoms / cm 3 The above 1.0 × 10 18 atoms / cm 3 The following is p + The p-type impurity concentration in the anodic region 203 is 1.0 × 10⁻⁶. 18 atoms / cm 3 Larger than 5.0 x 10 21 atoms / cm 3 The following is p + Type collector area 204 and p + The p-type impurity concentrations in each contact region 207 are 1.0 × 10⁻⁶. 18 atoms / cm 3 Larger than 1.0 × 10 21 atoms / cm 3 The following is the case: n + Shape emitter region 206 and n + The concentration of n-type impurities in each of the cathode regions 208 is 1.0 × 10⁻⁶. 18 atoms / cm 3 The above 1.0 × 10 21 atoms / cm 3 The following is true: The concentration of n-type impurities in the n-type buffer region 209 is 1.0 × 10⁻⁶. 14 atoms / cm 3 The above 1.0 × 10 18 atoms / cm 3The following applies:

[0063] The advantages of the second embodiment will be explained. In the semiconductor device 200 according to the second embodiment, the emitter electrode 212 includes a first portion 212a and a second portion 212b. The first portion 212a and the second portion 212b are provided in the diode region R1. The p-type impurity concentration of the p-type anode region 202 is p + The concentration of p-type impurities is lower than that of the p-type anode region 203, and a Schottky junction is formed between the p-type anode region 202 and the first portion 212a. The injection of holes from the first portion 212a into the p-type anode region 202 is suppressed, and electrons are ejected from the p-type anode region 202 into the first portion 212a, so that when the IGBT region R2 is ON, n - The carriers accumulated in the shaped base region 201 can be reduced. In particular, since the length L1 of the first part 212a is longer than the length L2 of the second part 212b, n - The carriers accumulated in the base region 201 can be further reduced. According to the second embodiment, the switching loss of the semiconductor device 200 can be reduced, similar to the first embodiment.

[0064] Furthermore, the semiconductor device 200 includes an IGBT region R2. The IGBT region R2 contains n - A parasitic diode exists consisting of a p-type base region 201 and a p-type base region 205. When diode region R1 is ON, holes pass through the parasitic diode of IGBT region R2. - The shaped base region 201 is injected. Therefore, in the RC-IGBT semiconductor device 200, more carriers than the designed value are n - It tends to accumulate in the base region 201, and the problem of switching loss tends to become significant. By providing the semiconductor device 200 with the first portion 212a and the second portion 212b, n - The carrier density in the base region 201 can be effectively reduced, thereby reducing the switching loss of the semiconductor device 200.

[0065] Similar to the semiconductor device 100d shown in Figure 8, a void V may be present in the first portion 212a. In the semiconductor device 200, a gate insulating layer 221a, insulating layer 222a, insulating layer 225, etc., are present on the surface side. When these insulating layers contain an oxidizing material, the compressive stress becomes greater. For this reason, cracks are more likely to occur in the semiconductor region around the gate insulating layer 221a, insulating layer 222a, insulating layer 225, etc. When a void V is present in the first portion 212a, the compressive stress can be reduced, and the leakage current due to cracks in the semiconductor device 200 can be reduced.

[0066] In the semiconductor device 200, the conductive portion 222 in the diode region R1 may be omitted. However, by providing the conductive portion 222 in the diode region R1 and the gate electrode 221 in the IGBT region R2, the uniformity and stability of the manufacturing process of the semiconductor device 200 can be improved. For example, differences in depth, shape, etc., of each gate electrode 221 can be reduced, suppressing variations in the characteristics of the semiconductor device 200 and improving the yield. In addition, it is possible to suppress current concentration caused by differences between the upper surface structure of the diode region R1 and the upper surface structure of the IGBT region R2.

[0067] Embodiments of the present invention include the following configurations. (Composition 1) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of the second conductivity type is provided on the second semiconductor region and has a higher impurity concentration of the second conductivity type than the second semiconductor region, A second electrode provided on the third semiconductor region, A first portion provided in the second semiconductor region, A second portion located above the first portion and in contact with the third semiconductor region in a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, The second electrode includes, wherein the length of the first portion in the second direction is longer than the length of the second portion in the second direction, A semiconductor device equipped with [the necessary components]. (Configuration 2) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A second electrode provided on the second semiconductor region, A first portion provided in the second semiconductor region, A second part located above the first part, The second electrode includes a first portion in a second direction perpendicular to a first direction toward the first semiconductor region from the first electrode, the length of the first portion in the second direction is longer than the length of the second portion in the second direction, and a Schottky junction is formed between the first portion and the second semiconductor region. A semiconductor device equipped with [the necessary components]. (Composition 3) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, Provided on the first semiconductor region, 1.0 × 10 16 atoms / cm 3 The above 1.0 × 10 18 atoms / cm 3 A second semiconductor region having the following impurity concentrations for the second conductivity type, A second electrode provided on the second semiconductor region, The first portion in contact with the second semiconductor region, A second part located above the first part, The second electrode includes a first electrode wherein the length of the first portion in a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode is longer than the length of the second portion in the second direction, A semiconductor device equipped with [the necessary components]. (Composition 4) In the second direction, the conductive portion further comprises a conductive portion facing the second semiconductor region via an insulating layer, The conductive portion is electrically connected to the second electrode, as described in any one of configurations 1 to 3, for the semiconductor device. (Composition 5) A fourth semiconductor region of a second conductivity type is provided between a part of the first electrode and a part of the first semiconductor region, A fifth semiconductor region of a second conductivity type is provided on a portion of the first semiconductor region, A sixth semiconductor region of the first conductivity type is provided on the fifth semiconductor region, A semiconductor device according to any one of configurations 1 to 4, further comprising a gate electrode facing the fifth semiconductor region via a gate insulating layer in the second direction. (Composition 6) The second electrode further includes a third portion located between the first portion and the second portion. The third portion is in contact with the second semiconductor region in the first direction, A semiconductor device according to any one of configurations 1 to 5, wherein the length of the third portion in the second direction is the same as the length of the second portion in the second direction. (Composition 7) The semiconductor device according to any one of configurations 1 to 6, wherein the first part includes a void.

[0068] According to each embodiment described above, a semiconductor device capable of reducing switching losses is provided.

[0069] The relative levels of impurity concentrations between semiconductor regions in each embodiment can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0070] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of symbols]

[0071] 100, 100a~100d: Semiconductor equipment, 101: n - Cathode region shape, 10¹x:n - 102:p-type semiconductor layer, 102:p-type anode region, 102x:p-type semiconductor region, 103:p + Shape of the anode region, 10³x:p + Semiconductor region, 10⁴:n + Cathode region shape, 10⁴x:n + Semiconductor layer, 111: cathode electrode, 111x: metal layer, 112: anode electrode, 112a: first part, 112b: second part, 112c: third part, 112x~112z: metal layer, 121: conductive part, 121a: insulating layer, 200: semiconductor device, 201: n - 202:p-type base region, 203:p-type anode region + Shape of the anode region, 204:p + Type collector area, 205: p-type base area, 206: n + Shape emitter region, 207:p + Shape of contact area, 208:n +209: n-type cathode region, 211: collector electrode, 212: emitter electrode, 212a: first part, 212b: second part, 212c: third part, 212d: fourth part, 213: gate pad, 213a: gate wiring, 221: gate electrode, 221a: gate insulating layer, 222: conductive part, 222a, 225: insulating layer, M: mask, OP1, OP2: opening, P: protective film, R1: diode region, R2: IGBT region, V: void

Claims

1. First electrode and A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of the second conductivity type is provided on the second semiconductor region and has a higher impurity concentration of the second conductivity type than the second semiconductor region, A second electrode provided on the third semiconductor region, The first portion provided in the second semiconductor region, A second portion located above the first portion and in contact with the third semiconductor region in a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, The second electrode includes, wherein the length of the first portion in the second direction is longer than the length of the second portion in the second direction, and the first portion is separated from the third semiconductor region in the first direction, A semiconductor device equipped with [the necessary components].

2. First electrode and A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A second electrode provided on the second semiconductor region, The first portion provided in the second semiconductor region, A second part located above the first part, The second electrode includes a first portion in a second direction perpendicular to a first direction toward the first semiconductor region from the first electrode, the length of the first portion in the second direction is longer than the length of the second portion in the second direction, and a Schottky junction is formed between the first portion and the second semiconductor region. A semiconductor device equipped with [the necessary components].

3. The semiconductor device according to claim 2, wherein the impurity concentration of the second conductivity type in the second semiconductor region is 1.0 × 10¹⁶ atoms / cm³ or more and 1.0 × 10¹⁸ atoms / cm³ or less.

4. A fourth semiconductor region of a second conductivity type is provided between a part of the first electrode and a part of the first semiconductor region, A fifth semiconductor region of a second conductivity type is provided on a part of the first semiconductor region, A sixth semiconductor region of the first conductivity type is provided on the fifth semiconductor region, The semiconductor device according to any one of claims 1 to 3, further comprising a gate electrode facing the fifth semiconductor region via a gate insulating layer in the second direction.

5. First electrode and A first semiconductor region of a first conductivity type provided on the first electrode, Provided on the first semiconductor region, 1.0 × 10 １６ atoms / cm ３ The above 1.0 x 10 １８ atoms / cm ３ A second semiconductor region having the following impurity concentrations for the second conductivity type, A second electrode provided on the second semiconductor region, The first portion in contact with the second semiconductor region, A second part located above the first part, The second electrode includes a first electrode wherein the length of the first portion in a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode is longer than the length of the second portion in the second direction, A fourth semiconductor region of a second conductivity type is provided between a part of the first electrode and a part of the first semiconductor region, A fifth semiconductor region of a second conductivity type is provided on a part of the first semiconductor region, A sixth semiconductor region of the first conductivity type is provided on the fifth semiconductor region, In the second direction, a gate electrode facing the fifth semiconductor region via the gate insulating layer, A semiconductor device equipped with [the necessary components].

6. In the second direction, the conductive portion further comprises a conductive portion facing the second semiconductor region via an insulating layer, The semiconductor device according to any one of claims 1 to 3 and 5, wherein the conductive portion is electrically connected to the second electrode.

7. The second electrode further includes a third portion located between the first portion and the second portion. The third portion is in contact with the second semiconductor region in the second direction, The semiconductor device according to any one of claims 1 to 3 and 5, wherein the length of the third portion in the second direction is the same as the length of the second portion in the second direction.

8. The semiconductor device according to any one of claims 1 to 3 and 5, wherein the first portion includes a void.

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