Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing the abrupt current rise during turn-on of the semiconductor device without significantly compromising the effective area of the semiconductor device.SOLUTION: A planar layout on a semiconductor substrate SB has a distribution of threshold voltages for switching. When a histogram is defined by multiple classes with a class width of 100 mV and multiple frequencies corresponding to an area of the planar layout belonging to each of the multiple classes for the threshold voltage, the planar layout includes multiple regions RG1 to RGn belonging to different classes among the multiple classes. The multiple regions RG1 to RGn include first to third regions RG1 to RG3. The histogram has a distribution PFL with a tail thereof extending, based on a normal distribution PNM, on a lower voltage side continuously from the normal distribution PNM.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices, and more particularly to insulated-gate bipolar transistors or reverse-conducting insulated-gate bipolar transistors. [Background technology]

[0002] According to International Publication No. 2012 / 141121 (Patent Document 1), in a semiconductor device having a power active element with an insulated gate such as a power MOSFET, a sub-active cell region is provided in the active cell region, which has a lower threshold voltage and a relatively smaller occupied area than other regions. The above document claims that this reduces the occurrence of a jump voltage because the sub-active cell region turns on first when the device is turned on.

[0003] According to Japanese Patent Publication No. 2016-154218 (Patent Document 2), a semiconductor device includes a transistor cell and an enhancement cell. Each transistor cell includes a drift structure and a body region that forms a first pn junction. The transistor cell forms an inversion channel within the body region when a first control signal exceeds a first threshold. A delay unit generates a second control signal whose trailing edge is delayed relative to the trailing edge of the first control signal. The enhancement cell forms an inversion layer within the drift structure when the second control signal falls below a second threshold that is lower than the first threshold. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2012 / 141121 [Patent Document 2] Japanese Patent Publication No. 2016-154218 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] In the technology described in the above-mentioned International Publication No. 2012 / 141121, simply providing a sub-active cell region tends to result in a large deviation from the switching characteristics originally desired by the user of the semiconductor device.

[0006] The technology disclosed in Japanese Patent Publication No. 2016-154218 involves forming different gate electrodes on different types of cells and sending a delayed signal corresponding to each cell. This causes some cells to turn off earlier, promoting carrier discharge. This reduces turn-off loss. Thus, it is thought that a configuration that provides separate control signals to each cell can be configured to obtain various effects, not just a reduction in turn-off loss. For example, it is thought that it is possible to suppress radiated noise from the semiconductor device by suppressing the rapid rise in current during turn-on. However, in order to receive multiple types of control signals, the semiconductor device needs to have multiple types of control pads (gate pads). As a result, the effective area of ​​the semiconductor device is greatly reduced.

[0007] This disclosure was made to solve the above-mentioned problems, and one of its objectives is to provide a semiconductor device that can suppress the rapid rise in current during turn-on of a semiconductor device without significantly reducing the effective area of ​​the semiconductor device. [Means for solving the problem]

[0008] One aspect according to the present disclosure is a semiconductor device that is an insulated gate bipolar transistor or a reverse-conducting insulated gate bipolar transistor, comprising a semiconductor substrate including a drift layer having a first conductivity type, and a gate structure having a gate electrode and a gate insulating film for switching of the semiconductor device. The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switching. When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to the area of the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include first to third regions, and the histogram has a distribution that continuously trails off to the low voltage side from the normal distribution with reference to the normal distribution.

Advantages of the Invention

[0009] According to one aspect of the present disclosure, the histogram has a continuous distribution that trails off to the low voltage side compared to the normal distribution. By utilizing this distribution, it is possible to suppress a rapid rise in current when the semiconductor device is turned on without significantly impairing the effective area of the semiconductor device.

[0010] The object, features, aspects, and advantages of the present disclosure will become clearer from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0011] [Figure 1] It is a plan view for explaining the definition of a plurality of regions that the planar layout on the semiconductor substrate of the semiconductor device has. [Figure 2] It is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to the first comparative example. [Figure 3] It is a plan view showing the configuration of the planar layout on the semiconductor substrate of the semiconductor device according to the first comparative example. [Figure 4]A graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to the second comparative example. [Figure 5] A graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to Embodiment 1. [Figure 6] A plan view showing the configuration of the planar layout on the semiconductor substrate of the semiconductor device according to Embodiment 1 or 2. [Figure 7] A plan view showing a modified example of FIG. 6. [Figure 8] A graph showing an example of the transfer characteristics of the semiconductor device according to Embodiment 1. [Figure 9] A graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to Embodiment 2. [Figure 10] A graph showing an example of the transfer characteristics of the semiconductor device according to Embodiment 2. [Figure 11] A cross-sectional view schematically showing the configuration of a typical insulated gate bipolar transistor. [Figure 12] A cross-sectional view showing the configuration of an insulated gate bipolar transistor as the semiconductor device according to Embodiment 1 or 2. [Figure 13] A cross-sectional view showing a modified example of FIG. 12. [Figure 14] A plan view showing a modified example of FIG. 6. [Figure 15] A plan view showing a modified example of FIG. 6. [Figure 16] A plan view showing a modified example of FIG. 6. [Figure 17] A plan view showing a modified example of FIG. 6. [Figure 18] A graph showing an assumed example of the distribution of threshold voltages along line XVIII-XVIII of FIG. 17.

Embodiments for Carrying Out the Invention

[0012] The embodiments will be described below with reference to the drawings. In the following drawings, identical or corresponding parts will be given the same reference numeral, and their descriptions will not be repeated.

[0013] Furthermore, the following explanation will mainly focus on the case where the first conductivity type is n-type and the second conductivity type is p-type, but the case where the first conductivity type is p-type and the second conductivity type is n-type is also possible. In addition, the description related to impurity concentration is "n - " indicates that the concentration is lower than "n", and "n + " indicates that the impurity concentration is higher than "n". Similarly, "p - " indicates that the impurity concentration is lower than "p", and "p + " indicates that the impurity concentration is higher than "p".

[0014] Furthermore, although the following explanation only mentions the concentration of impurities that determine the conductivity type, carbon, which is a congener of silicon, the main component of semiconductors, may also be present. In addition, if the MCZ (Magnetic Field Applied Czochralski) method is applied, oxygen, boron, or nitrogen introduced in conjunction with it may also be present.

[0015] Furthermore, it is stated below that the active cell region has regions RG1 to RGn (1st to nth regions) corresponding to the distribution of the switching threshold voltage of the semiconductor device. The region with the largest area ratio in the active cell region is called region RG1, and the other regions are called region RG2, region RG3, ... region RGn in order of decreasing area ratio. Histograms are also defined for regions RG1 to RGn, as will be described in detail later. Before describing the embodiments, the definitions of these regions in this specification will be explained first. The threshold voltage may be specifically defined as the gate voltage required to conduct a current of 1 / 10,000th of the rated current density when the rated voltage is applied between the collector and emitter. In that case, for example, if the rated current density of the semiconductor device is 15 A / cm² 2 If so, the current density is 1.5 mA / cm². 2The gate voltage at which this occurs is the threshold voltage.

[0016] First, the common aspects of this embodiment and the comparative example described later will be explained with reference to Figure 1. Figure 1 is a plan view illustrating the definitions of multiple regions RG1 to RGn in the planar layout of the semiconductor device 100 on the semiconductor substrate SB. The semiconductor device 100 is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). The planar layout of the semiconductor device 100 includes an active IGBT cell region 10, a termination region 30, and a gate pad region 41. The semiconductor device 100 may have a diode region (not shown) in a region different from the active IGBT cell region 10.

[0017] The planar layout has a distribution of threshold voltages for switching the semiconductor device 100. Multiple classes are defined for the threshold voltage with a class width of 100mV (in other words, a typical value ±50mV). The planar layout has multiple regions RG1 to RGn belonging to different classes among the multiple classes. In other words, different regions belong to different classes, and one region belongs to one class. The histogram (see, for example, Figure 2) is defined by these classes and multiple frequencies corresponding to the area of ​​the planar layout belonging to each of these multiple classes.

[0018] If the class width is made excessively small, the number of classes required to represent the threshold voltage distribution will increase indefinitely, and therefore the number of regions will also increase indefinitely. Conversely, if the class width is made excessively large, the number of regions will, in extreme cases, decrease to just one, regardless of the threshold voltage distribution. Histograms with these inappropriate class widths cannot properly evaluate the characteristics of the threshold voltage distribution in this embodiment, which will be described later. In order to evaluate these characteristics clearly, distinguishing them from the manufacturing variations that are naturally assumed in the conventional method, the class width must be appropriately selected, and according to the inventors' considerations, 100mV is one of the optimal values. Since the threshold voltage distribution range within the same substrate (in other words, the same chip) of a typical IGBT that is not intended to have multiple threshold voltages is 100mV or less, by setting the class width to 100mV, it is assumed that the histogram of this typical IGBT will fit within two or fewer classes (in other words, within the voltage range ±100mV), and even with an overestimation, it is thought to fit within five classes corresponding to five regions RG1 to RG5.

[0019] Figure 2 is a graph showing the histogram of the threshold voltage Vth distribution in the planar layout of semiconductor device 100P according to the first comparative example. Figure 3 is a planar view showing the configuration of the planar layout of semiconductor device 100P on the semiconductor substrate SB according to the first comparative example. As mentioned above, semiconductor device 100P has a threshold voltage distribution represented by five classes corresponding to five regions RG1 to RG5. The histogram distribution of semiconductor device 100P is substantially a normal distribution PNM as a whole. The frequency of each class in the histogram of Figure 2 corresponds to the respective areas of regions RG1 to RG5 in Figure 3. For example, in Figure 3, region RG2 has 10 scattered minute parts, and the total area of ​​these minute parts corresponds to the frequency of class "5.85-5.94" [V] in Figure 2. The threshold voltage distribution containing unintentional manufacturing variations includes regions with randomly scattered minute parts, as shown in Figure 3, for example. The distribution of semiconductor device characteristics in a planar layout is appropriately evaluated using the semiconductor device's unit cell as the unit. Therefore, if we define the area of ​​one unit cell as the unit area, then when the above-mentioned minute portion is composed of one unit cell, the area of ​​that minute portion corresponds to the unit area. Furthermore, when minute portions combine to form an island-like portion spanning multiple unit cells, the area of ​​the minute portion is the unit area multiplied by the number of unit cells.

[0020] Figure 4 is a graph showing a histogram of the threshold voltage distribution in the planar layout of semiconductor device 100Q according to the second comparative example. This is considered to be an example of simply applying the technique described in International Publication No. 2012 / 141121. Therefore, semiconductor device 100Q is an example of a semiconductor device in which multiple regions with different threshold voltages are intentionally formed. Specifically, as shown in the figure, large region A and large region B are provided corresponding to each intended threshold voltage. In each of large region A and large region B, there is a substantially normal distribution due to manufacturing variations, etc. On the other hand, the distribution of large region A and the distribution of large region B are not continuous. In other words, the distribution of large region A and the distribution of large region B do not overlap. Here, "not continuous" (or "does not overlap") means that a class with a frequency of zero is interposed between large region A and large region B.

[0021] As mentioned above, if the evaluation is performed using a histogram with an excessively wide class width, the distributions of large region A and large region B may be continuous. However, the configuration in which large region A and large region B are separated by a class of zero frequency, as shown in the histogram of Figure 4, is due to the designer's intention rather than manufacturing variability in this technical field. In order to appropriately evaluate such characteristics, this specification uses an evaluation with a class width of 100 mV.

[0022] Figure 5 is a graph showing a histogram of the threshold voltage distribution in the planar layout of the semiconductor device 101 according to Embodiment 1. Figure 6 is a planar view showing the configuration of the planar layout of the semiconductor device 101 on the semiconductor substrate SB.

[0023] The histogram of semiconductor device 101 (Figure 5) is essentially a normal distribution P, similar to the histogram of semiconductor device 100P (Figure 2). NM (Including the region with coarse hatching in Figure 5) the normal distribution P NM It has a distribution that is continuously biased towards lower voltages than the normal distribution P. NMIn addition, it also has a tailed distribution PFL (the densely hatched region in Figure 5), which is a distribution that has a tail on the low-voltage side. In other words, the histogram is a normal distribution P NM Based on the normal distribution P NM It has a tailed distribution PFL that continuously extends to the low-voltage side. The histogram of semiconductor device 101 (Figure 5) differs from the histogram of semiconductor device 100Q (Figure 4) in that there are no classes with zero frequency interspersed between classes with non-zero frequency. In Figure 5, the normal distribution P NM The histogram's distribution is formed by the overlap of the tailed distribution PFL on the low-voltage side. Therefore, the histogram is continuous.

[0024] The planar layout (Figure 6) has eight regions RG1 to RG8 belonging to different classes among the multiple classes shown in Figure 5. Note that the regions RG1 to RGn of the planar layout are not limited to the eight regions RG1 to RG8, but may include at least regions RG1 to RG3, and preferably regions RG1 to RG6. This also applies to Embodiment 2, which will be described later.

[0025] The frequencies of each class in the histograms of Figure 5 (and Figure 9 (of Embodiment 2, described later)) correspond to the respective areas of regions RG1 to RG8 in Figure 6. In the semiconductor device 101 of Embodiment 1 shown in Figure 6, for example, region RG2 has 16 scattered minute portions, and the total area of ​​these minute portions corresponds to the frequency of class "5.85-5.94" [V] in Figure 5. Furthermore, as in the modified semiconductor device 101M shown in Figure 7, island-like portions spanning multiple unit cells may be formed by the aggregation of minute portions.

[0026] In the example shown in Figure 5, the region RG8, which is the lowest voltage part of the tailed distribution PFL, is a normal distribution P NM They do not overlap. Therefore, the lowest voltage portion of the histogram distribution is composed solely of the tailed distribution PFL. On the other hand, the normal distribution P NMThe lowest voltage region, RG4, overlaps with the tailed distribution PFL.

[0027] Referring to Figure 8, the solid line in the graph shows an example of the transfer characteristics of semiconductor device 101 (Figure 5), and the dashed line in the graph shows an example of the transfer characteristics of semiconductor device 100P (Figure 2). Semiconductor device 101 (Figure 5) has a tailed distribution PFL on the low-voltage side, and the cells in the corresponding region turn on first during ON operation. Therefore, compared to the comparative example semiconductor device 100P, current begins to flow from a lower voltage. As the gate voltage increases, referring to Figure 5, the current gradually increases as regions RG8, RG6, RG5, RG4, and RG2 turn on in that order, then it increases sharply as the largest region RG1 turns on, and then increases slightly as regions RG3 and RG7 turn on in that order until it reaches a saturation state. Note that Figure 8 is just one example, and depending on the design, the threshold voltage of the tailed distribution PFL may differ from the threshold voltage of region RG1 by only 100mV. In that case, although it may be difficult to observe a clear inflection point like in Figure 8, the effect of the tailed distribution PFL can still be obtained.

[0028] According to this embodiment 1, the histogram (Figure 5) has a continuous distribution that is tailed towards the low-voltage side compared to a normal distribution. This suppresses the rapid rise of the current when the semiconductor device 101 is turned on. In other words, di / dt (time derivative of current) can be reduced. Therefore, radiated noise from the semiconductor device 101 can be suppressed. On the other hand, by making the proportion of region RG1, which has the largest occupied area in the active IGBT cell region 10 (Figure 1), sufficiently large, it is possible to avoid significantly increasing conduction losses due to the tailed distribution PFL. In Figure 5, the ratio of the total occupied area of ​​regions other than region RG1 to the occupied area of ​​region RG1 is, for example, 1:10 to 1:10. 7 It may be within this range. The ratio of the total occupied area of ​​other regions other than region RG1 is 1 / 10 7Even if it is suppressed to a small value, by applying the tailing distribution PFL, in a general IGBT with a saturation current of about several amperes, due to the tailing distribution PFL, 10 -7 A current on the order of A (100 nA) flows, so it is possible to easily determine the presence of the tailing distribution PFL from the waveform of the transfer characteristics.

[0029] FIG. 9 is a graph showing a histogram of the threshold voltage distribution in the planar layout of the semiconductor device 102 according to the second embodiment. The histogram (FIG. 9) of the semiconductor device 102 has a substantially normal distribution P similar to the histogram (FIG. 2) of the semiconductor device 100P NM (the region shaded coarsely in FIG. 9), while having a distribution continuously biased to the higher voltage side than the normal distribution P NM Specifically, the histogram of the semiconductor device 102 has, in addition to the normal distribution P NM further, a tailing distribution PFH (the region shaded densely in FIG. 9 ) that is a distribution trailing to the higher voltage side. In other words, the histogram has a tailing distribution PFH that continuously trails to the higher voltage side from the normal distribution P NM with the normal distribution P NM as a reference. The histogram of the semiconductor device 102 (FIG. 9) is different from the histogram of the semiconductor device 100Q (FIG. 4) in that there is no class with zero frequency intervening between classes with non-zero frequencies. In FIG. 9, the distribution of the histogram is constituted by the tailing distribution PFH overlapping on the higher voltage side of the normal distribution P NM . Therefore, the histogram is continuous.

[0030] In the example shown in FIG. 9, the region RG8, which is the highest voltage part of the tailing distribution PFH, does not overlap with the normal distribution P NM . Therefore, the highest voltage part of the histogram distribution is constituted only by the tailing distribution PFH. On the other hand, the region RG4, which is the highest voltage part of the normal distribution P NM , overlaps with the tailing distribution PFH.

[0031] Referring to Figure 10, the solid line in the graph shows an example of the transfer characteristics of semiconductor device 102 (Figure 9), and the dashed line in the graph shows an example of the transfer characteristics of semiconductor device 100P (Figure 2). Semiconductor device 102 (Figure 9) has a tailed distribution PFH on the high-voltage side, which causes a waveform different from the dashed line (comparative semiconductor device 100P) to appear near the saturation current. Cells in the corresponding region turn off earlier in the off operation. As a result, carrier sweeping is promoted compared to the comparative semiconductor device 100P.

[0032] According to this second embodiment, the histogram (Figure 9) has a continuous distribution with a tail on the high-voltage side compared to a normal distribution. This promotes the discharge of minority carriers when the semiconductor device 102 is turned off. Therefore, the turn-off loss of the semiconductor device 102 can be reduced. In addition, when the histogram of the threshold voltage changes continuously as shown in Figure 9, abrupt off operation of the entire chip (in other words, a single semiconductor substrate) constituting the semiconductor device 102 becomes less likely, thus providing an effect of suppressing voltage surges.

[0033] Note that in Figure 9, the total area occupied by the tailed distribution PFH and the normal distribution P NM The ratio of the total occupied area to the total occupied area is, for example, 1:10 to 1:10. 7 It may be within this range. The ratio of the total occupied area of ​​the tailed distribution PFH is 1 / 10 7 When the value is kept to a very small level, it can be difficult to determine the presence or absence of tailed PFH from the transfer characteristics (see Figure 10). Even in such cases, the presence or absence of tailed PFH can be determined from thermal analysis. Specifically, when the gate voltage is increased, for example, in steps of a few mV, if there is a region with a high threshold voltage inside the chip, the amount of current flowing will be lower only in that part, and heat generation will be suppressed. In other words, a distribution will be created inside the chip as a result of the thermal analysis. Generally, thermal analysis is a technique that can analyze defective areas at the unit cell level, so 1 / 10 7Even in a small region with only a small ratio, it is possible to distinguish regions with different threshold voltages. Therefore, thermal analysis is a useful means of determining whether or not the configuration of Embodiment 2 is applied. Similarly, luminescence analysis is also a useful means. It is also possible to determine whether or not the configuration of Embodiment 1 is applied using the same method.

[0034] Figure 11 is a cross-sectional view showing the specific configuration of the active IGBT cell region 10 (see Figure 1) of a semiconductor device corresponding to a typical trench gate type IGBT. Unlike Embodiments 1 or 2, each cell CM in this semiconductor device has substantially the same configuration in terms of design. Taking into account manufacturing variations, the histogram of this semiconductor device has a normally distributed PNM, similar to that of semiconductor device 100P (Figure 2).

[0035] In the active IGBT cell region 10 (see Figure 1) of the semiconductor device (Figure 11), the semiconductor substrate SB has an upper surface (first main surface) and a lower surface (second main surface). A portion of the upper surface of the semiconductor substrate SB is n + Type source layer 53 and p + Each of the contact layers 57 is formed by this. Also, at least a portion of the lower surface of the semiconductor substrate SB is formed by the p-type collector layer 55. Between the upper and lower surfaces is n - Includes drift layer 52. - Between the drift layer 52 and the p-type collector layer 55, n + Buffer layer 58 is included. - Between the drift layer 52 and the top surface, n - A charge storage layer (CS layer) 56 is included on the drift layer 52. The CS layer 56 has a higher impurity concentration than the drift layer 52. A p-type base layer 54 is included between the CS layer 56 and the top surface. Between the p-type base layer 54 and the top surface + It includes a type source layer 53 and a p+ contact layer 57.

[0036] Furthermore, the semiconductor substrate SB is provided with a gate structure 51 for switching the semiconductor device, which penetrates the p-type base layer 54 and the CS layer 56 from the top surface. The gate structure 51 has a gate electrode 51a and a gate insulating film 51b that are in contact with each other. The gate insulating film 51b is n within the trench in which the gate structure 51 is embedded. - Drift layer 52 and n + The gate insulating film 51b is in contact with the p-type source layer 53, the p-type base layer 54, and the CS layer 56, respectively. The gate insulating film 51b is, for example, an oxide film. An interlayer insulating film 60 is provided on the upper surface of the semiconductor substrate SB to insulate the gate electrode 51a from the emitter electrode (not shown in Figure 11) provided on the upper surface of the semiconductor substrate SB. A collector electrode (not shown) is provided on the lower surface of the semiconductor substrate SB.

[0037] The semiconductor device 101 or semiconductor device 102 described above can be obtained by appropriately replacing some of the multiple cells CM in the above semiconductor device with at least one type of cell having a different threshold voltage. The structure of the cells for this purpose will be described below with reference to Figure 12 or Figure 13.

[0038] Referring to Figure 12, cells CL1 to CL3 have lower threshold voltages compared to cell CM (Figure 11), while cells CH1 to CH3 have higher threshold voltages.

[0039] The p-type base layer 54a of cell CL1 has a lower impurity concentration compared to the p-type base layer 54 of cell CM (Figure 11). Conversely, the p-type base layer 54c of cell CH1 has a higher impurity concentration compared to the p-type base layer 54 of cell CM (Figure 11). By applying at least one of cell CL1 and cell CH1, the threshold voltage distribution of the semiconductor device can be controlled. In other words, the p-type base layer may have an impurity concentration distribution in its planar layout that corresponds to the threshold voltage distribution required for the semiconductor device.

[0040] The p-type base layer 54b of cell CL2 has a smaller depth from the top surface of the semiconductor substrate SB compared to the p-type base layer 54 of cell CM (Figure 11). The p-type base layer 54d of cell CH2 has a larger depth from the top surface of the semiconductor substrate SB compared to the p-type base layer 54 of cell CM (Figure 11). By applying at least one of cell CL2 and cell CH2, the threshold voltage distribution of the semiconductor device can be controlled. In other words, the p-type base layer may have a depth distribution in the planar layout that corresponds to the threshold voltage distribution required for the semiconductor device.

[0041] n of cell CL3 + The source layer 53a is n of cell CM (Figure 11). + Compared to the mold source layer 53, the depth from the top surface of the semiconductor substrate SB is greater. + The source layer 53b is n of cell CM (Figure 11). + The depth from the top surface of the semiconductor substrate SB is smaller compared to the type source layer 53. By applying at least one of cell CL3 and cell CH3, the threshold voltage distribution of the semiconductor device can be controlled. In other words, n + The type source layer may have a depth distribution in the planar layout that corresponds to the threshold voltage distribution required for the semiconductor device.

[0042] Furthermore, the threshold voltage of the cell can be lowered by reducing the thickness of the gate insulating film 51b, and raised by increasing the thickness of the gate insulating film 51b. By applying such a cell, the threshold voltage distribution of the semiconductor device can be controlled. In other words, the gate insulating film 51b may have a thickness distribution in the planar layout corresponding to the threshold voltage distribution.

[0043] Furthermore, the threshold voltage of the cell can also be controlled by the surface orientation of the channel of the gate structure 51. This will be explained below. The p-type base layer 54 of the semiconductor substrate SB has a channel region on the inner wall of the trench that faces the gate structure 51. The threshold voltage depends on the surface orientation of this portion (if the semiconductor substrate SB is a Si substrate, the crystallographic surface orientation of Si). Therefore, by applying a cell in which the surface orientation of this portion is different from that of cell CM (Figure 11), the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the portion of the p-type base layer 54 facing the gate structure 51 may have a surface orientation distribution in the planar layout that corresponds to the distribution of the threshold voltage.

[0044] Furthermore, the threshold voltage of the cell can also be controlled by the internal stress of the semiconductor substrate SB. In other words, the semiconductor substrate SB may have an internal stress distribution in its planar layout that corresponds to the threshold voltage distribution. Generally, the internal stress inherent in the channel region of a semiconductor is related to the interatomic distance, and it is known that when the interatomic distance changes, the band gap changes, and this easily changes the threshold voltage. Methods for controlling internal stress include heat treatment to mitigate ion implantation damage, gate oxide film formation conditions, interlayer insulating film type or formation conditions, emitter electrode formation conditions, glass coating film formation conditions, or polyimide coating film formation conditions. Here, the formation conditions for each element are, for example, the temperature during formation, the formation rate, the formed film thickness, or the heat treatment after formation.

[0045] Figure 13 is a cross-sectional view showing modified examples of cells CL11-CL13 and CH11-CH13 of cells CL1-CL3 and CH1-CH3 in Figure 12.

[0046] In the example shown in Figure 13, the drift layer 52 of the semiconductor substrate SB is the lifetime control layer 5 in cells CH11 to CH13. 2L This includes. Therefore, in a semiconductor device to which cells CH11~CH13 are applied, multiple regions RG1~RGn are included in the lifetime control layer 5 2LThe region where it is located, and the lifetime control layer 5 2L This may include areas where is not present. Lifetime control layer 5 2L By appropriately implementing this feature, minority carrier discharge becomes smoother, and turn-off losses are further reduced.

[0047] Furthermore, in the example shown in Figure 13, the charge storage layer 56 (Figure 12) of the semiconductor substrate SB is selectively adjusted. Specifically, the charge storage layer 56a of cells CL11 to CL13 has a different impurity concentration than the charge storage layer 56 of cell CM (Figure 11). Therefore, in a semiconductor device to which cells CL11 to CL13 are applied, multiple regions RG1 to RGn may have different impurity concentrations in the charge storage layer. By adjusting the impurity concentration distribution of the charge storage layer in this way, minority carrier discharge becomes smoother, and turn-off loss is reduced.

[0048] As mentioned above, the semiconductor device 101 or semiconductor device 102 described above can be obtained by applying at least one of the various cells described above, which have a threshold voltage different from that of cell CM (Figure 11). In addition, a cell that combines the characteristics of two or more of these multiple types of cells may be applied.

[0049] Figure 14 is a plan view showing the configuration of the planar layout of a semiconductor device 111 on a semiconductor substrate SB, according to a modified example of Figure 6. In the semiconductor device 111, the largest of the multiple regions RG1 to RGn (regions RG1 and RG2 in the illustrated example) of the planar layout, region RG1, includes the center of the semiconductor substrate SB. Region RG2 roughly surrounds region RG1. In the illustrated example, region RG2 and the gate pad region 41 surround region RG1.

[0050] The advantages of the semiconductor device 111 are explained below, divided into cases where the threshold voltage of region RG1 is higher than that of region RG2 and cases where it is lower.

[0051] Firstly, if the threshold voltage in region RG1 is relatively high, the turn-off loss in the center of the semiconductor substrate SB can be reduced. Since IGBTs generally accumulate the most heat in the center of the chip during steady-state operation, reducing the turn-off loss in the center can equalize the heat distribution in the semiconductor device 111. This equalization effect is particularly noticeable during high-speed switching. The uniform heat distribution improves the wear life of the semiconductor device 111.

[0052] Secondly, if the threshold voltage in region RG1 is relatively low, switching in the center, which tends to be farther from the gate trace 42 (see Figure 15), can be made faster. Generally, the gate signal of an IGBT tends to be delayed by the time it reaches the center of the semiconductor substrate SB. Therefore, by designing the threshold voltage of region RG1, located in the center of the semiconductor substrate SB, to be low, this delay can be compensated for. As a result, uniform switching can be achieved across the entire chip. This can be expected to increase the short-circuit withstand capability.

[0053] Therefore, with the semiconductor device 111, one of the above two effects can be obtained in both cases where the threshold voltage of region RG1 is higher than or lower than the threshold voltage of region RG2.

[0054] Figure 15 is a plan view showing the configuration of a planar layout of a semiconductor device 112 on a semiconductor substrate SB, which is a modified example of Figure 6. The semiconductor device 112 has gate wiring 42 provided on the semiconductor substrate SB. The gate wiring 42 is for applying the potential applied to the gate pad region 41 for switching to the gate electrode 51a (see Figure 11). The gate wiring 42 includes a portion that extends along one direction (the vertical direction in Figure 15). The boundaries between adjacent regions among the multiple regions RG1 to RG3 of the planar layout, in other words, the boundary between region RG1 and region RG2 and the boundary between region RG2 and region RG3, include a portion that extends along the aforementioned one direction (the vertical direction in Figure 15).

[0055] According to this modified example, if the boundaries between adjacent regions RG1 to RG3 in a planar layout include a portion extending along one direction, the arrangement of the regions RG1 to RG3 is determined according to their distance from the portion of the gate wiring that extends along one direction. In this case, if the threshold voltage is distributed such that it increases with distance from the portion of the gate wiring, the switching of regions further from the portion of the gate wiring is delayed, thereby further reducing turn-off loss. If the threshold voltage is distributed such that it decreases with distance from the portion of the gate wiring, the switching timing within the chip can be made more uniform.

[0056] Specifically, the semiconductor substrate SB has an approximately rectangular shape, and at least a portion of the boundary extends along its long or short side (the short side in the example of Figure 15). The gate traces 42 are generally arranged parallel to the long or short side of the chip. The gate signals sent from the gate traces 42 generally arrive quickly in the immediate vicinity of the gate traces 42 and slowly in the vicinity of the gate traces 42. This characteristic contributes to the suppression of turn-off loss. Therefore, the above effect can be further enhanced by setting the threshold voltage distribution so that the threshold voltage increases as the distance from the gate traces 42 increases. Conversely, by setting the threshold voltage distribution so that the threshold voltage decreases as the distance from the gate traces 42 increases, it is possible to perform uniform switching within the chip by canceling out the signal transmission delay that depends on the distance from the gate traces 42.

[0057] The semiconductor device 112 aims to achieve the above effect by providing a threshold voltage distribution that corresponds to the distance from the main portion of the gate wiring 42 (the portion extending vertically in Figure 15). To a sufficient extent to achieve this effect, the boundary is roughly aligned with the long or short side (more generally, the first direction) mentioned above. The first direction is not necessarily limited to the direction along which the long or short side of the semiconductor substrate SB aligns. For example, the first direction may be the direction in which the termination electrode pattern extends on the semiconductor substrate SB.

[0058] Figure 16 is a plan view showing the configuration of a planar layout of a semiconductor device 113 on a semiconductor substrate SB according to a modified example of Figure 6. Only the edge of the emitter electrode 50 provided on the semiconductor substrate SB is shown by a dashed line. The planar layout comprises multiple regions RG1 to RGn, the largest of which is region RG1, and region RG2 (more generally, at least one region) having a higher threshold voltage than region RG1. In the planar layout, at least a portion of the edge of the emitter electrode 50 is located in region RG2. As shown, approximately the entire edge of the emitter electrode 50 may be located in region RG2. Furthermore, region RG2 (more generally, at least one region other than region RG1) may extend along the edge of the emitter electrode 50.

[0059] This modified version allows for an increase in short-circuit withstand capability. Generally, short-circuit breakdown tends to occur at the edge of the emitter electrode 50 where current is concentrated. Therefore, by forming a region RG2 with a high threshold voltage along the edge of the emitter electrode 50, it is possible to suppress current concentration during a short circuit.

[0060] Figure 17 is a plan view showing the configuration of a planar layout of a semiconductor device 114 on a semiconductor substrate SB, which is a modified example of Figure 6. In the planar layout, the semiconductor substrate SB has a rectangular shape with a long side and a short side. In the planar layout, the boundaries between adjacent regions among the multiple regions RG1 to RGn extend along at least a portion of an ellipse. The major axis of the ellipse is aligned with the short side (vertical direction in Figure 17) of the rectangular shape. Therefore, the ellipse has a pair of opposing foci (not shown) in the direction along the short side.

[0061] Furthermore, the boundaries between adjacent regions among the multiple regions RG1 to RGn only need to substantially follow at least a portion of the ellipse; they do not need to perfectly follow a geometrically strict ellipse. The ellipse described above is a closed curve shape that is symmetrical with respect to both the X and Y directions in the XY coordinate system of the planar layout. Therefore, the boundaries described above are also substantially symmetrical with respect to both the X and Y directions. The axis of symmetry may pass approximately through the center of the semiconductor substrate SB.

[0062] The region RG1 to RGn shown in Figure 17 can be obtained due to the warp of the substrate. Figure 18 is a graph showing a hypothetical example of the threshold voltage Vth distribution along the line XVIII-XVIII in Figure 17. The solid line in the graph is a line obtained by assuming the measurement result of the warp amount of the semiconductor substrate SB and converting it to Vth. The range NA represents the region of the semiconductor substrate SB other than the active cell. The assumed measurement variation DM is also shown. The dashed line in the graph is an approximation line when the effects of the range NA and measurement variation DM are excluded. According to this approximation line, the threshold voltage distribution along the longitudinal direction of the chip has an axis of symmetry approximately in the center of the semiconductor substrate SB. Although not shown in the figure, the threshold voltage distribution along the short direction of the chip also has an axis of symmetry approximately in the center of the semiconductor substrate SB.

[0063] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0064] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0065] (Note 1) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, A semiconductor device in which, when a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include a first to a third region, and the histogram has a distribution that is based on a normal distribution and has tails that continuously fall to the lower voltage side from the normal distribution.

[0066] (Note 2) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, A semiconductor device in which, when a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the plurality of regions include a first to a third region, and the histogram has a distribution that is based on a normal distribution and has tails that continuously fall to the higher voltage side from the normal distribution.

[0067] (Note 3) A semiconductor device as described in Appendix 1 or 2, The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type. A semiconductor device wherein the base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0068] (Note 4) A semiconductor device as described in Appendix 1 or 2, The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type. A semiconductor device wherein the base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0069] (Note 5) A semiconductor device as described in Appendix 1 or 2, The semiconductor substrate further includes a source layer having the first conductivity type, A semiconductor device wherein the source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0070] (Note 6) A semiconductor device as described in Appendix 1 or 2, A semiconductor device wherein the gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0071] (Note 7) A semiconductor device as described in Appendix 1 or 2, The semiconductor substrate is provided with a trench in which the gate structure is embedded. The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and a portion facing the gate structure, wherein the portion facing the gate structure has a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0072] (Note 8) A semiconductor device described in any one of the appendices 1 to 7, A semiconductor device in which the largest of the multiple regions of the planar layout includes the center of the semiconductor substrate.

[0073] (Note 9) A semiconductor device described in any one of the appendices 1 to 7, The semiconductor substrate is provided with gate wiring for applying the switching potential to the gate electrode, including a portion that extends in one direction, A semiconductor device in which the boundaries between adjacent regions among the plurality of regions of the planar layout include portions that extend along one direction.

[0074] (Note 10) A semiconductor device described in any one of the appendices 1 to 7, The semiconductor substrate further comprises an emitter electrode having a border. The plurality of regions include the largest first region among the plurality of regions and at least one region having a higher threshold voltage than the first region. A semiconductor device in which, in the planar layout, at least a portion of the edge of the emitter electrode is located in the at least one region.

[0075] (Note 11) A semiconductor device described in any one of the appendices 1 to 7, In the aforementioned planar layout, the semiconductor substrate has a rectangular shape with a long side and a short side. A semiconductor device in which, in the planar layout, the boundaries between adjacent regions among the plurality of regions extend along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

[0076] (Note 12) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When multiple classes with a class width of 100mV are defined for the threshold voltage, the planar layout has multiple regions belonging to different classes among the multiple classes. A semiconductor device in which the largest of the multiple regions of the planar layout includes the center of the semiconductor substrate.

[0077] (Note 13) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, The semiconductor substrate is provided with gate wiring for applying the switching potential to the gate electrode, including a portion that extends in one direction, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When multiple classes with a class width of 100mV are defined for the threshold voltage, the planar layout has multiple regions belonging to different classes among the multiple classes. A semiconductor device in which the boundaries between adjacent regions among the plurality of regions of the planar layout include portions that extend along one direction.

[0078] (Note 14) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The semiconductor substrate further comprises an emitter electrode having a border, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When multiple classes with a class width of 100mV are defined for the threshold voltage, the planar layout has multiple regions belonging to different classes among the multiple classes. The plurality of regions include the largest first region among the plurality of regions and at least one region having a higher threshold voltage than the first region. A semiconductor device in which, in the planar layout, at least a portion of the edge of the emitter electrode is located in the at least one region.

[0079] (Note 15) A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When multiple classes with a class width of 100mV are defined for the threshold voltage, the planar layout has multiple regions belonging to different classes among the multiple classes. The semiconductor substrate further comprises an emitter electrode having a border. The plurality of regions includes the largest region among the plurality of regions and at least one region. In the aforementioned planar layout, the semiconductor substrate has a rectangular shape with a long side and a short side. A semiconductor device in which, in the planar layout, the boundaries between adjacent regions among the plurality of regions extend along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

[0080] (Note 16) A semiconductor device as described in any one of the appendices 1, 2, and 12 to 15, The semiconductor device is characterized in that the semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0081] (Note 17) A semiconductor device described in any one of the appendices 1 to 16, The semiconductor substrate further includes a charge storage layer on the drift layer having the first conductivity type and a higher impurity concentration compared to the drift layer. A semiconductor device in which the plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

[0082] (Note 18) A semiconductor device described in any one of the appendices 1 to 16, The drift layer of the semiconductor substrate includes a lifetime control layer. A semiconductor device in which the plurality of regions include regions where the lifetime control layer is disposed and regions where the lifetime control layer is not disposed. [Explanation of symbols]

[0083] 10 Active IGBT cell region, 41 Gate pad region, 42 Gate wiring, 50 Emitter electrode, 51 Gate structure, 51a Gate electrode, 51b Gate insulating film, 52 n - Drift layer, 53, 53a, 53b n + P-type source layers 53, 54, 54a~54d, p-type base layer, 56, 56a, charge storage layer, 59, lifetime control layer, 101, 101M, 102, 111~114, semiconductor device, RG1~RGn, 1st to nth regions, SB, semiconductor substrate.

Claims

1. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type. A semiconductor device wherein the base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

2. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type. A semiconductor device wherein the base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

3. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor substrate further includes a source layer having the first conductivity type, A semiconductor device wherein the source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

4. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, A semiconductor device wherein the gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

5. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor substrate is provided with a trench in which the gate structure is embedded. The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and a portion facing the gate structure, wherein the portion facing the gate structure has a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

6. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor device is characterized in that the semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage.

7. A semiconductor device which is an insulated-gate bipolar transistor or a reverse-conducting insulated-gate bipolar transistor, A semiconductor substrate including a drift layer having a first conductivity type, A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device, Equipped with, The planar layout on the semiconductor substrate has a threshold voltage distribution for the switching, When a histogram is defined by a plurality of classes with a class width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to the area of ​​the planar layout belonging to each of the plurality of classes, the planar layout has a plurality of regions belonging to different classes among the plurality of classes, the histogram has a distribution that is tailed continuously on the lower voltage side or the higher voltage side from the normal distribution, and the plurality of classes include a first class in which the normal distribution and the tailed distribution overlap, and a second class that is one class below or one class above the first class and deviates from the normal distribution, The semiconductor substrate further includes a charge storage layer on the drift layer having the first conductivity type and a higher impurity concentration compared to the drift layer. A semiconductor device in which the plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

8. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the largest of the multiple regions of the planar layout includes the center of the semiconductor substrate.

9. A semiconductor device according to any one of claims 1 to 5, The semiconductor substrate is provided with gate wiring for applying the switching potential to the gate electrode, including a portion that extends in one direction, A semiconductor device in which the boundaries between adjacent regions among the plurality of regions of the planar layout include portions that extend along one direction.

10. A semiconductor device according to any one of claims 1 to 5, The semiconductor substrate further comprises an emitter electrode having a border. The plurality of regions include the largest first region among the plurality of regions and at least one region having a higher threshold voltage than the first region. A semiconductor device in which, in the planar layout, at least a portion of the edge of the emitter electrode is located in the at least one region.

11. A semiconductor device according to any one of claims 1 to 5, In the aforementioned planar layout, the semiconductor substrate has a rectangular shape with a long side and a short side. A semiconductor device in which, in the planar layout, the boundaries between adjacent regions among the plurality of regions extend along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

12. A semiconductor device according to any one of claims 1 to 5, The semiconductor device is characterized in that the semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage.

13. A semiconductor device according to any one of claims 1 to 5, The semiconductor substrate further includes a charge storage layer on the drift layer having the first conductivity type and a higher impurity concentration compared to the drift layer. A semiconductor device in which the plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

14. A semiconductor device according to any one of claims 1 to 5, The drift layer of the semiconductor substrate includes a lifetime control layer. A semiconductor device in which the plurality of regions include regions where the lifetime control layer is disposed and regions where the lifetime control layer is not disposed.

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