Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving characteristics.SOLUTION: A semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first compound member and a first insulation member. The first semiconductor member contains Alx1Ga1-x1 N (0≤x1<1). The second semiconductor member contains Alx2Ga1-x2 N (0<x2≤1, x1<x2). The first compound member contains Alz1Ga1-z1 N (0<z1≤1, x2<z1). A third region of the first compound member contains crystals. At least a part of a first insulation portion of the first insulation member and at least a part of the first insulation member and a second insulation member are amorphous.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] For example, improvements in the characteristics of semiconductor devices such as transistors are desired. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Special Publication No. 2011-529639 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of improving performance. [Means for solving the problem]

[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a first compound member, and a first insulating member. The third electrode includes a first electrode portion. The position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction. The first semiconductor member is Al x1 Ga 1-x1It includes N(0≦x1<1). The first semiconductor member includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, a sixth partial region, and a seventh partial region. The direction from the first partial region to the first electrode is along a second direction that intersects the first direction. The direction from the second partial region to the second electrode is along the second direction. The direction from the third partial region to the first electrode portion is along the second direction. The position of the fourth partial region in the first direction is between the position of the first partial region in the first direction and the position of the third partial region in the first direction. The position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction. The position of the sixth partial region in the first direction is between the position of the fourth partial region in the first direction and the position of the third partial region in the first direction. The position of the seventh partial region in the first direction is between the position of the third partial region in the first direction and the position of the fifth partial region in the first direction. The second semiconductor member is Al x2 Ga 1-x2 It includes N(0<x2≦1, x1<x2). The second semiconductor member includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. The first compound member is Al z1 Ga 1-z1It includes N(0 < z1 ≤ 1, x2 < z1). The first compound member includes a first region, a second region, a third region, a fourth region, and a fifth region. The first region is between the fourth partial region and the first electrode portion in the first direction. The second region is between the first electrode portion and the fifth partial region in the first direction. The third region is between the third partial region and the first electrode portion in the second direction. The fourth region is between the first region and the third region. The fifth region is between the third region and the second region. The third region contains crystals. The first insulating member includes a first insulating portion and a second insulating portion. The first insulating portion is between the fourth partial region and the third region in the first direction. The first insulating portion is between the sixth partial region and the fourth region in the second direction. The second insulating portion is between the third region and the fifth partial region in the first direction. The second insulating portion is between the seventh partial region and the fifth region in the second direction. At least a part of the first insulating portion and at least a part of the second insulating portion are amorphous.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same reference numerals are given to the same elements as those described above with respect to the previously shown figures, and detailed descriptions are appropriately omitted.

[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor member 10, a second semiconductor member 20, a first compound member 31, and a first insulating member 41. In this example, the semiconductor device 110 includes a substrate 10S and a nitride member 10B.

[0009] The first direction D1 from the first electrode 51 to the second electrode 52 is defined as the X-axis direction. One direction perpendicular to the X-axis direction is defined as the Z-axis direction. The directions perpendicular to both the X-axis direction and the Z-axis direction are defined as the Y-axis direction.

[0010] The third electrode 53 includes the first electrode portion 53a. The position of the third electrode 53 in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second electrode 52 in the first direction D1.

[0011] The first semiconductor component 10 is Al x1 Ga 1-x1 N(0≦x1<1) is included. The composition ratio x1 may be, for example, 0 or more and 0.13 or less. The first semiconductor member 10 may be, for example, GaN. The first semiconductor member 10 does not need to contain impurities that impart conductivity.

[0012] The first semiconductor member 10 includes a first partial region 11, a second partial region 12, a third partial region 13, a fourth partial region 14, a fifth partial region 15, a sixth partial region 16, and a seventh partial region 17. The direction from the first partial region 11 to the first electrode 51 is along a second direction D2 that intersects with the first direction D1. The second direction D2 may be in the Z-axis direction.

[0013] The direction from the second partial region 12 to the second electrode 52 is along the second direction D2. The direction from the third partial region 13 to the first electrode portion 53a is along the second direction D2. The position of the fourth partial region 14 in the first direction D1 is between the position of the first partial region 11 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the fifth partial region 15 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the second partial region 12 in the first direction D1. The position of the sixth partial region 16 in the first direction D1 is between the position of the fourth partial region 14 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the seventh partial region 17 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the fifth partial region 15 in the first direction D1.

[0014] The second semiconductor member 20 contains Al x2 Ga 1-x2 N (0 < x2 ≤ 1, x1 < x2). The composition ratio x2 may be, for example, 0.15 or more and 0.35 or less. The second semiconductor member 20 is AlGaN. The second semiconductor member 20 may not contain impurities for imparting conductivity.

[0015] The second semiconductor member 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. The direction from the fifth partial region 15 to the second semiconductor portion 22 is along the second direction D2.

[0016] The first compound member 31 contains Al z1 Ga 1-z1 N (0 < z1 ≤ 1, x2 < z1). The composition ratio z1 may be 0.9 or more and 1 or less. The first compound member 31 may be, for example, AlGaN or AlN.

[0017] The first compound member 31 includes a first region 31a, a second region 31b, a third region 31c, a fourth region 31d, and a fifth region 31e. The first region 31a is located between the fourth subregion 14 and the first electrode portion 53a in the first direction D1. The second region 31b is located between the first electrode portion 53a and the fifth subregion 15 in the first direction D1. The third region 31c is located between the third subregion 13 and the first electrode portion 53a in the second direction D2. The fourth region 31d is located between the first region 31a and the third region 31c. The fifth region 31e is located between the third region 31c and the second region 31b. The third region 31c contains a crystal. At least a portion of the third region 31c contains a crystal. The third region 31c has, for example, polarization.

[0018] The first insulating member 41 includes a first insulating portion 41a and a second insulating portion 41b. The first insulating portion 41a is located between the fourth partial region 14 and the third region 31c in the first direction D1. The first insulating portion 41a is located between the sixth partial region 16 and the fourth region 31d in the second direction D2. The second insulating portion 41b is located between the third region 31c and the fifth partial region 15 in the first direction D1. The second insulating portion 41b is located between the seventh partial region 17 and the fifth region 31e in the second direction D2.

[0019] At least a portion of the first insulating portion 41a and at least a portion of the second insulating portion 41b are amorphous. These portions, for example, do not have polarization.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential referenced to the potential of the first electrode 51. The first electrode 51 functions, for example, as a source electrode. The second electrode 52 functions, for example, as a drain electrode. The third electrode 53 functions, for example, as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0021] The first semiconductor member 10 includes a portion facing the second semiconductor member 20. A carrier region 10C is formed in this portion. The carrier region 10C is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0022] In this embodiment, a third region 31c is provided. For example, the third sub-region 13 includes a portion facing the third region 31c. A carrier region 10C is formed in this portion. In the third region 31c, the Al composition ratio z1 is high. A high carrier density is obtained. For example, a low on-resistance is obtained.

[0023] In this embodiment, a first insulating portion 41a and a second insulating portion 41b are provided. In the sixth and seventh sub-regions 16 and 17 corresponding to these regions, the carrier density is low, or no carriers are generated. For example, a high threshold voltage can be stably obtained. For example, normally-off operation can be obtained. According to this embodiment, a high threshold voltage can be stably obtained. According to this embodiment, a semiconductor device with improved characteristics can be provided.

[0024] Depending on the voltage applied to the third electrode 53, carriers can flow through the sixth sub-region 16 and the seventh sub-region 17.

[0025] In the semiconductor device 110, two amorphous insulating portions (first insulating portion 41a and second insulating portion 41b) are provided. This divides the carrier region 10C at two locations, allowing for more stable control of the threshold voltage.

[0026] For example, the first region 31a and the second region 31b contain crystals. Low on-resistance is easily obtained.

[0027] At least a portion of the fourth region 31d and at least a portion of the fifth region 31e may be amorphous. For example, crystal strain is easily relieved. For example, high crystallinity is easily obtained in the third region 31c, the first region 31a, and the second region 31b.

[0028] The distance between the first electrode 51 and the third electrode 53 (first distance) is shorter than the distance between the third electrode 53 and the second electrode 52 (second distance). Stable operation is easily obtained. The first electrode 51, the second electrode 52, and the third electrode 53 may extend, for example, along a third direction D3. The third direction D3 intersects a plane containing the first direction D1 and the second direction D2. The third direction D3 may be, for example, along the Y-axis.

[0029] In this embodiment, the first electrode portion 53a is located between the fourth sub-region 14 and the fifth sub-region 15 in the first direction D1. The third electrode 53 is, for example, a recessed gate electrode. A high threshold voltage can be stably obtained.

[0030] As shown in Figure 1, the third electrode 53 may include a second electrode portion 53b. The second electrode portion 53b is connected to the first electrode portion 53a. A portion of the second electrode portion 53b overlaps with the fourth sub-region 14 in the second direction D2. Another portion of the second electrode portion 53b overlaps with the fifth sub-region 15 in the second direction D2.

[0031] As shown in Figure 1, the third electrode 53 includes a first electrode region 53F and a second electrode region 53M. At least a portion of the first electrode region 53F lies between the first semiconductor member 10 and the second electrode region 53M, and between the second semiconductor member 20 and the second electrode region 53M. The first electrode region 53F includes, for example, nitrogen and a metallic element. In one example, the first electrode region 53F includes TiN. The first electrode region 53F is, for example, an intermediate layer. The second electrode region 53M includes, for example, a metal. In one example, the second electrode region 53M includes, for example, aluminum.

[0032] The semiconductor device 110 may further include a second insulating member 42. The second insulating member 42 includes a first insulating region 42a, a second insulating region 42b, and a third insulating region 42c. The first insulating region 42a is located between the first region 31a and the first electrode portion 53a in the first direction D1. The second insulating region 42b is located between the first electrode portion 53a and the second region 31b in the first direction D1. The third insulating region 42c is provided between the third region 31c and the first electrode portion 53a, between the fourth region 31d and the first electrode portion 53a, and between the fifth region 31e and the first electrode portion 53a. The provision of the second insulating member 42 provides high insulation and stable operation.

[0033] For example, the second insulating member 42 contains silicon and oxygen. The first insulating member 41 contains silicon and nitrogen. The first insulating member 41 does not contain oxygen. Or, the oxygen concentration in the first insulating member 41 is lower than the oxygen concentration in the second insulating member 42. The first insulating member 41 contains, for example, SiN. The second insulating member 42 contains silicon oxide. The first insulating member 41 contains, for example, SiO2.

[0034] As shown in Figure 1, the first insulating member 41 may further include a third insulating portion 41c and a fourth insulating portion 41d. The first semiconductor portion 21 is located between the fourth partial region 14 and the third insulating portion 41c in the second direction D2. The second semiconductor portion 22 is located between the fifth partial region 15 and the fourth insulating portion 41d in the second direction D2.

[0035] As shown in Figure 1, the second insulating member 42 may further include a fourth insulating region 42d and a fifth insulating region 42e. The third insulating portion 41c is located between the first semiconductor portion 21 and the fourth insulating region 42d in the second direction D2. The fourth insulating portion 41d is located between the second semiconductor portion 22 and the fifth insulating region 42e in the second direction D2.

[0036] For example, the third region 31c is in contact with the third sub-region 13. The first insulating portion 41a is in contact with the sixth sub-region 16. The second insulating portion 41b is in contact with the seventh sub-region 17. The first insulating portion 41a is in contact with the fourth sub-region 14. The second insulating portion 41b is in contact with the fifth sub-region 15.

[0037] In the semiconductor device 110, a first semiconductor member 10 is provided between a substrate 10S and a second semiconductor member 20. A nitride member 10B is provided between the substrate 10S and the first semiconductor member 10. The substrate 10S may be, for example, a silicon substrate. The nitride member 10B may contain, for example, a nitride semiconductor. The nitride member 10B may contain, for example, Al, Ga, and nitrogen. The nitride member 10B is, for example, a buffer layer.

[0038] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. As shown in Figure 2, the length of the first insulating portion 41a along the first direction D1 is defined as the first insulating portion length w41a. The length of the first insulating portion 41a along the second direction D2 is defined as the first insulating portion thickness t41a. The length of the second insulating portion 41b along the first direction D1 is defined as the second insulating portion length w41b. The length of the second insulating portion 41b along the second direction D2 is defined as the second insulating portion thickness t41b.

[0039] In the embodiment, the first ratio of the length of the first insulating portion w41a to the thickness of the first insulating portion t41a is preferably 0.5 or more and 1.5 or less. The second ratio of the length of the second insulating portion w41b to the thickness of the second insulating portion t41b is preferably 0.5 or more and 1.5 or less. The electric field is effectively controlled in the corner portion including the first insulating portion 41a or the second insulating portion 41b. For example, the electric field distribution tends to be uniform at the bottom edge of the recess.

[0040] The sum of the length w41a of the first insulating portion and the thickness t41a of the first insulating portion is called the first sum. The sum of the length w41b of the second insulating portion and the thickness t41b of the second insulating portion is called the second sum. In this embodiment, the first sum may be different from the second sum. For example, the first sum may be shorter than the second sum. This allows for, for example, lowering the on-resistance on the side of the first electrode 51 (source electrode).

[0041] In one example, the length of the first insulating portion w41a is between 5 nm and 200 nm. The length of the second insulating portion w41b is between 5 nm and 200 nm.

[0042] The length of the third region 31c along the first direction D1 is defined as the third region length w31c. For example, the third region length w31c may be longer than the first insulation portion length w41a. The third region length w31c may be longer than the second insulation portion length w41b. For example, the ratio of the first insulation portion length w41a to the third region length w31c may be between 0.01 and 0.5. For example, the ratio of the first insulation portion length w41a to the third region length w31c may be 0.3 or less. The ratio of the second insulation portion length w41b to the third region length w31c may be between 0.01 and 0.5. The ratio of the second insulation portion length w41b to the third region length w31c may be 0.3 or less.

[0043] The first insulating portion thickness t41a may be, for example, 5 nm to 700 nm. The second insulating portion thickness t41b may be, for example, 5 nm to 700 nm.

[0044] As shown in Figure 2, the length of the first region 31a along the second direction D2 is defined as the first region length L31a. The first region length L31a may be, for example, 150 nm or more. The first region length L31a may be, for example, 500 nm or less. The length of the second region 31b along the second direction D2 is defined as the second region length L31b. The second region length L31b may be, for example, 150 nm or more. The second region length L31b may be, for example, 500 nm or less. For example, a high threshold voltage can be easily and stably obtained.

[0045] As shown in Figure 1, the fourth subregion 14 includes a first portion 14a in contact with the first region 31a and a second portion 14b in contact with the first insulating portion 41a. The first crystallinity of the first portion 14a may be higher than the second crystallinity of the second portion 14b. The fourth subregion 14 further includes a third portion 14c in contact with the fourth region 31d. For example, the third crystallinity of the third portion 14c may be lower than the first crystallinity. Crystal strain is easily relieved. For example, high crystallinity is easily obtained in the first portion 14a and the first region 31a. Low on-resistance is easily obtained.

[0046] As shown in Figure 1, the fifth subregion 15 includes a fourth portion 15d in contact with the second region 31b and a fifth portion 15e in contact with the second insulating portion 41b. The fourth crystallinity of the fourth portion 15d may be higher than the fifth crystallinity of the fifth portion 15e. The fifth subregion 15 further includes a sixth portion 15f in contact with the fifth region 31e. For example, the sixth crystallinity of the sixth portion 15f may be lower than the fourth crystallinity. Crystal strain is easily relieved. For example, high crystallinity is easily obtained in the fourth portion 15d and the second region 31b. Low on-resistance is easily obtained.

[0047] In the embodiment, when the gate is off, the resistance is high, and the effect of raising the threshold voltage due to the voltage drop is large. When the gate is on, the resistance decreases at both ends of the bottom of the recess. A high threshold voltage is obtained when the gate is off, and a low on-resistance is obtained when the gate is on.

[0048] The above configuration of the semiconductor device 110 can be formed, for example, by the following process: A trench is formed in a structure including the first semiconductor member 10 and the second semiconductor member 20. An insulating film is formed inside the trench. A first insulating portion 41a is obtained from a part of the insulating film. A second insulating portion 41b is obtained from another part of the insulating film. Subsequently, the first compound member 31 and the second insulating member 42 are formed. The first electrode portion 53a of the third electrode 53 is formed in the remaining space of the trench.

[0049] In the embodiment, information regarding length and thickness is obtained by electron microscopy observation or the like. Information regarding the material composition is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy) or the like.

[0050] The embodiments may include the following technical proposals. (Technical proposal 1) First electrode and, The second electrode and, A third electrode including a first electrode portion, wherein the position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, Al x1 Ga 1-x1 A first semiconductor member comprising N(0≦x1<1), wherein the first semiconductor member includes a first subregion, a second subregion, a third subregion, a fourth subregion, a fifth subregion, a sixth subregion, and a seventh subregion, the direction from the first subregion to the first electrode is along a second direction intersecting the first direction, the direction from the second subregion to the second electrode is along the second direction, the direction from the third subregion to the first electrode portion is along the second direction, and the position of the fourth subregion in the first direction is the same as the position of the first subregion in the first direction and the position of the third subregion in the first direction The position of the region and the position of the fifth subregion in the first direction are between the position of the third subregion in the first direction and the position of the second subregion in the first direction, the position of the sixth subregion in the first direction are between the position of the fourth subregion in the first direction and the position of the third subregion in the first direction, and the position of the seventh subregion in the first direction are between the position of the third subregion in the first direction and the position of the fifth subregion in the first direction, the first semiconductor member and Al x2 Ga 1-x2A second semiconductor member including N(0 < x2 ≤ 1, x1 < x2), wherein the second semiconductor member includes a first semiconductor portion and a second semiconductor portion, and the direction from the fourth partial region to the first semiconductor portion is along the second direction, and the direction from the fifth partial region to the second semiconductor portion is along the second direction, the second semiconductor member, Al z1 Ga 1-z1 A first compound member including N(0 < z1 ≤ 1, x2 < z1), wherein the first compound member includes a first region, a second region, a third region, a fourth region, and a fifth region, the first region is between the fourth partial region and the first electrode portion in the first direction, the second region is between the first electrode portion and the fifth partial region in the first direction, the third region is between the third partial region and the first electrode portion in the second direction, the fourth region is between the first region and the third region, the fifth region is between the third region and the second region, and the third region includes a crystal, the first compound member, A first insulating member, wherein the first insulating member includes a first insulating portion and a second insulating portion, the first insulating portion is between the fourth partial region and the third region in the first direction, the first insulating portion is between the sixth partial region and the fourth region in the second direction, the second insulating portion is between the third region and the fifth partial region in the first direction, the second insulating portion is between the seventh partial region and the fifth region in the second direction, and at least a part of the first insulating portion and at least a part of the second insulating portion are amorphous, the first insulating member, A semiconductor device comprising the above.

[0051] (Technical solution 2) The semiconductor device according to Technical solution 1, wherein the first region and the second region include a crystal.

[0052] (Technical solution 3) The semiconductor device according to Technical solution 2, wherein at least a part of the fourth region and at least a part of the fifth region are amorphous.

[0053] (Technical proposal 4) Further comprising a second insulating member, The second insulating member includes a first insulating region, a second insulating region, and a third insulating region. The first insulating region is located between the first region and the first electrode portion in the first direction. The second insulating region is located between the first electrode portion and the second region in the first direction. The semiconductor device according to any one of Technical Proposals 1 to 3, wherein the third insulating region is provided between the third region and the first electrode portion, between the fourth region and the first electrode portion, and between the fifth region and the first electrode portion.

[0054] (Technical proposal 5) The second insulating member comprises silicon and oxygen, The first insulating member contains silicon and nitrogen, The semiconductor device according to Technical Proposal 4, wherein the first insulating member does not contain oxygen, or the concentration of oxygen in the first insulating member is lower than the concentration of oxygen in the second insulating member.

[0055] (Technical proposal 6) The first insulating member further includes a third insulating portion and a fourth insulating portion, The first semiconductor portion is located between the fourth subregion and the third insulating portion in the second direction. The semiconductor device according to Technical Proposal 4 or 5, wherein the second semiconductor portion is located between the fifth partial region and the fourth insulating portion in the second direction.

[0056] (Technical proposal 7) The second insulating member further includes a fourth insulating region and a fifth insulating region, The third insulating portion is located between the first semiconductor portion and the fourth insulating region in the second direction. The semiconductor device according to Technical Proposal 6, wherein the fourth insulating portion is located between the second semiconductor portion and the fifth insulating region in the second direction.

[0057] (Technical proposal 8) The length of the first region along the second direction of the first region is 150 nm or more. The semiconductor device according to any one of Technical Proposals 1 to 7, wherein the length of the second region along the second direction of the second region is 150 nm or more.

[0058] (Technical proposal 9) The first distance between the first electrode and the third electrode is shorter than the second distance between the third electrode and the second electrode. The first sum is shorter than the second sum. The first sum is the sum of the length of the first insulating portion along the first direction of the first insulating portion and the thickness of the first insulating portion along the second direction of the first insulating portion. The semiconductor device according to any one of Technical Proposals 1 to 8, wherein the second sum is the sum of the second insulating portion length along the first direction of the second insulating portion and the second insulating portion thickness along the second direction of the second insulating portion.

[0059] (Technical proposal 10) The first ratio of the length of the first insulating portion along the first direction of the first insulating portion to the thickness of the first insulating portion along the second direction of the first insulating portion is 0.5 or more and 1.5 or less. A semiconductor device according to any one of Technical Proposals 1 to 8, wherein the second ratio of the length of the second insulating portion along the first direction of the second insulating portion to the thickness of the second insulating portion along the second direction of the second insulating portion is 0.5 or more and 1.5 or less.

[0060] (Technical proposal 11) The length of the first insulating portion along the first direction of the first insulating portion is 5 nm or more and 200 nm or less. The semiconductor device according to any one of Technical Proposals 1 to 8, wherein the length of the second insulating portion along the first direction of the second insulating portion is 5 nm or more and 200 nm or less.

[0061] (Technical proposal 12) The ratio of the length of the first insulating portion of the first insulating portion along the first direction to the length of the third region along the first direction of the third region is 0.01 or more and less than 0.5. The semiconductor device according to any one of Technical Proposals 1 to 8, wherein the ratio of the length of the second insulating portion along the first direction of the second insulating portion to the length of the third region is 0.01 or more and less than 0.5.

[0062] (Technical proposal 13) The thickness of the first insulating portion along the second direction of the first insulating portion is 5 nm or more and 700 nm or less. The semiconductor device according to any one of Technical Proposals 1 to 8, wherein the thickness of the second insulating portion along the second direction of the second insulating portion is 5 nm or more and 700 nm or less.

[0063] (Technical proposal 14) The first electrode portion is located between the fourth subregion and the fifth subregion in the first direction, as described in any one of the technical proposals 1 to 13, for the semiconductor device.

[0064] (Technical proposal 15) The third region is adjacent to the third subregion, The first insulating portion is in contact with the sixth partial region, The second insulating portion is in contact with the seventh partial region, and is a semiconductor device according to any one of the technical proposals 1 to 14.

[0065] (Technical proposal 16) The aforementioned fourth subregion is, The first portion in contact with the first region, The second portion in contact with the first insulating portion, Includes, The semiconductor device according to any one of Technical Proposals 1 to 15, wherein the first crystallinity of the first part is higher than the second crystallinity of the second part.

[0066] (Technical proposal 17) The fourth sub-region further includes a third sub-region adjacent to the fourth sub-region, The semiconductor device according to Technical Proposal 16, wherein the third crystallinity of the third portion is lower than that of the first crystallinity.

[0067] (Technical proposal 18) The aforementioned fifth subregion is, A fourth portion adjacent to the second region, A fifth portion in contact with the second insulating portion, Includes, The semiconductor device according to any one of Technical Proposals 1 to 17, wherein the fourth crystallinity of the fourth part is higher than the fifth crystallinity of the fifth part.

[0068] (Technical proposal 19) The fifth sub-region further includes a sixth sub-region adjacent to the fifth sub-region, The semiconductor device according to Technical Proposal 18, wherein the sixth crystallinity of the sixth portion is lower than that of the fourth crystallinity.

[0069] (Technical proposal 20) The semiconductor device described in any one of Technical Proposals 1 to 19, wherein z1 is between 0.9 and 1.

[0070] According to the embodiment, a semiconductor device capable of improving characteristics can be provided.

[0071] In the embodiment, "nitride semiconductor" is B x In y Al z Ga 1-x-y-z This includes semiconductors of all compositions obtained by varying the compositional ratios of x, y, and z within the respective ranges in the chemical formula N(0≦x≦1,0≦y≦1,0≦z≦1,x+y+z≦1). "Nitride semiconductors" also include semiconductors that further contain group V elements other than N (nitrogen) in the above chemical formula, semiconductors that further contain various elements added to control various physical properties such as conductivity, and semiconductors that further contain various elements unintentionally.

[0072] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element included in a semiconductor device, such as semiconductor members, electrodes, and insulating members, is included within the scope of the present invention as long as it can be implemented in the same way and similar effects can be obtained by appropriately selecting from the range known to those skilled in the art.

[0073] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0074] Furthermore, all semiconductor devices and their manufacturing methods that can be implemented by those skilled in the art by appropriately modifying the design based on the semiconductor device and its manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0075] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention.

[0076] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0077] 10, 20: First and second semiconductor components, 10B: Nitride component, 10C: Carrier region, 10S: Substrate, 11-17: First to sixth subregions, 14a-14c: First to third subregions, 15d-15f: Fourth to sixth subregions, 21, 22: First and second semiconductor subregions, 31: First compound component, 31a-31e: First to fifth regions, 41, 42: First and second insulating components, 41a-41d: First to fourth insulating subregions, 42a-42e: First to fifth insulating regions, 51-53: First to third electrodes, 53F: First electrode region, 53M: Second electrode region, 53a, 53b: First and second electrode subregions, 110: Semiconductor device, D1-D3: First to third directions L31a, L31b: First and second region lengths, t41a, t41b: First and second insulation portion thicknesses, w31c: Third region length, w41a, w41b: First and second insulation portion lengths

Claims

1. First electrode and The second electrode and A third electrode including a first electrode portion, wherein the position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction, Al ｘ１ Ga １－ｘ１ A first semiconductor member comprising N (0 ≤ x1 < 1), wherein the first semiconductor member includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, a sixth partial region and a seventh partial region, the direction from the first partial region to the first electrode is along a second direction intersecting the first direction, the direction from the second partial region to the second electrode is along the second direction, the direction from the third partial region to the first electrode portion is along the second direction, and the position of the fourth partial region in the first direction is the same as the position of the first partial region in the first direction and the position of the third partial region in the first direction The position of the region and the position of the fifth subregion in the first direction are between the position of the third subregion in the first direction and the position of the second subregion in the first direction, the position of the sixth subregion in the first direction are between the position of the fourth subregion in the first direction and the position of the third subregion in the first direction, and the position of the seventh subregion in the first direction are between the position of the third subregion in the first direction and the position of the fifth subregion in the first direction, the first semiconductor member and Al ｘ２ Ga １－ｘ２ A second semiconductor member comprising N (0 < x² ≤ 1, x1 < x²), wherein the second semiconductor member includes a first semiconductor portion and a second semiconductor portion, the direction from the fourth partial region to the first semiconductor portion is along the second direction, and the direction from the fifth partial region to the second semiconductor portion is along the second direction, Al ｚ１ Ga １－ｚ１ A first compound member comprising N (0 < z1 ≤ 1, x2 < z1), wherein the first compound member comprises a first region, a second region, a third region, a fourth region and a fifth region, the first region being located between the fourth subregion and the first electrode portion in the first direction, the second region being located between the first electrode portion and the fifth subregion in the first direction, the third region being located between the third subregion and the first electrode portion in the second direction, the fourth region being located between the first region and the third region, the fifth region being located between the third region and the second region, and the third region comprising a crystal, the first compound member and A first insulating member comprising a first insulating portion and a second insulating portion, wherein the first insulating portion is located between the fourth partial region and the third region in the first direction, the first insulating portion is located between the sixth partial region and the fourth region in the second direction, the second insulating portion is located between the third region and the fifth partial region in the first direction, the second insulating portion is located between the seventh partial region and the fifth region in the second direction, and at least a portion of the first insulating portion and at least a portion of the second insulating portion are amorphous, the first insulating member, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the first region and the second region include crystals.

3. The semiconductor device according to claim 2, wherein at least a portion of the fourth region and at least a portion of the fifth region are amorphous.

4. Further comprising a second insulating member, The second insulating member includes a first insulating region, a second insulating region, and a third insulating region. The first insulating region is located between the first region and the first electrode portion in the first direction. The second insulating region is located between the first electrode portion and the second region in the first direction. The semiconductor device according to claim 1, wherein the third insulating region is provided between the third region and the first electrode portion, between the fourth region and the first electrode portion, and between the fifth region and the first electrode portion.

5. The second insulating member comprises silicon and oxygen, The first insulating member contains silicon and nitrogen, The semiconductor device according to claim 4, wherein the first insulating member does not contain oxygen, or the concentration of oxygen in the first insulating member is lower than the concentration of oxygen in the second insulating member.

6. The first insulating member further includes a third insulating portion and a fourth insulating portion, The first semiconductor portion is located between the fourth subregion and the third insulating portion in the second direction. The semiconductor device according to claim 4, wherein the second semiconductor portion is located between the fifth partial region and the fourth insulating portion in the second direction.

7. The second insulating member further includes a fourth insulating region and a fifth insulating region, The third insulating portion is located between the first semiconductor portion and the fourth insulating region in the second direction. The semiconductor device according to claim 6, wherein the fourth insulating portion is located between the second semiconductor portion and the fifth insulating region in the second direction.

8. The length of the first region along the second direction of the first region is 150 nm or more. The semiconductor device according to claim 1, wherein the length of the second region along the second direction of the second region is 150 nm or more.

9. The first distance between the first electrode and the third electrode is shorter than the second distance between the third electrode and the second electrode. The first sum is shorter than the second sum. The first sum is the sum of the length of the first insulating portion along the first direction of the first insulating portion and the thickness of the first insulating portion along the second direction of the first insulating portion. The semiconductor device according to any one of claims 1 to 8, wherein the second sum is the sum of the second insulating portion length along the first direction of the second insulating portion and the second insulating portion thickness along the second direction of the second insulating portion.

10. The first ratio of the length of the first insulating portion along the first direction of the first insulating portion to the thickness of the first insulating portion along the second direction of the first insulating portion is 0.5 or more and 1.5 or less. The semiconductor device according to any one of claims 1 to 8, wherein the second ratio of the length of the second insulating portion along the first direction of the second insulating portion to the thickness of the second insulating portion along the second direction of the second insulating portion is 0.5 or more and 1.5 or less.

11. The semiconductor device according to any one of claims 1 to 8, wherein the first electrode portion is located between the fourth subregion and the fifth subregion in a first direction.

12. The aforementioned third region is in contact with the aforementioned third subregion, The first insulating portion is in contact with the sixth partial region, The semiconductor device according to any one of claims 1 to 8, wherein the second insulating portion is in contact with the seventh partial region.

13. The aforementioned fourth subregion is, The first portion in contact with the first region, The second portion in contact with the first insulating portion, Includes, The semiconductor device according to any one of claims 1 to 8, wherein the first crystallinity of the first portion is higher than the second crystallinity of the second portion.

14. The fourth sub-region further includes a third sub-region adjacent to the fourth sub-region, The semiconductor device according to claim 13, wherein the third crystallinity of the third portion is lower than that of the first crystallinity.

15. The aforementioned fifth subregion is, A fourth portion in contact with the second region, A fifth portion in contact with the second insulating portion, Includes, The semiconductor device according to any one of claims 1 to 8, wherein the fourth crystallinity of the fourth portion is higher than the fifth crystallinity of the fifth portion.

16. The fifth sub-region further includes a sixth sub-region adjacent to the fifth sub-region, The semiconductor device according to claim 15, wherein the sixth crystallinity of the sixth portion is lower than the fourth crystallinity.

17. The semiconductor device according to any one of claims 1 to 8, wherein z1 is 0.9 or more and 1 or less.

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