Thin-film transistor substrate and display device including the same

Abstract

To prevent the problem of shortening the channel length when an oxide semiconductor layer is made into a conductor, and to suppress the negative (-) shift of the threshold voltage (Vth).SOLUTION: A thin-film transistor substrate includes a substrate 100, an active layer 130 provided on the substrate, a gate electrode 150 provided on the active layer, a source electrode 171 connected to one side of the active layer, and a drain electrode 172 connected to the other side of the active layer, and the gate electrode includes a body 151 and at least one first protrusion 152a provided on one side of the body, and at least one first protrusion is superimposed on the active layer.SELECTED DRAWING: Figure 5B

Description

Technical Field

[0001] The present invention relates to a thin film transistor substrate and a display device including the same.

Background Art

[0002] Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is widely used as a switching element or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] In a display panel for driving an organic light emitting device (OLED), various types of thin film transistors such as a display area thin film transistor for emitting light from each pixel that emits light, a Logic-GIP thin film transistor for controlling the display area thin film transistor, and a Buffer-GIP thin film transistor for controlling the supply of overall power can be used.

[0004] In order to realize a high-mobility element, in a thin film transistor having a top gate structure, a conducting process for making an oxide semiconductor layer conductive can be performed using a gate electrode as a mask. However, in such a conducting process of the oxide semiconductor layer, the region made conductive may penetrate excessively, and the channel region may be formed smaller than the region where it is set, thereby shortening the channel length and causing the threshold voltage (Vth) to shift in the negative (-) direction (negative shift). In particular, when the width of the oxide semiconductor layer is large, the degree of penetration of the region made conductive increases, and the channel length can be further shortened.

[0005] If the threshold voltage (Vth) shifts in the negative direction, leakage current may occur in the initial image. As a result, the leakage current may cause the panel equipped with thin-film transistors to malfunction, potentially leading to increased power consumption of the panel. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The present invention was devised to solve the above-mentioned conventional problems, and aims to provide a thin-film transistor substrate and a display device including the same that can prevent the problem of shortening the channel length when the oxide semiconductor layer is made conductive, and can suppress the negative shift of the threshold voltage (Vth). [Means for solving the problem]

[0007] To achieve the above objective, the present invention provides a thin-film transistor substrate and a display device including the same, comprising a substrate, an active layer provided on the substrate, a gate electrode provided on the active layer, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer, wherein the gate electrode comprises a body portion and at least one first protrusion provided on one side of the body portion, superimposed on the active layer on a plane.

[0008] Furthermore, the present invention provides a display device comprising a substrate, an active layer provided on the substrate, a gate electrode provided on the active layer, a source electrode provided on one side of the active layer, and a drain electrode provided on the other side of the active layer, wherein the gate electrode includes a body portion and at least one first protrusion provided on a first side surface of the body portion, and the at least one first protrusion is superimposed on the active layer, a thin-film transistor substrate, a gate driver connected to the thin-film transistor substrate and transmitting a gate signal to the thin-film transistor substrate, and a data driver connected to the thin-film transistor substrate and transmitting a data signal to the thin-film transistor substrate. [Effects of the Invention]

[0009] According to the present invention as described above, the following effects are obtained.

[0010] According to one embodiment of the present invention, by providing protrusions on one and the other side of the gate electrode in a thin-film transistor with a top gate structure, it is possible to control the region in which the active layer superimposed on the gate electrode becomes conductive during the process of making the active layer conductive.

[0011] According to one embodiment of the present invention, since the region in which the active layer becomes conductive can be controlled, the phenomenon of shortening of the channel length can be controlled even in the case of a thin-film transistor having a wide active layer.

[0012] According to one embodiment of the present invention, since the region in which the active layer is made conductive can be controlled, elements with short channel lengths can be reliably realized in an active layer with a wide width. In other words, since the channel length is not excessively short, a thin-film transistor substrate that realizes the characteristics as designed can be provided.

[0013] According to one embodiment of the present invention, in a thin-film transistor with a top gate structure, protrusions are provided on one and the other sides of the gate electrode, and the active layer is provided with active holes that do not overlap with the protrusions of the gate electrode. This makes it possible to control the region of the active layer that overlaps with the gate electrode and becomes conductive during the process of making the active layer conductive.

[0014] According to one embodiment of the present invention, by controlling the conductive region within the channel region through the protrusions of the gate electrode and the active holes of the active layer, it is possible to prevent the threshold voltage (Vth) of a thin-film transistor having a wide channel from shifting to a negative (-).

[0015] According to one embodiment of the present invention, by preventing the threshold voltage (Vth) from shifting to a negative (-) state, leakage current of the thin-film transistor of a high-mobility element can be prevented, and furthermore, the power consumption of the panel equipped with the thin-film transistor can be reduced. In short, a low-power thin-film transistor substrate can be manufactured.

[0016] The effects of the present invention are not limited to those described above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description. [Brief explanation of the drawing]

[0017] [Figure 1A] This is a plan view of a thin-film transistor substrate according to one embodiment of the present invention. [Figure 1B] This is a plan view of a thin-film transistor substrate according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view of a thin-film transistor substrate according to one embodiment of the present invention, and is a cross-sectional view taken along the line I-I' in Figure 1B. [Figure 3] This is a cross-sectional view of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 4]When using the thin-film transistor according to an embodiment of the present invention, it is a Vgs-Ids graph showing how Vth changes compared to the conventional thin-film transistor. [Figure 5A] It is a plan view of a thin-film transistor substrate according to another embodiment of the present invention. [Figure 5B] It is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention, and it is a cross-sectional view taken along line II-II' of FIG. 5A. [Figure 6] It is a plan view of a thin-film transistor substrate according to another embodiment of the present invention. [Figure 7] It is a plan view of a thin-film transistor substrate according to another embodiment of the present invention. [Figure 8] It is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention, and it is a cross-sectional view taken along line III-III' of FIG. 7. [Figure 9] It is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention, and it is a cross-sectional view taken along line III-III' of FIG. 7. [Figure 10] It is a cross-sectional view of a display device including a thin-film transistor substrate according to an embodiment of the present invention. [Figure 11] It is a schematic view of a display device according to an embodiment of the present invention. [Figure 12] It is a circuit diagram of a shift register according to an embodiment of the present invention. [Figure 13] It is a circuit diagram of one pixel provided in a display device according to an embodiment of the present invention. [Figure 14] It is a circuit diagram of one pixel provided in a display device according to another embodiment of the present invention. [Figure 15] It is a circuit diagram of one pixel provided in a display device according to another embodiment of the present invention.

Mode for Carrying Out the Invention

[0018] The advantages and features of the present invention, as well as methods for achieving them, will become apparent by referring to the embodiments described below in detail with accompanying figures. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains of the invention of the scope of the invention, and the present invention is defined only by the claims.

[0019] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the figures illustrating embodiments of the present invention are illustrative, and the present invention is not limited to those shown in the figures. Throughout the specification, the same reference numeral may refer to the same component. In the description of the present invention, if a specific description of the relevant prior art is deemed to unnecessarily obscure the gist of the invention, such detailed description will be omitted. Where "includes," "has," "consists of," etc., as used herein, other parts may be added unless "only" is used. When a component is expressed singly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0020] In interpreting the constituent elements, even without further explicit mention, they shall be interpreted as including a margin of error.

[0021] When describing the positional relationship between two parts, for example, using phrases like "above," "above," "below," or "next to," one or more other parts can be located between the two parts, unless the expressions "immediately" or "directly" are used.

[0022] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0023] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of the present invention.

[0024] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or as a whole, and are technically capable of various interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or together in a related manner.

[0025] Preferred embodiments of the present invention will be described in detail below with reference to the figures.

[0026] Figures 1A and 1B are plan views of a thin-film transistor substrate according to one embodiment of the present invention. Here, Figure 1A shows the active layer 130 before the conductor formation process is carried out, and Figure 1B shows the active layer 130 after the conductor formation process has been carried out, with the active layer 130 including a channel area 131, a source region 132a, and a drain region 132b.

[0027] As shown in Figures 1A and 1B, a thin-film transistor substrate according to one embodiment of the present invention includes an active layer 130, a gate electrode 150 superimposed on the active layer 130, a source electrode 171 provided on one side of the active layer 130, and a drain electrode 172 provided on the other side of the active layer 130.

[0028] The active layer 130 may extend in a first direction, for example, the lateral direction, and the gate electrode 150 may extend in a second direction, for example, the vertical direction, but is not necessarily limited to these.

[0029] The thin-film transistor according to the present invention can consist of a top-gate structure in which a gate electrode 150 is provided on an active layer 130. In the top-gate structure, the gate electrode 150 can be used as a mask to carry out a conductorization process on a portion of the active layer 130 that is not covered by the gate electrode 150. Through the conductorization process, the active layer 130 can include a channel portion 131, a source region 132a, and a drain region 132b.

[0030] The conductive process refers to a process of increasing the electron concentration in a portion of the active layer 130, which is made of an oxide semiconductor, for example, a process of performing plasma treatment during the etching of the gate insulating film or a process of doping with dopant ions. As the conductive process proceeds, the electron concentration in a portion of the active layer 130 increases, and its conductivity improves, becoming the same as that of a conductor. When the conductive process is carried out by doping with dopant ions, the dopant ions may be boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0031] According to one embodiment of the present invention, a conductive process, such as a doping process with dopant ions, can be carried out using the gate electrode 150 as a mask. In this case, the active layer 130 can have regions that are superimposed on the gate electrode 150 but are not doped with dopant, such as the channel portion 131, and regions that are not superimposed on the gate electrode 150 but are doped with dopant, such as the source region 132a and the drain region 132b. On the other hand, the conductive process is not limited to a dopant doping process and can include a conductive process by plasma treatment.

[0032] As the conductive process progresses, dopant ions can diffuse into the active layer 130 superimposed on the gate electrode 150. Therefore, dopant ions are doped into the portion of the active layer 130 that does not superimpose on the gate electrode 150, forming a part of the source region 132a and a part of the drain region 132b. At the same time, dopant ions are also doped into a part of the active layer 130 that superimposes on the gate electrode 150, forming the remaining portions of the source region 132a and drain region 132b, specifically the first convex portion 133a and the second convex portion 133b.

[0033] If the thin-film transistor substrate includes only the main body portion 151 of the gate electrode 150 without the first protrusion 152a, the degree to which dopant ions diffuse into the active layer 130 superimposed on the gate electrode 150 during the conduction process will increase, potentially increasing the size of the first protrusion 133a. This could ultimately lead to the channel portion 131 being too short.

[0034] If the length of the channel portion 131 becomes too short, the threshold voltage (Vth) may shift to the negative (-) direction, which can cause leakage current to flow in the thin-film transistor substrate equipped with the active layer 130. When leakage current flows, the switching function of the thin-film transistor may not operate properly, and errors may occur in the quality of the initial image. Therefore, it is necessary to control the length of the channel portion 131 so that it is not formed to be too short in order to prevent the threshold voltage (Vth) from shifting to the negative (-) direction.

[0035] According to one embodiment of the present invention, by providing the gate electrode 150 with a first projection 152a on one side of the main body 151, the amount of dopant that diffuses into the active layer 130 superimposed on the gate electrode 150 can be adjusted to be less. This prevents the dopant from diffusing into the active layer 130 superimposed on the gate electrode 150, thereby preventing the first protrusion 133a from becoming too large. Therefore, according to one embodiment of the present invention, the size of the first protrusion 133a can be reduced, and the length of the channel portion 131 can not be made too short.

[0036] The configuration of the gate electrode 150 and the active layer 130 according to one embodiment of the present invention will be described in more detail below.

[0037] The main body portion 151 of the gate electrode 150 can overlap with the active layer 130, particularly the channel portion 131, and extend in a second direction.

[0038] As an example of one side of the main body 151, at least one first projection 152a is provided on the left side facing the source electrode 171. The at least one first projection 152a extends in a first direction from the main body 151, particularly toward the source electrode 171. On the other hand, as an example of the other side of the main body 151, a separate projection may not be provided on the right side facing the drain electrode 172.

[0039] Therefore, the gate electrode 150 can be formed asymmetrically on one side and the other side with respect to the main body 151. However, the structure of the gate electrode 150 is not limited to this, and as can be seen from the embodiment shown in Figure 5A, a projection can also be formed on the other side of the main body 151.

[0040] The main body portion 151 and at least one first projection 152a can be used as a mask during the process of making a portion of the active layer 130 conductive. Here, since one side of the main body portion 151 is provided with at least one first projection 152a, while the other side of the main body portion 151 is not provided with any additional projection 152a, the conductive region of the active layer 130 can be formed asymmetrically around the channel portion 131.

[0041] The areas of the active layer 130 not covered by the main body 151 and the first projection 152a are made conductive and become the source area 132a and the drain area 132b. The source area 132a is provided on the left side of the non-conducting channel portion 131, and the drain area 132b is provided on the right side of the non-conducting channel portion 131.

[0042] On the other hand, the region of the active layer 130 covered by the main body 151 and the first protrusion 152a must not be made conductive. However, for example, as the process actually progresses, the dopant ions doped during the conductivity process begin to diffuse into the interior of a portion of the active layer 130 covered by the main body 151 and the first protrusion 152a. Therefore, as an example, the region of the active layer 130 superimposed on the first protrusion 152a becomes conductive and constitutes the source region 132a.

[0043] Furthermore, a portion of the active layer 130 superimposed on the main body 151 is made conductive, forming the first protrusion 133a and the second protrusion 133b of the active layer 130.

[0044] The first protrusion 133a overlaps with the left end of the main body 151, and the second protrusion 133b overlaps with the right end of the main body 151. Here, since the left side of the main body 151 is provided with multiple first protrusions 152a, multiple first protrusions 133a are formed in the region that overlaps with the left end of the main body 151. In contrast, since the right side of the main body 151 is not provided with first protrusions 152a, one second protrusion 133b is formed in the region that overlaps with the right end of the main body 151.

[0045] On the other hand, the channel portion 131 of the active layer 130 corresponds to the non-conducting region excluding the source region 132a, the drain region 132b, the first protrusion 133a, and the second protrusion 133b. Here, the first protrusion 133a and the second protrusion 133b shorten the left-right length of the channel portion 131. However, according to one embodiment of the present invention, since the gate electrode 150 includes the first protrusion 152a, the left-right length of the channel portion 131 extending from the first protrusion 152a in the left-right direction is relatively increased.

[0046] Specifically, by providing multiple first protrusions 152a, the conductive region, for example, the region where dopant ions diffuse, is reduced, and the size of the first convex portion 133a is relatively reduced. Therefore, the size of the first convex portion 133a is formed to be smaller than the size of the second convex portion 133b. As a result, the length of the channel portion 131 in the region where the first convex portion 133a is formed becomes relatively longer.

[0047] Furthermore, since the first protrusion 152a is provided, the active layer 130 may not be conductive in the region between the multiple first protrusions 133a. Therefore, the length of the channel portion 131 in the region between the multiple first protrusions 133a becomes relatively longer.

[0048] As a result, multiple first protrusions 152a provided on one side of the main body 151, for example on the left side, can form multiple first convex portions 133a in the source region 132a while being separated from each other at predetermined intervals, and the left and right lengths of the channel portion 131 in the region where the multiple first convex portions 133a are separated become relatively longer.

[0049] When the length of the channel portion 131 is relatively longer, the problem of the channel portion 131 becoming too short is prevented, and the problem of the threshold voltage (Vth) of the thin-film transistor shifting in the negative direction can be reduced.

[0050] On the other hand, in the following section, referring to the enlarged view indicated by the arrows in Figure 1A, we will examine in detail the spacing between at least one first protrusion 152a and the lengths of at least one first protrusion 152a in the first and second directions to investigate the conditions under which a thin-film transistor substrate according to one embodiment of the present invention can obtain the optimal effect.

[0051] As shown in the enlarged view indicated by the arrow in Figure 1A, at least one first projection 152a may comprise multiple first projections 152a. Therefore, multiple first projections 152a can project in a first direction from one side of the main body 151.

[0052] Multiple first protrusions 152a can be formed in the same shape. On the other hand, multiple first protrusions 152a can consist of, for example, three first protrusions 152a. However, the number of multiple first protrusions 152a is not limited to this.

[0053] According to one embodiment of the present invention, the spacing (d) between the multiple first protrusions 152a can be constant. By adjusting the spacing (d) between the multiple first protrusions 152a, the conductivity of the active layer 130 can be controlled. For example, when the spacing (d) between the multiple first protrusions 152a is constant, the conductive active layer 130 can have uniform characteristics. However, the spacing (d) between the multiple first protrusions 152a is not limited to this, and the spacing (d) between the multiple first protrusions 152a can be formed differently.

[0054] The spacing (d) between the multiple first protrusions 152a can be formed to a length of 0.5 μm or more and 50 μm or less, and it is preferable that the spacing (d) between the multiple first protrusions 152a be formed to a length of 2 μm or more and 20 μm or less.

[0055] If the spacing (d) between the multiple first protrusions 152a is 50 μm or more, the size of the first convex portion 133a increases, the length of the channel portion 131 decreases, and it becomes difficult to secure a threshold voltage (Vth) in the positive (+) direction. If the spacing (d) between the multiple first protrusions 152a is 2 μm or less, the length of the channel portion 131 becomes excessively long, the resistance increases, and the amount of current flowing through the entire element may decrease.

[0056] Each of the multiple first protrusions 152a protrudes by a certain length (l) in the first direction. Specifically, as shown in Figure 1A, the first protrusions 152a protrude by a certain length (l) from one end of the main body 151, for example, the left end, toward the source electrode 171.

[0057] According to one embodiment of the present invention, since the multiple first protrusions 152a can each protrude with the same length (l), the multiple first convex portions 133a provided in the source region 132a can be formed to be the same size. On the other hand, the length (l) of each of the multiple first protrusions 152a is not limited to the same length, and the lengths (l) of each of the multiple first protrusions 152a can also be formed to be different lengths.

[0058] The length (l) of the multiple first protrusions 152a can be formed to be between 0.5 μm and 5 μm. If the length (l) of the multiple first protrusions 152a is less than 0.5 μm, it may not be possible to obtain the multiple first convex portions 133a, and if the length (l) of the multiple first protrusions 152a exceeds 5 μm, the length of the channel portion 131 may increase excessively.

[0059] On the other hand, the first protrusion 152a does not extend to the region where the source electrode 171 is located, and therefore does not overlap with the source electrode 171.

[0060] Each of the multiple first protrusions 152a is formed with a constant width (w) in the second direction. According to one embodiment of the present invention, each of the multiple first protrusions 152a is formed with the same width (w). However, the invention is not limited to this, and each of the multiple first protrusions 152a can be formed with different widths (w).

[0061] The width (w) of the multiple first protrusions 152a is preferably formed to be between 0.5 μm and 20 μm. If the width (w) of the multiple first protrusions 152a is less than 0.5 μm, it may not be possible to obtain the multiple first convex portions 133a, and if the width (w) of the multiple first protrusions 152a exceeds 20 μm, the parasitic capacitance generated by the gate electrode 150 may increase.

[0062] On the other hand, the spacing (d) between the multiple first protrusions 152a, the length (l) in the first direction, and the width (w) in the second direction are not limited to the matters described above, but can be optimized in various ways according to the knowledge of the industry and adjusted to suit the characteristics of the element.

[0063] As shown in Figure 1B, a portion of the active layer 130 superimposed on the main body 151 is made conductive to form a first protrusion 133a, and a first recess 131a is formed in the channel portion 131 corresponding to the first protrusion 133a. In addition, a second protrusion 133b is formed in another portion of the active layer 130 facing the first protrusion 133a, and a second recess 131b is formed in the channel portion 131 corresponding to the second protrusion.

[0064] The first recess 131a overlaps with the left end of the main body 151, and the second recess 131b overlaps with the right end of the main body 151. Here, since the left side of the main body 151 is provided with multiple first protrusions 152a, multiple first recesses 131a are formed in the area overlapping with the left end of the main body 151. In contrast, since the right side of the main body 151 is not provided with first protrusions 152a, one second recess 131b is formed in the area overlapping with the right end of the main body 151.

[0065] For example, as shown in Figure 1B, if three first protrusions 152a are provided on one side of the main body 151, then four first recesses 131a can be provided on the left side of the channel 131. On the other hand, the number of first protrusions 152a and first recesses 131a is not limited to this.

[0066] The first recess 131a and the second recess 131b may be provided in a rounded shape and correspond to the first protrusion 133a and the second protrusion 133b, respectively.

[0067] The source region 132a is formed on one side of the channel portion 131 and can be electrically connected to the source electrode 171. The drain region 132b is formed on the other side of the channel portion 131 and can be electrically connected to the drain electrode 172. However, the method by which the source region 132a and the drain region 132b are connected to the source electrode 171 and the drain electrode 172, respectively, is not limited to this. In some cases, the source region 132a can be electrically connected to the drain electrode 172, and in this case, the drain region 132b can be electrically connected to the source electrode 171.

[0068] The thin-film transistor shown in Figure 1B has a first protrusion 152a only on the left side of the main body 151, and no other protrusion 151 on the right side of the main body 151. Therefore, the source region 132a and the drain region 132b are provided asymmetrically around the channel 131.

[0069] On the other hand, according to one embodiment of the present invention, since the main body portion 151 is provided with a first projection 152a on one side, the first convex portion 133a can be formed by a plurality of first convex portions 133a. For example, as shown in Figure 1B, if three first projections 152a are provided on one side of the main body portion 151, four first convex portions 133a can be provided on the left side of the channel portion 131 that overlaps with the main body portion 151. However, the number of first projections 152a and first convex portions 133a is not limited to this.

[0070] The multiple first protrusions 133a are formed while a portion of the active layer 130, where the multiple first projections 152a are not formed, is made conductive. Therefore, the multiple first protrusions 133a do not overlap the multiple first projections 152a in the lateral direction.

[0071] Furthermore, since the spacing between multiple first protrusions 152a is formed to be equal, the spacing between multiple first convex portions 133a can also be formed to be the same. For example, the spacing between multiple first convex portions 133a can be formed to be the same as the width (w) of the first protrusion 152a in the second direction.

[0072] The first protrusion 133a and the second protrusion 133b can be provided in a rounded shape and correspond to the first recess 131a and the second recess 131b, respectively.

[0073] Here, since one side of the main body 151 is provided with at least one first projection 152a, while the other side of the main body 151 is not provided with any other projection 152a, the first convex portion 133a and the second convex portion 133b can be formed asymmetrically around the channel portion 131.

[0074] The drain region 132b may have one second protrusion 133b, the size of which the second protrusion 133b is formed to be relatively larger than the size of the first protrusion 133a.

[0075] Figure 2 is a cross-sectional view of a thin-film transistor substrate according to one embodiment of the present invention, and Figure 2 is a cross-sectional view along the line I-I' in Figure 1B. That is, Figure 2 corresponds to a cross-section of the region where the protrusion 152a of the gate electrode 150 is formed.

[0076] As shown in Figure 2, a thin-film transistor substrate according to one embodiment of the present invention may include a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating film 140, a gate electrode 150, an interlayer insulating film 160, a source electrode 171, a drain electrode 172, and a planarization layer 180.

[0077] The substrate 100 can be made of glass or plastic. In particular, the substrate 100 can be made of a transparent plastic having flexible properties, such as polyimide. When polyimide is used as the substrate 100, considering that a high-temperature deposition process is performed on the substrate 100, a heat-resistant polyimide that can withstand high temperatures can be used.

[0078] The light-blocking layer 110 is formed on the substrate 100. However, in some cases, the light-blocking layer 110 can be omitted.

[0079] By superimposing the light-blocking layer 110 on the channel portion 131 of the active layer 130, the light-blocking layer 110 can block light incident from below the substrate 100 and protect the channel portion 131 of the active layer 130.

[0080] The light-blocking layer 110 may contain at least one of the following: aluminum (Al) or aluminum alloys; silver (Ag) or silver alloys; copper (Cu) or copper alloys; molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti).

[0081] The buffer layer 120 is formed on the light-blocking layer 110. Specifically, by forming the buffer layer 120 on a part of the substrate 100 and on the light-blocking layer 110, the substrate 100 and the buffer layer 120 can be formed in a manner that encloses the light-blocking layer 110.

[0082] The buffer layer 120 can be made of an inorganic insulator such as silicon oxide, silicon nitride, or metal oxide, but is not necessarily limited to these, and can also be made of an organic insulator. The buffer layer 120 can consist of a single layer or multiple layers.

[0083] The active layer 130 is formed on top of the buffer layer 120.

[0084] The active layer 130 includes a channel portion 131, a source region 132a provided on one side of the channel portion 131, and a drain region 132b provided on the other side of the channel portion 131.

[0085] The channel portion 131 is superimposed on the gate electrode 150, particularly the main body portion 151.

[0086] The source region 132a is connected to one side of the channel section 131.

[0087] A portion of the source region 132a does not overlap with the gate electrode 150, while the remaining portion of the source region 132a overlaps with the gate electrode 150, particularly the first projection 152a. The source region 132a does not penetrate to the lower part of the main body 151 of the gate electrode 150. Therefore, in the region where the projection 152a of the gate electrode 150 is formed, the first convex portion 133a shown in Figure 1B is not formed on the source region 132a.

[0088] Thus, since the first protrusion 133a is not formed in the source region 132a that overlaps with the first protrusion 152a, the length of the channel portion 131 can be relatively longer. Therefore, it is possible to control the threshold voltage (Vth) of the thin-film transistor of the present invention from shifting to negative (-).

[0089] The drain region 132b is connected to the other side of the channel portion 131.

[0090] A portion of the drain region 132b does not overlap with the gate electrode 150, while the remaining portion of the drain region 132b overlaps with the gate electrode 150, particularly the main body portion 151. The drain region 132a can penetrate to the lower part of the main body portion 151, thereby providing the second protrusion 133b.

[0091] Furthermore, corresponding to the second protrusion 133b, the second recess 131b can be formed on the other side of the channel portion 131, for example, in a portion adjacent to the drain region 132b.

[0092] The active layer 130 forms a channel when a constant voltage is applied to the gate electrode 150, providing a space through which charge carriers can move. Therefore, current flows through the channel formed in the active layer 130, causing charge carriers to move and enabling current to flow through the thin-film transistor according to one embodiment of the present invention. The active layer 130 is superimposed on the gate electrode 150, and by applying a voltage of a threshold voltage (Vth) or higher to the gate electrode 150, charge carriers can move through the active layer 130.

[0093] The active layer 130 may comprise a semiconductor material, such as an oxide semiconductor material. The oxide semiconductor material may include at least one of the following: IZO(InZnO)-based oxide semiconductor material, IGO(InGaO)-based oxide semiconductor material, ITO(InSnO)-based oxide semiconductor material, IGZO(InGaZnO)-based oxide semiconductor material, IGZTO(InGaZnSnO)-based oxide semiconductor material, GZTO(GaZnSnO)-based oxide semiconductor material, GZO(GaZnO)-based oxide semiconductor material, ITZO(InSnZnO)-based oxide semiconductor material, and FIZO(FeInZnO)-based oxide semiconductor material.

[0094] The gate insulating film 140 is formed on the active layer 130.

[0095] As shown in Figure 2, a thin-film transistor substrate according to one embodiment of the present invention may have a structure in which the gate insulating film 140 is etched. An etched structure refers to a structure formed by patterning a portion of the gate insulating film 140 that is provided on the substrate 100 as a whole, using the gate electrode 150 as a mask, and leaving only the remaining portion of the gate insulating film 140 corresponding to the gate electrode 150.

[0096] The gate insulating film 140 may, but is not limited to, a silicon nitride film (SiNx) or a silicon oxide film (SiOx). The gate insulating film 140 may have a single-film structure or a multilayer structure.

[0097] Plasma can be used when patterning the gate insulating film 140, and the source region 132a and drain region 132b can be formed while such plasma is irradiated onto the exposed region of the active layer 130. However, this is not necessarily the only option, and the source region 132a and drain region 132b can also be formed by performing a separate ion doping process after the patterning process of the gate insulating film 140.

[0098] The gate electrode 150 can be formed on the gate insulating film 140.

[0099] The gate electrode 150 may include at least one of the following: aluminum (Al) or aluminum alloys; silver (Ag) or silver alloys; copper (Cu) or copper alloys; molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). The gate electrode 150 may also have a multilayer structure comprising at least two conductive films, each with different physical properties.

[0100] The gate electrode 150 is formed on the active layer 130 and superimposed on the active layer 130.

[0101] The gate electrode 150 comprises a main body 151 and a first projection 152a. The first projection 152a is provided on one side of the main body 151, for example, the left side. On the other hand, the other side of the main body 151, for example, the right side, does not have a separate projection, so the gate electrode 150 is formed asymmetrically with respect to the main body 151.

[0102] On the other hand, since the first protrusion 152a is provided on only one side of the main body 151, the source region 132a and drain region 132b of the active layer 130 are also formed asymmetrically with respect to the channel portion 131.

[0103] The gate electrode 150 protects the channel portion 131 during the process of making the active layer 130 conductive. For example, the main body portion 151 can protect the channel portion 131.

[0104] The first protrusion 152a also protects a portion of the active layer 130. On the other hand, the first protrusion 152a overlaps with the source region 132a provided in the active layer 130.

[0105] The interlayer insulating film 160 is provided on the gate electrode 150. Specifically, the interlayer insulating film 160 can be provided on a part of the buffer layer 120, a part of the active layer 130, a part of the gate insulating film 140, and on the gate electrode 150.

[0106] The interlayer insulating film 160 insulates between the gate electrode 150 and the source electrode 171, and further insulates between the gate electrode 150 and the drain electrode 172. The interlayer insulating film 160 may consist of a single layer or multiple layers containing inorganic and / or organic insulators.

[0107] The interlayer insulating film 160 is provided with a first contact hole (CH1) and a second contact hole (CH2). As a result, the source region 132a of the active layer 130 can be exposed by the first contact hole (CH1), and the drain region 132b of the active layer 130 can be exposed by the second contact hole (CH2).

[0108] The source electrode 171 and the first drain electrode 172 can be formed on the interlayer insulating film 160.

[0109] For example, the source electrode 171 is electrically connected to one side of the active layer 130, for example to the source region 132a, and the drain electrode 172 is electrically connected to the other side of the active layer 130, for example to the drain region 132b.

[0110] Specifically, the source electrode 171 is connected to the source region 132a via a first contact hole (CH1) provided in the interlayer insulating film 160, and the drain electrode 172 is connected to the drain region 132b via a second contact hole (CH2) provided in the interlayer insulating film 160.

[0111] The planarization layer 180 is provided on the interlayer insulating film 160, the source electrode 171, and the drain electrode 172. On the other hand, the planarization layer 180 may include a third contact hole (CH3), although this is not shown in the figure. This will be explained in conjunction with Figure 12.

[0112] Figure 3 is a cross-sectional view of a thin-film transistor substrate according to the present invention and another embodiment. The contents of Figure 3 are the same as those of the thin-film transistor substrate according to Figure 2, except that the gate insulating film 140 is formed in an etchless structure. Therefore, the following explanation will focus on the differences in configuration.

[0113] The gate insulating film 140 is formed on the active layer 130. For example, the gate insulating film 140 can be formed on a part of the buffer layer 120 and on the active layer 130, so that the active layer 130 is surrounded by the buffer layer 120 and the gate insulating film 140.

[0114] On the other hand, as shown in Figure 3, the gate insulating film 140 can be formed with an etchless structure.

[0115] An etchless structure refers to a structure in which the gate insulating film 140 formed on the substrate 100 is used as is without further patterning, thereby providing the gate insulating film 140 throughout the entire substrate 100.

[0116] On the other hand, since the gate insulating film 140 is formed with an etchless structure, the first contact hole (CH1) and the second contact hole (CH2) are also provided in the gate insulating film 140. Furthermore, the source electrode 171 is connected to one side of the active layer 130, for example to the source region 132a, via the gate insulating film 140 and the interlayer insulating film 160, and the drain electrode 172 is connected to the other side of the active layer 130, for example to the drain region 132b, via the gate insulating film 140 and the interlayer insulating film 160.

[0117] In the etchless structure, a separate ion doping process can be performed to form the source region 132a and drain region 132b of the active layer 130.

[0118] Figure 4 shows the Vgs-Ids graph of a thin-film transistor substrate according to one embodiment of the present invention.

[0119] The Vgs-Ids graph in Figure 4 shows the transfer curve for the embodiment and the transfer curve for the comparative example, respectively. Here, the thin-film transistor according to the embodiment of the present invention has a first projection 152a on one side of the main body 151. Conversely, the thin-film transistor according to the comparative example does not have a separate projection on the gate electrode 150.

[0120] In the case of the comparative example's transfer curve, the threshold voltage (Vth) is formed to the left compared to the example's transfer curve, while in the example's transfer curve, the threshold voltage (Vth) is located to the right compared to the comparative example's transfer curve, and the threshold voltage (Vth) has a positive (+) value.

[0121] In short, in the case of the thin-film transistor substrate according to the embodiment equipped with the first protrusion 152a, the threshold voltage (Vth) can be shifted in the positive direction compared to the thin-film transistor substrate according to the comparative example not equipped with the first protrusion 152a. The length of the channel portion 131 can be adjusted by the first protrusion 152a, and as a result, the length of the channel portion 131 is adjusted, causing the threshold voltage (Vth) of the thin-film transistor substrate of the present invention to shift in the positive direction (Positive Shift).

[0122] Figure 5A is a plan view of a thin-film transistor substrate according to the present invention and other embodiments.

[0123] Unlike Figure 1B, the thin-film transistor substrate shown in Figure 5A has a second projection 152b on the other side of the main body 151 of the gate electrode 150, thereby forming a second convex portion 133b in the drain region 132b of the active layer 130. Aside from this point, it is the same as Figure 1B, so only the configurations that differ from Figure 1B will be described below.

[0124] As shown in Figure 5A, the gate electrode 150 comprises a main body 151, at least one first projection 152a, and at least one second projection 152b.

[0125] One side of the main body 151, for example, the left side, is provided with at least one first projection 152a, and the other side of the main body 151, for example, the right side, is provided with at least one second projection 152b. Therefore, the gate electrode 150 can be formed symmetrically on one side and the other side with respect to the main body 151.

[0126] Here, since at least one first projection 152a and at least one second projection 152b are formed symmetrically around the main body 151, the source region 132a and drain region 132b, which are provided while the active layer 130 is conductive, can be formed symmetrically around the channel portion 131.

[0127] The description of at least one first projection 152a is the same as that described in Figure 1A, so it will be omitted here.

[0128] At least one second projection 152b is provided on the other side of the main body 151, for example on the right side, and can extend in a first direction around the main body 151.

[0129] Specifically, at least one second projection 152b can extend from the main body 151 toward the drain electrode 172, as shown in Figure 5A.

[0130] Furthermore, at least one second projection 152b may be provided so as to face at least one first projection 152a.

[0131] Thus, by having multiple first protrusions 152a and second protrusions 152b in the gate electrode 150, the active layer 130 comes to have multiple relatively small first convex portions 133a and second convex portions 133b, and the left-right length of the channel portion 131 increases relatively further than that of the thin-film transistor substrate shown in Figure 1B.

[0132] Furthermore, by including the first protrusion 152a and the second protrusion 152b, the active layer 130 is not made conductive in the regions between the multiple first protrusions 133a and the regions between the multiple second protrusions 133b. Therefore, the left-right length of the channel portion 131 in the regions between the multiple first protrusions 133a and the regions between the multiple second protrusions 133b becomes relatively longer than that of the thin-film transistor substrate shown in Figure 1B.

[0133] As a result, multiple first protrusions 152a provided on one side of the main body 151 and multiple second protrusions 152b provided on the other side of the main body 151 can form multiple first convex portions 133a in the source region 132a and multiple second convex portions 133b in the drain region 132b, and consequently the left and right lengths of the channel portion 131 will be relatively increased compared to the thin-film transistor substrate shown in Figure 1B.

[0134] On the other hand, since the second projection 152b is provided symmetrically with respect to the first projection 152a and the main body 151, the conditions regarding the number of first projections 152a, the spacing between multiple first projections 152a (d), and the length (l) in the first direction and width (w) in the second direction of at least one first projection 152a can be similarly applied to the second projection 152b.

[0135] The channel portion 131 may have a first recess 131a on one side, for example, the left side, and a second recess 131b on the other side, for example, the right side.

[0136] The thin-film transistor shown in Figure 5A has protrusions 152a and 152b on both sides of the main body 151. Therefore, the first recess 131a and the second recess 131b are provided symmetrically around the channel 131. Accordingly, the same explanation of the first recess 131a and the second recess 131b will be omitted.

[0137] In the thin-film transistor shown in Figure 5A, the first recess 131a and the second recess 131b are symmetrically provided in the channel portion 131, allowing the left and right lengths of the channel portion 131 to be made relatively longer.

[0138] The source region 132a and the drain region 132b can be formed symmetrically around the channel portion 131. In this case, one side of the source region 132a is provided with a first protrusion 133a, and the other side of the source region 132a is electrically connected to the source electrode 171. Similarly, one side of the drain region 132b is provided with a second protrusion 133b, and the other side of the drain region 132b is electrically connected to the drain electrode 172.

[0139] The drain region 132b may comprise at least one second protrusion 133b. The at least one second protrusion 133b may be formed symmetrically with respect to at least one first protrusion 133a and the channel region 131.

[0140] In the thin-film transistor shown in Figure 5A, the source region 132a has a first protrusion 133a, and the drain region 132b has a second protrusion 133b symmetrically arranged with the first protrusion 133a, so the length of the channel region 131 becomes relatively longer. Therefore, the threshold voltage (Vth) of the thin-film transistor substrate in the embodiment of Figure 5 can be controlled so as not to shift in the negative direction.

[0141] Figure 5B is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention, and is a cross-sectional view taken along line II-II' in Figure 5A.

[0142] The embodiment shown in Figure 5B is the same as the embodiment shown in Figure 2, except for the configuration of the gate electrode 150 and the configuration of the second protrusion 133b provided on the active layer 130. Therefore, only the differences in configuration will be described below.

[0143] As can be seen from Figure 5B, the active layer 130 includes a channel portion 131, a source region 132a, and a drain region 132b.

[0144] The drain region is connected to the other side of the channel section 131, for example, to the right side of the channel section 131 in the drawing.

[0145] A portion of the drain region 132b does not overlap with the gate electrode 150, while the remaining portion of the drain region 132b overlaps with the gate electrode 150, particularly the second projection 152a. The drain region 132b does not penetrate to the lower part of the main body 151 of the gate electrode 150. Therefore, in the region where the second projection 152b of the gate electrode 150 is formed, the second convex portion 133b shown in Figure 5A is not formed in the drain region 132b.

[0146] Thus, since the second protrusion 133b is not formed in the drain region 132b that overlaps with the second protrusion 152b, the length of the channel portion 131 can be relatively longer. Therefore, it is possible to control the threshold voltage (Vth) of the thin-film transistor of the present invention from shifting to negative (-).

[0147] According to one embodiment of the present invention, the gate electrode 150 comprises a main body portion 151 and a first projection 152a and a second projection 152b. Here, the first projection 152a and the second projection 152b can be formed symmetrically with respect to the main body portion 151.

[0148] The second protrusion 152b, like the main body 151 and the first protrusion 152a, protects a portion of the active layer 130. On the other hand, the second protrusion 152b overlaps with the drain region 132b provided in the active layer 130.

[0149] Figure 6 is a plan view of a thin-film transistor substrate according to the present invention and another embodiment.

[0150] The thin-film transistor substrate shown in Figure 6 is the same as the thin-film transistor substrate shown in Figure 5A, except that the multiple first protrusions 152a and second protrusions 152 each overlap with one or the other side of the active layer 130. Therefore, only the configurations that differ from Figure 5A will be described below.

[0151] In another embodiment of the present invention, as shown in Figure 6, one of the multiple first protrusions 152a of the thin-film transistor substrate overlaps with one side of the active layer 130. Here, one side of the active layer 130 corresponds to the side that overlaps with the gate electrode 150.

[0152] Furthermore, one of the multiple first protrusions 152a overlaps with another side of the active layer 130. Here, the other side of the active layer 130 corresponds to the side that overlaps with the gate electrode 150 and can be positioned in a direction opposite to one side of the active layer 130.

[0153] Specifically, one of the multiple first protrusions 152a can coincide with one side of the active layer 130, and one of the other first protrusions 152a can coincide with the other side of the active layer 130.

[0154] Since the first protrusion 152a and the second protrusion 152b are formed symmetrically around the main body 151, the above-mentioned provisions can also be applied to the second protrusion 152b. Therefore, the explanation of the second protrusion 152b will be omitted.

[0155] Figure 7 is a plan view of a thin-film transistor substrate according to the present invention and another embodiment.

[0156] The thin-film transistor substrate shown in Figure 7 is the same as the thin-film transistor substrate shown in Figure 5A, except that the active layer 130 includes a first active hole (H1) and a second active hole (H2). Therefore, only the configurations that differ from those in Figure 5A will be described below.

[0157] According to yet another embodiment of the present invention, as shown in Figure 7, the active layer 130 may include a channel portion 131, a source region 132a including at least one first protrusion 133a, a drain region 132b including at least one second protrusion 133b, at least one first active hole (H1), and at least one second active hole (H2).

[0158] At least one first active hole (H1) is provided on one side of the active layer 130, and at least one second active hole (H2) is provided on the other side of the active layer 130.

[0159] According to embodiments of the present invention, at least one first active hole (H1) and a second active hole (H2) can be formed by patterning a portion of the active layer 130. The active layer 130 may not be present at the locations where the first active hole (H1) and the second active hole (H2) are formed. On the other hand, the first active hole (H1) and the second active hole (H2) are not limited to these, and the active layer 130 may be partially present at the locations where the first active hole (H1) and the second active hole (H2) are formed. Therefore, the thickness of the portion of the active layer 130 present at the first active hole (H1) and the second active hole (H2) may be thinner than the thickness of the remaining portion of the active layer 130 that does not have the first active hole (H1) and the second active hole (H2).

[0160] At least one first active hole (H1) may be provided between the channel portion 131 and the source region 132a. Furthermore, a portion of at least one first active hole (H1) may not overlap with the entire gate electrode 150, while the remaining portion of at least one first active hole (H1) may overlap with the body portion 151 of the gate electrode 150. However, at least one first active hole (H1) may not overlap with the first projection 152a of the gate electrode 150.

[0161] Therefore, at least one first active hole (H1) is formed in the region between the multiple first protrusions 152a. Alternatively, at least one first active hole (H1) can be formed in the region between the multiple first convex portions 133a.

[0162] At least one first active hole (H1) can be comprised of multiple first active holes (H1), and these multiple first active holes (H1) can be arranged in a line with the same shape. The spacing between the multiple first active holes (H1) can also be made the same. By making the spacing between each first active hole (H1) the same, the source region 132a can be formed uniformly overall.

[0163] The formation of the first active hole (H1) in this manner reduces the degree to which the active layer 130 becomes conductive during the conductive process, decreasing the size of the first protrusion 133a, and consequently increasing the length of the channel portion 131.

[0164] Similarly, at least one second active hole (H2) may be provided between the channel portion 131 and the drain region 132b. Furthermore, a portion of at least one second active hole (H2) may not overlap with the entire gate electrode 150, while the remaining portion of at least one second active hole (H2) may overlap with the body portion 151 of the gate electrode 150. However, at least one second active hole (H2) may not overlap with the second projection 152b of the gate electrode 150.

[0165] Therefore, at least one second active hole (H2) is formed in the region between the multiple second protrusions 152b. Alternatively, at least one second active hole (H2) can be formed in the region between the multiple second convex portions 133b.

[0166] At least one second active hole (H2) can be comprised of multiple second active holes (H2), and these multiple second active holes (H2) can be arranged in a line with the same shape. The spacing between the multiple second active holes (H2) can also be made the same. By making the spacing between each second active hole (H2) the same, the drain region 132b can be formed uniformly overall.

[0167] The formation of the second active hole (H2) in this way reduces the degree to which the active layer 130 becomes conductive during the conductive process, decreases the size of the second protrusion 133b, and consequently increases the length of the channel portion 131.

[0168] As a result, the left and right lengths of the channel portion 131 become relatively longer, so the threshold voltage (Vth) of the thin-film transistor substrate shown in Figure 7 may not shift in the negative direction.

[0169] Figure 8 is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present invention, and Figure 8 is a cross-sectional view taken along line III-III' in Figure 7.

[0170] Figure 8 is a cross-sectional view of the thin-film transistor substrate shown in Figure 7, including the first protrusion 152a and the second active hole (H2).

[0171] The thin-film transistor substrate shown in Figure 8 is identical to the thin-film transistor substrate shown in Figure 2, except that the active layer 130 is equipped with a second active hole (H2). Therefore, only the configurations that differ from those in Figure 2 will be described below.

[0172] As shown in Figure 8, the active layer 130 may include a channel portion 131, a source region 132a, a drain region 132b, and a second active hole (H2). Here, the second active hole (H2) may be formed between the channel portion 131 and the drain region 132b.

[0173] On the other hand, although not shown in the figure, the active layer 130 can also be formed in a multilayer structure. For example, the active layer 130 can be formed in a two-layer structure. Here, the active layer 130 may include a first active layer and a second active layer provided on the first active layer. The first active layer 130 may have second active holes (H2) formed thereon, while the second active layer may not have second active holes (H2) formed thereon. Here, due to the second active holes (H2) formed only in the first active layer, a portion of the second active layer can come into contact with the buffer layer 120 through the second active holes (H2). However, the active layer 130 is not limited to a two-layer structure, and can also be formed in a three-layer or four-layer structure.

[0174] The interior of the second active hole (H2) may include a portion of the gate insulating film 140 formed on the active layer 130 and a portion of the interlayer insulating film 160 formed on the gate insulating film 140.

[0175] In the etch structure of the gate insulating film 140, the gate insulating film 140 is patterned using the gate electrode 150 as a mask. As a result, only the portion of the gate insulating film 140 that overlaps with the gate electrode 150 remains, and the portion of the gate insulating film 140 that does not overlap with the gate electrode 150 is removed.

[0176] Furthermore, since the interlayer insulating film 160 is formed after patterning the gate insulating film 140, a portion of the interlayer insulating film 160 can be formed in the second active hole (H2).

[0177] Therefore, the portion where the second active hole (H2) and the gate electrode 150 overlap may be provided with a gate insulating film 140, but the portion where the second active hole (H2) and the gate electrode 150 do not overlap is not provided with a gate insulating film 140, and only a portion of the interlayer insulating film 160 is provided.

[0178] Figure 9 is a cross-sectional view of a thin-film transistor substrate according to the present invention and other embodiments. Figure 9 is a cross-sectional view taken along line III-III' in Figure 7.

[0179] The contents of Figure 9 are the same as those of the thin-film transistor substrate shown in Figure 8, except that the gate insulating film 140 is formed in an etchless structure. Therefore, the following explanation will focus on the differences in configuration.

[0180] The gate insulating film 140 is formed on the active layer 130. For example, the gate insulating film 140 can be provided on a part of the buffer layer 120, the channel portion 131, the source region 132a, and the drain region 132b. The gate insulating film 140 can also be provided on the second active hole (H2) located between the channel region 131 and the drain region 132b.

[0181] On the other hand, the gate insulating film 140 can be formed with an etchless structure as explained in Figure 3, and the etchless structure is the same as described in Figure 3, so it will be omitted here.

[0182] Since the gate insulating film 140 is formed with an etchless structure, the second active hole (H2) can be provided with the gate insulating film 140, as shown in Figure 8.

[0183] Figure 10 is a cross-sectional view of a display device including a thin-film transistor substrate according to one embodiment of the present invention.

[0184] As can be seen from Figure 10, a display device according to one embodiment of the present invention comprises a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating film 140, a gate electrode 150, an interlayer insulating film 160, a source electrode 171, a drain electrode 172, a planarization layer 180, a first electrode 190, a bank layer 200, a light-emitting layer 210, and a second electrode 220.

[0185] The substrate 100, light-blocking layer 110, buffer layer 120, active layer 130, gate insulating film 140, gate electrode 150, interlayer insulating film 160, source electrode 171, drain electrode 172, and planarization layer 180 are the same as in the previously described embodiment, so a repetitive explanation will be omitted.

[0186] A third contact hole (CH3) is provided on the planarization layer 180, and the drain electrode 172 is exposed by the third contact hole (CH3). However, in some cases, the source electrode 171 can also be exposed by the third contact hole (CH3).

[0187] The first electrode 190 is formed on the planarization layer 180 and is connected to the source electrode 171 or the drain electrode 172 via a third contact hole (CH3). The first electrode 190 can function as an anode.

[0188] The bank layer 200 is provided so as to cover the edge of the first electrode 190 and defines the light-emitting region. Therefore, the upper surface region of the first electrode 190 that is exposed and not covered by the bank layer 200 becomes the light-emitting region.

[0189] The light-emitting layer 210 is provided on the first electrode 190. The light-emitting layer 210 may include patterned red, green, and blue light-emitting layers for each pixel, or it may consist of a white light-emitting layer connected to all pixels. When the light-emitting layer 210 consists of a white light-emitting layer, it may, but is not limited to, a first stack including, for example, a blue light-emitting layer, a second stack including, for example, a yellow-green light-emitting layer, and a charge generation layer provided between the first and second stacks.

[0190] The second electrode 220 is provided on the light-emitting layer 210. The second electrode 220 can function as a cathode.

[0191] Although not shown in the diagram, a sealing layer can be further formed on the second electrode 220 to prevent the penetration of moisture or oxygen.

[0192] Figure 11 is a schematic diagram of a display device according to one embodiment of the present invention.

[0193] As can be seen from Figure 11, a display device according to one embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340.

[0194] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged in the intersection region of the gate lines (GL) and data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), data lines (DL), and pixels (P) can be arranged on the substrate 100.

[0195] The control unit 340 controls the gate driver 320 and the data driver 330. The control unit 340 outputs a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330 using signals supplied from an external system (not shown). The control unit 340 also samples the input video data received from the external system, rearranges it, and supplies the rearranged digital video data (RGB) to the data driver 330.

[0196] The gate control signal (GCS) includes the gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). The gate control signal (GCS) may also include control signals for controlling the shift register.

[0197] Data control signals (DCS) include source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), polarity control signal (POL), etc.

[0198] The data driver 330 supplies data voltage to the data lines (DL) of the display panel 310. Specifically, the data driver 330 converts the video data (RGB) input from the control unit 340 into analog data voltage and supplies the data voltage to the data lines (DL).

[0199] The gate driver 320 can be mounted on the display panel 310. This structure, in which the gate driver 320 is directly mounted on the display panel 310, is called a Gate In Panel (GIP) structure. Specifically, in a Gate In Panel (GIP) structure, the gate driver 320 can be placed on the substrate 100.

[0200] The gate driver 320 may include a shift register 350.

[0201] The shift register 350 sequentially supplies gate pulses to the gate line (GL) for one frame using a start signal or gate clock transmitted from the control unit 340. Here, one frame refers to the period during which one image is output via the display panel 310. The gate pulses have a turn-on voltage that can turn on the switching element (thin-film transistor) placed in the pixel (P).

[0202] Furthermore, the shift register 350 supplies a gate-off signal to the gate line (GL) during the remaining period in a frame when no gate pulse is supplied, which can turn off the switching element. The gate pulse and the gate-off signal can be collectively referred to as the gate signal (GS).

[0203] Figure 12 is a circuit diagram of a shift register according to one embodiment of the present invention.

[0204] As can be seen from Figure 12, the GIP circuit includes a Full-Up Node (Q), a Full-Down Node (QB), a Node Control Unit (NC), and a Buffer Unit (Buffer).

[0205] The buffer section is connected to the output terminal and includes a full-up transistor (Tu), a full-down transistor (Td), and a capacitor (C).

[0206] A full-up transistor (Tu) turns on and outputs a gate-on signal when the full-up node (Q) is charged with a gate-high voltage.

[0207] The full-down transistor (Td) turns on and outputs a gate-off signal when the full-down node (QB) is charged with a gate-low voltage.

[0208] The capacitor (C) is responsible for maintaining the gate high voltage supplied to the full-up transistor (Tu) for one frame, and is located between the gate and source terminals of the full-up transistor (Tu).

[0209] The node control unit (NC) controls the charging and discharging of the full-up node (Q) and the full-down node (QB). Such a node control unit (NC) may include a full-up node control unit (NC_Q) for controlling the charging and discharging of the full-up node (Q) and a full-down node control unit (NC_QB) for controlling the charging and discharging of the full-down node (QB). The full-up node control unit (NC_Q) controls the full-up node (Q) with at least one transistor (T Q The full down node control unit (NC_QB) includes at least one transistor (T) for controlling the full down node (QB). QB ) is included in this.

[0210] The node control unit (NC) can stably control the output of the gate signal (Vout). Specifically, the node control unit (NC) discharges the full-down node (QB) with a gate-low voltage when the full-up node (Q) is charged with a gate-high voltage, and discharges the full-up node (Q) with a gate-low voltage when the full-down node (QB) is charged with a gate-high voltage.

[0211] Therefore, when the start signal (Vst) is applied, multiple transistors (T) provided in the node control unit (NC) are activated. Q , T QB The operation of the full-up node (Q) charges the full-up node (QB) with a gate high voltage, and the full-down node (QB) discharges to a gate low voltage, outputting a high supply voltage (VDD) as the gate signal (Vout). QB When a current is applied, multiple transistors (T) provided in the node control unit (NC) are activated. Q , T QB The operation of the full-up node (Q) charges the full-down node (QB) with a gate-low voltage and the full-down node (QB) charges with a gate-high voltage, outputting a low supply voltage (VSS) to the gate signal (Vout).

[0212] Figure 13 is a circuit diagram of one pixel in a display device according to one embodiment of the present invention.

[0213] As can be seen from Figure 13, a display device according to one embodiment of the present invention comprises first and second thin-film transistors (T1, T2) and a capacitor (Cst).

[0214] The first thin-film transistor (T1) is a driving thin-film transistor, and the second thin-film transistor (T2) is a switching thin-film transistor. At least one of the first thin-film transistor (T1) and the second thin-film transistor (T2) can be made up of the various thin-film transistors described above.

[0215] The first thin-film transistor (T1) is switched by the data voltage (Vdata) supplied from the second thin-film transistor (T2), and generates a data current from the drive voltage (VDD) supplied from the power line (PL) and supplies it to the organic light-emitting diode (OLED).

[0216] The second thin-film transistor (T2) is switched by a gate signal (GS) supplied to the gate line (GL) and supplies a data voltage (Vdata) from the data line (DL) to the first thin-film transistor (T1).

[0217] The capacitor (Cst) is responsible for maintaining the data voltage supplied to the first thin-film transistor (T1) for one frame, and is located between the gate electrode and source electrode of the first thin-film transistor (T1).

[0218] An organic light-emitting diode (OLED) emits a predetermined amount of light in response to a data current supplied from a first thin-film transistor (T1).

[0219] Figure 14 is a circuit diagram of a single pixel in a display device according to another embodiment of the present invention.

[0220] As can be seen from Figure 14, another embodiment of the present invention comprises a first to third thin-film transistor (T1, T2, T3) and a capacitor (Cst).

[0221] The first thin-film transistor (T1) is a driving thin-film transistor, and the second and third thin-film transistors (T2 and T3) are switching thin-film transistors. At least one of the first to third thin-film transistors (T1, T2, and T3) can be composed of the various thin-film transistors described above.

[0222] The first thin-film transistor (T1) is switched by the data voltage (Vdata) supplied from the second thin-film transistor (T2), and generates a data current from the drive voltage (VDD) supplied from the power line (PL) and supplies it to the organic light-emitting diode (OLED).

[0223] The second thin-film transistor (T2) is switched by a gate signal (GS) supplied to the gate line (GL) and supplies a data voltage (Vdata) from the data line (DL) to the first thin-film transistor (T1).

[0224] The third thin-film transistor (T3) responds to the sensing control signal (SENSE) supplied from the scan line (SCL) by supplying current from the first thin-film transistor (T1) to the reference line (RL). A reference voltage (Vref) is supplied to the reference line (RL).

[0225] The capacitor (Cst) is responsible for maintaining the data voltage supplied to the first thin-film transistor (T1) for one frame, and is located between the gate electrode and source electrode of the first thin-film transistor (T1).

[0226] An organic light-emitting diode (OLED) emits a predetermined amount of light in response to a data current supplied from a first thin-film transistor (T1).

[0227] Figure 15 is a circuit diagram of a single pixel in a display device according to the present invention or other embodiments.

[0228] As can be seen from Figure 15, another embodiment of the present invention includes a display device comprising first to fourth thin-film transistors (T1, T2, T3, T4) and a capacitor (Cst).

[0229] The first thin-film transistor (T1) is a driving thin-film transistor, and the second to fourth thin-film transistors (T2 to T4) are switching thin-film transistors. At least one of the first to fourth thin-film transistors (T1, T2, T3, T4) can be composed of the various thin-film transistors described above.

[0230] The first thin-film transistor (T1) is switched by the data voltage (Vdata) supplied from the second thin-film transistor (T2), and generates a data current from the drive voltage (VDD) supplied from the power line (PL) and supplies it to the organic light-emitting diode (OLED).

[0231] The second thin-film transistor (T2) is switched by a gate signal (GS) supplied to the gate line (GL) and supplies a data voltage (Vdata) from the data line (DL) to the first thin-film transistor (T1).

[0232] The third thin-film transistor (T3) responds to the sensing control signal (SENSE) supplied from the scan line (SCL) by supplying current from the first thin-film transistor (T1) to the reference line (RL). A reference voltage (Vref) is supplied to the reference line (RL).

[0233] The fourth thin-film transistor (T4) is switched by a light emission control signal (EM) supplied to the light emission control line (EML), and supplies a drive voltage (VDD) from the power supply line (PL) to the first thin-film transistor (T1).

[0234] The capacitor (Cst) is responsible for maintaining the data voltage supplied to the first thin-film transistor (T1) for one frame, and is located between the gate electrode and source electrode of the first thin-film transistor (T1).

[0235] An organic light-emitting diode (OLED) emits a predetermined amount of light in response to a data current supplied from a first thin-film transistor (T1).

[0236] Although embodiments of the present invention have been described in more detail above with reference to the attached figures, the present invention is not necessarily limited to these embodiments and can be implemented in various modifications without departing from the technical concept of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and not limiting in all respects. The scope of protection of the present invention should be interpreted by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of the present invention. [Explanation of symbols]

[0237] 100: Circuit board 110: Light-blocking layer 120: Buffer layer 130: Active layer 131: Channel section 131a: First concave portion 131b: Second concave portion 132a: Source area 132b: Drain area 133a: First convex portion 133b: Second convex portion H1: First active hole H2: Second active hole 140: Gate Insulator 150: Gate Shutdown 160: Interlayer insulating film 171: Source electrode 172: Drain electrode 180: Flattening layer 190: 1st electrode 200: Bank Layer 210: Emitting layer 220: 2nd electrode 310: Display Panel 320: Gate Driver 330: Data Driver 340: Control Unit 350: Shift Register

Claims

1. substrate, An active layer provided on the substrate, A gate electrode provided on the active layer, A source electrode connected to the first side of the active layer, and The active layer includes a drain electrode connected to the second side, The gate electrode includes a main body, a plurality of first protrusions provided on the first side of the main body, and a plurality of second protrusions provided on the second side of the main body, wherein the plurality of first protrusions and the plurality of second protrusions overlap with the active layer in a plan view. The active layer includes a channel region, The channel region comprises a plurality of first recesses and a plurality of second recesses, Each first recess is separated by the width of the first protrusion. The plurality of first recesses and the plurality of second recesses are arranged symmetrically with respect to the center line of the channel region along the direction in which the plurality of first recesses are aligned. A thin-film transistor substrate in which the plurality of first recesses and the plurality of second recesses are formed to be the same size.

2. A first channel region is provided on the first side of the channel region, connected to the source electrode, and the source region is made conductive, and A drain region is provided on the second side of the channel region, connected to the drain electrode, and includes a conductive drain region. The thin-film transistor substrate according to claim 1, wherein the plurality of first protrusions overlap with the source region.

3. The thin-film transistor substrate according to claim 2, wherein the source region comprises a plurality of first protrusions in regions corresponding to the plurality of first recesses.

4. The thin-film transistor substrate according to claim 3, wherein the plurality of first protrusions do not overlap with the plurality of first projections.

5. The thin-film transistor substrate according to claim 3, wherein the plurality of first protrusions have a rounded shape.

6. The thin-film transistor substrate according to claim 1, wherein each of the plurality of first protrusions has the same shape.

7. The thin-film transistor substrate according to claim 1, wherein the spacing between adjacent plurality of first protrusions is 0.5 μm or more and 50 μm or less.

8. The length of each of the plurality of first protrusions in the first direction is 0.5 μm or more and 5 μm or less. The width, which is the length of the plurality of first protrusions in the second direction, is 0.5 μm or more and 20 μm or less. The first direction is the direction in which the plurality of first protrusions protrude from the first side of the main body. The thin-film transistor substrate according to claim 1, wherein the second direction is a direction orthogonal to the first direction.

9. The thin-film transistor substrate according to claim 1, wherein the plurality of first protrusions do not overlap with the source electrode and the drain electrode.

10. The thin-film transistor substrate according to claim 1, wherein the plurality of first protrusions and the plurality of second protrusions are provided symmetrically with respect to the main body.

11. A first channel region is provided on the first side of the channel region, connected to the source electrode, and the source region is made conductive, and A drain region is provided on the second side of the channel region, connected to the drain electrode, and includes a conductive drain region. The thin-film transistor substrate according to claim 1, wherein the plurality of first protrusions overlap with the source region, and the plurality of second protrusions overlap with the drain region.

12. The source region comprises a plurality of first protrusions in the region corresponding to the plurality of first recesses, The thin-film transistor substrate according to claim 11, wherein the drain region comprises a plurality of second protrusions in regions corresponding to the plurality of second recesses.

13. The thin-film transistor substrate according to claim 12, wherein the plurality of first protrusions and the plurality of second protrusions are provided symmetrically with respect to the channel region.

14. The plurality of first protrusions overlap with the longitudinal ends of the active layer, The thin-film transistor substrate according to claim 1, wherein the longitudinal direction is the direction in which the plurality of first protrusions protrude from the first side of the main body.

15. substrate, An active layer provided on the substrate, A gate electrode provided on the active layer, A source electrode connected to the first side of the active layer, and The active layer includes a drain electrode connected to the second side, The gate electrode includes a main body and at least one first projection provided on the first side of the main body, the at least one first projection superimposed on the active layer in a plan view, The active layer comprises at least one active hole, A thin-film transistor substrate in which the at least one active hole does not overlap with the at least one first protrusion.

16. A portion of at least one of the active holes overlaps with the main body, The thin-film transistor substrate according to claim 15, wherein the remaining portion of the at least one active hole does not overlap with the main body.

17. The gate insulating film is further provided between the gate electrode and the active layer, The thin-film transistor substrate according to claim 15, wherein the gate insulating film is provided inside the at least one active hole.

18. The source electrode further includes an interlayer insulating film between the source electrode and the active layer, The thin-film transistor substrate according to claim 17, wherein the interlayer insulating film is provided inside the at least one active hole.

19. Thin-film transistor substrate, The thin-film transistor substrate, substrate, An active layer provided on the substrate, A gate electrode provided on the active layer, A source electrode connected to the first side of the active layer, and The active layer includes a drain electrode connected to the second side, The gate electrode includes a main body, a plurality of first protrusions provided on the first side of the main body, and a plurality of second protrusions provided on the second side of the main body, wherein the plurality of first protrusions and the plurality of second protrusions overlap with the active layer, a thin-film transistor substrate, A gate driver connected to the thin-film transistor substrate and supplying a gate signal to the thin-film transistor substrate, and The system includes a data driver connected to the thin-film transistor substrate and supplying data signals to the thin-film transistor substrate, The active layer includes a channel region, The channel region comprises a plurality of first recesses and a plurality of second recesses, Each first recess is separated by the width of the first protrusion. The plurality of first recesses and the plurality of second recesses are arranged symmetrically with respect to the center line of the channel region along the direction in which the plurality of first recesses are aligned. A display device in which the plurality of first recesses and the plurality of second recesses are formed to be the same size.

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