Fusion Modular Multiply-Accumulate Operations
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- INTERNATIONAL BUSINESS MACHINE CORPORATION
- Filing Date
- 2022-10-11
- Publication Date
- 2026-08-07
Smart Images
Figure 0007902256000003 
Figure 0007902256000004 
Figure 0007902256000005
Abstract
Description
Technical Field
[0001] The present invention generally relates to computer technology, and more particularly to performing arithmetic operations by implementing fused modular multiply-add (FMMA) operations.
[0002] Computers are typically used for applications that perform arithmetic operations. Some applications, such as cryptography, blockchain, machine learning, image processing, computer games, e-commerce, etc., require that such operations be performed efficiently (e.g., quickly). Thus, the performance of integer arithmetic has been the focus of both academic and industrial research.
[0003] Some existing techniques are used to improve the performance of computers, particularly processors and / or arithmetic logic units, by leveraging the computational process or implementing arithmetic instructions that adapt to the hardware architecture. Examples of such techniques include splitting one instruction into multiple operations, where each operation is executed in parallel, combining two or more operations to reduce memory access, ordering the operations to reduce memory access time, storing operands in a specific order to reduce access time, etc. Different types of arithmetic operations may be required for applications such as cryptography and machine learning.
Summary of the Invention
[0004] According to one or more embodiments of the present invention, a computer implementation method comprises the step of receiving an instruction from a processing unit to perform a fused modular multiply-accumulate operation, where a, b, and c are provided as a set of operands. The method further comprises the step of a first multiplier unit performing a binary multiplication, where a*b. The method further comprises the step of a second multiplier unit performing a first intermediate result by updating the result of the binary multiplication with p. The method further comprises the step of initializing an accumulator of a third multiplier unit with c. The method further comprises the step of a third multiplier unit performing a second intermediate result using the first intermediate result and c. The method further comprises the step of an adder subtracting a portion of the second intermediate result from a portion of the result of the binary multiplication. The method further comprises the step of outputting the output of the adder as a result of the fused modular multiply-accumulate operation.
[0005] According to one or more embodiments of the present invention, the system comprises a set of registers and a set of multiplicative units having three multiplicative units, each including a multiplier and an accumulator. The set of multiplicative units is coupled to the set of registers. The set of multiplicative units is configured to perform a method of performing a fused modular multiply-accumulate operation, which calculates d = ((a*b) + c) % p, where a, b, and c are provided in the set of registers. The method of performing the fused modular multiply-accumulate operation comprises the step of a first multiplicative unit calculating a*b. The method further comprises the step of a second multiplicative unit calculating a first intermediate result by updating the result of the binary multiplier using p. The method further comprises the step of initializing the accumulator of a third multiplicative unit with c. The method further comprises the step of a third multiplicative unit calculating a second intermediate result using the first intermediate result and c. The method further comprises the step of subtracting a portion of the second intermediate result from a portion of the result of the binary multiplication using an adder. The method further comprises the step of outputting the output of the adder as a result of the fused modular multiply-accumulate operation.
[0006] According to one or more embodiments of the present invention, a computer program product comprises a computer-readable memory storing computer-executable instructions, which, when executed by a processor, cause the processor to perform a method of performing a fused modular multiply-accumulate operation, where a, b, and c are provided as operands, which calculates d = ((a*b) + c) % p. The method of performing the fused modular multiply-accumulate operation comprises a step of calculating a binary multiplication by a first multiplier unit, which calculates a*b. The method further comprises a step of calculating a first intermediate result by updating the result of the binary multiplication with p by a second multiplier unit. The method further comprises a step of initializing an accumulator of a third multiplier unit with c. The method further comprises a step of calculating a second intermediate result by the third multiplier unit, which uses the first intermediate result and c. The method further comprises a step of subtracting a portion of the second intermediate result from a portion of the result of the binary multiplication by an adder. The method further comprises a step of outputting the output of the adder as a result of the fused modular sum-of-products operation.
[0007] Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered to be part of the subject matter claimed. For a better understanding, refer to the detailed description and drawings. [Brief explanation of the drawing]
[0008] Details of the exclusive rights described herein are specifically indicated and are explicitly claimed in the claims in the conclusions herein. The aforementioned and other features and advantages of embodiments of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.
[0009] [Figure 1] This diagram shows a set of hardware components of a processor used to calculate modular sum-of-products.
[0010] [Figure 2] This figure shows an architecture of modular arithmetic and logic units that facilitates the execution of fused sum-accumulate instructions, according to one or more embodiments of the present invention.
[0011] [Figure 3] This is a flowchart of a method for executing the FMMA_B instruction according to one or more embodiments of the present invention.
[0012] [Figure 4] This figure shows an architecture of modular arithmetic and logic units that facilitates the execution of fused sum-accumulate instructions, according to one or more embodiments of the present invention.
[0013] [Figure 5] This is a flowchart of a method for executing the FMMA_M instruction according to one or more embodiments of the present invention.
[0014] [Figure 6] This figure shows an exemplary scenario in which fused modular multiply-accumulate instructions improve the efficiency of calculations according to one or more embodiments of the present invention.
[0015] [Figure 7] This is a block diagram of a processor according to one or more embodiments of the present invention.
[0016] [Figure 8] This figure shows a computing system according to one or more embodiments of the present invention.
[0017] The drawings shown herein are illustrative. Many variations may exist to the drawings or the actions described herein without departing from the scope of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term “combined” and its variations describe a communication path between two elements, and do not imply a direct connection between elements without an intervening element / connection. All of these variations are considered part of this specification.
[0018] In the accompanying figures and the following detailed description of the disclosed embodiments, various elements shown in the figures are given two- or three-digit reference numbers. With few exceptions, the leftmost digit of each reference number corresponds to the figure in which the element first appeared. [Modes for carrying out the invention]
[0019] Technical solutions for improving the efficiency of computer processors by facilitating the execution of fused modular multiply-accumulate (FMMA) operations are described herein. Addition and multiplication arithmetic operations are frequently used in computer systems. Fused multiply-accumulate instructions (FMMA) are a common method for performing multiply-accumulate operations in a single instruction in order to reduce the number of instructions to be executed, reduce memory access, and thus improve execution efficiency. FMA instructions are widely used in both integer and floating-point operations.
[0020] Embodiments of the present invention address the technical challenge of improving performance by performing fused operations that reduce the number of instructions and memory accesses compared to performing modular addition and modular multiplication operations separately. Embodiments of the present invention facilitate a single instruction for performing FMMA operations and techniques for implementing such operations on current-generation hardware.
[0021] Modular arithmetic is frequently used in several computer applications such as encryption, blockchain, artificial intelligence, etc. Thus, by providing FMMA operations / instructions to provide improvements in the execution of such applications, embodiments of the present invention provide practical applications in the field of computing technology and at least in fields where such FMMA operations are used. Further, embodiments of the present invention provide improvements to the computing technology itself by improving the execution of modular multiply-accumulate operations.
[0022] Computer systems typically use binary number representation when performing arithmetic operations. Further, computer systems, and particularly processors and the arithmetic logic units (ALUs) of such processors, have a pre-defined "width" or "word size" (w), e.g., 32 bits, 64 bits, 128 bits, etc. The width indicates the maximum number of bits that a processor can process at one time. The width of a processor can be indicated by the size of the registers, the size of the ALU processing width, or any other such processing constraint of components associated with the processor.
[0023] Table 1 provides the Barrett modular multiplication algorithm typically used to perform modular multiplication in a computing system. Column 1 of Table 1 shows the sequence of calculations performed to compute the modular multiplication of operands a, b with a prime number p. Given a, b, and p as inputs, the output of the modular multiplication is r = (a * b) % p which is computed as shown in Column 1. In Column 2 of Table 1, assuming that k is the bit width of the processor, the bit widths required for the calculations are shown. Table 1 [Table 1]
[0024] Table 2 provides the Montgomery modular multiplication algorithm, a typical alternative form used to perform modular multiplication in computing systems. Column 1 of Table 2 shows the sequence of calculations performed to compute the modular multiplication of operands a and b with prime numbers p. Given a, b, and p as inputs, the output of the modular multiplication in this case is: c=(a*b*R -1 )%p This is calculated as shown in column 1, where X(lo) and X(hi) represent the lower half of the bits in X and the higher half of the bits in X, respectively. Column 2 of Table 2 shows the bit width required for the calculation, assuming k is the processor's bit width, where w is a value that depends on the processor's word size. Table 2 [Table 2]
[0025] Furthermore, as can be seen from Tables 1 and 2, existing solutions require at least three separate multiplications to be performed. Embodiments of the present invention, as described herein, fuse such multiplications to reduce data access and instruction execution time. In addition, embodiments of the present invention facilitate the fusion of addition operations.
[0026] Figure 1 shows a set of hardware components of a processor used to calculate a modular sum-of-products operation. Processor 10 may include an ALU 15 having one or more components for calculating the modular sum-of-products operation. One or more components of the ALU 15 may use pipeline processing to improve computational efficiency in one or more embodiments of the present invention. Furthermore, in some embodiments of the present invention, the results of one or more of the shown components may be stored as intermediate values, for example, in memory, registers, etc. The component that stores the intermediate (or final) results is also identified in Figure 1.
[0027] The components of ALU15 include one or more instances of adder 22, multiplier 24, and accumulator 26. Figure 1 also shows a code array 14 containing instructions to be executed, which include operands to be used for modular sum-of-products.
[0028] Furthermore, Figure 1 shows the bit widths of one or more components in ALU15 (e.g., 128b, 256b) and the width of the data transferred from one component to another during computation. It is understood that the bit widths may vary in one or more embodiments of the present invention. However, the bit width of the hardware may limit the modular sum-of-products operations that can be performed on that hardware.
[0029] The pipelines shown in Figure 1 are used in typical implementations of Barrett and Montgomery modular multiplication, as shown in Tables 1 and 2, respectively. As can be seen, three multipliers 24 are required. Furthermore, the pipelines do not include the addition operation that embodiments of the present invention provide after the multiplication is fused.
[0030] Embodiments of the present invention provide two FMMA instructions. The first FMMA instruction computes Barrett modular multiplication and subsequent addition in a fused manner. The syntax for the first FMMA instruction is fmma_b a, b, c, d. The second FMMA instruction provided computes Montgomery modular multiplication and subsequent addition in a fused manner. The syntax for the second FMMA instruction is fmma_m a, b, c, d. In the case of the Montgomery algorithm, the operands are in Montgomery form, and the resulting output is also in Montgomery form. Conversion of numbers to and from Montgomery form can be performed using techniques already known or to be developed in the future without affecting the technical solutions provided by embodiments of the present invention.
[0031] Here, a, b, c, and d are operands and can be registers in processor 10. In both cases, the output calculates d = ((a*b) + c) % p. In some embodiments of the present invention, a prime number p can also be an operand in the instruction syntax, but for the purposes of this description, p is used here assuming that ALU 15 is initialized with a prime number (step 1 in both Barrett and Montgomery instructions) and that pre-computation is called before the fmma_b / fmma_m instructions.
[0032] Figure 2 shows the architecture of a modular ALU that facilitates the execution of FMMA instructions according to one or more embodiments of the present invention. The modular ALU 25 includes one or more instances of an adder 22, a multiplier 24, and an accumulator 26, and uses pipeline processing similar to that of ALU 15. However, the accumulator 26 is used instead of the adder 22. Therefore, ALU 25 includes three multiplicative-accumulator (MAC) units 21, 23, and 27, each MAC block including a multiplier 24 and an accumulator 26. Furthermore, following the three MAC units 21, 23, and 27, an adder 29 having an additional bit width (e.g., 129 bits) is used. In some embodiments of the present invention, the bit width of the adder 29 is one more than the bit width of the multiplier 24 in the three MAC units 21, 23, and 27.
[0033] In ALU25, operands a and b are read and used by MAC21, and operand c is read by MAC27, specifically by the adder 26 of MAC27. Adder 29, which has a wider bit width, receives the output from MAC27.
[0034] Figure 3 shows a flowchart of a method for executing an FMMA_B instruction according to one or more embodiments of the present invention. Method 300 includes, in block 301, reading first and second operands a and b into a first MAC 21. The operands are read from data array 8. In block 302, the first MAC 21 performs binary multiplication of the first and second operands and accumulates the partial products.
[0035] In block 303, the second MAC23 performs binary multiplication of the result of block 302 with a predefined constant Mu. In one or more embodiments of the present invention, Mu is stored in the second MAC23.
[0036] In block 304, the third operand c is read, and the accumulator 26 in the third MAC 27 is initialized. The third operand is read into the lower bits of the accumulator 26 in the third MAC 27. For example, if the accumulator 26 is 256 bits wide and the operand c is 128 bits wide, then c is stored in bits 128 to 255 of the accumulator 26. Note that the third operand can be read into the third MAC in parallel with the binary multiplication in the first MAC 21 and the second MAC 23.
[0037] In block 305, the third MAC 27 multiplies the most significant bits of the result from step 303 by a coefficient p and accumulates the result in the pre-initialized accumulator 26 of the third MAC 27. Here, “most significant bits” can represent the first half of the result from step 303 (for example, the first 128 bits from a 256-bit value).
[0038] In block 306, the adder 22 subtracts the lower bits of the result in step 305 from the lower bits of the result in step 302. The results of steps 302 and 305 are the values stored in the accumulators 26 in the first MAC 21 and the third MAC 27, respectively.
[0039] In block 307, conditional correction is performed to ensure that the result from step 306 falls within the valid range of 0 to p.
[0040] The FMMA_B instruction, executed in this manner, is more efficient than the current sequential pipeline execution of modular multiply-accumulate operations. In one or more embodiments of the present invention, we consider executing fmma_b on a 512-bit operand using ALU25. As described, the third operand is used to initialize the lower 512 bits of the accumulator 26 in the third MAC27. The "storage MAX OP size" ensures that the accumulator has a bit width sufficient to write to the third operand. The accumulator 26 in the third MAC27 then operates on the output of the multiplier 24 and accumulates the data (i.e., adds the output with the pre-initialized third operand). The result of the third MAC27 may have a total of 513 bits, i.e., 512 bits from the multiplication plus additional bits due to the initial state of the accumulator 26. These bits are fed into the 129-bit adder 29 to execute step 5 in Table 1.
[0041] Here, since the 512-bit operation is performed with a 128-bit width, the bits are fed over a period of four clock cycles in some embodiments of the present invention. The first three clock cycles will each have 128 bits, and the final clock cycle will leave the last 129 bits empty. In other embodiments, the read operation can be performed with fewer or additional clock cycles.
[0042] In this way, fused modular sum-of-products is performed by ALU25 using Montgomery modular multiplication. FMMA_M, performed in this manner, improves efficiency by requiring fewer resources compared to performing modular sum-of-products separately and sequentially.
[0043] Figure 4 shows an ALU that facilitates the execution of an FMMA instruction according to one or more embodiments of the present invention. The modular ALU 35 includes one or more instances of an adder 22, a multiplier 24, and an accumulator 26, and uses pipeline processing similar to that of ALU 15. Here, ALU 35 includes three MAC units, namely a first MAC 31, a second MAC 33, and a third MAC 37. Following the three MAC units 31, 33, and 37, an adder 39 having an additional bit width (e.g., 129 bits) is used. In some embodiments of the present invention, the bit width of the adder 39 is one more than the bit width of the multiplier 24 in the three MAC units 31, 33, and 37.
[0044] In ALU35, the third operand c is read and used to initialize the upper bits of the adder 26 of the first MAC unit 31. The adder 39, which has a wider bit width, receives the output from MAC37.
[0045] Figure 5 shows a flowchart of a method for executing an FMMA_M instruction according to one or more embodiments of the present invention. Method 500 includes, in block 501, reading first and second operands a and b into a first MAC 31. The operands are read from data array 8. In block 502, the accumulator 26 of the first MAC 31 is initialized by reading a third operand c into the upper bits of the accumulator 26.
[0046] In block 503, the binary multiplication of the first and second operands is performed, and the result is accumulated in the pre-initialized accumulator 26 of the first MAC 31. The third operand c is added accordingly to the result of the binary multiplication of the first two operands.
[0047] In block 504, the lower bits of 503 are multiplied by the reciprocal of the coefficient P, which is pre-calculated by a second MAC33. In some embodiments of the present invention, the second MAC33 is initialized with the value of p before calling method 500.
[0048] In block 505, the third MAC37 multiplies the lower bits of step 504 by a coefficient p. The coefficient p is stored in the third MAC37 before calling method 500 in some embodiments of the present invention.
[0049] Furthermore, in block 506, adder 39 subtracts the upper bits of the result of step 505 from the upper bits of the result of step 503. Adder 39 can compute the subtraction using two's complement or any other known technique.
[0050] In block 507, conditional corrections are performed to ensure that the result from step 506 falls within the valid range of 0 to p.
[0051] Here, the “higher bits” can represent the first half of the result from one or more steps (e.g., bits 0 to 127 from a 256-bit value), and the “lower bits” can represent the second half of the result (e.g., bits 128 to 255 from a 256-bit value). The results of steps 503, 504, and 505 are values stored in the accumulator 26 in the first MAC31, second MAC33, and third MAC37, respectively.
[0052] The FMMA_M instruction, executed in this manner, is more efficient than the current sequential pipeline execution of modular multiply-accumulate operations. In one or more embodiments of the present invention, we consider executing fmma_m on a 128-bit operand using ALU35. The third operand is used to initialize the upper 128 bits of the 256-bit accumulator 26 of the first MAC unit 31. The lower 128 bits of the result of the accumulator 26 are passed to the next, i.e., the second and third MAC units 33, 37. In some cases, there may be 129 upper bits, i.e., 128 resulting from the multiplication and additional bits resulting from the initial state of the accumulator 26 of the first MAC 31. These 129 bits are then passed to the adder 39 to execute step 5 in Table 2.
[0053] Embodiments of the present invention improve support for existing modular arithmetic units to support fused multiply-accumulate with minimal hardware modification. The amount of hardware modification is only increasing the width of the adder by one bit (e.g., adders 29, 39). By initializing the accumulator with a third operand, FMMA can be achieved using any modular multiplication algorithm desired by the user. Furthermore, by performing FMMA by initializing the accumulator, embodiments of the present invention improve the processor's computation when modular multiply-accumulate operations are requested sequentially. The overall latency of modular multiplication and fused modular multiply-accumulate operations are both exactly the same. Thus, embodiments of the present invention provide improvements in the number of instructions required and, similarly, in the total latency of operations that can leverage FMMA.
[0054] Figure 6 illustrates an exemplary scenario in which the FMMA instruction improves the efficiency of calculations according to one or more embodiments of the present invention. Consider example code 600 of an algorithm that performs an iterative number theoretic transform (NTT) algorithm that includes butterfly operations. It is understood that any other algorithm / code that requires FMMA operations can be used instead of the example shown, and that the FMMA instruction described herein can be used in any other code. For Example 60, assume that A[k+j] is in register R0, A[k+j+m / 2] is in R1, w is in R2, and R3, R4 are temporary scratchpad registers.
[0055] As shown in block 61, an ALU (e.g., ALU15) that cannot execute a fused modular multiply-accumulate instruction uses two scratchpad registers (e.g., R2, R4), and four instruction calls are required to execute the request. As shown in block 62, by using any one of the fmma instructions described herein, the number of required scratchpad registers is reduced from two to one. Furthermore, the overall latency is reduced by the time of at least one modular add.
[0056] Accordingly, embodiments of the present invention facilitate improvements to computing technology by providing practical applications for implementing a single instruction that performs a fused modular multiply-accumulate operation. As provided herein, the fused operation can be implemented on current-era hardware without significant hardware modifications.
[0057] Figure 7 shows a block diagram of a processor according to one or more embodiments of the present invention. Among its components, the processor 10 may include, in particular, an instruction fetch unit 601, an instruction decoding operand fetch unit 602, an instruction execution unit 603, a memory access unit 604, a write-back unit 605, a set of registers 12, and an FMMA executor 606. In one or more embodiments of the present invention, the FMMA executor 606 may be part of an arithmetic logic unit (ALU) (not shown).
[0058] In one or more embodiments of the present invention, the processor 10 may be one of several computer processors in a processing unit, such as a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), or any other processing unit in a computer system. Alternatively, or in addition, the processor 10 may be a computing core that is part of one or more processing units.
[0059] The instruction fetch unit 601 is responsible for fetching program instructions from memory, organizing them so that they are executed in the correct order, and transferring them to the instruction execution unit 603. The instruction decoding operand fetch unit 602 facilitates parsing instructions and operands, such as address resolution and prefetching, before transferring the instructions to the instruction execution unit 603. The instruction execution unit 603 performs operations and calculations according to the instructions. The memory access unit 604 facilitates access to specific locations in memory devices coupled to the processor 10. The memory devices can be cache memory, volatile memory, non-volatile memory, etc. The write-back unit 605 facilitates recording the contents of register 12 to one or more locations in the memory device. The FMMA executor 606 facilitates the execution of FMMA instructions (fmma_b, or either fmma_b) as described herein.
[0060] It should be noted that the components of the processor may vary in one or more embodiments of the present invention without affecting the features of the technical solutions described herein. In some embodiments of the present invention, the components of the processor 10 may be combined with those described herein, or may be separate from them, or may be different from them.
[0061] Referring here to Figure 8, the computer system 1500 is shown overall according to one embodiment. The computer system 1500 can be a target computing system used to perform one or more functions that require modular multiply-accumulate operations to be performed. The computer system 1500 can be an electronic computer framework comprising and / or utilizing any number and combination of computing devices and networks that utilize various communication technologies, as described herein. The computer system 1500 can be readily scalable, extensible, and modular in its ability to change into different services or to reconfigure several features independently of others. The computer system 1500 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, the computer system 1500 may be a cloud computing node. The computer system 1500 may be described in the general context of computer system executable instructions, such as program modules, which are executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform a particular task or implement a particular abstract data type. The computer system 1500 may be implemented in a distributed cloud computing environment in which tasks are performed by remote processing devices linked through a communication network. In the distributed cloud computing environment, program modules may be located on both local computer system storage media, including memory storage devices, and remote computer system storage media.
[0062] As shown in Figure 8, the computer system 1500 has one or more central processing units (CPUs) 1501a, 1501b, 1501c, etc. (collectively or generally referred to as the processor 1501). The processor 1501 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The processor 1501, also referred to as the processing circuit, is coupled to the system memory 1503 and various other components via the system bus 1502. The system memory 1503 may include read-only memory (ROM) 1504 and random access memory (RAM) 1505. The ROM 1504 is coupled to the system bus 1502 and may include a basic input / output system (BIOS) that controls certain basic functions of the computer system 1500. The RAM is read-write memory coupled to the system bus 1502 for use by the processor 1501. The system memory 1503 provides temporary memory space for the operation of the above instructions during operation. The system memory 1503 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.
[0063] The computer system 1500 includes an input / output (I / O) adapter 1506 and a communication adapter 1507 coupled to a system bus 1502. The I / O adapter 1506 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 1508 and / or any other similar component. The I / O adapter 1506 and the hard disk 1508 are collectively referred to as mass storage 1510 in this specification.
[0064] Software 1511 for execution on computer system 1500 may be stored in mass storage 1510. Mass storage 1510 is an example of a tangible storage medium readable by processor 1501, where software 1511 is stored in computer system 1500 as instructions executed by processor 1501 to operate as described below in this specification with respect to various figures. Examples of computer program products and the execution of such instructions are discussed in more detail in this specification. A communication adapter 1507 interconnects system bus 1502 with network 1512, which may be an external network, enabling computer system 1500 to communicate with other such systems. In one embodiment, the system memory 1503 and the mass storage 1510 portion collectively store an operating system, which may be any suitable operating system such as the z / OS or AIX operating system from IBM Corporation for coordinating the functions of the various components shown in Figure 8.
[0065] Additional input / output devices are shown connected to the system bus 1502 via display adapter 1515 and interface adapter 1516. In one embodiment, adapters 1506, 1507, 1515, and 1516 may be connected to one or more I / O buses connected to the system bus 1502 via an intermediate bus bridge (not shown). A display 1519 (e.g., a screen or display monitor) is connected to the system bus 1502 by display adapter 1515, which may include a graphics controller to improve the performance of graphics-intensive applications and video controllers. Keyboards 1521, mice 1522, speakers 1523, etc., can be interconnected to the system bus 1502 via interface adapter 1516, which may include a Super I / O chip that integrates multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Therefore, as configured in Figure 8, the computer system 1500 includes processing capabilities in the form of a processor 1501, storage capabilities including system memory 1503 and mass storage 1510, input means such as a keyboard 1521 and a mouse 1522, and output capabilities including a speaker 1523 and a display 1519.
[0066] In some embodiments, the communication adapter 1507 can transmit data using any suitable interface or protocol, such as, in particular, an Internet Small Computer System interface. The network 1512 may be, in particular, a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet. An external computing device may connect to the computer system 1500 through the network 1512. In some examples, the external computing device may be an external web server or a cloud computing node.
[0067] It should be understood that the block diagram in Figure 8 is not intended to show that the computer system 1500 includes all the components shown in Figure 8. Rather, the computer system 1500 may include any suitable fewer or additional components not shown in Figure 8 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, embodiments of the computer system 1500 described herein may be implemented with any suitable logic, which, as referred herein, in various embodiments may include any suitable hardware (e.g., processors, embedded controllers, or application-specific integrated circuits), software (e.g., applications), firmware, or any suitable combination of hardware, software, and firmware.
[0068] The present invention may be a system, method, and / or computer program product at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or multiple mediums) having computer-readable program instructions for causing a processor to perform aspects of the present invention.
[0069] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of those described above. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved raised structures recording instructions, and any suitable combination of those described above. When used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmitting media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.
[0070] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers such instructions for storage in a computer-readable storage medium within the respective computing / processing device.
[0071] The computer-readable program instructions that perform the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, the one or more programming languages including object-oriented programming languages such as Smalltalk®, C++, etc., and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially executed on the user's computer as a standalone software package, partially executed on the user's computer and partially executed on a remote computer, or fully executed on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may be personalized by executing computer-readable program instructions using state information of computer-readable program instructions in order to perform an aspect of the present invention.
[0072] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.
[0073] These computer-readable program instructions can be provided to the processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to generate a machine, thereby creating means for instructions executed via the processor of the computer or other programmable data processing device to implement functions / operations specified in one or more blocks of a flowchart and / or block diagram. Furthermore, these computer-readable program instructions can be stored in a computer-readable storage medium, which can instruct computers, programmable data processing devices, and / or other devices to function in a specific manner, thereby resulting in a computer-readable storage medium containing instructions that include instructions for implementing modes of functions / operations specified in one or more blocks of a flowchart and / or block diagram.
[0074] Furthermore, computer-readable program instructions can be loaded into a computer, other programmable data processing device, or other device to execute a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process in which the instructions executed on the computer, other programmable device, or other device implement the functions / operations specified in one or more blocks of a flowchart and / or block diagram.
[0075] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions that implement a specified logical function. In some alternative implementations, the functions described in the blocks may be performed in an order different from the order shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart diagram, and combinations of blocks in the block diagram and / or flowchart diagram, can be implemented by a dedicated hardware-based system that performs a specified function or operation, or a combination of dedicated hardware and computer instructions.
[0076] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit to the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles, practical applications, or technical improvements to the technologies available on the market of the embodiments, or to enable other those skilled in the art to understand the embodiments disclosed herein.
Claims
1. The processing unit receives an instruction to perform a fused modular sum-of-accumulate operation, where d = ((a * b) + c) % p, where a, b, and c are provided as a set of operands; The first multiplication unit calculates a*b using a binary multiplication; A second multiplication unit calculates the first intermediate result by updating the result of the binary multiplication using p; Step c is the stage in which the accumulator of the third power accumulation unit is initialized; A third step in which the third multiplication unit calculates a second intermediate result using the first intermediate result and c; A step of subtracting a portion of the second intermediate result from a portion of the result of the binary multiplication using an adder; and The step of outputting the adder's output as a result of the fused modular sum-of-products operation. A computer implementation method comprising the above.
2. The computer implementation method according to claim 1, wherein the adder has a wider bit width than the multiplier in the first multiplication unit.
3. The computer implementation method according to claim 2, wherein the bit width of the adder is 1 greater than the bit width of the multiplier in the first multiplication unit.
4. The computer implementation method according to claim 1, wherein the step of initializing the accumulator of the third power accumulation unit with c includes the step of storing the value of c in the lower bits of the accumulator.
5. The computer implementation method according to any one of claims 1 to 4, wherein the step of calculating the first intermediate result comprises the step of performing a second binary multiplication of the result of the binary multiplication of a*b by a pre-calculated constant.
6. The computer implementation method according to claim 5, wherein the step of calculating the second intermediate result includes multiplying the upper bits of the first intermediate result by a coefficient p, the value of p being stored in the third multiplication unit before calling the instruction.
7. The computer implementation method according to any one of claims 1 to 4, further comprising the step of correcting the output of an adder to ensure that the output is between 0 and p.
8. A set of registers; and A set of multiplication units comprises three multiplication units, each containing a multiplier and an accumulator, the set of multiplication units is coupled to the set of registers, and the set of multiplication units is configured to perform a method of performing a fused modular multiply-accumulate operation, where a, b, and c are provided in the set of registers, and the performance of the fused modular multiply-accumulate operation is, The first multiplication unit calculates a*b using a binary multiplication; The second multiplication unit updates the result of the binary multiplication using p. The step of calculating the first intermediate result by means of; Step c is the stage in which the accumulator from the third power accumulation unit is initialized; A third step in which the third multiplication unit calculates a second intermediate result using the first intermediate result and c; A step of subtracting a portion of the second intermediate result from a portion of the result of the binary multiplication using an adder; and The step of outputting the adder's output as a result of the fused modular sum-of-products operation. A system equipped with these features.
9. The system according to claim 8, wherein the adder has a wider bit width than the multiplier in the first multiplication unit.
10. The system according to claim 9, wherein the bit width of the adder is 1 greater than the bit width of the multiplier in the first multiplication unit.
11. The system according to claim 8, wherein the step of initializing the accumulator from the third power accumulation unit with c comprises the step of storing the value of c in the lower bits of the accumulator.
12. The system according to any one of claims 8 to 11, wherein the step of calculating the first intermediate result comprises performing a second binary multiplication of the result of the binary multiplication of a*b by a pre-calculated constant.
13. The system according to claim 12, wherein the step of calculating the second intermediate result comprises multiplying the upper bits of the first intermediate result by a coefficient p, the value of which is stored in the third multiplication unit before calling the instruction to perform the fused modular multiply-accumulate operation.
14. The system according to any one of claims 8 to 11, further comprising the step of correcting the output of the adder to ensure that the output is between 0 and p.