Selective silicon deposition

Abstract

An exemplary semiconductor processing method may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The method may include providing a hydrogen-containing precursor to a processing region of the semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. The forming of the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of about 1000 W or less. The method may include depositing a silicon-containing material in the one or more patterned features along the substrate. The silicon-containing material may be deposited in the patterned features at a ratio of at least 2:1 relative to deposition on exposed regions of the substrate.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 500,664, filed on October 13, 2021, the entire content of which is incorporated herein by reference.

[0002]

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and systems for selectively depositing silicon - containing materials.

Background Art

[0003]

[0003] Integrated circuits are enabled by a process of forming complex - patterned material layers on a substrate surface. To form patterned materials on the substrate, a controlled method for forming and removing materials is required. As device sizes shrink, features within the integrated circuit may become smaller, the aspect ratio of the structures may increase, and it may become a challenge to maintain the dimensions of these structures during processing steps. Some processes involve etching of materials to form recessed features. However, this etching can create unwanted structures in the recessed features and the materials near the recessed features. It has been difficult to develop materials that can avoid the occurrence of undesirable side effects.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. These and other needs are addressed by this technology.

Summary of the Invention

[0005]

[0005] An exemplary semiconductor processing method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may include one or more patterned features separated by exposed areas of the substrate. The method may include supplying a hydrogen-containing precursor to the processing area of ​​the semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor can be performed with a plasma source power of about 1000 W or less. The method may include depositing a silicon-containing material on one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features in a ratio of at least 2:1 to the deposition on the exposed areas of the substrate.

[0006]

[0006] In some embodiments, the silicon-containing material may be silicon tetrachloride (SiCl4) or may contain silicon tetrachloride (SiCl4). One or more patterned features may be tin oxide, silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC), or may contain tin oxide, silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC). One or more patterned features may be on a carbon-containing layer. One or more patterned features may protrude from the carbon-containing layer by about 5 nm or more. The temperature in the semiconductor processing chamber may be maintained at about 100°C or less while the silicon-containing material is deposited on one or more patterned features. The pressure in the semiconductor processing chamber may be maintained at about 50 mTorr or less while the silicon-containing material is deposited on one or more patterned features. The method may include applying bias power to the processing area of ​​the semiconductor processing chamber while the silicon-containing material is deposited on one or more metal-containing features. The bias power can be approximately 100W or less.

[0007]

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may define one or more patterned features along the substrate. The method may include forming a plasma of the silicon-containing precursor. Forming the plasma of the silicon-containing precursor can be performed at a plasma output of about 1000 W or less. The method may include depositing a discontinuous silicon-containing layer on the substrate. The silicon-containing layer may be selectively deposited on one or more patterned features along the substrate.

[0008]

[0008] In some embodiments, the temperature inside the semiconductor processing chamber can be maintained at approximately 75°C or less while the silicon-containing material is deposited. The pressure inside the semiconductor processing chamber can be maintained at approximately 50 mTorr or less while the silicon-containing material is deposited. The method may include depositing a discontinuous silicon-containing layer on a substrate, and then etching one or more recesses in the carbon-containing layer deposited on the substrate using a plasma of an oxygen-containing precursor. The oxygen-containing precursor may be diatomic oxygen or may contain diatomic oxygen. After etching, one or more recesses may be characterized by undercuts of approximately 2 nm or less.

[0009]

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include supplying a silicon-containing precursor and a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may include a layer of carbon-containing material. The substrate may include a patterned metal-containing photoresist on top of the layer of carbon-containing material. At least a portion of the layer of carbon-containing material may be exposed through the patterned metal-containing photoresist. The method may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor can be performed at a plasma output of about 1000 W or less. The method may include depositing the silicon-containing material on a metal-containing photoresist patterned along the substrate. The method may include supplying an oxygen-containing precursor to a processing area of ​​a semiconductor processing chamber. The method may include forming a plasma of the oxygen-containing precursor. The method may include etching one or more recesses using the plasma of the oxygen-containing precursor.

[0010]

[0010] In some embodiments, the silicon-containing material is silicon tetrachloride (SiCl4). The method may include applying bias power to the processing area of ​​a semiconductor processing chamber while depositing the silicon-containing material onto a patterned metal-containing photoresist. The bias power may be about 100 W or less. The method may include reducing the pressure in the semiconductor processing chamber before supplying an oxygen-containing precursor to the processing area of ​​the semiconductor processing chamber. Forming the plasma of the oxygen-containing precursor can be performed with a plasma output of about 300 W or more.

[0011]

[0011] The above technology may offer numerous advantages over conventional methods and techniques. For example, this process can selectively deposit silicon-containing materials, such as metal-containing or silicon-containing features, onto non-carbon materials. Furthermore, this process can reduce or limit the removal of patterned features or undercuts when etching recesses in the material beneath the patterned features. These and other embodiments will be described in more detail below, along with their many advantages and features, in conjunction with the accompanying figures.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic top view showing an exemplary processing system according to several embodiments of this technology. [Figure 2] This is a schematic cross-sectional view showing an exemplary processing system according to several embodiments of this technology. [Figure 3] This figure shows selected steps in a semiconductor processing method according to several embodiments of this technology. [Figure 4] Figures A to C show exemplary schematic cross-sectional structures that include and are formed with material layers according to several embodiments of this technology. [Modes for carrying out the invention]

[0014]

[0017] Some of the figures are included as schematic diagrams. Please understand that the figures are for illustrative purposes only and should not be considered to scale unless the scale is specifically stated. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0015]

[0018] In the attached diagrams, similar components and / or features may be given the same reference label. Furthermore, various components of the same type may be distinguished by adding a letter after the reference label to distinguish similar components. If only the first reference label is used herein, its description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016]

[0019] As device sizes continue to shrink, many material layers may also be reduced in thickness, width, and size to scale the device. As the size of features within a semiconductor structure decreases, it can become more difficult to perform various processes such as lithography, deposition, and etching while maintaining structural integrity.

[0017]

[0020] Conventional techniques have struggled to etch recesses between patterned features, such as those in metal oxide photoresists. While metal oxide photoresists can be useful in many etching processes, their films are formed to much thinner thicknesses than conventional photoresist materials. Therefore, etching processes for patterning materials two to three times the thickness of the metal oxide photoresist can cause the photoresist to be removed or altered, potentially resulting in tapered etching shapes or incomplete processing. Etching of recesses can unintentionally etch the patterned features themselves, undercut features, or etch recesses with angled sidewalls. Any of these side effects during etching can lead to undesirable structures. Furthermore, conventional techniques sometimes require performing the etching process in one chamber, releasing the vacuum to transfer the structure, and then performing the deposition process in another chamber. This transfer can introduce undesirable contamination during processing. Consequently, many conventional techniques have limited ability to prevent structural defects in the final device.

[0018]

[0021] This technology overcomes these problems by depositing silicon-containing materials on metal oxide photoresist materials or other silicon-containing materials, for example, selectively onto patterned features. The deposition can be performed in the same chamber as the etching process, thereby improving structural integrity by limiting waiting times and exposure to the atmosphere. By depositing the silicon-containing material as a protective layer on the patterned features, this technology ensures that the photoresist remains intact throughout the process. During the subsequent etching process, the silicon-containing material can protect the patterned material from being removed and act as a second mask to form recesses in the underlying material deposited on the substrate. By depositing the silicon-containing material, this technology can prevent problems in any subsequent integration process and / or defects in the final device.

[0019]

[0022] While the remaining disclosure always identifies specific deposition and etching processes that utilize the disclosed technology, it will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may be carried out in the described chambers. Therefore, the technology should not be considered limited to use only in the described deposition or etching processes. Before describing the systems and methods or steps of exemplary process sequences according to several embodiments of the technology, this disclosure describes one possible system and chamber that may be used with the technology. It should be understood that the technology is not limited to the described equipment, and the processes described may be carried out in any number of processing chambers and systems.

[0020]

[0023] Figure 1 is a top view showing one embodiment of a deposition, etching, firing, and / or curing chamber processing system 10 according to an embodiment. The tool or processing system 10 shown in Figure 1 may include a plurality of process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated measurement chamber 28, and a pair of load lock chambers 16a-b. The process chambers may include any number of structures or components, and any number or combination of process chambers.

[0021]

[0024] To transfer substrates between chambers, the transfer chamber 20 may include a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a, each attached to the distal end of an extendable arm 22b. The blades 22a can be used to transport individual substrates in and out of process chambers. In the process, one of the substrate transport blades, such as the blades 22a of the transport mechanism 22, can take a substrate W from one of the load-lock chambers, such as chambers 16a-b, and transport the substrate W to the first stage of processing, such as a treatment process, as described later, in chambers 24a-d. Chambers may be included to perform individual or combined steps of the described technology. For example, one or more chambers may be configured to perform a deposition or etching step, while one or more other chambers may be configured to perform the described pre-treatment steps and / or one or more post-treatment steps. Any number of configurations capable of performing any number of additional manufacturing steps commonly performed in semiconductor processing are included in the technology.

[0022]

[0025] If a chamber is occupied, the robot can wait until processing is complete, after which it can remove the processed substrate from the chamber with one blade 22a and insert a new substrate with a second blade. Once the substrate is processed, it can then be moved to the second stage of processing. For each move, the transport mechanism 22 may generally have one blade for carrying the substrate and one empty blade for performing the substrate exchange. The transport mechanism 22 can wait in each chamber until the exchange can be completed.

[0023]

[0026] Once the processing in the process chamber is completed, the transport mechanism 22 can move the substrate W from the last process chamber and transport the substrate W to the cassette in the load lock chambers 16a - b. From the load lock chambers 16a - b, the substrate can move into the factory interface 12. The factory interface 12 can generally operate to transfer the substrate between the pod loaders 14a - d and the load lock chambers 16a - b in a clean environment at atmospheric pressure. The clean environment of the factory interface 12 can generally be obtained through an air filtration process such as HEPA filtration. The factory interface 12 can also include a substrate orienter / aliner that can be used to properly align the substrate before processing. At least one substrate robot, such as robots 18a - b, can be positioned within the factory interface 12 to transport the substrate between various positions / places within the factory interface 12 and other locations connected thereto. The robots 18a - b can be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0024]

[0027] The processing system 10 can further include an integrated measurement chamber 28 for supplying a control signal that can provide adaptive control for any of the processes being executed in the processing chamber. The integrated measurement chamber 28 can include any of various measurement devices for measuring various film characteristics such as thickness, roughness, composition, etc., and the measurement devices can further be capable of characterizing grating parameters such as critical dimensions, sidewall angles, and feature heights under vacuum in an automated manner.

[0025]

[0028] Each of the processing chambers 24a - d may be configured to perform one or more process steps in the manufacture of semiconductor structures, and any number of processing chambers and combinations of processing chambers may be used in the multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing steps including any number of deposition processes such as cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, as well as other processes including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Specific processes that may be performed in any of the chambers, or any combination of chambers, may include metal deposition, surface cleaning and pre-treatment, thermal annealing such as rapid thermal processing, plasma treatment, etc. As will be readily understood by those skilled in the art, any other process may equally be performed in a particular chamber incorporated in the multi-chamber processing system 10, including any of the processes described below.

[0026]

[0029] Figure 2 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer placed on a substrate 302 in the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that embodiments of the art can be performed in any number of chambers, and the substrate support relating to the art may be contained in an etching chamber, a deposition chamber, a treatment chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber region 101 in which the substrate can be processed. The chamber body 105 may have side walls 112 and a bottom 118 coupled to a ground 126. The side walls 112 may have a liner 115 to protect the side walls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limited and may generally be proportionally larger than the size of the substrate 302 processed therein. Examples of substrate sizes include diameters of 200mm, 250mm, 300mm, and 450mm, and display substrates and solar cell substrates are similar in size.

[0027]

[0030] The chamber body 105 can support a chamber lid assembly 110 to enclose the chamber region 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 may be formed through the side wall 112 of the chamber body 105 to facilitate the transfer of substrates 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled to the transfer chamber and / or other chambers of the substrate processing system, as described above. A pumping port 145 may be formed through the side wall 112 of the chamber body 105 and connected to the chamber region 101. A pumping device can be coupled to the chamber region 101 through the pumping port 145 to exhaust and control the pressure within the processing region. The pumping device may include one or more pumps and throttle valves.

[0028]

[0031] The gas panel 160 can be connected to the chamber body 105 by a gas line 167 to supply process gas into the chamber region 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases so that it can be used for any number of processes. Examples of process gases that can be supplied by the gas panel 160 include, but are not limited to, methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, or oxygen gas, and any number of additional materials. Furthermore, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among any number of additional precursors.

[0029]

[0032] Valve 166 can control the flow of process gas from sources 161, 162, 163, and 164 of the gas panel 160, and can be managed by controller 165. The flow of gas supplied from the gas panel 160 to the chamber body 105 may include a combination of gases from one or more sources. The lid assembly 110 may include nozzles 114. Nozzles 114 may be one or more ports for introducing process gas from sources 161, 162, 164, and 163 of the gas panel 160 into the chamber region 101. After the process gas is introduced into the plasma processing chamber 100, a voltage may be applied to the gas to form a plasma. One or more antennas 148, such as induction coils, may be provided adjacent to the plasma processing chamber 100. Antenna power supply 142 can supply power to the antennas 148 through a matching circuit 141 to inductively couple energy, such as RF energy, to the process gas and maintain the plasma formed from the process gas in the chamber region 101 of the plasma processing chamber 100. Instead of, or in addition to, the antenna power supply 142, process electrodes below and / or above the substrate 302 can be used to capacitively couple RF power to the process gas to maintain the plasma in the chamber region 101. The operation of the power supply 142 may be controlled by a controller such as the controller 165, which also controls the operation of other components of the plasma processing chamber 100.

[0030]

[0033] A substrate support pedestal 135 may be positioned in the chamber region 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 can hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include electrodes 121 embedded in a dielectric. The electrodes 121 may be coupled to the RF power supply 125 and can supply a bias that attracts plasma ions formed by the process gas in the chamber region 101 to the ESC 122 and the substrate 302 seated on the pedestal. The RF power supply 125 repeatedly turns on and off or supplies pulses during processing of the substrate 302. The ESC122 may have an isolator 128 to prevent plasma from being attracted to the sidewalls of the ESC122 and to extend the maintenance life of the ESC122. Furthermore, the substrate support pedestal 135 may have a cathode dryer 136 to protect the sidewalls of the substrate support pedestal 135 from plasma gas and to extend the maintenance interval of the plasma processing chamber 100.

[0031]

[0034] Electrode 121 may be coupled to a power supply 150. The power supply 150 can supply a chucking voltage to electrode 121 ranging from approximately 200 volts to approximately 2000 volts. The power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing a DC current to electrode 121 for chucking and dechucking the substrate 302. ESC 122 may include a heater located within a pedestal and connected to the power supply for heating the substrate, and a cooling base 129 supporting ESC 122 may include conduits for circulating a heat transfer fluid to maintain the temperature of ESC 122 and the substrate 302 placed on it. ESC 122 may be configured to operate within the temperature range required by the thermal balance of the device fabricated on the substrate 302. For example, ESC 122 may be configured to maintain the substrate 302 at a temperature ranging from approximately -150°C or below to approximately 500°C or above, depending on the process being performed.

[0032]

[0035] A cooling base 129 can be provided to assist in temperature control of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 can be kept substantially constant by the cooling base 129 while the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 can be maintained between approximately -150°C and approximately 500°C during the subsequent cleaning process, although any temperature is also possible. A covering 130 may be positioned on the ESC 122 and along the periphery of the substrate support pedestal 135. The covering 130 may be configured to contain etching gases to desired portions of the exposed upper surface of the substrate 302 while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins can selectively translate through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135, facilitating access to the substrate 302 by a transfer robot or other suitable transfer mechanism, as described above.

[0033]

[0036] The controller 165 may be used to control the process sequence, regulate the gas flow from the gas panel 160 into the plasma processing chamber 100, and control other process parameters. When executed by the CPU, the software routines transform the CPU into a computer for a particular purpose, such as a controller, which can control the plasma processing chamber 100 so that the process is carried out in accordance with this disclosure. The software routines may also be stored and / or executed by a second controller which may be associated with the plasma processing chamber 100.

[0034]

[0037] The processing chambers described above can be used in methods according to embodiments of this technology. Figure 3 shows a semiconductor processing method 300 in which the process can be performed in one or more chambers 100 incorporated into a multi-chamber processing system 10, for example, as described above. It is also possible to utilize any other chambers in which one or more steps of any described method or process can be performed. Method 300 may include one or more steps prior to the commencement of the described method steps, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that can be performed before the described steps. This method may include a number of optional steps, as shown in the figure, which may or may not be particularly related to the methods relating to this technology. For example, many steps have been described to provide a broader range of semiconductor processes, but may not be important to this technology, or may be performed by alternative methodologies, as will be described further later.

[0035]

[0038] Method 300 may include a number of steps that can be performed in numerous variations, including starting at different stages of the process. Generally, Method 300 may include a deposition step that can be performed in a chamber in which the etching process can be carried out. Often, deposition can be performed before etching. Therefore, although Method 300 is described in a specific order, it should be understood that the method can be performed in numerous different variations according to embodiments of the Art. Method 300 can be described in the steps schematically shown in Figures 4A to 4C, and these illustrations will be described in conjunction with the steps of Method 300. It should be understood that the structure 400 in Figures 4A to 4C is only a partial schematic, and the substrate 405 may include any number of structural parts having the illustrated configurations, as well as alternative structural configurations that can also benefit from the steps of the Art.

[0036]

[0039] The substrate 405 may be placed within the processing area of ​​the semiconductor processing chamber 100, or in any other processing chamber in which the processes of the present technology can be performed. In embodiments, the substrate 405 may have a substantially flat surface or a surface with irregularities. The substrate 405 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have various dimensions, such as a rectangular or square panel, or a wafer with a diameter of 200 mm or 300 mm. As shown in Figure 4A, the substrate 405 may include one or more patterned features 415, such as a patterned metal-containing photoresist, separated by the exposed area of ​​the substrate 405. In other words, the patterned material may be a patterned metal-containing photoresist. The patterned feature 415 may be any number of metals, or may contain any number of metals. For example, the patterned feature 415 may contain a metal oxide, or any material composed of metal and oxygen. In embodiments, the patterned feature 415 may be tin oxide, silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC), or tungsten, or may contain tin oxide, silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC), or tungsten. While the remaining disclosure always refers to metal oxide photoresists, it should be understood that the technology may encompass additional materials on which selective deposition may be performed. Therefore, it should be understood that feature 415 is not limited to metal oxide photoresists, and in embodiments encompassed by this technology, it may be or may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), tin oxide (SnO), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and crystalline silicon.

[0037]

[0040] In embodiments, the patterned features 415 may lie on a carbon-containing layer 410 deposited on a substrate 405. The carbon-containing layer 410 may be, for example, a spin-on carbon hard mask, chemically vapor-deposited carbon, or plasma vapor-deposited carbon. The carbon-containing layer 410 may have a thickness of about 20 nm or more, about 25 nm or more, about 30 nm or more, or greater. Similarly, the carbon-containing layer 410 may have a thickness of about 40 nm or less, about 35 nm or less, about 30 nm or less, or less. One or more patterned features 415 may protrude from the carbon-containing layer 410 by about 5 nm or more, for example, about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, or greater. In embodiments, at least a portion of the carbon-containing layer 410 may be exposed through the patterned features 415, such as a patterned metal-containing photoresist.

[0038]

[0041] Referring to Figures 4A to 4B, in step 305, method 300 may include supplying a silicon-containing precursor to the processing area of ​​a semiconductor processing chamber. The silicon-containing precursor that can be used in step 305 may be any number of silicon-containing precursors, or may include any number of silicon-containing precursors. For example, the silicon-containing precursor may be silane (SiH4), disilane (Si2H6), silicon tetrachloride (SiCl4), or any other precursor capable of forming materials such as silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC), or may include the same. The selected silicon-containing precursor may affect the deposition rate or film properties. The flow rate of the silicon-containing precursor may be about 5 sccm or more, for example, about 10 sccm or more, about 15 sccm or more, or greater. The flow rate of the silicon-containing precursor may be adjusted according to the desired growth rate.

[0039]

[0042] In step 310, method 300 may include supplying a hydrogen-containing precursor to the processing area of ​​a semiconductor processing chamber. The hydrogen-containing precursor that can be used in step 310 may be, or include, any number of hydrogen-containing precursors, such as diatomic hydrogen, without limitation. The flow rate of the hydrogen-containing precursor may be about 40 sccm or more, for example, about 50 sccm or more, about 60 sccm or more, or more.

[0040]

[0043] The flow rates of the silicon-containing precursor and the hydrogen-containing precursor may be related. For example, the flow rate of the hydrogen-containing precursor can be maintained at a flow rate ratio of approximately 1:1 or higher to the silicon-containing precursor while the silicon-containing material 420 is being deposited, as described below. Higher flow rates may reduce the selectivity of the silicon-containing material 420, potentially leading to reduced deposition, as described later. Higher flow rates also mean that more silicon-containing precursor is supplied to the semiconductor processing chamber, and therefore more silicon-containing material 420 is available for deposition. Furthermore, depending on the silicon-containing precursor used, the atomic percentage of silicon in the deposited silicon-containing material 420 may decrease, and other components of the silicon-containing precursor may become more abundant, potentially leading to less selectivity for the patterned features 415. Therefore, the flow rate ratio can be approximately 2:1 or higher, approximately 3:1 or higher, approximately 4:1 or higher, approximately 5:1 or higher, approximately 6:1 or higher, approximately 7:1 or higher, approximately 8:1 or higher, approximately 9:1 or higher, approximately 10:1 or higher, or higher.

[0041]

[0044] In step 315, method 300 may include forming a plasma. The plasma may be formed from a silicon-containing precursor and / or a hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and / or hydrogen-containing precursor may be performed at a plasma output of about 3000 W or less. At higher plasma outputs, it may be difficult to maintain linewidth even during the deposition process due to the energy and etchant capacity of the radical effluent. Furthermore, the silicon-containing material 420 deposited on the patterned feature 415 may grow so rapidly that the resulting material on the patterned feature 415 is prone to top ringing. In addition, higher plasma outputs may result in shorter step times, making it difficult to control the amount of silicon-containing material 420 deposited. Therefore, the plasma output can be maintained at approximately 2000W or less, approximately 1000W or less, approximately 900W or less, approximately 800W or less, approximately 700W or less, approximately 600W or less, approximately 500W or less, approximately 400W or less, approximately 300W or less, approximately 200W or less, or less.

[0042]

[0045] In step 320, method 300 may include depositing silicon-containing material 420 onto one or more patterned features 415. The silicon-containing material 420 may be selectively deposited on the patterned material and not on the underlying carbon-containing layer 410, which may be based on hydrogen interactions, as will be further described below. However, it is also conceivable that some of the silicon-containing material 420 may be deposited on the carbon-containing layer 410. The silicon-containing material 420 may be deposited on the patterned features 415 in a ratio of at least 2:1 to deposition on the exposed areas of the substrate 405, and may be deposited on the patterned features in a ratio of about 5:1 or more, about 10:1 or more, about 15:1 or more, about 20:1 or more, or more.

[0043]

[0046] In step 320, method 200 may include applying bias power to the plasma while depositing silicon-containing material 420 onto one or more patterned features 415. The application of bias power may be used to increase the selectivity of the deposition of silicon-containing material 420 onto the patterned features 415, instead of overexposed areas of the substrate 405 such as the carbon-containing layer 410. Applying a bias may cause plasma wastewater of hydrogen-containing precursors to react and interact more readily with the carbon-containing layer 410, resulting in less hydrogen being available at those locations for reaction with the silicon-containing precursors, potentially causing silicon to bond with carbon. Without bias power, the silicon-containing material 420 may deposit more conformally with reduced selectivity for the patterned features 415. However, increasing the bias power may decrease the deposition rate of the silicon-containing material 420, potentially causing etching of already deposited silicon-containing material 420 or patterned features 415 during step 320. Therefore, the bias power can be applied at approximately 90W or less, approximately 80W or less, approximately 70W or less, approximately 60W or less, approximately 50W or less, approximately 40W or less, approximately 30W or less, approximately 20W or less, approximately 10W or less, or less.

[0044]

[0047] The bias power may be applied continuously or pulsed according to several embodiments of the present technology. In embodiments in which the bias power is pulsed, the pulsing frequency may be about 2000 Hz or less, and may be pulsed at frequencies of about 1500 Hz or less, about 1000 Hz or less, or about 500 Hz or less. Furthermore, the duty cycle at the pulsing frequency may be maintained at about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, or less. This can further reduce the effective bias power applied during the deposition process. By increasing the flow rate of the hydrogen-containing precursor compared to the silicon-containing precursor, the bias power used to control formation on the carbon material can be made much lower, further limiting the etching of the material deposited on the photoresist.

[0045]

[0048] During the deposition of silicon-containing material 420 onto one or more patterned features 415, the temperature in the semiconductor processing chamber, such as the substrate support temperature or substrate temperature, can be maintained at approximately 100°C or lower. At higher temperatures, the deposition rate may decrease, and the silicon-containing material 420 may deposit on the sidewalls of the patterned features 415. At higher temperatures, the silicon-containing material 420 may become more fluid, making it impossible to deposit directly onto the top of the patterned features 415. Therefore, the temperature can be maintained at approximately 90°C or lower, approximately 80°C or lower, approximately 70°C or lower, approximately 60°C or lower, approximately 50°C or lower, or below.

[0046]

[0049] The pressure inside the semiconductor processing chamber 100 can be maintained at about 50 mTorr or less while depositing silicon-containing material 420 onto one or more patterned features 415. Higher pressures may result in more conformal deposition, preventing the silicon-containing material 420 from being selectively deposited onto the patterned material. Therefore, in some embodiments, the pressure can be maintained at about 40 mTorr or less, about 30 mTorr or less, about 20 mTorr or less, about 10 mTorr or less, or less.

[0047]

[0050] Referring to Figure 4C, in the optional step 325, method 300 may include an etching process. The etching process of optional step 325 may be carried out in the same chamber as step 320 or in a different chamber. Step 325 may include etching one or more recesses within the carbon-containing layer 410 deposited on the substrate 405. More specifically, the etching process may include supplying an oxygen-containing precursor, such as diatomic oxygen, to the processing area of ​​the semiconductor processing chamber. After supplying the oxygen-containing precursor, the process may include forming a plasma of the oxygen-containing precursor. Finally, the process may include etching exposed areas of the carbon-containing layer 410 with the plasma of the oxygen-containing precursor to form recesses in the silicon-containing material 420. The etching process may cause a reduction or removal of the mask layer due to collisions or other interactions, but some or all of the silicon-containing material and photoresist may remain during etching.

[0048]

[0051] During the etching process of this embodiment, the patterned features can be preserved without damage, and etching can yield vertical recesses made of the deposited silicon-containing material 420. This makes it possible to use a structure 400 with improved structural integrity in subsequent processes or in the final product. After etching, the recesses may feature undercuts of approximately 3 nm or less.

[0049]

[0052] The etching process can be performed with higher processing power compared to the deposition process. For example, both the power supply power and the bias power can be increased between the deposition and etching processes in the processing chamber. For instance, the power supply power can be increased from the power during deposition to a second power of approximately 300W or more, approximately 350W or more, approximately 400W or more, or higher. Similarly, the bias power can be increased from the first bias power during deposition to a second bias power of approximately 50W or more, approximately 60W or more, approximately 70W or more, approximately 80W or more, approximately 90W or more, approximately 100W or more, or higher. Furthermore, the duty cycle applied to the bias pulsing frequency can be increased from the first duty cycle during deposition to a second duty cycle of approximately 20% or more, approximately 30% or more, approximately 40% or more, approximately 50% or more, or higher. As the bias decreases, the isotropy of the plasma increases, which can result in larger undercuts during etching. However, by increasing the power between deposition and etching, improved etching shapes may be obtained.

[0050]

[0053] In conventional embodiments where the silicon-containing material is not deposited before the etching process, the final structure may suffer from reduced or complete removal of the remaining patterned features, and / or undercuts in the etched recesses. Embodiments of the present disclosure can avoid or mitigate these problems as described above. The deposited silicon-containing material 420 described above allows the present disclosure to reduce the amount of patterned features 415 consumed during step 325, and to maintain bias power during step 325, thereby allowing the sidewalls within the recesses to be straighter.

[0051]

[0054] In the specifications described so far, numerous details have been included for explanatory purposes to enable an understanding of the various embodiments of this technology. However, it will be clear to those skilled in the art that certain embodiments can be implemented by omitting some of these details or by adding additional details.

[0052]

[0055] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, some well-known processes and elements have not been described. Therefore, the above specifications should not be construed as limiting the scope of the Art.

[0053]

[0056] Where a range of values ​​is provided, unless the context explicitly indicates otherwise, each intervening value between the upper and lower limits of that range, down to the smallest unit of the lower limit, is also specifically disclosed. This includes any narrower range between any listed value or an unlisted intervening value of a listed range and any other listed value or intervening value of that range. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range that includes one or both limits of the range, or neither limits of the range, is also included in this technology according to any specifically excluded limits in the listed range. Where a listed range includes one or both limits, ranges that exclude one or both of those included limits are also included.

[0054]

[0057] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context explicitly indicates otherwise. Thus, for example, a reference to "silicon-containing precursors" includes multiple such precursors, and a reference to "silicon-containing materials" includes one or more materials and their equivalents that are well known to those skilled in the art.

[0055]

[0058] Furthermore, as used herein and in the following claims, the terms “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” specify the presence of the described feature, integer, component, or process, but do not preclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, The present invention relates to supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed within the processing area of ​​the semiconductor processing chamber, a carbon-containing layer is placed on the substrate, and the substrate includes one or more patterned features separated by exposed areas of the substrate on the carbon-containing layer, and the present invention relates to supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed within the processing area of ​​the semiconductor processing chamber, a carbon-containing layer is placed on the substrate, and the substrate includes one or more patterned features separated by exposed areas of the substrate on the carbon-containing layer, The process involves supplying a hydrogen-containing precursor to the processing area of ​​the semiconductor processing chamber, Forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor, performed with a plasma output of 1000 W or less; Depositing a silicon-containing material onto the one or more patterned features, wherein the silicon-containing material is deposited on the patterned features in a ratio of at least 2:1 to the deposition on the exposed areas of the substrate. Includes, A method wherein the one or more patterned features include at least one of silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC).

2. The silicon-containing precursor is silicon tetrachloride (SiCl ４ The semiconductor processing method according to claim 1, including ).

3. The semiconductor processing method according to claim 1, wherein the carbon-containing layer has a thickness of 20 nm or more.

4. The semiconductor processing method according to claim 3, wherein the one or more patterned features protrude 5 nm or more from the carbon-containing layer.

5. The semiconductor processing method according to claim 1, wherein the temperature in the semiconductor processing chamber is maintained at 100°C or less while the silicon-containing material is deposited on the one or more patterned features.

6. The semiconductor processing method according to claim 1, wherein the pressure in the semiconductor processing chamber is maintained at 40 mTorr or less while the silicon-containing material is deposited on the one or more patterned features.

7. The semiconductor processing method according to claim 1, further comprising applying bias power to the processing area of ​​the semiconductor processing chamber while depositing the silicon-containing material onto the one or more patterned features, wherein the bias power is 100 W or less.

8. The oxygen-containing precursor is supplied to the processing area of ​​the semiconductor processing chamber, Forming a plasma of the oxygen-containing precursor, To form a recess in the silicon-containing material, the plasma of the oxygen-containing precursor is used to etch a portion of the silicon-containing material and the exposed region of the substrate, wherein, after etching, the recess has an undercut of 3 nm or less, and the portion of the silicon-containing material and the exposed region of the substrate are etched. The semiconductor processing method according to claim 1, further comprising:

9. The semiconductor processing method according to claim 8, wherein the formation of the plasma of the oxygen-containing precursor is performed with a plasma output of 300 W or more.

10. A semiconductor processing method, The method involves supplying a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed within the processing area of ​​the semiconductor processing chamber, a carbon-containing layer is placed on the substrate, and the substrate defines one or more patterned features along the carbon-containing layer on the substrate. Forming the silicon-containing precursor plasma, which is performed with a plasma output of 1000 W or less, A discontinuous silicon-containing layer is deposited on the substrate, wherein the silicon-containing layer is selectively deposited on the one or more patterned features along the substrate, Includes, A method wherein the one or more patterned features include at least one of silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC).

11. During the deposition of the aforementioned discontinuous silicon-containing layer, the temperature inside the semiconductor processing chamber is maintained at 75°C or below. The semiconductor processing method according to claim 10, wherein the pressure in the semiconductor processing chamber is maintained at 40 mTorr or less while the discontinuous silicon-containing layer is deposited.

12. The semiconductor processing method according to claim 10, further comprising depositing a discontinuous silicon-containing layer on the substrate, and then etching one or more recesses in the carbon-containing layer deposited on the substrate using plasma of an oxygen-containing precursor.

13. The semiconductor processing method according to claim 12, wherein the oxygen-containing precursor contains diatomic oxygen.

14. The semiconductor processing method according to claim 12, wherein, after etching, the one or more recesses have an undercut of 2 nm or less.

15. A semiconductor processing method, Supplying silicon-containing precursors and hydrogen-containing precursors to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area of ​​the semiconductor processing chamber, a layer of carbon-containing material is placed on the substrate, the substrate includes patterned features on the layer of carbon-containing material, and at least a portion of the layer of carbon-containing material is exposed through the patterned features, and supplying silicon-containing precursors and hydrogen-containing precursors to a processing area of ​​a semiconductor processing chamber, wherein the substrate is placed within the processing area of ​​the semiconductor processing chamber, a layer of carbon-containing material is placed on the substrate, the substrate includes patterned features on the layer of carbon-containing material, and at least a portion of the layer of carbon-containing material is exposed through the patterned features, Forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor, performed with a plasma output of 1000 W or less; Depositing a silicon-containing material onto the patterned features along the substrate, The oxygen-containing precursor is supplied to the processing area of ​​the semiconductor processing chamber, Forming a plasma of the oxygen-containing precursor, Etching one or more recesses using the plasma of the oxygen-containing precursor. Includes, The method wherein the patterned feature comprises at least one of silicon, silicon oxide, silicon oxynitride, or a silicon-containing anti-reflective layer (SiARC).

16. The silicon-containing precursor is silicon tetrachloride (SiCl ４ The semiconductor processing method according to claim 15, including ).

17. The semiconductor processing method according to claim 15, further comprising applying bias power to the processing area of ​​the semiconductor processing chamber while depositing the silicon-containing material on the patterned features, wherein the bias power is 100 W or less.

18. The semiconductor processing method according to claim 15, further comprising reducing the pressure inside the semiconductor processing chamber before supplying the oxygen-containing precursor to the processing area of ​​the semiconductor processing chamber.

19. The semiconductor processing method according to claim 15, wherein the formation of the plasma of the oxygen-containing precursor is performed with a plasma output of 300 W or more.

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