Bridge tip with through-via

Abstract

Techniques are provided for interconnecting chips using a bridge chip with through vias. In one embodiment, a structure includes a bridge chip attached to at least a first chip and a second chip, the bridge chip having at least one conductive through via connecting the bridge chip to one of the first chip and the second chip. The bridge chip can include a wiring layer having a plurality of metal lines present between a first capping layer and a second capping layer, and the at least one conductive through via can directly contact at least a sidewall of at least one of the plurality of metal lines. A method of integrating chips using the bridge chip is also provided.

Description

[Technical Field]

[0001] The present invention relates to chip interconnection technology, and more particularly to a technology for interconnecting chips using a bridge chip having through-vias that eliminate external connections between chips. [Background technology]

[0002] In heterogeneous integration for artificial intelligence workloads, high bandwidth is crucial for inter-chip communication. In some configurations, this inter-chip communication must occur while the chips are connected to a laminated package.

[0003] Bridge chips are sometimes used to connect chips to each other to enable them to communicate with each other with relatively low power loss while mounted in a laminate package. Solder or other suitable types of interconnecting materials (such as adhesive) may then be used to attach the bridge chip to the laminate package.

[0004] However, there are several significant challenges associated with integrating bridge chips into chip layout designs. For example, some designs have bridge chips embedded in laminate packages. In such cases, a dedicated recess-containing laminate is required. This inevitably involves customized laminates, which can be difficult and costly to manufacture with good production yields due to the need to precisely position recesses (or possibly multiple recesses) of tightly controlled depths within a certain area of ​​the laminate.

[0005] Furthermore, conventional methods for integrating bridge chips into chip layout designs often require external solder connections with uneven pitches, making it difficult to reduce chip dimensions to small sizes. Copper (Cu)-to-Cu chip connections offer the potential for tighter pitches than conventional soldering methods. However, Cu-to-Cu chip connections are difficult to implement in practice due to the challenges associated with the Cu / dielectric flatness requirement and obtaining a contamination-free Cu-to-Cu interface for bonding.

[0006] Therefore, improvements in technology for integrating bridge chips into chip layout designs are desirable. [Overview of the Initiative]

[0007] The present invention provides a technique for interconnecting chips using bridge chips having through-vias that eliminate external connections between chips. In one aspect of the invention, a structure is provided, which includes a bridge chip attached to at least a first chip and a second chip, the bridge chip having at least one conductive through-via connecting the bridge chip to one of the first chip and the second chip. For example, the sidewall along the upper portion of at least one conductive through-via may be joined by a step to the sidewall along the bottom portion of at least one conductive through-via, so that the upper portion of at least one conductive through-via has a width W1 CONDUCTIVE VIA The bottom portion of at least one conductive through-via has a width W2 CONDUCTIVE VIA It has W1 CONDUCTIVE VIA >W2 CONDUCTIVE VIA That is the case.

[0008] In another aspect of the invention, another structure is provided, which includes a bridge chip attached to at least a first chip and a second chip, the bridge chip having at least one conductive through-via connecting the bridge chip to one of the first chip and the second chip, and a wiring layer having metal lines present between a first capping layer and a second capping layer, wherein at least one conductive through-via is in direct contact with at least one sidewall of the plurality of metal lines. For example, at least one conductive through-via can be in direct contact with the top surface and sidewall of at least one of the plurality of metal lines. Alternatively, at least one conductive through-via can be in direct contact with only the sidewall of at least one of the plurality of metal lines.

[0009] In yet another aspect of the invention, a method for integrating chips is provided. The method comprises forming a bridge chip having at least one via present in a substrate, a first capping layer disposed on the substrate, a wiring layer having metal lines disposed on the first capping layer, and a second capping layer disposed on the wiring layer, wherein at least one via is filled with sacrificial material; installing the bridge chip over at least the first and second chips; removing sacrificial material from at least one via; extending at least one via through the first capping layer, the wiring layer, and the second capping layer to the first and second chips; and filling at least one via with at least one metal to form at least one conductive through via, wherein at least one conductive through via is in direct contact with at least one sidewall of at least one of a plurality of metal lines, and at least one conductive through via connects the bridge chip to one of the first and second chips.

[0010] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by referring to the detailed description and drawings below. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view illustrating vias patterned on a substrate according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view illustrating a via filled with sacrificial material according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating an embodiment of the present invention, comprising a (first) capping layer formed on a substrate covering vias / sacrificial material, a wiring layer having metal lines formed on the first capping layer, and a (second) capping layer formed on the wiring layer covering the metal lines. [Figure 4] This is a cross-sectional view illustrating a handle wafer attached to the side of a second capping layer opposite to the wiring layer, and vias opened on the other side of the substrate to form a bridge chip, according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating an inverted bridge chip and a block mask formed on a substrate with via openings marked, according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating an embodiment of the present invention, showing a (first / second) tip having a metal pad located on a fixture, and a bridge tip installed covering and spanning the first / second tip. [Figure 7] This is an enlarged view illustrating how a metal pad is installed directly beneath a via according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating a sealing material deposited and embedded on a fixture, covering the bridge chip and the first / second chip, according to an embodiment of the present invention. [Figure 9]A cross-sectional view illustrating deposited sealant that has been planarized and removed from a block mask covering vias, in accordance with an embodiment of the present invention. [Figure 10] A cross-sectional view illustrating sacrificial material being selectively removed, thereby reopening vias, in accordance with an embodiment of the present invention. [Figure 11] A cross-sectional view illustrating an etch being performed to extend a via through first / second capping layers and wiring layers all the way to a metal pad, in accordance with an embodiment of the present invention. [Figure 12] A cross-sectional view illustrating a via filled with a metal or combination of metals to form a conductive through-via that is in direct contact with metal pads of first / second chips, as well as the top surface and sidewalls (i.e., shoulders) of metal lines, in accordance with an embodiment of the present invention. [Figure 13A] A top-down view illustrating an exemplary arrangement of conductive through-vias with respect to metal lines in which the conductive through-vias are aligned adjacent to each other, in accordance with an embodiment of the present invention. [Figure 13B] A top-down view illustrating an arrangement of conductive through-vias with respect to metal lines in which the conductive through-vias are offset from each other, according to an alternative embodiment, in accordance with an embodiment of the present invention. [Figure 14] A cross-sectional view illustrating through-mold vias patterned in a sealant covering first / second chips, in accordance with an embodiment of the present invention. [Figure 15] A cross-sectional view illustrating a through-mold via filled with metal to form a conductive mold via in direct contact with first / second chips on both sides of a bridge chip, a flipped assembly, a solder bond portion formed between the conductive through-via / conductive mold via and a laminate package, and the removal of a fixture, in accordance with an embodiment of the present invention. [Figure 16] A top-down view illustrating a final assembly, in accordance with an embodiment of the present invention. [Figure 17] A cross-sectional view continuing from FIG. 12 illustrating, according to another alternative embodiment, a (third) chip attached to a bridge chip covering a block mask and in direct contact with an end of a conductive through-via opposite a metal pad. [Figure 18] A cross-sectional view illustrating a through-mold via patterned in a sealant covering the first / second chips according to an embodiment of the present invention. [Figure 19] A cross-sectional view illustrating a through-mold via filled with metal to form a conductive mold via for directly contacting both sides of the first / second chips with a bridge chip / a third chip according to an embodiment of the present invention, a flipped assembly, a solder bond portion formed between the conductive mold via and a laminate package, and that a fixture has been removed. [Figure 20] A top-down view illustrating a final assembly according to an embodiment of the present invention. [Figure 21] A cross-sectional view illustrating, according to yet another alternative embodiment, a conductive through-via that directly contacts only the metal pads of the first / second chips according to an embodiment of the present invention and the sidewalls of metal lines (i.e., a skim-by connection). [Figure 22] A cross-sectional view illustrating, according to still another alternative embodiment, a modified fixture that has been adopted and includes a recess for accommodating chips of various heights according to an embodiment of the present invention. [Figure 23] A cross-sectional view illustrating a conductive through-via formed in contact with chips of various heights according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0012] As mentioned above, conventional chip integration technologies generally employ solder or copper (Cu)-to-Cu interface connections between chips. However, each of these methods has significant drawbacks. For example, solder connections inherently suffer from poor parasitism, strict pitch limitations, and can fail due to thermal stress. Proper Cu-to-Cu bonding requires an oxide-free Cu-to-Cu interface, adding the constraint that bonding must be performed in a reduced-pressure atmosphere.

[0013] This specification provides a technique for interconnecting multiple chips using a bridge chip having formed through-vias. Advantageously, placing through-vias within the bridge chip eliminates the need for solder or external connections such as Cu-to-Cu interface connections between chips. In terms of scalability, tighter pitches can be achieved using this technique compared to solder connections or even Cu-to-Cu interface connections. Furthermore, the through-via transmission supported by this bridge chip design provides high-quality back-end-of-line (BEOL) connectivity between chips at very high bandwidths.

[0014] An exemplary method for forming the bridge chip having through vias is described herein by reference to Figures 1 to 5. As shown in Figure 1, the process for forming the bridge chip begins with patterning at least two vias 104 onto a substrate 102. According to the exemplary embodiment, the substrate 102 is a bulk semiconductor wafer such as bulk silicon (Si), bulk germanium (Ge), bulk silicon-germanium (SiGe), or bulk III-V semiconductor wafer or a combination thereof. Alternatively, the substrate 102 may be a semiconductor-on-insulator (SOI) wafer. An SOI wafer includes an SOI layer separated from the underlying substrate by a buried insulator. When the buried insulator is an oxide, it is also referred to herein as a buried oxide or BOX. The SOI layer may include any of the following preferred semiconductor materials, such as Si, Ge, SiGe, or III-V semiconductors or a combination thereof. Furthermore, the substrate 102 may already have pre-fabricated structures (not shown) such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc.

[0015] Standard lithography and etching techniques may be employed to pattern vias 104 on the substrate 102. Using standard lithography and etching techniques, a lithography laminate (not shown), e.g., a photoresist / anti-reflective coating (ARC) / organic planarization layer (OPL), is used to pattern a hard mask (not shown) having the footprint and location of the feature to be patterned (in this case, vias 104). Alternatively, the hard mask may be formed by other preferred techniques, including, but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and other self-aligned multiple patterning (SAMP). Etching is then used to transfer the pattern from the hard mask to the underlying substrate 102 to form the vias 104. Directional (anisotropic) etching processes, such as reactive ion etching (RIE), may be employed for via etching. Suitable hard mask materials include, but are not limited to, nitride hard mask materials such as silicon nitride (SiN), silicon oxynitride (SiON), and / or silicon carbonitride (SiCN), or oxide hard mask materials such as SiOx, or combinations thereof.

[0016] As shown in Figure 1, the patterned via 104 extends only partway through the substrate 102. Later in the process, the via 104 will be opened on the other side of the substrate 102 to form a through via (i.e., a via that extends through the substrate 102 from one side to the other). According to exemplary embodiments, each of the vias 104 has a diameter ranging from about 1 micrometer (μm) to about 10 μm and in between, and an aspect ratio (height to diameter) ranging from about 5 to about 10 and in between. It should be noted that the depiction of the two vias 104 in the figure is merely an example used to illustrate the art. Embodiments herein assume that more (or fewer) vias 104 are formed on the substrate 102 than those shown. Following the patterning of vias 104, an oxide liner (not shown) with a nominal thickness in the range of about 0.1 micrometers (μm) to about 1 μm and in between may be deposited and lined into vias 104 using a reduced-pressure chemical vapor deposition (SACVD), plasma chemical vapor deposition (PECVD) / chemical vapor deposition (CVD), or atomic layer deposition (ALD) process to electrically insulate vias 104 from substrate 102. The oxide liner may be annealed (for example, at temperatures in the range of about 800 degrees Celsius (°C) to about 1100°C and in between) to improve its quality and resistance to wet and dry etching.

[0017] Via 104 is then filled with sacrificial material 202. See Figure 2. As used herein, the term “sacrificial” refers to a structure that is removed in whole or in part during the manufacturing process. Preferred sacrificial materials include, but are not limited to, dielectric materials such as silicon oxide (SiOx) or silicon nitride (SiN) or both, and these dielectric materials may be deposited using processes such as CVD, ALD, physical vapor deposition (PVD) or casting processes such as spin coating or spray casting. Following deposition, an optional quality-stabilizing annealing may be performed. Sacrificial material 202 is then polished to the surface of substrate 102 using a process such as chemical mechanical polishing (CMP). A dotted line is used here to outline via 104 (which is filled here with sacrificial material 202).

[0018] The capping layer 302 is then formed on the substrate 102, covering the vias 104 / sacrificial material 202. See Figure 3. Suitable materials for the capping layer 302 include, but are not limited to, nitride materials such as SiN, silicon oxynitride (SiON), or silicon oxycarbonite (SiOCN) or a combination thereof, and these nitride materials may be deposited using processes such as CVD, ALD, or PVD. According to exemplary embodiments, the capping layer 302 has a thickness ranging from about 2 nanometers (nm) to about 500 nm and in between.

[0019] A back-end-of-line (BEOL) wiring layer 304 is then formed on the capping layer 302. According to an exemplary embodiment, the wiring layer 304 is formed by first depositing an interlayer dielectric (ILD) 306 onto the capping layer 302. Suitable ILD 306 materials include, but are not limited to, oxide materials such as SiOx and / or organosilicate glass (SiCOH), or ultra-low-κ interlayer dielectric (ULK-ILD) materials having a dielectric constant κ of less than 2.7, or a combination thereof. Suitable ultra-low-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH). Processes such as CVD, ALD, or PVD may be used to deposit the ILD 306. Following deposition, the ILD 306 may be polished using a process such as CMP.

[0020] Standard lithography and etching techniques (see above) are then employed to pattern features such as vias or trenches or both onto the ILD306, and these features are then filled with metal (or a combination of multiple metals) to form metal lines 308 within the ILD306. Suitable metals include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or platinum (Pt) or combinations thereof, and these metals may be deposited onto the features using processes such as vapor deposition, sputtering, or electrochemical plating. Following deposition, metal overburden may be removed using processes such as CMP. Prior to depositing metal onto the features, a conformal barrier layer (not shown) may be deposited and lined onto the features. The use of such a barrier layer helps to prevent the diffusion of metal into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN), or combinations thereof. In addition, a seed layer (not shown) may be deposited and lined onto the feature prior to metal deposition. The seed layer facilitates the plating of the metal onto the feature.

[0021] Next, a capping layer 310 is formed on the wiring layer 304, covering the metal line 308. For clarity, the terms “first” and “second” may also be used herein when referring to capping layer 302 and capping layer 310, respectively. Preferred materials for capping layer 310 include, but are not limited to, nitride materials such as SiN, SiON, or SiOCN or a combination thereof, and these nitride materials may be deposited using processes such as CVD, ALD, or PVD. According to exemplary embodiments, capping layer 310 has a thickness ranging from about 2 nm to about 500 nm and in the range in between.

[0022] As given above, the patterned via 104 extends only to a portion of the substrate 102. However, when the handle wafer 402 is then attached to the capping layer 310 opposite the wiring layer 304, the via 104 opens to the other side of the substrate 102 to form a through via. See Figure 4. Simply as an example, the handle wafer 402 may be attached to the capping layer 310 using an adhesive, dielectric bonding, or any other standard wafer bonding technique known in the art, or a combination thereof. According to an exemplary embodiment, a temporary adhesive is used to attach the handle wafer 402 to the capping layer 310. Thus, the handle wafer can be easily removed after the completion of the bridge chip structure (see below). Simply as an example, suitable temporary adhesives are commercially available from Brewer Science, Inc. in Laura, Missouri and from 3M in St. Paul, Minnesota. Optionally, the adhesive used is a photo-peelable adhesive, such as ultraviolet (UV) tape. Suitable photo-peelable adhesives are commercially available, for example, from Furukawa Electric Co., Ltd. in Tokyo, Japan.

[0023] With the handle wafer 402 in place to securely fix the structure, backside thinning of the substrate 102 is performed to expose vias 104 / sacrificial material 202 on the back side of the substrate 102 (i.e., the side of the substrate 102 opposite to the handle wafer 402). Processes such as CMP or grinding may be used to thin the substrate 102.

[0024] The bridge chip 501 (i.e., the substrate 102 having (through) vias 104 / capping layer 302 / wiring layer 304 / capping layer 310) is formed here. While the bridge chip 501 is still mounted on the handle wafer 402, the bridge chip is then flipped over, and the block mask 502 is formed on the substrate 102 to mark the openings for the (through) vias 104. See Figure 5. "Flipping over" means that the bottom components of the bridge chip structure are now at the top, and vice versa.

[0025] As described in detail below, a bridge chip will be used to interconnect at least two chips. During the process, the sacrificial material 202 will be removed and replaced with metal to form conductive through vias within the bridge chip. The block mask 502 will facilitate the selective removal of the sacrificial material 202 and the deposition of metal into the (through) vias 104. Suitable materials for the block mask 502 include, but are not limited to, nitride materials such as SiN, SiON, or SiCN or a combination thereof, and these nitride materials may be deposited using processes such as CVD, ALD, or PVD. According to an exemplary embodiment, the block mask 502 has a thickness ranging from about 2 nm to about 500 nm and in between. Standard lithography and etching techniques (see above) may be employed to pattern the block mask 502. Following the deposition and patterning of the block mask 502, the bridge chip may be peeled off from the handle wafer 402.

[0026] Although this example focuses on the formation of a given bridge chip, it will be apparent to those skilled in the art that the process described above may be carried out in the same manner as described in the manufacture of multiple bridge chips on a common substrate. Following the deposition and patterning of the block mask 502, a standard wafer dicing procedure may then be employed to divide the substrate into individual bridge chips for use and, if necessary, for placement.

[0027] The bridge chip is then used to interconnect at least two other chips. An exemplary method for chip integration using this bridge chip design is described herein with reference to Figures 6–16. As shown in Figure 6, chips 604 and 606 are located on fixture 602, and the bridge chip 501 is installed covering and straddling chips 604 and 606. Specifically, the bridge chip 501 is bonded to the side of chips 604 and 606 opposite to fixture 602. More specifically, the capping layer 310 of the bridge chip 501 is bonded to at least a portion of the upper surface of each of chips 604 and 606. Simply as an example, the bridge chip 501 may be bonded to chips 604 and 606 using adhesive, dielectric bonding, or bonding layers. These wafer bonding techniques are known to those skilled in the art and are therefore not further described herein.

[0028] Fixture 602 generally represents any type of substrate on which chips 604 and 606 can be placed. For example, according to an exemplary embodiment, fixture 602 is a glass plate or silicon wafer to which chips 604 and 606 are attached using a temporary adhesive (see above) that allows for the removal of fixture 602 once chips 604 and 606 have been attached to a bridge chip. Advantageously, the glass plate or silicon wafer is transparent to light. In that case, a photo-peelable adhesive may be employed to attach chips 604 and 606 to fixture 602 for easy removal using laser radiation, ultraviolet (UV) radiation, optical radiation, or infrared (IR) radiation, or a combination thereof, irradiated through the (transparent) fixture 602. According to an exemplary embodiment, chips 604 and 606 are logic chips or memory chips or both. Although chips 604 and 606 are shown in this example to have similar dimensions, embodiments are assumed herein to be configured to accommodate chips of varying heights.

[0029] As shown in Figure 6, the tips 604 and 606 each have metal pads 608 and 610 on their upper surfaces, respectively. Standard metallization techniques may be employed to form the metal pads 608 and 610 on the tips 604 and 606. In particular, at least a portion of these metal pads 608 and 610 is placed directly beneath one of the multiple vias 104. Furthermore, a portion or "shoulder" of the metal line 308 is placed in the path between the metal pads 608 / 610 and the respective vias 104. To help illustrate this concept, an enlarged view of region 612 is provided in Figure 7. As shown in Figure 7, the metal pad 610 is placed directly beneath one of the multiple vias 104. Thus, when the sacrificial material 202 is later removed and the etch is used to penetrate the capping layer 302 / ILD 306 / capping layer 310 and extend the vias 104, the etch will reach sufficiently onto the metal pad 610. Although not visible in the enlarged view, the same arrangement applies to the metal pad 608. Furthermore, arrow 702 is used in Figure 7 to indicate the path between the metal pad 610 and each via 104. Using this configuration, a portion of one of the multiple metal lines 308 lies within the path between the metal pad 610 and the via 104. In this particular case, a portion of the top / bottom surface and sidewalls (collectively referred to herein as the "shoulders") of the metal line 308 lies within the path between the metal pad 610 and the via 104. Again, the same arrangement applies to the metal pad 608. Thus, conductive through vias later formed during the process between the via 104 and the metal pad 610 will also contact the "shoulders" of the metal line 308. It should be noted that other configurations are also assumed herein. For example, in the alternative embodiment described in detail below, a "skim-by" configuration is employed in which contact occurs only with the side walls of the metal line 308 (rather than with the entire "shoulder").

[0030] The sealant 802 is then deposited onto fixture 602, covering the bridge chips 501 / chips 604 and 606, and embedding the chips. See Figure 8. Suitable sealant materials include, but are not limited to, cyanate esters. The deposited sealant 802 is then planarized using a process such as CMP. See Figure 9. The block mask 502 acts as an etch stop for this planarization process. As shown in Figure 9, the sealant 802 is removed from the block mask 502 above the via 104. The amount of sealant 802 remaining after planarization is minimal and can be easily removed using a suitable wet or dry etching process with little or no impact on the bulk sealant 802 on either side of the bridge chip 501, if any.

[0031] As described above, the block mask 502 leaves sacrificial material 202 inside the exposed via 104. The sacrificial material 202 is then selectively removed to reopen the via 104. See Figure 10. According to an exemplary embodiment, the sacrificial material 202 is selectively removed using an omnidirectional (i.e., isotropic) etching process such as wet chemical etching or gas-phase etching.

[0032] Etching is then performed to extend via 104 through capping layers 302, ILD 306 and 310, up to metal pads 608 and 610. See Figure 11. In this particular example, the “shoulder” of the metal line 308 is located in the path between via 104 and metal pads 608 and 610. Extending via 104 around this “shoulder” of the metal line 308 results in via 104 having stepped sidewalls covering the “shoulder” and having different top and bottom widths. That is, as shown in Figure 11, one sidewall of via 104 (i.e., the sidewall opposite the “shoulder”) is continuous and linear, while the opposing sidewall along the top portion of via 104 (i.e., above the metal line 308) is joined to the sidewall along the bottom portion of via 104 (i.e., below the metal line 308) by a step. Based on this configuration, the top portion of via 104 has a width W1VIA has, and the bottom portion of via 104 has a width W2 VIA has, where W1 VIA is greater than W2 VIA i.e., W1 VIA >W2 VIA is. Following the via extension etch, an additional deposited oxide liner (not shown) is applied within via 104 to insulate it from the surrounding BEOL structures that were exposed during the via extension etch. Processes such as SACVD, PECVD / CVD, or ALD may be used to deposit this additional oxide liner to a thickness in the range of about 0.1 μm to about 1 μm and in between.

[0033] Via 104 is then filled with one or more metals to form a conductive through via 1202. See Figure 12. However, before filling via 104 with metal, collimated dry etch is performed to remove all oxides from the top of the BEOL layer metal structure of bridge tip 501 and from the top of tips 604 and 606 to be connected by bridge tip 501. Reactive ion etch using argon (Ar) ions, for example, may be used. This etch leaves the top surface of the metal structure free of oxides and ready to be connected during the subsequent metallization process. Suitable metals for conductive through via 1202 include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or platinum (Pt) or combinations thereof, and these metals may be deposited onto via 104 using processes such as vapor deposition, sputtering, or electrochemical plating. Following deposition, the metal overburden may be removed using processes such as CMP. After collimated dry etching has been performed, but before depositing metal into via 104, a conformal barrier layer (not shown) may be deposited and lined onto via 104. The use of such a barrier layer helps to prevent the diffusion of metal into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN), or a combination thereof. In addition, a seed layer (not shown) may be deposited and lined onto via 104 prior to metal deposition. The seed layer facilitates the plating of metal into via 104.

[0034] As shown in Figure 12, the conductive through-via 1202 makes direct contact with the metal pads 608 / 610 in the tip 604 / 606, as well as the top surface and sidewalls (also referred to herein as “shoulders”) of the metal line 308. As a result of this configuration, the conductive through-via 1202 has stepped sidewalls covering the “shoulders” and different top and bottom widths. That is, one sidewall of the conductive through-via 1202 (i.e., the sidewall opposite the “shoulders”) is continuous and straight, while the opposing sidewall along the top portion of the conductive through-via 1202 (i.e., above the metal line 308) is joined to the sidewall along the bottom portion of the conductive through-via 1202 (i.e., below the metal line 308) by a step. Based on this configuration, the top portion of the conductive through-via 1202 has a width W1 CONDUCTIVE VIA The bottom portion of the conductive through via 1202 has a width W2 CONDUCTIVE VIA It has, and here, W1 CONDUCTIVE VIA W2 CONDUCTIVE VIA Larger than, that is, W1 CONDUCTIVE VIA >W2 CONDUCTIVE VIA That is the case.

[0035] Furthermore, as shown in Figure 12, each conductive through-via 1202 connects the bridge chip 501 to one of the chips 604 and 606. For example, the conductive through-via 1202 shown on the left in Figure 12 contacts both the metal line 308 and the metal pad 608, thereby connecting the bridge chip 501 to chip 604. Similarly, the conductive through-via 1202 shown on the right in Figure 12 contacts both the metal line 308 and the metal pad 610, thereby connecting the bridge chip 501 to chip 606. Although this example employs a pair of conductive through-vias 1202, it should be noted that this is merely an illustrative and non-limiting example, and it should be understood that more (or fewer) conductive through-vias 1202 may be employed than those shown. For example, embodiments herein assume that the bridge chip 501 employs only a single conductive through-via 1202.

[0036] Figure 13A is a top-down view (e.g., from viewpoint A - see Figure 12) of an exemplary arrangement of conductive through vias 1202 relative to metal line 308. For example, Figure 12 (and the preceding figures) illustrates a cross section of the top-down view cut along line A-A'. For ease of depiction and clarity, the layers present covering metal line 308 are omitted from the top-down view. It should be noted that the exact routing of the shown metal line 308 is arbitrary. The important thing is that the conductive through vias 1202 serve to interconnect the metal pads 608 and 610 of chips 604 and 606 to the metal line 308, respectively. It should be further noted that the arrangement of the conductive through vias 1202 may also be varied. For example, rather than being aligned adjacent to each other (as in Figure 13A), the conductive through vias 1202 may instead be offset from each other, and the arrangement of metal line 308 will be adjusted accordingly. For example, see the alternative embodiment illustrated in Figure 13B (which is also a top-down diagram).

[0037] Optionally, standard lithography and etching techniques (see above) are then used to pattern through-molded vias 1402 into the encapsulant 802 covering chips 604 and 606. See Figure 14. As shown in Figure 14, the through-molded vias 1402 are positioned to the right and left of the bridge chip 501 and extend through the encapsulant 802 to chips 604 and 606. As will be described in detail below, the through-molded vias 1402 will be used to form a connection between chips 604 / 606 and the laminate package.

[0038] The through-molded via 1402 is then filled with metal to form conductive molded vias 1502 that directly contact the tips 604 / 606 on both sides of the bridge tip 501. See Figure 15. Suitable metals include, but are not limited to, Cu, W, Ru, Co, Ni, or Pt or combinations thereof, and these metals may be deposited into the through-molded via 1402 using processes such as vapor deposition, sputtering, or electrochemical plating. Following deposition, the metal overburden may be removed using processes such as CMP. Prior to depositing the metal into the through-molded via 1402, a conformal barrier layer (not shown) may be deposited and lined into the through-molded via 1402. As provided above, the use of such a barrier layer helps to prevent the diffusion of the metal into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, Ru, Ta, TaN, Ti, or TiN or combinations thereof. In addition, a seed layer (not shown) may be deposited and lined into the through-molded via 1402 prior to metal deposition. The seed layer facilitates metal plating onto the through-molded via 1402.

[0039] As shown in Figure 15, the conductive molded via 1502 may then be used to mount the bridge chip 501 / chip 604 / 606 assembly onto the laminated package 1506. That is, the bridge chip 501 / chip 604 / 606 assembly may be inverted so that the chip 604 / 606 is at the top and the bridge chip 501 is at the bottom. The solder bond portion 1504 is then formed between the conductive through via 1202 / conductive molded via 1502 and the laminated package 1506. According to an exemplary embodiment, the solder bond portion includes tin (Sn), silver (Ag), Cu, or alloys thereof such as tin-silver (SnAg) solder and / or tin-silver-copper (SnAgCu) solder or a combination thereof.

[0040] Fixture 602 may then be removed. For example, as described above, the fixture may be attached to the tips 604 and 606 using a temporary adhesive such as a photopeelable adhesive. In that case, a light-transparent fixture 602 may be employed, and the light would allow for the removal of the fixture 602 from the tips 604 and 606 using laser radiation, ultraviolet (UV) radiation, optical radiation, or infrared (IR) radiation, or a combination thereof, shone through the (transparent) fixture 602. Figure 16 is a top-down view of the final assembly (e.g., from viewpoint B - see Figure 15). For ease of depiction and clarity, the sealant 802 has been omitted from the top-down view.

[0041] Embodiments also assume, as herein, that at least one additional chip 1702 (e.g., logic or memory or both) is integrated into the assembly. See Figure 17. For clarity, the terms “first,” “second,” and “third” may also be used herein when referring to chips 604, 606, and 1702, respectively. In this exemplary embodiment, the integration process flow proceeds in the same manner as above with a bridge chip 501 manufactured as described in conjunction with the description in Figures 1 to 5 above, the bridge chip is then installed over / across the conductive through vias 1202 formed in direct contact with at least the sidewalls of chips 604 and 606 and metal line 308 (mounted on fixture 602), as described in conjunction with the description in Figures 6 to 12 above. Thus, what is depicted in Figure 17 follows from the assembly shown in Figure 12. Similar structures are similarly numbered in the figures. Here, however, the chip 1702 is then attached to the bridge chip 501 by covering the block mask 502, and directly contacts the end of the conductive through via 1202 opposite to the metal pads 608 / 610. See Figure 17. Simply as an example, the chip 1702 may be attached to the bridge chip 501 using adhesive, dielectric bonding, or any other standard wafer bonding technique known in this art, or a combination thereof.

[0042] In the same manner as described above, standard lithography and etching techniques are then used to pattern through-molded vias 1802 onto the sealant 802 covering chips 604 and 606. See Figure 18. As shown in Figure 18, chip 1702 directly covers bridge chip 501, and through-molded vias 1802 are placed to the right and left of bridge chip 501 / chip 1702. The through-molded vias 1802 extend through the sealant 802 to chips 604 and 606. As will be described in detail below, through-molded vias 1402 will be used to form the connection between chips 604 / 606 and the laminate package.

[0043] The through-molded via 1802 is then filled with metal to form conductive molded vias 1902 on both sides of the bridge tip 501 / tip 1702 that are in direct contact with tips 604 / 606. See Figure 19. Suitable metals include, but are not limited to, Cu, W, Ru, Co, Ni, or Pt or combinations thereof, and these metals may be deposited into the through-molded via 1802 using processes such as vapor deposition, sputtering, or electrochemical plating. Following deposition, the metal overburden may be removed using processes such as CMP. Prior to depositing the metal into the through-molded via 1802, a conformal barrier layer (not shown) may be deposited and lined into the through-molded via 1902. As provided above, the use of such a barrier layer helps to prevent the diffusion of the metal into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, Ru, Ta, TaN, Ti, or TiN or combinations thereof. In addition, a seed layer (not shown) may be deposited and lined into the through-molded via 1802 prior to metal deposition. The seed layer facilitates metal plating into the through-molded via 1802.

[0044] As shown in Figure 19, the conductive molded via 1902 may then be used to mount the bridge chip 501 / chip 604 / 606 / 1702 assembly onto the laminated package 1906. That is, the bridge chip 501 / chip 604 / 606 / 1702 assembly may be inverted so that chip 604 / 606 is at the top and bridge chip 501 / 1702 is at the bottom. The solder bond portion 1904 is then formed between the conductive molded via 1902 and the laminated package 1906. According to an exemplary embodiment, the solder bond portion includes Sn, Ag, Cu, or alloys thereof such as SnAg solder and / or SnAgCu solder or a combination thereof.

[0045] Fixture 602 can then be removed. For example, as described above, fixture 602 may be attached to chips 604 and 606 using a temporary adhesive such as a photopeelable adhesive. In that case, fixture 602 may be made transparent to light, and the light would allow for the removal of fixture 602 from chips 604 and 606 using laser radiation, UV radiation, optical radiation, or IR radiation, or a combination thereof, irradiated through the (transparent) fixture 602. Figure 20 is a top-down view of the final assembly (e.g., from viewpoint C - see Figure 19). For ease of depiction and clarity, the sealant 802 is omitted from the top-down view. The dashed line is used to indicate the location of chip 1702.

[0046] In the example above, the conductive through-via 1202 contacts the “shoulder” (i.e., the top surface and sidewall) of the metal line 308. However, a proper connection can be made as long as the conductive through-via 1202 contacts at least the sidewall of the metal line 308. For example, according to an alternative embodiment, the metal line is positioned such that the conductive through-via contacts only the sidewall of the metal line. See Figure 21. This configuration is also referred to herein as a “skim-by” connection because the conductive through-via passes just above the sidewall surface of the metal line. For clarity, the metal line and conductive through-via in this alternative embodiment are given reference numerals 308' and 1202'. As noted above, similar structures are given similar numbering in the figures. In this case, the selective oxide liner deposition process described above is used to deposit additional oxide material (not shown) into the BEOL layer of the bridge chip 501 to enable electrical connections between the metal line 308' and the conductive through via 1202' within the bridge chip 501.

[0047] As shown in Figure 21, the conductive through-via 1202' makes direct contact with the metal pads 608 / 610 within the chip 604 / 606. However, the metal line 308' is positioned so that the conductive through-via 1202' makes contact only with the sidewall of the metal line 308'. Advantageously, by using a "skim-by" connection, the width of the conductive through-via 1202' is not reduced below the metal line 308'. That is, as shown in Figure 21, the conductive through-via 1202' has a uniform width W'. CONDUCTIVE VIA and has straight, vertical side walls. In comparison, in the previous example (see, for example, Figure 12), the presence of the “shoulder” of the metal line 308 in the path between via 104 and metal pad 608 / 610 means that the width of the conductive through via 1202 below the metal line 308 (i.e., W2 CONDUCTIVE VIAThis causes a decrease in the contact area between the conductive through-via 1202' and the metal line 308', and creates a step along the side wall. In a "skim-by" connection, the contact area of ​​the conductive through-via 1202' with the metal line 308' is reduced, while the uniform width of the conductive through-via 1202' reduces the overall resistance of the interconnect.

[0048] In the previous example, tips 604 and 606 are shown to have similar dimensions. However, embodiments herein assume that the assembly is configured to accommodate tips of different dimensions, such as varying heights. See Figure 22. As noted above, similar structures are similarly numbered in the figures. As shown in Figure 22, tip 604' has a first height H1 and tip 606' has a second height H2, where H2 is greater than H1, i.e., H2 > H1. To address this height difference between tips 604' and 606', a modified fixture 602' is employed, which includes a recess 2202 (shown by a dotted line) on which the taller tip 606' is located, thereby bringing the surfaces of tips 604' and 606' to which the bridge tip 501 is mounted to a uniform height. The remainder of the process is then the same as described above. For completeness, a depiction of the assembly having tips 604' and 606' of varying heights following the formation of the conductive through-via 1202 is shown in Figure 23.

[0049] Although exemplary embodiments of the present invention have been described herein, it should be understood that the invention is not limited to these detailed embodiments and that various other changes and modifications may be made by those skilled in the art without deviating from the scope of the invention.

Claims

1. A method for integrating chips, The method involves forming a bridge chip comprising at least one via present in the substrate, a first capping layer disposed on the substrate, a wiring layer having a plurality of metal lines disposed on the first capping layer, and a second capping layer disposed on the wiring layer, wherein the at least one via is filled with sacrificial material. The bridge chip is installed so as to cover at least the first chip and the second chip, Removing the sacrificial material from at least one of the vias, Extending the at least one via through the first capping layer, the wiring layer, and the second capping layer to the first chip and the second chip, The method involves filling the at least one via with at least one metal to form at least one conductive through via, wherein the at least one conductive through via is in direct contact with at least one sidewall of at least one of the plurality of metal lines, and the at least one conductive through via connects the bridge chip to one of the first chip and the second chip, and the method involves filling the at least one via. Methods that include...

2. Mounting at least one third chip on the side of the bridge chip opposite to the first chip and the second chip, wherein at least one conductive through via is in contact with the at least one third chip. The method according to claim 1, further comprising:

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