semiconductor element

Abstract

To obtain a semiconductor element that operates over a wide frequency band and with high luminous efficiency.SOLUTION: A semiconductor element 500 according to the present disclosure includes a semiconductor substrate 101, a mesa structure 150 having a striped laminated semiconductor layer formed on the semiconductor substrate 101 and including a first semiconductor layer 102 of a first conductivity type, an active layer 103, and a semiconductor layer 104 of a second conductivity type, buried layers 105 and 106 buried on both side surfaces of the mesa structure 150, a second semiconductor layer 109 of the first conductivity type formed on the buried layers 105 and 106, and an insulating film 110 formed in contact with the second semiconductor layer 109 of the first conductivity type.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure concerns semiconductor elements to child To relate to. [Background technology]

[0002] In InP-based semiconductor lasers used in optical communication applications, a wide modulation frequency band is required for individual elements to accommodate high-capacity communication. Furthermore, improved luminous efficiency of individual elements is required to reduce the overall power consumption of the optical communication system. Both frequency bandwidth and luminous efficiency are greatly influenced by the element resistance of the semiconductor element. However, between electrons and holes, holes have lower mobility, and within the element resistance of the semiconductor layer, the resistance of the p-type semiconductor layer accounts for a large proportion of the total resistance of the semiconductor layer.

[0003] Considering the circumstances described above, in InP-based semiconductor lasers for optical communication, n-type semiconductor substrates are generally used to apply a low-resistance n-type semiconductor layer to the long current path. In other words, the n-type semiconductor substrate is located on the back side of the device, and the p-type semiconductor layer is located on the front side of the device. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] J Chevallier, A Jalil, B Theys, JC Pesant, M Aucouturier, B Rose and A Mircea, “Hydrogen passivation of shallow acceptors in p-type InP”, Semicond. Sci. Technol. 4 (1989) pp.87-90 [Non-Patent Document 2] Hiroshi Ito, Shoji Yamahata, Naoteru Shigekawa and Kenji Kurishima, “Heavily Carbon Doped Base InP / InGaAs Heterojunction Bipolar Transistors Grown by Two-Step Metalorganic Chemical Vapor Deposition”, Jpn. J. Appl. Phys., vol.35 (1996) pp.6139-6144

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, in an InP-based semiconductor laser for optical communication, a configuration in which a p-type semiconductor layer is formed on the surface side of the element is common. An insulating film is formed on the surface side of the element for surface protection of the semiconductor layer. Characteristics required for the insulating film include good step coverage on the semiconductor surface and a dense film quality. As a film formation technique for an insulating film that can meet these requirements, it is common to use the plasma CVD (Plasma Chemical Vapor Deposition) method.

[0006] However, when the plasma CVD method is used as a method for forming an insulating film for the purpose of surface protection of a semiconductor layer, a phenomenon occurs in which hydrogen enters the inside of the insulating film from hydrogen radicals generated during the film formation of the insulating film. The hydrogen incorporated into the insulating film may diffuse into the p-type semiconductor layer during processes such as annealing in the manufacturing process after film formation. Furthermore, depending on conditions such as the storage, operation, and use environment of the semiconductor device after the device is completed, hydrogen may also diffuse into the p-type semiconductor layer.

[0007] In Non-Patent Document 1, it is pointed out that hydrogen in the p-type semiconductor layer causes a decrease in carrier concentration. Since the decrease in the carrier concentration of the p-type semiconductor layer directly leads to an increase in the device resistance of the semiconductor device, there was a risk that the device characteristics would vary due to variations in conditions such as the process, storage, operation, and usage environment. Also, it is known that hydrogen in the semiconductor layer moves relatively easily, and in the worst case, there is concern that it may affect the long-term reliability of the semiconductor device. On the other hand, Non-Patent Document 2 describes that by providing an n-type semiconductor layer on the surface of the semiconductor layer, the diffusion of hydrogen from the insulating film into the p-type semiconductor layer can be suppressed.

[0008] The present disclosure has been made to solve the above problems, and by suppressing the diffusion of hydrogen from the insulating film into the p-type semiconductor layer and preventing an increase in the device resistance of the semiconductor device, it aims to provide a semiconductor device that can operate with a wide frequency band and high luminous efficiency.

Means for Solving the Problem

[0009] The semiconductor device according to the present disclosure is a semiconductor substrate, a mesa structure in which a stacked semiconductor layer composed of a first semiconductor layer of a first conductivity type, an active layer, and a semiconductor layer of a second conductivity type is formed in a stripe shape on the semiconductor substrate, embedded layers embedded on both side surfaces of the mesa structure, on the embedded layer and the upper side of the mesa structure a second semiconductor layer of a first conductivity type formed thereon, and an insulating film formed in contact with the second semiconductor layer of the first conductivity type.

Effect of the Invention

[0011] According to the semiconductor device of the present disclosure, since an n-type semiconductor layer is provided directly under the insulating film provided on the outermost surface of each semiconductor layer, the n-type semiconductor layer prevents the diffusion of hydrogen contained in the insulating film, and thus there is an effect that a semiconductor device that can operate with a wide frequency band and high luminous efficiency can be obtained.

[0012] According to the semiconductor device manufacturing method described herein, an n-type semiconductor layer is crystallized on the outermost surface of each semiconductor layer, and an insulating film in contact with the n-type semiconductor layer is formed by plasma CVD. Since the n-type semiconductor layer prevents the diffusion of hydrogen contained in the insulating film, this method provides the advantage of easily manufacturing a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of an embedded semiconductor laser to which the semiconductor device structure according to Embodiment 1 is applied. [Figure 3] This is a cross-sectional view showing the configuration of a semiconductor element according to a modified example 1 of Embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of an embedded semiconductor laser to which the semiconductor device structure according to Modification 1 of Embodiment 1 is applied. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor element according to a modified example 2 of Embodiment 1. [Figure 6] This is a cross-sectional view showing another configuration of the semiconductor device according to a modified example 2 of Embodiment 1. [Figure 7] This is a cross-sectional view showing the configuration of an embedded semiconductor laser to which the semiconductor device structure according to Embodiment 2 is applied. [Figure 8] This is a cross-sectional view showing an example of the configuration of a semiconductor device to which the semiconductor device structure according to Embodiment 3 is applied. [Figure 9] This is a cross-sectional view showing an example of the configuration of a ridge-type semiconductor laser to which the semiconductor device structure according to Modification 1 of Embodiment 3 is applied. [Figure 10] This is a cross-sectional view showing an example of the configuration of an embedded semiconductor laser to which the semiconductor device structure according to Modification 2 of Embodiment 3 is applied. [Figure 11] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4. [Figure 12]This is a cross-sectional view showing the configuration of an embedded semiconductor laser to which the semiconductor device structure according to Embodiment 4 is applied. [Modes for carrying out the invention]

[0014] Embodiment 1. Figure 1 is a cross-sectional view showing the configuration of a semiconductor device 500 according to Embodiment 1. In Figure 1, as an example of a semiconductor device 500 according to Embodiment 1, an embedded semiconductor laser is shown using an n-type InP (indium phosphide) substrate 101 and having an AlGaInAs active layer 103.

[0015] <Configuration of the semiconductor element according to Embodiment 1> The semiconductor device 500 has a mesa structure 150 in which a multilayer semiconductor layer is formed in a stripe pattern on a (100)-plane S-doped n-type InP substrate 101, consisting of sequentially stacked S-doped n-type InP cladding layers (first semiconductor layer of the first conductivity type) 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, and a Zn-doped p-type InP first cladding layer (second semiconductor layer of the second conductivity type) 104, and Fe-doped semi-insulating InP embedded layers formed on both sides of the stripe-shaped mesa structure 150. The structure consists of a cladding layer 105 and an S-doped n-type InP embedding layer 106, a Zn-doped p-type InP second cladding layer (second conductivity type cladding layer) 107 formed to cover the top surface of the stripe-shaped mesa structure 150 and the surface of the S-doped n-type InP embedding layer 106, a Zn-doped p-type InGaAs contact layer (second conductivity type contact layer) 108, and an S-doped n-type InP barrier layer (first conductivity type second semiconductor layer) 109, as well as an SiO2 insulating film 110 formed on the S-doped n-type InP barrier layer 109.

[0016] A semiconductor layer consisting of a first semiconductor layer of the first conductivity type, an active layer, and a semiconductor layer of the second conductivity type is also called a stacked semiconductor layer.

[0017] Each layer constituting the semiconductor device 500 is described below. The doping concentration of the S-doped n-type InP substrate 101 is 5.0 × 10⁻⁶. 18cm -3 The layer thickness of the S-doped n-type InP cladding layer 102 is 1.0 μm, and the doping concentration is 1.0×10 18 cm -3 . The layer thickness of the undoped AlGaInAs active layer 103 is 0.3 μm, the layer thickness of the Zn-doped p-type InP first cladding layer 104 is 0.3 μm, and the doping concentration is 1.0×10 18 cm -3 . The height of the striped mesa structure 150 is 2.0 μm. As an example of the active layer, an active layer composed of undoped AlGaInAs is given, but any active layer composed of a semiconductor layer containing Ga (gallium) and As (arsenic) may be used, and it may be an n-type or p-type semiconductor layer other than undoped type.

[0018] The layer thickness of the Fe-doped semi-insulating InP buried layer 105 is 1.8 μm, and the doping concentration is 5.0×10 16 cm -3 , the layer thickness of the S-doped n-type InP buried layer 106 is 0.2 μm, and the doping concentration is 5.0×10 18 cm -3 .

[0019] The layer thickness of the Zn-doped p-type InP second cladding layer 107 is 2.0 μm, and the doping concentration is 1.0×10 18 cm -3 , the layer thickness of the Zn-doped p-type InGaAs contact layer 108 is 0.3 μm, and the doping concentration is 1.0×10 19 cm -3 , the layer thickness of the S-doped n-type InP barrier layer 109 is 0.5 μm, and the doping concentration is 1.0×10 18 cm -3 .

[0020] <Manufacturing method of semiconductor device according to Embodiment 1> The manufacturing method of the semiconductor device 500 according to Embodiment 1 will be described below. On a (100)-sided S-doped n-type InP substrate 101, a multilayer semiconductor layer consisting of an S-doped n-type InP cladding layer 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, and a Zn-doped p-type InP first cladding layer 104 is sequentially grown using a crystal growth method such as metal-organic chemical vapor deposition (MOCVD) (first crystal growth step).

[0021] After crystal growth in each of the above layers, the surface of the Zn-doped p-type InP first cladding layer 104 is treated with photolithography and etching techniques. <011> A striped SiO2 mask with a width of 1.5 μm is formed in the direction.

[0022] By using a striped SiO2 mask as an etching mask, dry etching is performed from the Zn-doped p-type InP first cladding layer 104 to the S-doped n-type InP substrate 101 to form a striped mesa structure 150 with a height of 2.0 μm from the bottom surface (mesa structure formation process).

[0023] After forming a striped mesa structure 150, Fe-doped semi-insulating InP embedded layer 105 and S-doped n-type InP embedded layer 106 are sequentially crystal-grown on both sides of the striped mesa structure 150 by MOCVD (second crystal growth step). The Fe-doped semi-insulating InP embedded layer 105 and the S-doped n-type InP embedded layer 106 function as current blocking layers when driving the semiconductor device 500. After the formation of each embedded layer, the SiO2 mask is removed by wet etching with hydrofluoric acid as the etchant.

[0024] Next, on the top surface of the striped mesa structure 150 and the surface of the S-doped n-type InP embedding layer 106, the Zn-doped p-type InP second cladding layer 107, the Zn-doped p-type InGaAs contact layer 108, and the S-doped n-type InP barrier layer 109 are sequentially grown by the MOCVD method (third crystal growth step).

[0025] Next, a SiO2 insulating film 110 is deposited over the entire surface using the plasma CVD method (insulating film formation process), completing the semiconductor device 500 shown in Figure 1. The SiO2 insulating film 110 deposited using the plasma CVD method is also called a plasma CVD insulating film.

[0026] <Effect 1 of Embodiment 1> According to the semiconductor device of Embodiment 1, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, resulting in the effect of obtaining a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency.

[0027] <Configuration of the embedded semiconductor laser according to Embodiment 1> Figure 2 is a cross-sectional view showing the configuration of an embedded semiconductor laser 550 to which the semiconductor element 500 shown in Figure 1 is applied. The element structure of the embedded semiconductor laser 550 is based on the semiconductor element 500. The embedded semiconductor laser 550 has an element structure in which an opening 110a is formed in the SiO2 insulating film 110 of the semiconductor element 500, a surface electrode 111 is provided on the SiO2 insulating film 110 including the opening 110a, and a back electrode 112 is provided on the back side of the n-type InP substrate 101.

[0028] <Manufacturing method for embedded semiconductor laser according to Embodiment 1> The manufacturing method for the embedded semiconductor laser 550 according to Embodiment 1 is the same as the manufacturing method for the semiconductor element 500 up to the point of forming the SiO2 insulating film 110 using the plasma CVD method, so the subsequent manufacturing method will be described below.

[0029] After the deposition of the SiO2 insulating film 110, an opening 110a with an opening width of 3 μm is formed in the portion of the SiO2 insulating film 110 facing the top surface of the striped mesa structure 150 using photolithography and dry etching techniques (opening formation step).

[0030] A surface electrode 111 is formed on the SiO2 insulating film 110, which includes an opening 110a. After the formation of the surface electrode 111, the back surface is polished, and a back surface electrode 112 is formed on the back side of the n-type InP substrate 101 (electrode formation process), thereby completing the device structure as an embedded semiconductor laser 550 as shown in Figure 2.

[0031] When the InP layer and InGaAs layer are doped with S, they become n-type conductive, and when they are doped with Zn, they become p-type conductive. In the device structure of the semiconductor device 500 and the embedded semiconductor laser 550, an S-doped n-type InP barrier layer 109 exists between the SiO2 insulating film 110 and the Zn-doped p-type InGaAs contact layer 108. Therefore, the S-doped n-type InP barrier layer 109 can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0032] The above explanation showed an example of an embedded semiconductor laser 550, but similar effects can be obtained with a ridge-type semiconductor laser, which will be discussed later.

[0033] In the above examples, sulfur (S) and zinc (Zn) were shown as dopants for the semiconductor layer, but similar effects can be obtained by using any dopant of the n-type and p-type, respectively.

[0034] Furthermore, in the above-described embodiment, the current blocking layer was constructed using an Fe-doped semi-insulating InP embedded layer 105 and an S-doped n-type InP embedded layer 106, but other embedded structures such as thyristor types may also be used.

[0035] <Effect 2 of Embodiment 1> In the embedded semiconductor laser according to Embodiment 1, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110. This results in an embedded semiconductor laser that can operate with a wide frequency bandwidth and high luminous efficiency.

[0036] Modification 1 of Embodiment 1. Figure 3 is a cross-sectional view showing the configuration of a semiconductor element 600 according to Modification 1 of Embodiment 1. Figure 4 is a cross-sectional view showing the configuration of an embedded semiconductor laser 650 to which the semiconductor element structure according to Modification 1 of Embodiment 1 is applied.

[0037] <Configuration of a semiconductor element according to a modified example 1 of Embodiment 1> As shown in the cross-sectional view of Figure 3, the semiconductor element 600 according to the first modification of Embodiment 1 has an opening 110b provided in the portion of the n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109 and the SiO2 insulating film 110 that are facing the top surface of the stripe-shaped mesa structure 150, in the configuration of the semiconductor element 500 according to Embodiment 1.

[0038] The opening width of the opening 110b is 3 μm, and the p-type InGaAs contact layer 108 is exposed at the bottom of the opening 110b.

[0039] <Manufacturing method for semiconductor element according to modified example 1 of Embodiment 1> The manufacturing method for the semiconductor element 600 according to Modification 1 of Embodiment 1 is the same as the manufacturing method for the embedded semiconductor laser 550 up to the point of forming an opening in the SiO2 insulating film 110, so the subsequent manufacturing method will be described below.

[0040] After forming an opening in the SiO2 insulating film 110 on the surface of the device, the S-doped n-type InP barrier layer 109 is etched using an etching-selective chemical for InGaAs until it reaches the Zn-doped p-type InGaAs contact layer 108, thereby forming the opening 110b shown in Figure 3. Because an etching-selective chemical is used, etching proceeds within the S-doped n-type InP barrier layer 109 but stops at the surface of the Zn-doped p-type InGaAs contact layer 108. Therefore, the Zn-doped p-type InGaAs contact layer 108 is exposed at the bottom of the opening 110b.

[0041] <Effect 1 of Modified Example 1 of Embodiment 1> According to the semiconductor device of Modification 1 of Embodiment 1, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, resulting in the effect of obtaining a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency.

[0042] <Configuration of an embedded semiconductor laser according to a modified example 1 of Embodiment 1> Figure 4 is a cross-sectional view showing the configuration of an embedded semiconductor laser 650 to which a semiconductor device structure according to a modified example 1 of Embodiment 1 is applied. The embedded semiconductor laser 650 has an element structure in which an opening 110b is formed in the SiO2 insulating film 110 and the n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109 of the semiconductor device 500, a surface electrode 111 is provided on the SiO2 insulating film 110 including the opening 110b, and a back electrode 112 is provided on the back side.

[0043] In the embedded semiconductor laser 650, an n-type InP barrier layer 109 is inserted across the entire area between the p-type InGaAs contact layer 108 and the SiO2 insulating film 110. Therefore, the n-type InP barrier layer 109 can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0044] Furthermore, in the embedded semiconductor laser 650, the n-type InP barrier layer 109 is removed between the surface electrode 111 and the p-type InGaAs contact layer 108 at the opening 110b of the SiO2 insulating film 110, which also has the effect of reducing the contact resistance between the surface electrode 111 and the semiconductor layer.

[0045] <Effect 2 of Modified Example 1 of Embodiment 1> According to the embedded semiconductor laser of the first modified embodiment, an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110. Since the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, an embedded semiconductor laser with a wide frequency bandwidth and high luminous efficiency can be obtained.

[0046] Modification 2 of Embodiment 1. Figure 5 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 2 of Embodiment 1. Figure 6 is a cross-sectional view showing another configuration of the semiconductor device according to Modification 2 of Embodiment 1.

[0047] <Configuration of the semiconductor element according to modified example 2 of Embodiment 1> As shown in the cross-sectional view of Figure 5, the semiconductor element 700 according to the modified example 2 of Embodiment 1 consists of the following semiconductor layers sequentially stacked on a (100) plane S-doped n-type InP substrate 101: an S-doped n-type InP cladding layer (first semiconductor layer of the first conductivity type) 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, a Zn-doped p-type InP cladding layer (second semiconductor layer of the second conductivity type) 104a, a Zn-doped p-type InGaAs contact layer 108, and an S-doped n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109, and an SiO2 insulating film 110 formed on the S-doped n-type InP barrier layer 109 with an opening 110c. As an example of an active layer, an active layer composed of undoped AlGaInAs was given, but any active layer composed of a semiconductor layer containing Ga (gallium) and As (arsenic) is acceptable, and it may be an n-type or p-type semiconductor layer other than an undoped one.

[0048] <Other configurations of the semiconductor element according to modified example 2 of Embodiment 1> The semiconductor element 750 according to the modified example 2 of Embodiment 1 has an element structure in which, in addition to the SiO2 insulating film 110 of the semiconductor element 700, an opening 110d that reaches the n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109 is provided.

[0049] <Effects of Modified Example 2 of Embodiment 1> According to the semiconductor device of the modified embodiment 2, an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110. Since the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, a semiconductor device with a wide frequency bandwidth and high luminous efficiency is obtained.

[0050] Embodiment 2. Figure 7 is a cross-sectional view showing the configuration of a semiconductor device 800 according to Embodiment 2. In Figure 7, as an example of a semiconductor device 800 according to Embodiment 2, an embedded semiconductor laser is shown that uses an n-type InP substrate 101 and has an AlGaInAs active layer 103, similar to Embodiment 1.

[0051] <Configuration of semiconductor element according to Embodiment 2> The semiconductor device 800 has a mesa structure 160 in which a stacked semiconductor layer is formed in a stripe pattern on a (100) plane S-doped n-type InP substrate 101, consisting of sequentially stacked S-doped n-type InP cladding layers (first semiconductor layer of the first conductivity type) 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, a Zn-doped p-type InP cladding layer (second semiconductor layer of the second conductivity type) 104a, and a Zn-doped p-type InGaAs contact layer 108. The structure consists of semiconductor layers, each comprising an Fe-doped semi-insulating InP embedding layer 105 and an S-doped n-type InP embedding barrier layer (second semiconductor layer of the first conductivity type) 109a formed on both sides of a pip-shaped mesa structure 160; an SiO2 insulating film 110 formed on the S-doped n-type InP embedding barrier layer 109a with an opening 110e; a surface electrode 111 provided on the SiO2 insulating film 110 including the opening 110e; and a back electrode 112 provided on the back side of the S-doped n-type InP substrate 101.

[0052] Each layer that makes up the semiconductor device 800 is described below. The doping concentration of the S-doped n-type InP substrate 101 is 5.0 × 10⁻⁶. 18 cm -3 The thickness of the S-doped n-type InP cladding layer 102 is 1.0 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The undoped AlGaInAs active layer 103 has a thickness of 0.3 μm, the Zn-doped p-type InP cladding layer 104a has a thickness of 2.3 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3The Zn-doped p-type InGaAs contact layer 108 has a thickness of 0.3 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 As an example of an active layer, an active layer composed of undoped AlGaInAs was given, but any active layer composed of a semiconductor layer containing Ga (gallium) and As (arsenic) is acceptable, and it may be an n-type or p-type semiconductor layer other than an undoped one.

[0053] The Fe-doped semi-insulating InP embedded layer 105 has a thickness of 4.0 μm and a doping concentration of 5.0 × 10⁻⁶. 16 cm -3 The thickness of the S-doped n-type InP embedded barrier layer 109a is 0.5 μm, and the doping concentration is 5.0 × 10⁻⁶. 18 cm -3 The height of the striped mesa structure 160 is 4.5 μm.

[0054] <Manufacturing method for semiconductor elements according to Embodiment 2> The method for manufacturing the semiconductor element 800 according to Embodiment 2 is described below. On a (100)-sided S-doped n-type InP substrate 101, a multilayer semiconductor layer consisting of an S-doped n-type InP cladding layer 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, a Zn-doped p-type InP cladding layer 104a, and a Zn-doped p-type InGaAs contact layer 108 is sequentially grown using a crystal growth method such as MOCVD (first crystal growth step).

[0055] After crystal growth in each of the above layers, the surface of the Zn-doped p-type InGaAs contact layer 108 is treated with photolithography and etching techniques. <011> A striped SiO2 mask with a width of 1.5 μm is formed in the direction.

[0056] By using a striped SiO2 mask as an etching mask, dry etching is performed from the Zn-doped p-type InGaAs contact layer 108 to the S-doped n-type InP substrate 101 to form a striped mesa structure 160 with a height of 4.5 μm from the bottom surface (mesa structure formation process).

[0057] After forming a striped mesa structure 160, Fe-doped semi-insulating InP embedding layer 105 and S-doped n-type InP embedding barrier layer 109a are sequentially crystal-grown on both sides of the striped mesa structure 160 by MOCVD (second crystal growth step). The Fe-doped semi-insulating InP embedding layer 105 and S-doped n-type InP embedding barrier layer 109a function as current blocking layers when driving the semiconductor device 800.

[0058] After each embedded layer is formed, the SiO2 mask is removed by wet etching using hydrofluoric acid as the etchant. Then, a SiO2 insulating film 110 is deposited over the entire surface using plasma CVD (insulating film formation process).

[0059] After the deposition of the SiO2 insulating film 110, an opening 110e with an opening width of 3 μm is formed in the portion of the SiO2 insulating film 110 facing the top surface of the striped mesa structure 160 using photolithography and dry etching techniques (opening formation step).

[0060] A surface electrode 111 is formed on the SiO2 insulating film 110, which includes an opening 110a. After the formation of the surface electrode 111, the back surface is polished, and a back surface electrode 112 is formed on the back side of the n-type InP substrate 101 (electrode formation process), thereby completing the device structure as an embedded semiconductor laser as shown in Figure 7.

[0061] In the device structure of semiconductor device 800, an n-type InP embedding barrier layer 109a exists between the SiO2 insulating film 110 and the semi-insulating InP embedding layer 105. Therefore, the n-type InP embedding barrier layer 109a can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0062] <Effects of Embodiment 2> According to the semiconductor device of Embodiment 2, since an n-type InP embedded barrier layer 109a is provided directly beneath the SiO2 insulating film 110, the n-type InP embedded barrier layer 109a prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, resulting in the effect of obtaining a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency.

[0063] Embodiment 3. Figure 8 is a cross-sectional view showing the configuration of a semiconductor element 850 according to Embodiment 3. In Figure 8, as an example of a semiconductor element 850 according to Embodiment 2, a ridge-type semiconductor laser is shown that uses an n-type InP substrate 101 and has an AlGaInAs active layer 103, similar to Embodiment 1.

[0064] <Configuration of the semiconductor element according to Embodiment 3> The semiconductor device 850 is a (100)-plane S-doped n-type InP substrate 101, on which a striped layer of semiconductor material is formed, consisting of sequentially stacked S-doped n-type InP cladding layers (first semiconductor layer of the first conductivity type) 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, a Zn-doped p-type InP cladding layer (second semiconductor layer of the second conductivity type) 104a, and a Zn-doped p-type InGaAs contact layer 108. The structure consists of a ridge structure 170, an S-doped n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109 formed on both sides of the stripe-shaped ridge structure 170, an SiO2 insulating film 110 formed on the S-doped n-type InP barrier layer 109 with an opening 110f provided at the top surface of the ridge structure 170, a surface electrode 111 provided on the SiO2 insulating film 110 including the opening 110f, and a back electrode 112 provided on the back side of the S-doped n-type InP substrate 101.

[0065] Each layer that makes up the semiconductor device 850 is described below. The doping concentration of the S-doped n-type InP substrate 101 is 5.0 × 10⁻⁶. 18 cm -3 The thickness of the S-doped n-type InP cladding layer 102 is 1.0 μm, and the doping concentration is 1.0 × 10⁻⁶.18 cm -3 The undoped AlGaInAs active layer 103 has a thickness of 0.3 μm, the Zn-doped p-type InP cladding layer 104a has a thickness of 2.3 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The Zn-doped p-type InGaAs contact layer 108 has a thickness of 0.3 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 As an example of an active layer, an active layer composed of undoped AlGaInAs was given, but any active layer composed of a semiconductor layer containing Ga (gallium) and As (arsenic) is acceptable, and it may be an n-type or p-type semiconductor layer other than an undoped one.

[0066] The thickness of the S-doped n-type InP barrier layer 109 is 0.5 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The height of the striped ridge structure 170 is 2.6 μm.

[0067] <Manufacturing method for semiconductor elements according to Embodiment 3> The method for manufacturing the semiconductor element 850 according to Embodiment 3 is described below. On a (100)-sided S-doped n-type InP substrate 101, a multilayer semiconductor layer consisting of an S-doped n-type InP cladding layer 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, a Zn-doped p-type InP cladding layer 104a, and a Zn-doped p-type InGaAs contact layer 108 is sequentially grown using a crystal growth method such as MOCVD (first crystal growth step).

[0068] After crystal growth in each of the above layers, the surface of the Zn-doped p-type InGaAs contact layer 108 is treated with photolithography and etching techniques. <011> A striped SiO2 mask with a width of 1.5 μm is formed in the direction.

[0069] Using a striped SiO2 mask as an etching mask, the Zn-doped p-type InGaAs contact layer 108 and the Zn-doped p-type InP cladding layer 104a are dry-etched to form a ridge shape, thereby creating a striped ridge structure 170 with a height of 2.6 μm from the bottom surface (ridge structure formation process).

[0070] After forming a striped ridge structure 170, an S-doped n-type InP barrier layer 109 is crystallized on the striped ridge structure 170 by MOCVD (second crystal growth step).

[0071] After each embedded layer is formed, the SiO2 mask is removed by wet etching using hydrofluoric acid as the etchant. Next, an SiO2 insulating film 110 is deposited over the entire surface using plasma CVD (insulating film formation process).

[0072] After the deposition of the SiO2 insulating film 110, an opening 110f with an opening width of 3 μm is formed in the portion of the SiO2 insulating film 110 on the top surface of the stripe-shaped ridge structure 170 using photolithography and dry etching techniques (opening formation step).

[0073] A surface electrode 111 is formed on the SiO2 insulating film 110 containing the aperture 110f. After the formation of the surface electrode 111, the back surface is polished, and a back surface electrode 112 is formed on the back side of the S-doped n-type InP substrate 101 (electrode formation process), thereby completing the device structure as a ridge-type semiconductor laser as shown in Figure 8.

[0074] In the semiconductor device 850, an n-type InP barrier layer 109 is inserted across the entire area between the undoped AlGaInAs active layer 103 and the SiO2 insulating film 110. Therefore, the n-type InP barrier layer 109 can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0075] <Effects of Embodiment 3> According to the semiconductor device of Embodiment 3, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, resulting in the effect of obtaining a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency.

[0076] Modification 1 of Embodiment 3. Figure 9 is a cross-sectional view showing the configuration of a ridge-type semiconductor laser 900 to which the semiconductor device structure of Embodiment 3 is applied. The ridge-type semiconductor laser 900 has an element structure in which an opening 110g is formed in the SiO2 insulating film 110 and the n-type InP barrier layer 109 on the top surface of the ridge structure 170 of the semiconductor device 850, a surface electrode 111 is provided on the SiO2 insulating film 110 including the opening 110g, and a back electrode 112 is provided on the back side of the n-type InP substrate 101.

[0077] In the ridge-type semiconductor laser 900, an n-type InP barrier layer 109 is inserted between a portion of each of the undoped AlGaInAs active layer 103, the p-type InGaAs contact layer 108, and the Zn-doped p-type InP cladding layer 104a and the SiO2 insulating film 110. Therefore, the n-type InP barrier layer 109 can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0078] Furthermore, in the ridge-type semiconductor laser 900, the n-type InP barrier layer 109 is removed between the surface electrode 111 and the p-type InGaAs contact layer 108, which also has the effect of reducing the contact resistance between the surface electrode 111 and the semiconductor layer.

[0079] <Effects of Modification 1 of Embodiment 3> According to the semiconductor laser of Modification 1 of Embodiment 3, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, and furthermore, the contact resistance between the surface electrode 111 and the semiconductor layer can also be reduced, resulting in the effect of obtaining a ridge-type semiconductor laser that can operate with a wider frequency bandwidth and higher luminous efficiency.

[0080] Modification 2 of Embodiment 3. Figure 10 is a cross-sectional view showing the configuration of an embedded semiconductor laser 950 to which the semiconductor device structure of Embodiment 3 is applied. The embedded semiconductor laser 950 has a configuration in which the mesa structure 150 of the embedded semiconductor laser 550 according to Embodiment 1 is further processed into a mesa-shaped structure 180.

[0081] The embedded semiconductor laser 950 has an element structure in which an opening 110h is provided in the SiO2 insulating film 110 and n-type InP barrier layer 109 on the top surface of the mesa-shaped structure 180, a surface electrode 111 is provided on the SiO2 insulating film 110 including the opening 110h, and a back electrode 112 is provided on the back side.

[0082] In the embedded semiconductor laser 950, an n-type InP barrier layer (second semiconductor layer of the first conductivity type) 109 is inserted between a portion of each of the semi-insulating InP embedded layer 105, n-type InP embedded layer 106, p-type InP second cladding layer 107, and p-type InGaAs contact layer 108 and the SiO2 insulating film 110. Therefore, the n-type InP barrier layer 109 can suppress the diffusion of hydrogen contained in the SiO2 insulating film 110 into each semiconductor layer.

[0083] Furthermore, in the embedded semiconductor laser 950, the n-type InP barrier layer 109 is removed between the surface electrode 111 and the p-type InGaAs contact layer 108, which also has the effect of reducing the contact resistance between the surface electrode 111 and the semiconductor layer.

[0084] <Effects of Modification 2 of Embodiment 3> According to the embedded semiconductor laser of the modified example 2 of Embodiment 3, since an n-type InP barrier layer 109 is provided directly beneath the SiO2 insulating film 110, the n-type InP barrier layer 109 prevents the diffusion of hydrogen contained in the SiO2 insulating film 110, and furthermore, the contact resistance between the surface electrode 111 and the semiconductor layer can also be reduced. As a result, an embedded semiconductor laser with a wide frequency bandwidth and high luminous efficiency can be obtained.

[0085] Embodiment 4. Figure 11 is a cross-sectional view showing the configuration of a semiconductor device 1000 according to Embodiment 4. In Figure 11, an embedded semiconductor laser is shown as an example of a semiconductor device 1000 according to Embodiment 1, using an n-type InP substrate 101 and having an AlGaInAs active layer 103.

[0086] <Configuration of the semiconductor element according to Embodiment 4> The semiconductor device 1000 has a mesa structure 150 in which a multilayer semiconductor layer is formed in a stripe shape on a (100)-plane S-doped n-type InP substrate 101, consisting of sequentially stacked S-doped n-type InP cladding layers (first semiconductor layer of the first conductivity type) 102, an undoped AlGaInAs active layer 103 sandwiched between AlGaInAs photoconfinement layers on its upper and lower surfaces, and a Zn-doped p-type InP first cladding layer (second semiconductor layer of the second conductivity type) 104, and Fe-doped semi-insulating InP embedding layers 105 and S-doped n-type InP formed on both sides of the stripe-shaped mesa structure 150. The structure consists of a embedding layer 106, a Zn-doped p-type InP second cladding layer (second conductivity type cladding layer) 107 formed to cover the top surface of the striped mesa structure 150 and the surface of the S-doped n-type InP embedding layer 106, a Zn-doped p-type InGaAs contact layer (second conductivity type contact layer) 108, and an S-doped n-type InP barrier layer (first conductivity type second semiconductor layer) 109, as well as an SiO2 insulating film consisting of two layers, an SiO2 first insulating film 115a and an SiO2 second insulating film 115b, formed on the S-doped n-type InP barrier layer 109.

[0087] Each layer constituting the semiconductor device 1000 is described below. The doping concentration of the S-doped n-type InP substrate 101 is 5.0 × 10⁻⁶. 18 cm -3 The thickness of the S-doped n-type InP cladding layer 102 is 1.0 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The thickness of the undoped AlGaInAs active layer 103 is 0.3 μm, the thickness of the Zn-doped p-type InP first cladding layer 104 is 0.3 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The height of the striped mesa structure 150 is 2.0 μm. As an example of an active layer, an active layer composed of undoped AlGaInAs was given, but any active layer composed of a semiconductor layer containing Ga (gallium) and As (arsenic) is acceptable, and it may be an n-type or p-type semiconductor layer other than an undoped one.

[0088] The Fe-doped semi-insulating InP embedded layer 105 has a thickness of 1.8 μm and a doping concentration of 5.0 × 10⁻⁶. 16 cm -3 The thickness of the S-doped n-type InP embedded layer 106 is 0.2 μm, and the doping concentration is 5.0 × 10⁻⁶. 18 cm -3 That is the case.

[0089] The thickness of the Zn-doped p-type InP second cladding layer 107 is 2.0 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 The Zn-doped p-type InGaAs contact layer 108 has a thickness of 0.3 μm and a doping concentration of 1.0 × 10⁻⁶. 19 cm -3 The thickness of the S-doped n-type InP barrier layer 109 is 0.2 μm, and the doping concentration is 1.0 × 10⁻⁶. 18 cm -3 That is the case.

[0090] <Manufacturing method for semiconductor device according to Embodiment 4> The only difference between the semiconductor device manufacturing method according to Embodiment 4 and the semiconductor device manufacturing method according to Embodiment 1 is the process of forming the SiO2 insulating film, which consists of two layers: a first SiO2 insulating film 115a and a second SiO2 insulating film 115b. Therefore, the formation of the SiO2 insulating film will be described below.

[0091] By depositing a first SiO2 insulating film 115a over the entire surface of the S-doped n-type InP barrier layer 109 using the sputtering method, and then depositing a second SiO2 insulating film 115b on top of the first SiO2 insulating film 115a using the plasma CVD method (insulating film formation process), the structure of the semiconductor device 1000 shown in Figure 11 is completed.

[0092] Since the SiO2 first insulating film 115a formed using the sputtering method does not contain hydrogen, the influence of hydrogen diffusion from the SiO2 second insulating film 115b formed using the plasma CVD method into each semiconductor layer can be suppressed. Therefore, the thickness of the n-type InP barrier layer 109 on the semiconductor surface can be reduced. However, Non-Patent Literature 2 points out that the hydrogen diffusion prevention effect is small when the thickness of the n-type InP layer is thin.

[0093] <Effects of the semiconductor element according to Embodiment 4> According to the semiconductor device of Embodiment 4, since the SiO2 insulating film is composed of two layers, a first SiO2 insulating film 115a and a second SiO2 insulating film 115b, it is possible to reduce the thickness of the n-type InP barrier layer 109 directly beneath the SiO2 insulating film. This results in a semiconductor device that can operate with a wide frequency bandwidth and high luminous efficiency.

[0094] <Configuration of the embedded semiconductor laser according to Embodiment 4> Figure 12 is a cross-sectional view showing the configuration of an embedded semiconductor laser 1100 to which the semiconductor device structure of Embodiment 4 is applied. The embedded semiconductor laser 1100 has an element structure in which an opening 110i is formed in the SiO2 first insulating film 115a and SiO2 second insulating film 115b and the n-type InP barrier layer 109 facing the top surface of the mesa structure 150 of the semiconductor device 1000, a surface electrode 111 is provided on the SiO2 second insulating film 115b including the opening 110i, and a back electrode 112 is provided on the back side of the n-type InP substrate 101.

[0095] The aperture 110i of the embedded semiconductor laser 1100 is formed by first creating a 3 μm wide aperture in the SiO2 first insulating film 115a and SiO2 second insulating film 115b facing the top surface of the mesa structure 150 using photolithography and dry etching techniques, and then etching the n-type InP barrier layer 109 with a chemical solution that is etching-selective for InGaAs.

[0096] Since the SiO2 first insulating film 115a deposited using the sputtering method does not contain hydrogen, the influence of hydrogen diffusion from the SiO2 second insulating film 115b deposited using the plasma CVD method into each semiconductor layer can be suppressed. Therefore, the thickness of the n-type InP barrier layer 109 on the semiconductor surface can be reduced.

[0097] <Effects of the embedded semiconductor laser according to Embodiment 4> According to the embedded semiconductor laser of Embodiment 4, since the SiO2 insulating film is composed of two layers, a first SiO2 insulating film 115a and a second SiO2 insulating film 115b, it is possible to reduce the thickness of the n-type InP barrier layer 109 directly beneath the SiO2 insulating film. This results in an embedded semiconductor laser that can operate with a wide frequency bandwidth and high luminous efficiency.

[0098] In Embodiment 4, the SiO2 insulating film is described as being composed of two layers: a first SiO2 insulating film 115a and a second SiO2 insulating film 115b. However, such a two-layer SiO2 insulating film may also be applied to semiconductor devices or semiconductor lasers according to Embodiments 1 to 3.

[0099] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but can be applied individually or in various combinations to the embodiments.

[0100] Accordingly, countless variations not illustrated are conceivable within the scope of the technology disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component and its combination with components of other embodiments. [Explanation of Symbols]

[0101] 101 n-type InP substrate, 102 n-type InP cladding layer, 103 undoped AlGaInAs active layer, 104 p-type InP first cladding layer, 104a p-type InP cladding layer, 105 semi-insulating InP embedding layer, 106 n-type InP embedding layer, 107 p-type InP second cladding layer, 108 p-type InGaAs contact layer, 109 n-type InP barrier layer, 109a n-type InP embedding barrier layer, 110 SiO2 insulating film, 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110i openings, 115a SiO2 first insulating film, 115b SiO2 second insulating film, 150, 160 mesa structure, 170 ridge structure, 180 Mesa-shaped structure, 500, 600, 700, 750, 800, 850, 1000; Semiconductor element, 550, 650, 950, 1100; Embedded semiconductor laser, 900; Ridge-type semiconductor laser

Claims

1. Semiconductor substrate and A mesa structure is formed on the semiconductor substrate in which a stacked semiconductor layer consisting of a first semiconductor layer of a first conductivity type, an active layer, and a semiconductor layer of a second conductivity type is formed in a stripe pattern. The embedded layers are embedded on both sides of the mesa structure, A second semiconductor layer of the first conductivity type formed on the embedded layer and on the upper surface side of the mesa structure, An insulating film formed in contact with the second semiconductor layer of the first conductivity type, A semiconductor element equipped with the following features.

2. The semiconductor element according to claim 1, characterized in that an opening is provided in the portion of the insulating film facing the top surface of the mesa structure, and the second semiconductor layer of the first conductivity type is exposed at the bottom of the opening.

3. The semiconductor element according to claim 1, characterized in that an opening is provided in the portion of the insulating film and the second semiconductor layer of the first conductivity type that is facing the top surface of the mesa structure.

4. The semiconductor element according to claim 3, characterized in that the region including the mesa structure and the embedded layer further exhibits a mesa shape.

5. The semiconductor element according to any one of claims 1 to 3, characterized in that a cladding layer of the second conductivity type and a contact layer of the second conductivity type are further formed between the semiconductor layer of the second conductivity type and the second semiconductor layer of the first conductivity type.

6. The semiconductor element according to any one of claims 1 to 4, characterized in that the insulating film is composed of a first insulating film and a second insulating film, and the first insulating film is a plasma CVD insulating film.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor substrate, the first semiconductor layer of the first conductivity type, and the semiconductor layer of the second conductivity type are composed of indium phosphide, and the active layer is composed of a semiconductor layer containing gallium and arsenic.

8. The semiconductor element according to any one of claims 1 to 4, characterized in that the first conductivity type is n-type and the second conductivity type is p-type.

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