Gate drive unit and display device including the same

Abstract

The present invention provides a gate drive unit capable of controlling the drive frequency for each area of ​​the display panel, and a display device including the same. [Solution] The gate drive unit is a light-emitting drive unit including a plurality of cascaded light-emitting stages, wherein the plurality of light-emitting stages output a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals. The output control unit includes a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages includes an output unit that outputs a pull-up control signal and a pull-down control signal based on a light-emitting control signal, a clock signal, a carry unit that outputs a carry signal, a control clock signal, a first power supply and a second power supply.

Description

Technical Field

[0001] This specification relates to a gate driving unit and a display device including the same, and more particularly, to a gate driving unit capable of controlling a driving frequency and a display device including the same.

Background Art

[0002] As the information age has entered, the display field that visually represents electrical information signals has been rapidly developing. In response to this, various display devices with excellent performance in thinning, weight reduction, and low power consumption have been developed. Examples of such display devices include a liquid crystal display device (LCD), an organic light emitting display device (OLED), and the like.

[0003] Such a display device may include a display panel on which a plurality of pixels for displaying an image are arranged, a data driving unit that supplies data signals to the plurality of pixels through a plurality of data wirings, a gate driving unit that supplies gate signals to the plurality of pixels through a plurality of gate wirings, and a driving circuit such as a timing control unit that controls the data driving unit and the gate driving unit.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a gate driving unit capable of controlling the driving frequency for each region of the display panel and a display device including the same.

[0005] Another problem to be solved by this specification is to provide a gate driving unit with minimized bezels and a display device including the same.

[0006] Another problem that this specification seeks to solve is to provide a gate drive unit and a display device including the same, with improved display image quality.

[0007] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A gate drive unit according to one embodiment of this specification includes a light-emitting drive unit including a plurality of cascaded light-emitting stages, wherein the plurality of light-emitting stages output a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals, and an output control unit including a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light-emitting control signal from the plurality of light-emitting control signals, at least one clock signal from the plurality of clock signals, a first power supply and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, a first power supply and a second power supply.

[0009] An embodiment of the gate drive unit according to this specification may include an output control unit comprising a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply; and a scan drive unit comprising a plurality of cascaded gate stages, wherein the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals and a plurality of pull-up control signals and a plurality of pull-down control signals. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light emission control signal from a plurality of light emission control signals, at least one clock signal from a plurality of clock signals, a first power supply and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from a plurality of control clock signals, a first power supply and a second power supply.

[0010] An embodiment of the Specified Information includes a display panel containing a plurality of pixels, a scan drive unit that outputs a plurality of gate signals to the plurality of pixels, a light-emitting drive unit that outputs a plurality of light-emitting control signals to the plurality of pixels, and an output control unit that includes a plurality of stages that output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light-emitting control signal from the plurality of light-emitting control signals, at least one clock signal from the plurality of clock signals, a first power supply, and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, a first power supply, and a second power supply.

[0011] Specific details of other embodiments are included in the detailed description and drawings.

[0012] This specification may include an output control unit for controlling the output level of the gate signal output from the scan drive unit. This allows the specification to freely divide the display area in accordance with the displayed image and control the drive frequency for each area, rather than being limited to a fixed area. In this way, since the drive frequency is controlled in accordance with the display area, power consumption may be improved.

[0013] Furthermore, since this specification controls the signal level of the gate signal using an output control unit that is commonly connected to multiple scan drive units, the size of the bezel area where the gate drive units are located can be minimized.

[0014] Furthermore, this specification may include a voltage selection unit for controlling the voltage level of the bias voltage for controlling the on-bias state of pixels, according to the drive frequency for each display area. This prevents a decrease in display quality even if the drive frequency is controlled differently for each sub-display area of ​​the display area.

[0015] The effects relating to the examples in this specification are not limited to those exemplified above, and a wider variety of effects are included in this specification. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram showing a display device according to one embodiment of this specification. [Figure 2a] This figure shows an example of a display panel included in the display device shown in Figure 1. [Figure 2b] This figure shows an example of a display panel included in the display device shown in Figure 1. [Figure 3] This is a circuit diagram showing an example of pixels included in the display device shown in Figure 1. [Figure 4a] This waveform diagram illustrates an example of pixel driving in Figure 3. [Figure 4b]It is a waveform diagram for explaining an example of driving of pixels of 3. [Figure 5] It is a block diagram showing a gate driving unit according to an embodiment of the present specification. [Figure 6a] It is a block diagram showing an example of the gate driving unit of FIG. 5. [Figure 6b] It is a block diagram showing an example of the gate driving unit of FIG. 5. [Figure 7] It is a circuit diagram showing an example of the first stage included in the output control unit of the gate driving unit of FIG. 6a. [Figure 8a] It is a waveform diagram for explaining an example of driving of the first stage of FIG. 7. [Figure 8b] It is a waveform diagram for explaining an example of driving of the first stage of FIG. 7. [Figure 9] It is a waveform diagram for explaining an example of driving of the gate driving unit of FIG. 6a. [Figure 10] It is a block diagram showing an example of the scan driving unit included in the gate driving unit of FIG. 5. [Figure 11] It is a circuit diagram showing an example of the first gate stage included in the scan driving unit of FIG. 10. [Figure 12] It is a waveform diagram for explaining an example of driving of the scan driving unit of FIG. 10. [Figure 13] It is a circuit diagram showing another example of the first gate stage included in the scan driving unit of FIG. 10. [Figure 14] It is a waveform diagram for explaining another example of driving of the scan driving unit of FIG. 10. [Figure 15] It is a block diagram showing another example of the gate driving unit of FIG. 5. [Figure 16] It is a block diagram showing still another example of the gate driving unit of FIG. 5. [Figure 17] It is a waveform diagram showing an example of the control clock signal provided to the gate driving unit of FIG. 16. [Figure 18] It is a block diagram showing still another example of the gate driving unit of FIG. 5. [Figure 19]Figure 18 shows a waveform diagram illustrating an example of a control clock signal provided to the gate drive unit. [Figure 20] Figure 5 shows a block diagram illustrating yet another example of a gate drive unit. [Figure 21] Figure 20 shows a waveform diagram illustrating an example of a control clock signal provided to the gate drive unit. [Figure 22] Figure 5 shows a block diagram illustrating yet another example of a gate drive unit. [Figure 23] Figure 22 shows a waveform diagram illustrating an example of a control clock signal provided to the gate drive unit. [Figure 24] This is a block diagram showing a gate drive unit according to one embodiment of this specification. [Figure 25] This is a circuit diagram showing an example of the first selection stage of the voltage selection unit included in the gate drive unit of Figure 24. [Figure 26a] This waveform diagram illustrates an example of driving the first selection stage in Figure 25. [Figure 26b] This waveform diagram illustrates an example of driving the first selection stage in Figure 25. [Figure 26c] This waveform diagram illustrates an example of driving the first selection stage in Figure 25. [Figure 27] This waveform diagram illustrates another example of pixel driving in Figure 3. [Modes for carrying out the invention]

[0017] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs.

[0018] The shapes, areas, proportions, angles, numbers, etc. disclosed in the drawings illustrating the embodiments of this specification are illustrative and the specification is not limited to those illustrated. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of this specification, such detailed explanation will be omitted. Where "includes," "has," "is made," etc., are used in this specification, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0019] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0020] Throughout the specification, the same reference numeral refers to the same component.

[0021] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0022] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0023] In the following, this specification will be described with reference to the drawings.

[0024] Figure 1 is a block diagram showing a display device according to one embodiment of this specification.

[0025] Figures 2a and 2b show examples of display panels included in the display device shown in Figure 1.

[0026] Referring to Figure 1, the display device 100 according to one embodiment of this specification may include a timing control unit 110, a gate drive unit 120, a data drive unit 130, and a display panel 140.

[0027] The display panel 140 can generate an image to be provided to the user. For example, the display panel 140 may include a display area in which a plurality of pixels PX, each having a pixel circuit, are arranged, and a non-display area excluding the display area. For example, the pixel circuits may, but are not limited to, being arranged in each of the plurality of pixels PX. For example, the non-display area may extend from the display area. For example, the non-display area may completely or partially enclose the display area. For example, the non-display area may, but are not limited to, be curved towards the rear of the display panel 140 when viewed from the front of the display panel 140, thus being partially or completely invisible. For example, the non-display area may be flat.

[0028] Each of the multiple pixels PX is connected to a corresponding gate wiring GL and data wiring DL, and can display an image in response to the gate signal provided to the gate wiring GL and the data signal provided to the data wiring DL.

[0029] In one embodiment, the display area of ​​the display panel 140 may be divided into multiple areas. For example, the display area may include multiple sub-display areas. For example, referring further to Figure 2a, the display area AA of the display panel 140 may be divided into a first sub-display area AA1 and a second sub-display area AA2.

[0030] The first sub-display area AA1 and the second sub-display area AA2, which are included in the display area AA, may each contain at least one pixel PX. For example, at least one pixel PX may be placed on the first sub-display area AA1 and the second sub-display area AA2, respectively.

[0031] In one embodiment, display area AA is partitioned into sub-display areas of the same size, so that the first sub-display area AA1 and the second sub-display area AA2 can contain the same number of pixels PX. For example, display area AA may be divided into sub-display areas having different sizes. For example, the first sub-display area AA1 and the second sub-display area AA2 may have different numbers of pixels PX. For example, display area AA may be divided into sub-display areas perpendicular to the direction in which the gate lines extend, but is not limited thereto. For example, the first sub-display area AA1 and the second sub-display area AA2 contained in display area AA may share one or more pixels PX, and / or the number of pixels PX in one sub-display area may be greater than the number of pixels PX in the other sub-display area.

[0032] On the other hand, for the sake of explanation, Figure 2a describes the case where the display area AA is divided into two sub-display areas, but the embodiments described herein are not limited to this, and the display area AA may be divided into three or more sub-display areas. For example, as shown in Figure 2b, the display area AA may be divided into a second sub-display area AA2, and a first sub-display area AA1 and a third sub-display area AA3 located on either side of the second sub-display area AA2. For example, the display area AA may be divided into three or more sub-display areas having the same or different sizes. For example, the three or more sub-display areas may have the same or different number of pixels PX, but are not limited to this.

[0033] Referring to Figure 1, the timing control unit 110 can control the gate drive unit 120 and the data drive unit 130 based on input video RGB and input control signal CS provided from an external source (e.g., a host system). For example, the input control signal CS includes timing signals such as a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, and a clock signal, and the timing control unit 110 can generate a gate control signal GCS and a data control signal DCS based on the input control signal CS. The gate control signal GCS may be provided to the gate drive unit 120, and the data control signal DCS may be provided to the data drive unit 130.

[0034] Furthermore, the timing control unit 110 can rearrange the input video RGB in digital video data format to match the resolution of the display panel 140 to generate video data DATA, and provide it to the data drive unit 130.

[0035] The gate drive unit 120 can generate gate signals based on the gate control signal GCS and output gate signals to multiple gate wirings GL. For example, the gate drive unit 120 can sequentially output gate signals to multiple gate wirings GL on a pixel row basis. The gate control signal GCS may include a start signal for gate signal generation, multiple clock signals, etc.

[0036] In one embodiment, the gate drive unit 120 can generate a scan signal and a light emission control signal based on the gate control signal GCS. For example, the gate drive unit 120 may include at least one scan drive unit and at least one light emission drive unit. The scan drive unit can generate scan signals in a row-by-row manner to drive at least one scan wiring connected to each pixel row and supply them to a plurality of scan wirings. The light emission drive unit can generate light emission control signals in a row-by-row manner to drive at least one light emission control wiring connected to each pixel row and supply them to a plurality of light emission control wirings.

[0037] The data drive unit 130 can convert the digital video data DATA provided by the timing control unit 110 into an analog data signal based on the data control signal DCS and supply it to multiple data wirings DL.

[0038] A display device 100 according to one embodiment of this specification can display images at various drive frequencies depending on the driving conditions. Here, the drive frequency may mean the number of times a data signal is substantially written to the drive transistor included in the pixel PX. For example, the drive frequency may indicate the number of times the display image is reproduced per second. That is, the display device 100 can display images in response to various drive frequencies. On the other hand, in this specification, the drive frequency may be named the image refresh rate, screen reproduction rate, or screen scanning rate.

[0039] In one embodiment, the output frequency of the data drive unit 130 and / or the output frequency of the gate drive unit 120 that outputs a gate signal for a single horizontal line, for example, a single pixel row, can be determined in accordance with the drive frequency of the display device 100. For example, the drive frequency for driving video may be approximately 60Hz or higher, for example, 60Hz, 80Hz, 96Hz, 120Hz, 240Hz, etc., which may be considered a relatively high frequency. As another example, the drive frequency for driving still images, etc., may be approximately 30Hz or lower, for example, 30Hz, 10Hz, 1Hz, etc., which may be considered a relatively low frequency. Therefore, the display device 100 can adjust the output frequency of the gate drive unit 120 and the corresponding output frequency of the data drive unit 130 for a single horizontal line, for example, a single pixel row, depending on the drive conditions.

[0040] In one embodiment, the display device 100 can independently drive multiple sub-display areas included in display area AA. For example, depending on the drive mode of the display device 100, the display device 100 can drive multiple sub-display areas included in display area AA at the same drive frequency, or drive at least some of the multiple sub-display areas at different drive frequencies.

[0041] On the other hand, when the display device 100 controls the drive frequency for each sub-display area of ​​display area AA, the corresponding sub-display area does not have to be a fixed area. That is, the display device 100 according to one embodiment of this specification can divide display area AA into two or more sub-display areas based on a position where the drive frequency is to be divided in accordance with the displayed image, for example, a horizontal line where the drive frequency is to be divided, and drive each sub-display area with a different drive frequency.

[0042] Thus, the display device 100 according to one embodiment of this specification is not limited to a fixed area, but can be freely divided into display area AA of the display device 100 in accordance with the displayed image, and the drive frequency can be controlled for each area. Therefore, by controlling the drive frequency for each area in accordance with the displayed image, power consumption can be improved.

[0043] In the following, the pixel PX and its driving method will be described in more detail with reference to Figures 3 to 4b, and the driving method by which the display device 100 according to the embodiment of this specification displays images at various driving frequencies will be described in more detail with reference to Figures 5 to 27.

[0044] Figure 3 is a circuit diagram showing an example of pixels included in the display device shown in Figure 1.

[0045] Referring to Figure 3, a pixel PX may include a light-emitting element ED, a drive transistor DT, multiple switching transistors M1-M7, and a storage capacitor Cst. For example, depending on the design, at least one of the switching transistors M1, M2, M3, M4, M5, M6, and M7 may be omitted. For example, one or more additional transistors or capacitors may be included, but are not limited to these.

[0046] A drive transistor DT may be connected between a first power supply wire PL1 providing a high potential supply voltage VDD and a second power supply wire PL2 providing a low potential supply voltage VSS. The drive transistor DT can control the drive current applied to the light-emitting element ED by the source-gate voltage. For example, the drive transistor DT can control the drive current flowing from the first power supply wire PL1, which provides a high potential supply voltage VDD in accordance with the voltage of the gate electrode, through the light-emitting element ED to the second power supply wire PL2, which provides a low potential supply voltage VSS. For this purpose, the high potential supply voltage VDD may be set to a higher voltage than the low potential supply voltage VSS. For example, the high potential supply voltage VDD may be a positive voltage, and the low potential supply voltage VSS may be a negative voltage.

[0047] The first switching transistor M1 may be connected between the data trace DL, which provides the data signal Vdata, and the first electrode of the drive transistor DT, for example, the source electrode, which is the second node N2. The gate electrode of the first switching transistor M1 may be connected to the second scan trace SL2. The first switching transistor M1 can be turned on when the second scan signal SCAN2 is supplied to the second scan trace SL2, thereby electrically connecting the data trace DL and the second node N2.

[0048] The second switching transistor M2 may be connected between the second electrode of the driving transistor DT, for example, the drain electrode at the third node N3 and the gate electrode at the first node N1. The gate electrode of the second switching transistor M2 may be connected to the first scan wiring SL1. The second switching transistor M2 can be turned on when the first scan signal SCAN1 is supplied to the first scan wiring SL1, thereby electrically connecting the gate electrode and drain electrode of the driving transistor DT, for example, the first node N1 and the third node N3. When the second switching transistor M2 is turned on, the driving transistor DT may be connected in diode form.

[0049] A third switching transistor M3 may be connected between the first node N1 and the third power supply wiring PL3, which provides the first initialization voltage Vini. The gate electrode of the third switching transistor M3 may be connected to the fourth scan wiring SL4. The third switching transistor M3 can be turned on when the fourth scan signal SCAN4 is supplied to the fourth scan wiring SL4, supplying the first initialization voltage Vini to the first node N1. In this case, the gate electrode of the drive transistor DT, which is the first node N1, may be initialized to the first initialization voltage Vini. For this purpose, the first initialization voltage Vini may be set to a voltage lower than the lowest level of the data signal Vdata supplied to the data wiring DL.

[0050] A fourth switching transistor M4 may be connected between a fourth node N4, which is the first electrode of the light-emitting element ED, and a fourth power supply line PL4, which provides a second initialization voltage VAR. The gate electrode of the fourth switching transistor M4 may be connected to a third scan line SL3. The fourth switching transistor M4 can be turned on when a third scan signal SCAN3 is supplied to the third scan line SL3, supplying the second initialization voltage VAR to the fourth node N4, which is the first electrode of the light-emitting element ED. In this case, the parasitic capacitor of the light-emitting element ED may be discharged. This may prevent unintended micro-emissions, thereby improving the black representation capability of the pixel PX.

[0051] On the other hand, the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR may be different from each other. That is, the voltage used to initialize the first node N1 and the voltage used to initialize the fourth node N4 may be set to be different from each other.

[0052] In low-frequency driving, where the length of a single frame period is long, if the first initialization voltage Vini supplied to the first node N1 is too low, a strong on-bias is applied to the drive transistor DT, which can cause a shift in the threshold voltage of the drive transistor DT during that frame period. Such hysteresis characteristics can cause flicker in low-frequency driving. Therefore, in a low-frequency driven display device 100, a first initialization voltage Vini higher than the low-potential power supply voltage VSS may be required.

[0053] However, if the voltage level of the second initialization voltage VAR supplied to the fourth node N4 for the initialization of the light-emitting element ED is higher than a predetermined standard, the voltage of the parasitic capacitor of the light-emitting element ED may not be discharged but rather charged. Therefore, the voltage level of the second initialization voltage VAR must be low enough to discharge the voltage of the parasitic capacitor of the light-emitting element ED. For example, taking into account the threshold voltage of the light-emitting element ED, the voltage level of the second initialization voltage VAR may be set so that it is lower than the sum of the threshold voltage of the light-emitting element ED and the low-potential power supply voltage VSS.

[0054] However, this is illustrative, and the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR can be set in various ways. For example, the voltage levels of the first initialization voltage Vini and the second initialization voltage VAR may be substantially the same.

[0055] A fifth switching transistor M5 may be connected between the first power supply wiring PL1 and the second node N2. The gate electrode of the fifth switching transistor M5 may be connected to the light emission control wiring EL. The fifth switching transistor M5 may be turned off when a light emission control signal EM is supplied to the light emission control wiring EL, and turned on otherwise. When the fifth switching transistor M5 is turned on, the second node N2 may be electrically connected to the first power supply wiring PL1.

[0056] The sixth switching transistor M6 may be connected between the drain electrode of the drive transistor DT, for example, the third node N3, and the first electrode of the light-emitting element ED, for example, the fourth node N4. The gate electrode of the sixth switching transistor M6 may be connected to the light-emitting control wiring EL. The sixth switching transistor M6 may be controlled substantially identically to the fifth switching transistor M5. When the sixth switching transistor M6 is turned on, the third node N3 and the fourth node N4 may be electrically coupled.

[0057] The seventh switching transistor M7 may be connected between the second node N2 and the fifth power supply wiring PL5, which provides the bias voltage Vobs. The gate electrode of the seventh switching transistor M7 may be connected to the third scan wiring SL3. The seventh switching transistor M7 can be turned on when the third scan signal SCAN3 is supplied to the third scan wiring SL3 and supply the bias voltage Vobs to the second node N2, which is the source electrode of the drive transistor DT.

[0058] In one embodiment, the bias voltage Vobs may have a level similar to the voltage level of the black tone data signal Vdata. For example, the bias voltage Vobs may have a voltage level of approximately 5-7V, but this is illustrative and the voltage level of the bias voltage Vobs is not limited thereto.

[0059] As a result, a predetermined high voltage can be applied to the source electrode of the drive transistor DT by turning on the seventh switching transistor M7. At this time, if the second switching transistor M2 is in the turned-off state, the drive transistor DT may be in an on-bias state.

[0060] Here, by periodically supplying a bias voltage Vobs to the second node N2, the bias state of the drive transistor DT changes periodically, and the threshold voltage characteristics of the drive transistor DT can be altered. Therefore, it is possible to prevent the characteristics of the drive transistor DT from becoming fixed in a specific state and degrading during low-frequency driving.

[0061] A storage capacitor Cst may be connected between the first power supply wiring PL1 and the first node N1. By connecting one electrode of the storage capacitor Cst to the first power supply wiring PL1, a constant high-potential power supply voltage VDD can be continuously supplied to that electrode of the storage capacitor Cst. Therefore, the voltage at the first node N1 can be maintained at the voltage level of the voltage supplied to the first node N1 without being affected by other parasitic capacitors. In other words, the storage capacitor Cst can store the voltage applied to the first node N1.

[0062] On the other hand, the drive transistor DT, the first switching transistor M1, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 may be composed of polysilicon semiconductor transistors, such as PMOS transistors, and the second switching transistor M2 and the third switching transistor M3 may be composed of oxide semiconductor transistors, such as NMOS transistors, but are not limited thereto. For example, the drive transistor DT, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 may be composed of NMOS transistors or PMOS transistors. For example, the drive transistor DT, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 may be composed of polycrystalline silicon semiconductor transistors, oxide semiconductor transistors, amorphous silicon semiconductor transistors, single crystal silicon semiconductor transistors, compound semiconductor transistors, organic semiconductor transistors, etc., but are not limited thereto.

[0063] The first electrode of the light-emitting element ED, for example, the anode electrode, may be connected to a fourth node N4, and the second electrode, for example, the cathode electrode, may be connected to a second power supply wiring PL2 that provides a low potential power supply voltage VSS. The light-emitting element ED can generate light of a predetermined brightness in response to the drive current supplied from the drive transistor DT.

[0064] Figures 4a and 4b are waveform diagrams illustrating an example of pixel driving in Figure 3.

[0065] For example, Figure 4a shows an example of a signal supplied to pixel PX during the first display period DP1, and Figure 4b shows an example of a signal supplied to pixel PX during the second display period DP2.

[0066] Referring to Figures 3, 4a, and 4b, the pixel PX can be driven during a first display period DP1 and a second display period DP2.

[0067] In a variable frequency drive that controls the frame frequency, one frame period may include a first display period DP1. Furthermore, depending on the frame frequency, a second display period DP2 may occur at least once. For example, one frame period may involve the display device 100 being driven during the first display period DP1, followed by the display device 100 being driven during the second display period DP2. However, while the drawings show that a pixel PX may operate for two display periods, it is not limited to this. For example, a pixel PX may operate for three or more distinct display periods, but is not limited to this.

[0068] The first display period DP1 may include a first non-emitting period NEP1 and a first emitting period EP1. The second display period DP2 may include a second non-emitting period NEP2 and a second emitting period EP2. For example, the first non-emitting period NEP1 and the second non-emitting period NEP2 may represent a period during which the path of the drive current flowing from the first power supply wiring PL1 through the light-emitting element ED to the second power supply wiring PL2 is interrupted, and the first emitting period EP1 and the second emitting period EP2 may represent a period during which the path of the drive current is formed and the light-emitting element ED emits light based on the drive current.

[0069] The first display period DP1 may include a period during which data signals Vdata corresponding to the displayed image are written to pixels PX. For example, data signals Vdata may be written during the first non-emitting period NEP1 of the first display period DP1.

[0070] During the second display period DP2, the data signal Vdata is not supplied, and the third scan signal SCAN3 may be supplied to the third scan wiring SL3 to control the drive transistor DT of the pixel PX to an on-bias state and initialize the light-emitting element ED.

[0071] As shown in Figures 4a and 4b, the first non-emission period NEP1 includes the first to sixth drive periods S1 to S6, and the second non-emission period NEP2 may include the seventh drive period S7.

[0072] In one embodiment, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may be supplied only during the first non-emitting period NEP1. On the other hand, the first scan signal SCAN1 may be supplied multiple times during the first non-emitting period NEP1.

[0073] In one embodiment, the third scan signal SCAN3 may be supplied during the first non-emission period NEP1 and the second non-emission period NEP2. Furthermore, as shown in Figures 4a and 4b, the third scan signal SCAN3 may be supplied multiple times during the first non-emission period NEP1 and once during the second non-emission period NEP2. However, the embodiments herein are not limited thereto; for example, the third scan signal SCAN3 may also be supplied multiple times during the second non-emission period NEP2.

[0074] On the other hand, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fourth scan signal SCAN4 are supplied from at least one scan drive unit included in the gate drive unit 120, and the light emission control signal EM may be supplied from at least one light emission drive unit included in the gate drive unit 120.

[0075] The light emission control signal EM can be maintained at a gate-off level, for example, a high level H, during the first non-emission period NEP1 and the second non-emission period NEP2. This keeps the fifth switching transistor M5 and the sixth switching transistor M6 in a turned-off state, respectively, during the first non-emission period NEP1 and the second non-emission period NEP2, thereby interrupting the path of the drive current flowing from the first power supply wiring PL1 through the light-emitting element ED to the second power supply wiring PL2.

[0076] First, to explain the first display period DP1, referring to Figures 3 and 4a, during the first drive period S1, the first scan signal SCAN1 is supplied to the first scan wiring SL1, and the second switching transistor M2 can be turned on. This connects the gate electrode and drain electrode of the drive transistor DT, and a diode connection can be established.

[0077] Thereafter, during the second drive period S2, the first scan signal SCAN1 may be supplied to the first scan wiring SL1, and the third scan signal SCAN3 may be supplied to the third scan wiring SL3. For example, the supply of the first scan signal SCAN1 supplied during the first drive period S1 may be maintained until the second drive period S2. That is, after the second switching transistor M2 is turned on during the first drive period S1 and the second drive period S2, the fourth switching transistor M4 and the seventh switching transistor M7 may be turned on.

[0078] As a result, when the seventh switching transistor M7 is turned on with the gate electrode and drain electrode of the driving transistor DT connected, the bias voltage Vobs can be transmitted from the second node N2 to the first node N1. For example, the voltage difference between the second node N2 and the first node N1 can be reduced to the threshold voltage level of the driving transistor DT. Therefore, the magnitude of the gate-source voltage of the driving transistor DT can be very low during the second driving period S2. For example, the driving transistor DT can be set to an off-bias state. Thus, in order to prevent an unintended increase in brightness due to the supply of the bias voltage Vobs before writing the data signal during the second driving period S2, the supply of the first scan signal SCAN1 and the third scan signal SCAN3 can be controlled so that the seventh switching transistor M7 is turned on while the second switching transistor M2 is turned on.

[0079] Furthermore, a third scan signal SCAN3 supplied during the second drive period S2 can turn on a fourth switching transistor M4. This can supply a second initialization voltage VAR to the first electrode of the light-emitting element ED, for example, at the fourth node N4. This initializes the first electrode of the light-emitting element ED based on the voltage level of the second initialization voltage VAR, and can discharge the parasitic capacitor of the light-emitting element ED. This can improve the black representation capability of the pixel PX.

[0080] Subsequently, during the third drive period S3, the fourth scan signal SCAN4 is supplied to the fourth scan wiring SL4, and the third switching transistor M3 can be turned on. When the third switching transistor M3 is turned on, the first initialization voltage Vini can be supplied to the gate electrode of the drive transistor DT. This allows the gate voltage of the drive transistor DT to be initialized based on the first initialization voltage Vini. Consequently, a strong on-bias is applied to the drive transistor DT, and its hysteresis characteristics may change. For example, the threshold voltage may be shifted.

[0081] On the other hand, the supply of the fourth scan signal SCAN4 can be maintained even after the third drive period S3. For example, as shown in Figure 4a, the fourth scan signal SCAN4 can maintain a gate-on level, for example, a high level H, during the fourth drive period S4 after the third drive period S3.

[0082] Subsequently, during the fourth drive period S4, the first scan signal SCAN1 is supplied to the first scan wiring SL1, and the second switching transistor M2 can be turned on again.

[0083] Thereafter, the second scan signal SCAN2 may be supplied to the second scan wiring SL2 in superimposition with at least a portion of the period during which the first scan signal SCAN1 is supplied in the fifth drive period S5. As a result, the first switching transistor M1 may be turned on by the second scan signal SCAN2, and the data signal Vdata may be provided to the second node N2.

[0084] Here, the drive transistor DT is connected in diode form by the turned-on second switching transistor M2, so that both data signal writing and threshold voltage compensation can be performed. On the other hand, the first scan signal SCAN1 is supplied before the supply of the second scan signal SCAN2 and after the supply of the second scan signal SCAN2 is interrupted, so that the threshold voltage of the drive transistor DT can be compensated for a sufficient amount of time.

[0085] Subsequently, during the sixth drive period S6, the third scan signal SCAN3 is again supplied to the third scan wiring SL3, and the fourth switching transistor M4 and the seventh switching transistor M7 may be turned on. Turning on the seventh switching transistor M7 may supply a bias voltage Vobs to the first node N1.

[0086] On the other hand, the effect of the strong on-bias applied during the third drive period S3 can be eliminated by writing the data signal Vdata and performing threshold voltage compensation. For example, threshold voltage compensation during the supply interval of the first scan signal SCAN1, including the fourth drive period S4 and the fifth drive period S5, can significantly reduce the voltage difference between the gate voltage and source voltage of the drive transistor DT. This then changes the characteristics of the drive transistor DT, and an increase in the drive current during the first light emission period EP1 or a lifting of the black gradation may be observed.

[0087] To prevent such characteristic changes, the seventh switching transistor M7 can be turned on during the sixth drive period S6 by supplying the third scan signal SCAN3. Accordingly, the drive transistor DT can be set to an on-bias state during the sixth drive period S6 by supplying a bias voltage Vobs to the first electrode of the drive transistor DT, for example, the source electrode.

[0088] Furthermore, a second initialization voltage VAR can be supplied to the first electrode of the light-emitting element ED by the fourth switching transistor M4, which is turned on during the sixth drive period S6. This allows the first electrode of the light-emitting element ED to be initialized based on the voltage level of the second initialization voltage VAR.

[0089] After the sixth drive period S6, the supply of the light emission control signal EM to the light emission control wiring EL is interrupted, for example, the light emission control signal EM transitions to a low level L, ending the first non-light emission period NEP1 and allowing the first light emission period EP1 to proceed. In this case, the fifth switching transistor M5 and the sixth switching transistor M6 may be turned on.

[0090] During the first light emission period EP1, a drive current corresponding to the data signal Vdata written in the fifth drive period S5 is supplied to the light-emitting element ED, and the light-emitting element ED can emit light based on the drive current.

[0091] Next, referring to Figures 3 and 4b to describe the second display period DP2, the second display period DP2 may include a second non-emitting period NEP2 and a second emitting period EP2, and the second non-emitting period NEP2 may include a seventh drive period S7.

[0092] In one embodiment, the waveform of the light emission control signal EM during the second display period DP2 may be substantially the same as the waveform of the light emission control signal EM during the first display period DP1.

[0093] In one embodiment, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may not be supplied during the second display period DP2. For example, during the second display period DP2, the first scan signal SCAN1 and the fourth scan signal SCAN4 may be maintained at a gate-off level, e.g., a low level L, and the second scan signal SCAN2 may be maintained at a gate-off level, e.g., a high level H. This allows the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 to be maintained in a turn-off state during the second display period DP2.

[0094] During the second non-emitting period NEP2, the third scan signal SCAN3 is supplied during the seventh driving period S7, which can turn on the fourth switching transistor M4 and the seventh switching transistor M7. As a result, the turned-on fourth switching transistor M4 supplies the second initialization voltage VAR to the first electrode of the light-emitting element ED, thereby initializing the first electrode of the light-emitting element ED based on the second initialization voltage VAR, and the turned-on seventh switching transistor M7 can supply the bias voltage Vobs to the source electrode of the driving transistor DT, for example, the first node N1.

[0095] After the seventh drive period S7, the supply of the light emission control signal EM to the light emission control wiring EL is interrupted, for example, the light emission control signal EM transitions to a low level L, ending the second non-light emission period NEP2 and allowing the second light emission period EP2 to proceed. In this case, the fifth switching transistor M5 and the sixth switching transistor M6 may be turned on.

[0096] During the second light emission period EP2, a drive current corresponding to the data signal Vdata written during the first display period DP1 is supplied to the light-emitting element ED, and the light-emitting element ED can emit light based on the drive current.

[0097] On the other hand, while Figure 4b describes the case where the third scan signal SCAN3 is supplied to the third scan wiring SL3 once, the embodiments of this specification are not limited thereto, and for example, the third scan signal SCAN3 may be supplied multiple times during the second non-emitting period NEP2.

[0098] Figure 5 is a block diagram showing a gate drive unit according to one embodiment of this specification.

[0099] On the other hand, Figure 5 shows both the gate drive unit 120, the display panel 140 (as described with reference to Figure 1), and the pixels PX arranged on the display panel 140.

[0100] Referring to Figures 1 to 5, the gate drive unit 120 can include a first scan drive unit SDV1, a second scan drive unit SDV2, a third scan drive unit SDV3, a fourth scan drive unit SDV4, and a light emission drive unit EDV.

[0101] The gate control signal GCS provided from the timing control unit 110 to the gate drive unit 120 may include a first scan start signal SVST1, a second scan start signal SVST2, a third scan start signal SVST3, a fourth scan start signal SVST4, and an illumination start signal EVST. The first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the illumination start signal EVST may be supplied to the first scan drive unit SDV1, the second scan drive unit SDV2, the third scan drive unit SDV3, the fourth scan drive unit SDV4, and the illumination drive unit EDV, respectively.

[0102] The width, supply timing, etc., of the first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the light emission start signal EVST may be determined by the pixel PX driving conditions and the frame frequency. For example, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the light emission control signal EM may be output based on the first scan start signal SVST1, the second scan start signal SVST2, the third scan start signal SVST3, the fourth scan start signal SVST4, and the light emission start signal EVST, respectively.

[0103] The first scan drive unit SDV1 can sequentially supply the first scan signal SCAN1 to a plurality of first scan lines S11 to S1n in response to the first scan start signal SVST1 (where n is an integer greater than 0). For example, the first scan drive unit SDV1 may include a plurality of scan stages (e.g., shown as "SST11 to SST1n" in Figure 5) that sequentially output the first scan signal SCAN1 to a plurality of first scan lines S11 to S1n on a pixel row basis. For example, the first scan signal SCAN1 may be output sequentially to a plurality of first scan lines SL11 to SL1n on a pixel row basis. For example, the first scan signal SCAN1 may be output to a plurality of first scan lines SL11 to SL1n in an order other than sequential, but is not limited to this.

[0104] The second scan drive unit SDV2 can sequentially supply the second scan signal SCAN2 to a plurality of second scan lines S21 to S2n in response to the second scan start signal SVST2. For example, the second scan drive unit SDV2 may include a plurality of scan stages (e.g., shown as "SST21 to SST2n" in Figure 5) that sequentially output the second scan signal SCAN2 to a plurality of second scan lines S21 to S2n on a pixel row basis.

[0105] The third scan drive unit SDV3 can sequentially supply the third scan signal SCAN3 to a plurality of third scan lines S31 to S3n in response to the third scan start signal SVST3. For example, the third scan drive unit SDV3 may include a plurality of scan stages (e.g., shown as "SST31 to SST3n" in Figure 5) that sequentially output the third scan signal SCAN3 to a plurality of third scan lines S31 to S3n on a pixel row basis.

[0106] The fourth scan drive unit SDV4 can sequentially supply the fourth scan signal SCAN4 to a plurality of fourth scan lines S41 to S4n in response to the fourth scan start signal SVST4. For example, the fourth scan drive unit SDV4 may include a plurality of scan stages (e.g., shown as "SST41 to SST4n" in Figure 5) that sequentially output the fourth scan signal SCAN4 to a plurality of fourth scan lines S41 to S4n on a pixel row basis.

[0107] The light-emitting drive unit EDV can sequentially supply light-emitting control signals EM to multiple light-emitting control wires EL1 to ELn in response to the light-emitting start signal EVST. For example, the light-emitting drive unit EDV may include multiple light-emitting stages EST1 to ESTn that sequentially output light-emitting control signals EM to multiple light-emitting control wires EL1 to ELn on a pixel row basis.

[0108] On the other hand, as described above, the display device 100 according to one embodiment of this specification can display images at various drive frequencies depending on the driving conditions. For example, the display device 100 can control the drive frequency of the display panel 140 by adjusting the number of times the second display period DP2, as described with reference to Figures 3 to 4b. For example, in the second display period DP2, the third scan drive unit SDV3 can sequentially supply the third scan signal SCAN3 to a plurality of third scan wirings S31 to S3n, and the light emission drive unit EDV can sequentially supply the light emission control signal EM to a plurality of light emission control wirings EL1 to ELn. On the other hand, in the second display period DP2, the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 may not supply the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4, respectively. That is, in the second display period DP2, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 may each be maintained at the gate-off level.

[0109] Furthermore, as explained with reference to Figures 1 to 2b, in one embodiment, the display device 100 can independently drive the drive frequencies of multiple sub-display areas included in the display area AA. For example, in the display panel 140 of Figure 2b, if the first sub-display area AA1 and the third sub-display area AA3 are driven at a low frequency and the second sub-display area AA2 is driven at a high frequency, the number of times the pixels PX located in the first sub-display area AA1 and the pixels PX located in the third sub-display area AA3 are driven during the second display period DP2 during one frame period may be greater than the number of times the pixels PX located in the second sub-display area AA2 are driven during the second display period DP2. In other words, in the display panel 140 of Figure 2b, if the first sub-display area AA1 and the third sub-display area AA3 are driven at a low frequency and the second sub-display area AA2 is driven at a high frequency, the display device 100 can increase the number of times the pixel PX is driven in the second display period DP2 in the first sub-display area AA1 and the third sub-display area AA3, thereby enabling them to be driven at a low frequency.

[0110] On the other hand, in the case of a typical conventional gate drive unit, it is implemented using a shift register method, in which the current stage outputs a gate signal in response to a carry signal output from a previous stage. In order to control the drive frequency of pixels arranged on the display panel, a conventional display device can either provide the gate drive unit with a start signal for generating the corresponding scan signals at a gate-off level to maintain the signal levels of the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 at a gate-off level during the second display period DP2 described above, or it can control the gate drive unit so that the carry signal is output at a gate-off level.

[0111] However, as mentioned above, when the first sub-display area AA1 and the third sub-display area AA3 of the display panel 140 are driven at a low frequency, and the second sub-display area AA2 is driven at a high frequency, in the case of a conventional gate drive unit implemented using a general shift register method, the carry signal output from the stage for providing the gate signal (scan signal) to the pixels located in the first sub-display area AA1 is output at the gate-off level. Therefore, the gate signal (scan signal) provided to the pixels located in the second sub-display area AA2 is inevitably maintained at the gate-off level. Thus, conventional gate drive units and display devices including them have limitations in controlling the drive frequency by dividing the display area into separate areas.

[0112] Therefore, the gate drive unit 120 according to one embodiment of this specification may further include an output control unit SCTR for controlling the signal levels of gate signals output from at least one scan drive unit, for example, the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 output from the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4.

[0113] In one embodiment, the output control unit SCTR can control the output of gate signals (scan signals) output from the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4, respectively, using a variable frequency drive that controls the frame frequency. For example, the output control unit SCTR can be connected in common to the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4, and can control the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4. For example, the output control unit SCTR can be individually connected to one or more of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4. For example, the output control unit SCTR can be further connected to the light emission drive unit EDV or the third scan drive unit SDV3, but is not limited to this.

[0114] For example, the output control unit SCTR can control the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 to have gate-on level pulses when the pixel PX is driven during the first display period DP1, and can control the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 to be maintained at the gate-off level when the pixel PX is driven during the second display period DP2.

[0115] As a result, the gate drive unit 120 and the display device 100 including it according to one embodiment of this specification can divide the display area AA into areas and control the drive frequency.

[0116] Furthermore, in the case of the gate drive unit 120 and the display device 100 including it according to one embodiment of this specification, there is no separate control unit for controlling the signal levels of the gate signals (scan signals) output from the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4. Instead, the signal levels of the gate signals (scan signals) are controlled using the output control unit SCTR, which is connected in common to the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4. As a result, the size of the bezel area in which the gate drive unit 120 is located can be minimized.

[0117] For a more detailed explanation of the output control unit SCTR, please refer to Figures 6a to 23 below.

[0118] Figures 6a and 6b are block diagrams showing an example of the gate drive unit in Figure 5.

[0119] On the other hand, Figures 6a and 6b show only the light-emitting drive unit EDV and the output control unit SCTR1, in relation to the various configurations included in the gate drive units 620 and 620_1.

[0120] On the other hand, for the sake of explanation, Figures 6a and 6b show, respectively, 32 stages EST1 to EST32 from among the multiple light-emitting stages included in the light-emitting drive unit EDV and multiple light-emitting control signals EM1 to EM32 output from them, and 4 stages STG1 to STG4 from among the multiple stages included in the output control unit SCTR1 and multiple pull-up control signals PUS1 to PUS4 and multiple pull-down control signals PDS1 to PDS4 output from them.

[0121] Referring to Figure 6a, the gate drive unit 620 according to one embodiment of this specification may include a light-emitting drive unit EDV and an output control unit SCTR1.

[0122] The light-emitting drive unit EDV may include multiple light-emitting stages EST1 to EST32. Each of the multiple light-emitting stages EST1 to EST32 is connected to a corresponding light-emitting control signal and can output light-emitting control signals EM1 to EM32 based on a first light-emitting clock signal ECLK1 and a second light-emitting clock signal ECLK2.

[0123] In one embodiment, multiple light-emitting stages EST1 to EST32 included in the light-emitting drive unit EDV are cascaded, and the multiple light-emitting stages EST1 to EST32 may have substantially the same configuration.

[0124] Each of the multiple light-emitting stages EST1 to EST32 can receive a light-emitting start signal EVST or a carry signal from a previous light-emitting stage, for example, a light-emitting control signal EM1 to EM32 from a previous light-emitting stage.

[0125] Each of the multiple light-emitting stages EST1 to EST32 can receive either the first light-emitting clock signal ECLK1 or the second light-emitting clock signal ECLK2. For example, even-numbered light-emitting stages can receive the first light-emitting clock signal ECLK1, and odd-numbered light-emitting stages can receive the second light-emitting clock signal ECLK2, but this is not limited to this configuration.

[0126] The first light-emitting clock signal ECLK1 and the second light-emitting clock signal ECLK2 may have waveforms with the same period and no phase superimposition. For example, the second light-emitting clock signal ECLK2 may be set to a signal shifted by approximately 1 / 2 period from the first light-emitting clock signal ECLK1.

[0127] Light emission control signals EM1 to EM32 are output through the output terminals of each of the multiple light emission stages EST1 to EST32 and can be provided to the next light emission stage. In addition, at least some of the multiple light emission control signals EM1 to EM32 output from the multiple light emission stages EST1 to EST32 can be provided to the output control unit SCTR1. A more detailed explanation of this will be given later in relation to the output control unit SCTR1.

[0128] The output control unit SCTR1 may include multiple stages STG1 to STG4. The multiple stages STG1 to STG4 can output multiple pull-up control signals PUS1 to PUS4 and multiple pull-down control signals PDS1 to PDS4 based on multiple clock signals CLK1 and CLK2 and multiple control clock signals CCLK1, CCLK2, CCLK3, and CCLK4.

[0129] In one embodiment, the multiple stages STG1 to STG4 included in the output control unit SCTR1 can be cascaded.

[0130] For example, Stage 2 STG2 may be cascaded to Stage 1 STG1, Stage 3 STG3 may be cascaded to Stage 2 STG2, and Stage 4 STG4 may be cascaded to Stage 3 STG3. Here, multiple stages STG1 to STG4 may have substantially the same configuration.

[0131] In one embodiment, the multiple stages STG1 to STG4 included in the output control unit SCTR1 are not formed in units of horizontal lines, for example, pixel rows, but can be formed in units of at least two or more horizontal lines. For example, as shown in Figure 6a, the multiple stages STG1 to STG4 can be formed in units of eight horizontal lines. As a result, in the embodiment of Figure 6a, each of the multiple stages STG1 to STG4 included in the output control unit SCTR1 can commonly control eight scan stages formed in units of eight horizontal lines from among the multiple scan stages included in the scan drive unit. This will be explained in more detail with reference to Figures 10 to 14.

[0132] Each of the multiple stages STG1 to STG4 may include a carry unit for outputting a carry signal and an output unit for outputting pull-up control signals and pull-down control signals. For example, the first stage STG1 includes a first carry unit CRY1 for generating a first carry signal CR1 and a first output unit OUT1 for generating a first pull-up control signal PUS1 and a first pull-down control signal PDS1; the second stage STG2 includes a second carry unit CRY2 for generating a second carry signal CR2 and a second output unit OUT2 for generating a second pull-up control signal PUS2 and a second pull-down control signal PDS2; the third stage STG3 includes a third carry unit CRY3 for generating a third carry signal CR3 and a third output unit OUT3 for generating a third pull-up control signal PUS3 and a third pull-down control signal PDS3; and the fourth stage STG4 includes a fourth carry unit CRY4 for generating a fourth carry signal CR4 and a fourth output unit OUT4 for generating a fourth pull-up control signal PUS4 and a fourth pull-down control signal PDS4.

[0133] Each of the multiple carry units CRY1 to CRY4 included in the multiple stages STG1 to STG4 can receive a light emission control signal from the light emission drive unit EDV.

[0134] In one embodiment, the kth stage (where k is an integer greater than 0) can receive light emission control signals output from the 8th-7th light emission stages. For example, the first carry unit CRY1 included in the first stage STG1 can receive the first light emission control signal EM1 output from the first light emission stage EST1, the second carry unit CRY2 included in the second stage STG2 can receive the ninth light emission control signal EM9 output from the ninth light emission stage EST9, the third carry unit CRY3 included in the third stage STG3 can receive the seventeenth light emission control signal EM17 output from the seventeenth light emission stage EST17, and the fourth carry unit CRY4 included in the fourth stage STG4 can receive the twenty-fifth light emission control signal EM25 output from the twenty-fifth light emission stage EST25. In this way, since each of the multiple stages STG1 to STG4 controls eight scan stages formed in units of eight horizontal lines, the multiple carry units CRY1 to CRY4 included in each of the multiple stages STG1 to STG4 can receive a light emission control signal from one of the eight light emission stages formed in units of eight horizontal lines. For example, the multiple carry units CRY1 to CRY4 included in each of the multiple stages STG1 to STG4 can receive a light emission control signal from any one of the eight light emission stages formed in units of eight horizontal lines, except for the 8k-7th light emission stage. For example, the kth stage can receive a light emission control signal output from any one of the light emission stages from the 8k-7th to the 8kth stage, but is not limited to this.

[0135] Furthermore, each of the multiple carry units CRY1 to CRY4 may be provided with one of multiple clock signals, for example, either a first clock signal CLK1 or a second clock signal CLK2.

[0136] In one embodiment, the carry units included in odd-numbered stages can receive the first clock signal CLK1, and the carry units included in even-numbered stages can receive the second clock signal CLK2. For example, the first carry unit CRY1 and the third carry unit CRY3 can each receive the first clock signal CLK1, and the second carry unit CRY2 and the fourth carry unit CRY4 can each receive the second clock signal CLK2.

[0137] The first clock signal CLK1 and the second clock signal CLK2 may have waveforms with the same period but no phase superimposition. For example, the second clock signal CLK2 may be set to a signal shifted by approximately half a period from the first clock signal CLK1.

[0138] Each of the multiple carry units CRY1 to CRY4 can output carry signals CR1 to CR4 through its output terminal. Furthermore, each of the multiple carry signals CR1 to CR4 output from the multiple carry units CRY1 to CRY4 contained within each of the multiple stages STG1 to STG4 can be provided to the output units OUT1 to OUT4 of the corresponding stage.

[0139] For example, the first carry signal CR1 output from the first carry unit CRY1 of the first stage STG1 is provided to the first output unit OUT1, the second carry signal CR2 output from the second carry unit CRY2 of the second stage STG2 is provided to the second output unit OUT2, the third carry signal CR3 output from the third carry unit CRY3 of the third stage STG3 is provided to the third output unit OUT3, and the fourth carry signal CR4 output from the fourth carry unit CRY4 of the fourth stage STG4 is provided to the fourth output unit OUT4.

[0140] Furthermore, each of the multiple output units OUT1 to OUT4 can receive one of several control clock signals, for example, a first control clock signal CCLK1, a second control clock signal CCLK2, a third control clock signal CCLK3, and a fourth control clock signal CCLK4.

[0141] In one embodiment, the output unit included in the i-th stage (where i is an integer greater than 0) can receive the first control clock signal CCLK1, the output unit included in the i+1-th stage can receive the second control clock signal CCLK2, the output unit included in the i+2-th stage can receive the third control clock signal CCLK3, and the output unit included in the i+3-th stage can receive the fourth control clock signal CCLK4.

[0142] For example, the first output unit OUT1 can receive the first control clock signal CCLK1, the second output unit OUT2 can receive the second control clock signal CCLK2, the third output unit OUT3 can receive the third control clock signal CCLK3, and the fourth output unit OUT4 can receive the fourth control clock signal CCLK4.

[0143] The first control clock signal CCLK1 and the second control clock signal CCLK2 may have waveforms with the same period and no phase superimposition. For example, the second control clock signal CCLK2 may be set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1.

[0144] Furthermore, the third control clock signal CCLK3 and the fourth control clock signal CCLK4 may have the same period and waveforms whose phases do not overlap with each other. For example, the fourth control clock signal CCLK4 may be set to a signal that is shifted by approximately 1 / 2 period from the third control clock signal CCLK3.

[0145] In one embodiment, the signal level of at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled by the drive mode. For example, the signal levels of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled independently.

[0146] For example, as mentioned above, when a pixel PX is driven during the first display period DP1, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may all be at a gate-on level, e.g., a low level, during that period. In this case, the multiple pull-up control signals PUS1 to PUS4 output from the multiple output units OUT1 to OUT4 may be at a gate-on level, e.g., a low level, and the multiple pull-down control signals PDS1 to PDS4 output from the multiple output units OUT1 to OUT4 may be at a gate-off level, e.g., a high level. As a result, during the first display period DP1, the scan drive unit connected to the output control unit SCTR1 can output a gate signal (scan signal) having a gate-on level pulse.

[0147] In contrast, as mentioned above, when the pixel PX is driven during the second display period DP2, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can toggle between a gate-off level and a gate-on level, for example, a high level and a low level, during that period. In this case, due to the operation of the multiple output units OUT1 to OUT4, the pull-up control signals PUS1 to PUS4 may have a gate-off level, for example, a high-level pulse, for at least a portion of the section, and the pull-down control signals PDS1 to PDS4 may have a gate-on level, for example, a low-level pulse, for at least the same portion of the section. As a result, during the second display period DP2, the gate signal (scan signal) output from the scan drive unit connected to the output control unit SCTR1 may have a gate-off level. A more detailed explanation of this will be given later with reference to Figures 7 to 14.

[0148] In one embodiment, unless the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 are maintained at a gate-on level, for example, a low level, corresponding to the first display period DP1 of the pixel PX as described above, the first control clock signal CCLK1 and the third control clock signal CCLK3 may have the same waveform, and the second control clock signal CCLK2 and the fourth control clock signal CCLK4 may have the same waveform.

[0149] Multiple output units OUT1 to OUT4 included in multiple stages STG1 to STG4 can output pull-up control signals PUS1 to PUS4 and pull-down control signals PDS1 to PDS4, respectively.

[0150] On the other hand, although not shown separately in Figure 6a, each of the multiple stages STG1 to STG4 includes multiple power input terminals, and the power supply voltage required to drive the multiple stages STG1 to STG4 can be applied through these multiple power input terminals.

[0151] For example, each of the multiple stages STG1 to STG4 can receive the voltage of a first power supply (e.g., the first power supply VGH in Figure 7) and the voltage of a second power supply (e.g., the second power supply VGL in Figure 7). The voltages of the first and second power supplies may have DC voltage levels. Here, the voltage level of the first power supply may be set higher than the voltage level of the second power supply.

[0152] On the other hand, the above description has been based on the premise that each of the multiple carry units CRY1 to CRY4 included in the multiple stages STG1 to STG4 receives a light emission control signal from the light emission drive unit EDV, but the embodiments described herein are not limited thereto.

[0153] For example, referring to Figure 6b, at least some of the multiple carry units CRY1 to CRY4 included in each of the multiple stages STG1 to STG4 of the output control unit SCTR1 included in the gate drive unit 620_1 can receive the light emission start signal EVST, and the remaining portion can receive the light emission control signal from the light emission drive unit EDV.

[0154] For example, among the multiple stages STG1 to STG4 included in the output control unit SCTR1, the first carry unit CRY1 included in the first stage STG1 receives the light emission start signal EVST, and for the remaining stages excluding the first stage STG1, the lth stage (where l is an integer greater than 1) can receive the light emission control signal output from the eighth (l-1) light emission stage. As an example, the second carry unit CRY2 included in the second stage STG2 receives the eighth light emission control signal EM8 output from the eighth light emission stage EST8, the third carry unit CRY3 included in the third stage STG3 receives the sixteenth light emission control signal EM16 output from the sixteenth light emission stage EST16, and the fourth carry unit CRY4 included in the fourth stage STG4 can receive the twenty-fourth light emission control signal EM24 output from the twenty-fourth light emission stage EST24.

[0155] Here, the first light emission control signal EM1 output from the first light emission stage EST1 has the same pulse width as the light emission start signal EVST and has a waveform shifted by one horizontal period. Therefore, as shown in Figure 6b, when the first carry unit CRY1 included in the first stage STG1 receives the light emission start signal EVST, the remaining stages excluding the first stage STG1 can receive the light emission control signal output from the 8th (l-1) light emission stage.

[0156] Here, in the case of the gate drive unit 620_1 in Figure 6b, the gate drive unit 620_1 in Figure 6b can operate substantially identically or similarly to the gate drive unit 620 in Figure 6a, except that the multiple carry signals CR1~CR4 output from each of the multiple carry units CRY1~CRY4, the multiple pull-up control signals PUS1~PUS4 and the multiple pull-down control signals PDS1~PDS4 output from each of the multiple stages STG1~STG4 are shifted by one horizontal period due to the connection relationship of the multiple carry units CRY1~CRY4. Therefore, we will not repeat redundant explanations.

[0157] Referring to Figure 6a, in one embodiment, the multiple stages STG1 to STG4 included in the output control unit SCTR1 may have substantially the same configuration except for the input signal. For example, the multiple stages STG1 to STG4 may have substantially the same circuit configuration and operate substantially identically.

[0158] Accordingly, for the sake of convenience in the following explanation, when describing the multiple stages STG1 to STG4 included in the output control unit SCTR1, the configuration and driving method of the multiple stages STG1 to STG4 included in the output control unit SCTR1 will be described based on the first stage STG1.

[0159] On the other hand, the transistors constituting each stage can be embodied in n-type or p-type MOSFET transistors. In the following examples, p-type transistors are used as examples, but the examples herein are not limited thereto.

[0160] Figure 7 is a circuit diagram showing an example of the first stage included in the output control unit of the gate drive unit in Figure 6a.

[0161] Referring to Figures 6a and 7, the first stage STG1 may include a first carry unit CRY1 that outputs a first carry signal CR1, and a first output unit OUT1 that outputs a first pull-up control signal PUS1 and a first pull-down control signal PDS1. More specifically, the first output unit OUT1 may output a first pull-up control signal PUS1 having a gate-on level and a first pull-down control signal PDS1 having a gate-off level, depending on the drive mode, or it may output a first pull-up control signal PUS1 having a gate-off level pulse and a first pull-down control signal PDS1 having a gate-on level pulse for at least a portion of the section.

[0162] The first carry unit CRY1 receives the first light emission control signal EM1 as an input signal through the first input terminal 721, receives the first clock signal CLK1 through the second input terminal 722, is connected to the first power supply VGH through the first power supply input terminal 728, and can be connected to the second power supply VGL through the second power supply input terminal 729. Based on the first light emission control signal EM1, the first clock signal CLK1, the first power supply VGH, and the second power supply VGL, the first carry unit CRY1 can generate and output the first carry signal CR1 through the first output terminal 723.

[0163] On the other hand, as explained with reference to Figure 6b, in this embodiment, the first carry unit CRY1 can also receive the light emission start signal EVST as an input signal through the first input terminal 721.

[0164] The first output unit OUT1 receives a first carry signal CR1 through a third input terminal 724, for example, a third input terminal 724 connected to the first output terminal 723 of the first carry unit CRY1, receives a first control clock signal CCLK1 through a fourth input terminal 725, is connected to a first power supply VGH through a first power supply input terminal 728, and is connected to a second power supply VGL through a second power supply input terminal 729. Based on the first carry signal CR1, the first control clock signal CCLK1, the first power supply VGH, and the second power supply VGL, the first output unit OUT1 can generate and output a first pull-up control signal PUS1 through a second output terminal 726, and a first pull-down control signal PDS1 through a third output terminal 727.

[0165] More specifically, the first carry portion CRY1 of the first stage STG1 may include first to sixth transistors T1 to T6, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Depending on the embodiment, the first carry portion CRY1 may further include a first bridge voltage transistor Tbv1.

[0166] The first transistor T1 is connected between the first input terminal 721 and the first control node CN1 and may include a gate electrode connected to the second input terminal 722. The first transistor T1 can be turned on when the first clock signal CLK1 supplied through the second input terminal 722 has a gate-on level, for example, a low level, thereby electrically coupling the first input terminal 721 and the first control node CN1. When the first transistor T1 is turned on, the first light emission control signal EM1 supplied through the first input terminal 721 may be supplied to the first control node CN1.

[0167] In one embodiment, the first transistor T1 may include first and second subtransistors T1a and T1b connected in series with each other. Each of the first and second subtransistors T1a and T1b may include a gate electrode commonly connected to the second input terminal 722. For example, the first transistor T1 may have a dual-gate structure. This can minimize current leakage from the first transistor T1.

[0168] The second transistor T2 is connected between the first power input terminal 728 and the second control node CN2 and may include a gate electrode connected to the first input terminal 721. The second transistor T2 can be turned on when the first light emission control signal EM1 supplied through the first input terminal 721 has a gate-on level, e.g., a low level, and can supply the second control node CN2 with a gate-off level, e.g., a high level voltage of the first power supply VGH provided from the first power input terminal 728.

[0169] In one embodiment, the second transistor T2 may include third and fourth subtransistors T2a and T2b connected in series with each other. Each of the third and fourth subtransistors T2a and T2b may include a gate electrode commonly connected to the first input terminal 721. For example, the second transistor T2 may have a dual-gate structure. This may minimize current leakage from the second transistor T2.

[0170] The third transistor T3 is connected between the second input terminal 722 and the first QB node QB1 and may include a gate electrode connected to the second control node CN2. The third transistor T3 can be turned on or turned off based on the voltage of the second control node CN2. When the third transistor T3 is turned on, the second input terminal 722 and the first QB node QB1 are electrically connected, and the first clock signal CLK1 provided to the second input terminal 722 may be provided to the first QB node QB1.

[0171] In one embodiment, the third transistor T3 may include fifth and sixth subtransistors T3a and T3b connected in series with each other. Each of the fifth and sixth subtransistors T3a and T3b may include a gate electrode commonly connected to the second control node CN2. For example, the third transistor T3 may have a dual-gate structure. This can minimize current leakage from the third transistor T3.

[0172] The fourth transistor T4 is connected between the first power input terminal 728 and the first QB node QB1 and may include a gate electrode connected to the first control node CN1. The fourth transistor T4 can be turned on or turned off based on the voltage of the first control node CN1. When the fourth transistor T4 is turned on, the voltage of the first power supply VGH provided through the first power input terminal 728 can be supplied to the first QB node QB1.

[0173] In one embodiment, the fourth transistor T4 may include seventh and eighth subtransistors T4a and T4b connected in series with each other. Each of the seventh and eighth subtransistors T4a and T4b may include a gate electrode commonly connected to the first control node CN1. For example, the fourth transistor T4 may have a dual-gate structure. This can minimize current leakage from the fourth transistor T4.

[0174] The fifth transistor T5 is connected between the second power input terminal 729 and the first output terminal 723 and may include a gate electrode connected to the first Q node Q1. For example, the gate electrode of the fifth transistor T5 connected to the first Q node Q1 may be connected to the first control node CN1 via the first bridge voltage transistor Tbv1. The fifth transistor T5 can be turned on or turned off by the voltage of the first Q node Q1.

[0175] Here, the first bridge voltage transistor Tbv1 is connected between the first control node CN1 and the first Q node Q1 and may include a gate electrode connected to the second power input terminal 729. Since the gate electrode of the first bridge voltage transistor Tbv1 is connected to the second power input terminal 729, which is supplied with the voltage of the second power supply VGL having a gate-on level, e.g., a low level, the first bridge voltage transistor Tbv1 can always remain turned on. This allows the voltage at the first control node CN1 and the voltage at the first Q node Q1 to have substantially the same value. Thus, the fifth transistor T5 can be turned on or turned off by the voltage at the first control node CN1.

[0176] For example, the fifth transistor T5 can be turned on when the voltage at the first Q node Q1 or the voltage at the first control node CN1 is at the gate-on level, for example, a low level, thereby electrically connecting the second power input terminal 729 and the first output terminal 723. As a result, the first carry signal CR1 output through the first output terminal 723 during the period when the fifth transistor T5 is turned on may have the gate-on level, for example, a low level.

[0177] The sixth transistor T6 is connected between the first power input terminal 728 and the first output terminal 723 and may include a gate electrode connected to the first QB node QB1. The sixth transistor T6 can be turned on or turned off by the voltage at the first QB node QB1.

[0178] For example, the sixth transistor T6 can be turned on when the voltage at the first QB node QB1 is at the gate-on level, e.g., a low level, thereby electrically connecting the first power input terminal 728 and the first output terminal 723. This allows the first carry signal CR1 output through the first output terminal 723 during the period when the sixth transistor T6 is turned on to be at the gate-off level, e.g., a high level.

[0179] Thus, the fifth transistor T5 of the first carry unit CRY1 can perform the pull-up function, and the sixth transistor T6 of the first carry unit CRY1 can perform the pull-down function.

[0180] A first capacitor C1 (or first boosting capacitor) may be connected between the second input terminal 722 and the second control node CN2. For example, the first capacitor C1 may include a first electrode connected to the second input terminal 722 and a second electrode connected to the second control node CN2.

[0181] The second capacitor C2 may be connected between the first Q node Q1 and the first output terminal 723. For example, the second capacitor C2 may include a first electrode connected to the first Q node Q1 and a second electrode connected to the first output terminal 723.

[0182] The third capacitor C3 may be connected between the first QB node QB1 and the first output terminal 723. For example, the third capacitor C3 may include a first electrode connected to the first QB node QB1 and a second electrode connected to the first output terminal 723.

[0183] Next, the first output section OUT1 of the first stage STG1 may have a similar circuit structure to the first carry section CRY1, differing only in the input and output signals. For example, the first output section OUT1 may include the seventh to twelfth transistors T7 to T12, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6. In some embodiments, the first output section OUT1 may further include the second bridge voltage transistor Tbv2.

[0184] The seventh transistor T7 is connected between the third input terminal 724 and the third control node CN3 and may include a gate electrode connected to the fourth input terminal 725. The seventh transistor T7 can be turned on when the first control clock signal CCLK1 supplied through the fourth input terminal 725 has a gate-on level, for example, a low level, thereby electrically coupling the third input terminal 724 and the third control node CN3. When the seventh transistor T7 is turned on, the first carry signal CR1 supplied through the third input terminal 724 may be supplied to the third control node CN3.

[0185] In one embodiment, the seventh transistor T7 may include ninth and tenth subtransistors T7a and T7b connected in series with each other. Each of the ninth and tenth subtransistors T7a and T7b may include a gate electrode commonly connected to the fourth input terminal 725. For example, the seventh transistor T7 may have a dual-gate structure. This can minimize current leakage from the seventh transistor T7.

[0186] The eighth transistor T8 is connected between the first power input terminal 728 and the fourth control node CN4 and may include a gate electrode connected to the third input terminal 724. The eighth transistor T8 can be turned on when the first carry signal CR1 supplied through the third input terminal 724 has a gate-on level, e.g., a low level, and can provide the fourth control node CN4 with a gate-off level, e.g., a high level first power supply voltage VGH provided from the first power input terminal 728.

[0187] In one embodiment, the eighth transistor T8 may include eleventh and twelfth subtransistors T8a and T8b connected in series with each other. Each of the eleventh and twelfth subtransistors T8a and T8b may include a gate electrode commonly connected to the third input terminal 724. For example, the eighth transistor T8 may have a dual-gate structure. This may minimize current leakage from the eighth transistor T8.

[0188] The ninth transistor T9 is connected between the fourth input terminal 725 and the second QB node QB2 and may include a gate electrode connected to the fourth control node CN4. The ninth transistor T9 can be turned on or turned off based on the voltage at the fourth control node CN4. When the ninth transistor T9 is turned on, the fourth input terminal 725 and the second QB node QB2 are electrically connected, and a first control clock signal CCLK1 provided to the fourth input terminal 725 may be provided to the second QB node QB2.

[0189] In one embodiment, the ninth transistor T9 may include thirteenth and fourteenth subtransistors T9a and T9b connected in series with each other. Each of the thirteenth and fourteenth subtransistors T9a and T9b may include a gate electrode commonly connected to the fourth control node CN4. For example, the ninth transistor T9 may have a dual-gate structure. This can minimize current leakage from the ninth transistor T9.

[0190] The tenth transistor T10 is connected between the first power input terminal 728 and the second QB node QB2 and may include a gate electrode connected to the third control node CN3. The tenth transistor T10 can be turned on or turned off based on the voltage of the third control node CN3. When the tenth transistor T10 is turned on, the voltage of the first power supply VGH provided through the first power input terminal 728 can be supplied to the second QB node QB2.

[0191] In one embodiment, the tenth transistor T10 may include the fifteenth and sixteenth subtransistors T10a and T10b connected in series with each other. Each of the fifteenth and sixteenth subtransistors T10a and T10b may include a gate electrode commonly connected to the third control node CN3. For example, the tenth transistor T10 may have a dual-gate structure. This may minimize current leakage from the tenth transistor T10.

[0192] The 11th transistor T11 is connected between the second power input terminal 729 and the second output terminal 726 and may include a gate electrode connected to the second Q node Q2. For example, the gate electrode of the 11th transistor T11 connected to the second Q node Q2 may be connected to the third control node CN3 via the second bridge voltage transistor Tbv2. The 11th transistor T11 can be turned on or turned off by the voltage at the second Q node Q2.

[0193] Here, since the second bridge voltage transistor Tbv2 includes a gate electrode connected to the second power input terminal 729, just like the first bridge voltage transistor Tbv1, the second bridge voltage transistor Tbv2 can always remain in the turned-on state. As a result, the voltage at the third control node CN3 and the voltage at the second Q node Q2 can have substantially the same value. Thus, the eleventh transistor T11 can be turned on or turned off by the voltage at the third control node CN3.

[0194] For example, the 11th transistor T11 can be turned on when the voltage at the second Q node Q2 or the voltage at the third control node CN3 is at a gate-on level, such as a low level, thereby electrically connecting the second power input terminal 729 and the second output terminal 726. This allows the first pull-up control signal PUS1 output through the second output terminal 726 during the period when the 11th transistor T11 is turned on to be at a gate-on level, such as a low level.

[0195] The twelfth transistor T12 is connected between the first power input terminal 728 and the second output terminal 726 and may include a gate electrode connected to the second QB node QB2. The twelfth transistor T12 can be turned on or turned off by the voltage at the second QB node QB2.

[0196] For example, the 12th transistor T12 can be turned on when the voltage at the second QB node QB2 is at the gate-on level, e.g., a low level, thereby electrically connecting the first power input terminal 728 and the second output terminal 726. This allows the first pull-up control signal PUS1 output through the second output terminal 726 during the period when the 12th transistor T12 is turned on to be at the gate-off level, e.g., a high level.

[0197] Thus, the 11th transistor T11 of the first output unit OUT1 can perform the pull-up function, and the 12th transistor T12 of the first output unit OUT1 can perform the pull-down function.

[0198] Furthermore, a first pull-down control signal PDS1 may be output through the third output terminal 727 corresponding to the second QB node QB2. Here, since the second Q node Q2 and the second QB node QB2 have opposite phases, the first pull-up control signal PUS1 output through the second output terminal 726 and the first pull-down control signal PDS1 output through the third output terminal 727 may have opposite phases.

[0199] A fourth capacitor C4 (or a second boosting capacitor) may be connected between the fourth input terminal 725 and the fourth control node CN4. For example, the fourth capacitor C4 may include a first electrode connected to the fourth input terminal 725 and a second electrode connected to the fourth control node CN4.

[0200] A fifth capacitor C5 may be connected between the second Q node Q2 and the second output terminal 726. For example, the fifth capacitor C5 may include a first electrode connected to the second Q node Q2 and a second electrode connected to the second output terminal 726.

[0201] The sixth capacitor C6 may be connected between the second QB node QB2 and the first power input terminal 728. For example, the sixth capacitor C6 may include a first electrode connected to the second QB node QB2 and a second electrode connected to the first power input terminal 728.

[0202] Figures 8a and 8b are waveform diagrams illustrating an example of the first stage drive shown in Figure 7.

[0203] For example, Figure 8a shows an example of the signals input to and output to the output control unit SCTR1, for example, the first stage STG1 when the first stage STG1 is driven in the first mode, and Figure 8b shows an example of the signals input to and output to the output control unit SCTR1, for example, the first stage STG1 when the first stage STG1 is driven in the second mode.

[0204] On the other hand, in this specification, the first mode means a mode in which multiple gate signals (scan signals) are sequentially output to all pixel rows, and pixels PX located in all pixel rows are driven in a first display period DP1 as described with reference to Figure 4a, and the second mode may mean a mode in which the gate signal (scan signal) output to pixels PX located in at least one of the multiple pixel rows is driven in a second display period DP2 in which it is maintained at a gate-off level.

[0205] On the other hand, as explained with reference to Figure 7, the gate electrodes of the first bridge voltage transistor Tbv1 and the second bridge voltage transistor Tbv2 are each connected to the second power supply input terminal 729 to which the voltage of the second power supply VGL is supplied. Therefore, the first bridge voltage transistor Tbv1 and the second bridge voltage transistor Tbv2 can each maintain a turned-on state for the entire duration in which the output control unit SCTR1 is driven. As a result, the voltage at the first control node CN1 and the voltage at the first Q node Q1 can be substantially the same throughout the entire duration, and the voltage at the third control node CN3 and the voltage at the second Q node Q2 can be substantially the same throughout the entire duration.

[0206] Referring to Figures 7 through 8b, the first clock signal CLK1 and the second clock signal CLK2 can be supplied at different timings. For example, the second clock signal CLK2 can be set to a signal that is shifted by half a period from the first clock signal CLK1.

[0207] Referring to Figure 8a, in one embodiment, in the first mode, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be maintained at a gate-on level, for example, a low level L.

[0208] Referring to Figure 8b, in one embodiment, in the second mode, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can toggle between gate-off levels and gate-on levels, for example, between low level L and high level H, for at least a portion of the time. In this case, the first control clock signal CCLK1 and the third control clock signal CCLK3 may have the same waveform as the first clock signal CLK1, and the second control clock signal CCLK2 and the fourth control clock signal CCLK4 may have the same waveform as the second clock signal CLK2.

[0209] On the other hand, the high voltage level shown in Figures 8a and 8b, for example, high level H, corresponds to the voltage of the first power supply VGH, and the low voltage level, for example, low level L, may correspond to the voltage of the second power supply VGL. For example, the voltage of the first power supply VGH may be a positive voltage, and the voltage of the second power supply VGL may be a negative voltage. However, this is illustrative, and high level H and low level L are not limited to these. For example, the voltages of high level H and low level L may be set depending on the type of transistor, the operating environment of the display device, etc.

[0210] In the following, with reference to Figures 6a, 7, 8a, and 8b, we will examine the operation of the output control unit SCTR1 according to one embodiment of this specification, for example, the first stage STG1. For the sake of explanation, we will first describe the operation of the first carry unit CRY1 in each mode, and then describe the operation of the first output unit OUT1.

[0211] First, to explain the first mode, refer to Figures 6a, 7, and 8a. In the first period P1 and the second period P2, the first Q node Q1 may be maintained at a low level L, and the first QB node QB1 may be maintained at a high level H.

[0212] For example, in the first period P1, the first transistor T1 is turned on by the first clock signal CLK1 which is gate-on level, for example, low level L, and the first light emission control signal EM1 which is low level L is supplied to the first control node CN1, so the first Q node Q1 has a low level L, and the fourth transistor T4 is turned on by the low level L voltage of the first control node CN1, and the voltage of the first power supply VGH is supplied to the first QB node QB1, so the first QB node QB1 may have a high level H.

[0213] Furthermore, in the second period P2, even if the first clock signal CLK1 transitions to a high level H, the voltages applied to the first Q node Q1 and the first QB node QB1 in the first period P1 are maintained, and the first Q node Q1 may have a low level L, while the first QB node QB1 may have a high level H.

[0214] As a result, during the first period P1 and the second period P2, the fifth transistor T5 is kept in the turned-on state and the sixth transistor T6 is kept in the turned-off state, so that the first carry signal CR1 can be output at a low level L.

[0215] Thereafter, during the third period P3 through the fifth period P5, a high-level H first light emission control signal EM1 may be provided. This allows the second transistor T2 to be turned off or remain in the turned-off state during the third period P3 through the fifth period P5.

[0216] Furthermore, during the fourth period P4, the first clock signal CLK1 may transition from its existing high level H to a low level L. This may cause the first transistor T1 to turn on during the fourth period P4, providing the first light emission control signal EM1 at a high level H to the first control node CN1. This may cause the first Q node Q1 to transition from its existing low level L to a high level H during the fourth period P4.

[0217] Furthermore, as mentioned above, during the third period P3 through the fifth period P5, the second transistor T2 is kept in the turned-off state. Therefore, during the fourth period P4, the signal level of the first clock signal CLK1 transitions from the existing high level H to the low level L, and the coupling operation of the first capacitor C1 can also cause the voltage of the second control node CN2 to transition from the existing high level H to the low level L. As a result, during the fourth period P4, the third transistor T3 is turned on, and the low-level L first clock signal CLK1 is supplied to the first QB node QB1, causing the first QB node QB1 to transition from the existing high level H to the low level L.

[0218] As a result, in the fourth period P4, the voltages at the first Q node Q1 and the first QB node QB1 cause the fifth transistor T5 to turn off and the sixth transistor T6 to turn on, so that the first carry signal CR1 can be output at a high level H.

[0219] Thereafter, during the fifth period P5, even if the first clock signal CLK1 toggles between a high level H and a low level L, the first light emission control signal EM1 is maintained at a high level H, so the first Q node Q1 can be maintained at a high level H and the first QB node QB1 can be maintained at a low level L.

[0220] Subsequently, in the sixth period P6, the first light emission control signal EM1 may transition from a high level H to a low level L, and thereafter, in the seventh period P7, the first clock signal CLK1 may transition from a high level H to a low level L. In the seventh period P7, the first transistor T1 is turned on by the low-level L first clock signal CLK1, and the turned-on first transistor T1 supplies the low-level L first light emission control signal EM1 to the first control node CN1, causing the first Q node Q1 to transition from its existing high level H to a low level L.

[0221] Furthermore, since the first control node CN1 has a low level L during the seventh period P7, the fourth transistor T4 is turned on, and the first QB node QB1 can transition from its existing low level L to a high level H by the voltage of the first power supply VGH.

[0222] As a result, in the seventh period P7, the voltages at the first Q node Q1 and the first QB node QB1 cause the fifth transistor T5 to turn on and the sixth transistor T6 to turn off, so that the first carry signal CR1 can be output at a low level L.

[0223] Next, considering the operation of the first output OUT1 in the first mode, as mentioned above, in the first mode, the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may have a gate-on level, for example, a low level L. This allows the seventh transistor T7 to always be kept in a turned-on state in the first mode.

[0224] Here, in the intervals where the first carry signal CR1 is at a low level L, for example, in the first period P1, the second period P2, the sixth period P6, and the seventh period P7, the first carry signal CR1 at a low level L can be supplied to the third control node CN3 by the turned-on seventh transistor T7. As a result, the second Q node Q2 has a low level L, and the voltage of the third control node CN3 at a low level L can turn on the tenth transistor T10, causing the second QB node QB2 to have a high level H.

[0225] As a result, in the first period P1, the second period P2, the sixth period P6, and the seventh period P7, the eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, a low-level L first pull-up control signal PUS1 is output, and a high-level H first pull-down control signal PDS1 is output corresponding to the voltage of the second QB node QB2.

[0226] Next, during the interval in which the first carry signal CR1 is at a high level H, for example, from the third period P3 to the fifth period P5, the turned-on seventh transistor T7 can supply the first carry signal CR1 at a high level H to the third control node CN3. As a result, the second Q node Q2 may have a high level H.

[0227] However, in the intervals where the first light emission control signal EM1 is at a low level L, for example, in the first period P1 and the second period P2, the fourth control node CN4 may have a high level H before the third period P3, due to the eighth transistor T8 being turned on by the first light emission control signal EM1 at a low level L. Here, since the first control clock signal CCLK1 is maintained at a high level H for the entire interval, the fourth control node CN4 is also maintained at a high level H by the fourth capacitor C4 during the third period P3 to the fifth period P5, and the ninth transistor T9 can always be kept in a turned-off state. As a result, the second QB node QB2 can be maintained at its existing high level H because there is no supply of any other voltage or signal during the third period P3 to the fifth period P5. That is, in the first mode, the second QB node QB2 can be maintained at the gate-off level, for example, at a high level H.

[0228] As a result, during the third period P3 through the fifth period P5, both the second Q node Q2 and the second QB node QB2 have a high level H, so both the eleventh transistor T11 and the twelfth transistor T12 are turned off or kept in a turned-off state, and during the corresponding period, the voltage levels of the second output terminal 726 and the third output terminal 727 can be maintained at the voltage levels of the previous period.

[0229] As a result, during the entire section driven in the first mode, the first pull-up control signal PUS1 output through the second output terminal 726 may have a gate-on level, for example, a low level L, and the first pull-down control signal PDS1 output through the third output terminal 727 may have a gate-off level, for example, a high level H.

[0230] Next, referring to Figures 6a, 7, and 8b to describe the second mode, the operation of the first carry unit CRY1 in the second mode may be substantially the same as the operation of the first carry unit CRY1 in the first mode. For example, the first carry unit CRY1 can generate and output a first carry signal CR1 having a high-level H pulse based on a first light emission control signal EM1, a first clock signal CLK1, a first power supply VGH, and a second power supply VGL.

[0231] Next, considering the operation of the first output unit OUT1 in the second mode, the second Q node Q2 may be maintained at a low level L during the eighth period P8 and the ninth period P9, while the second QB node QB2 may be maintained at a high level H.

[0232] For example, in the eighth period P8, the seventh transistor T7 is turned on by the first control clock signal CCLK1, which is gate-on level, for example, low level L, and the first carry signal CR1, which is low level L, is supplied to the third control node CN3, so the second Q node Q2 has a low level L, and the tenth transistor T10 is turned on by the low level L voltage of the third control node CN3, and the voltage of the first power supply VGH is supplied to the second QB node QB2, so the second QB node QB2 may have a high level H.

[0233] Furthermore, in the ninth period P9, even if the first control clock signal CCLK1 transitions to a high level H, the voltages applied to the second Q node Q2 and the second QB node QB2 in the eighth period P8 are maintained, and the second Q node Q2 may have a low level L, while the second QB node QB2 may have a high level H.

[0234] As a result, during the 8th period P8 and the 9th period P9, the 11th transistor T11 is kept in the turn-on state and the 12th transistor T12 is kept in the turn-off state, and the first pull-up control signal PUS1 can be output at a low level L.

[0235] Furthermore, corresponding to the voltage of the second QB node QB2, the first pull-down control signal PDS1 can be output at a high level (H) during the eighth period P8 and the ninth period P9.

[0236] Thereafter, during the tenth period P10 through the twelfth period P12, a high-level H first carry signal CR1 may be provided. This allows the eighth transistor T8 to be turned off or remain in the turned-off state during the tenth period P10 through the twelfth period P12.

[0237] Furthermore, during the 11th period P11, the first control clock signal CCLK1 may transition from its existing high level H to a low level L. This may cause the 7th transistor T7 to turn on during the 11th period P11, providing the 1st carry signal CR1 at a high level H to the 3rd control node CN3. This may cause the 2nd Q node Q2 to transition from its existing low level L to a high level H during the 11th period P11.

[0238] Furthermore, as mentioned above, since the eighth transistor T8 is kept in the turned-off state during the tenth period P10 to the twelfth period P12, the signal level of the first control clock signal CCLK1 transitions from the existing high level H to the low level L during the eleventh period P11, and the voltage of the fourth control node CN4 can also transition from the existing high level H to the low level L due to the coupling operation of the fourth capacitor C4. As a result, the ninth transistor T9 is turned on during the eleventh period P11, and the first control clock signal CCLK1 at the low level L is supplied to the second QB node QB2, which can then transition from the existing high level H to the low level L.

[0239] As a result, during the 11th period P11, the voltages of the 2nd Q node Q2 and the 2nd QB node QB2 cause the 11th transistor T11 to turn off and the 12th transistor T12 to turn on, so that the first pull-up control signal PUS1 can be output at a high level H.

[0240] Furthermore, in the 11th period P11, corresponding to the voltage of the second QB node QB2, the first pull-down control signal PDS1 can be output at a low level L.

[0241] Thereafter, during the 12th period P12, even if the first control clock signal CCLK1 toggles between a high level H and a low level L, the first carry signal CR1 is maintained at a high level H, so the second Q node Q2 can be maintained at a high level H and the second QB node QB2 can be maintained at a low level L.

[0242] Subsequently, in the 13th period P13, the first carry signal CR1 may transition from a high level H to a low level L, and thereafter, in the 14th period P14, the first control clock signal CCLK1 may transition from a high level H to a low level L. In the 14th period P14, the low level L of the first control clock signal CCLK1 turns on the 7th transistor T7, and the turned-on 7th transistor T7 supplies the low level L of the first carry signal CR1 to the 3rd control node CN3, causing the 2nd Q node Q2 to transition from its existing high level H to a low level L.

[0243] Furthermore, during the 14th period P14, the third control node CN3 has a low level L, so the 10th transistor T10 is turned on, and the second QB node QB2 can transition from its existing low level L to a high level H by the voltage of the first power supply VGH.

[0244] As a result, in the 14th period P14, the voltages of the 2nd Q node Q2 and the 2nd QB node QB2 cause the 11th transistor T11 to turn on and the 12th transistor T12 to turn off, and the first pull-up control signal PUS1 can be output at a low level L.

[0245] Furthermore, in the 14th period P14, corresponding to the voltage of the second QB node QB2, the first pull-down control signal PDS1 may be output at a high level H.

[0246] Thus, in the first mode, the first pull-up control signal PUS1 may have a low level L, and the first pull-down control signal PDS1 may have a high level H. In the second mode, the first pull-up control signal PUS1 may have a high-level H pulse for at least a portion of the interval, and the first pull-down control signal PDS1 may have a low-level L pulse for at least the same portion of the interval.

[0247] Here, in the second mode, for example, during the interval in the second mode in which the first pull-up control signal PUS1 has a high-level H pulse and the first pull-down control signal PDS1 has a low-level L pulse, the output of the gate signal (scan signal) of the scan drive unit connected to the output control unit SCTR1, for example, the first stage STG1, can be controlled. For example, in the interval in which the first pull-up control signal PUS1 has a high-level H pulse and the first pull-down control signal PDS1 has a low-level L pulse, the gate signal (scan signal) output from the scan drive unit may have a gate-off level.

[0248] As a result, the gate drive unit 620 and the display device 100 including it according to one embodiment of this specification can control the signal levels of the pull-up control signal and pull-down control signal output from the output unit by controlling the signal levels of a plurality of control clock signals CCLK1 to CCLK4 applied to the output unit of each stage included in the output control unit SCTR1. Here, the scan drive units connected to the output control unit SCTR1, for example, the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4, have their signal levels of the gate signals (scan signals) output by the signal levels of the pull-up control signal and pull-down control signal controlled, and the output frequencies of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 can be controlled.

[0249] Therefore, the gate drive unit 620 and the display device 100 including it according to one embodiment of this specification can freely control the drive frequency for each pixel row, for example, for each region of the display area AA.

[0250] A more detailed explanation of this will be provided later with reference to Figures 10 to 14.

[0251] On the other hand, as mentioned above, in the first mode and the second mode, the first pull-up control signal PUS1 and the first pull-down control signal PDS1 may have opposite phases to each other.

[0252] On the other hand, due to the operation of the first carry unit CRY1 and the first output unit OUT1, the pulse width of the high-level H of the first pull-up control signal PUS1 and the pulse width of the low-level L of the first pull-down control signal PDS1 may have the same pulse width as the pulse width of the first light emission control signal EM1 provided to the stage. For example, the high-level H pulse of the first pull-up control signal PUS1 and the low-level L pulse of the first pull-down control signal PDS1 may, at least in part, superimpose with the pulse of the first light emission control signal EM1 provided to the stage, but are not limited to this. For example, the high-level H pulse of the first pull-up control signal PUS1 and the low-level L pulse of the first pull-down control signal PDS1 may occur later than the pulse of the first light emission control signal EM1 provided to the stage, but are not limited to this.

[0253] Figure 9 is a waveform diagram illustrating an example of the drive operation of the gate drive unit in Figure 6a.

[0254] For example, Figure 9 shows waveform diagrams of the following signals from the output control unit STCR1: multiple light emission control signals (e.g., EM1, EM9, EM17, EM25, EM33, EM41, EM49, EM57) applied to the output control unit STCR1 based on the connection relationship between the multiple light emission stages of the light emission drive unit EDV and the output control unit STCR1; multiple control clock signals CCLK1 to CCLK4 applied to the output control unit STCR1; multiple carry signals CR1 to CR8 output from the carry section of the output control unit STCR1; and multiple pull-up control signals PUS1 to PUS8 output from the output section of the output control unit STCR1.

[0255] On the other hand, although not shown separately in Figure 9, as mentioned above, a pull-down control signal may have a phase opposite to that of a pull-up control signal.

[0256] Referring to Figures 6a to 9, based on the light emission control signals (e.g., EM1, EM9, EM17, EM25, EM33, EM41, EM49, EM57) output from the light emission stage connected to the output control unit SCTR1 among the multiple light emission stages of the light emission drive unit EDV, the multiple carry units of the output control unit STCR1 can sequentially output multiple carry signals CR1 to CR8.

[0257] In one embodiment, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may be maintained at a gate-on level, for example, a low level L, for at least a portion of the interval. For example, at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 may not perform a toggle operation in the interval in question.

[0258] On the other hand, as an example of this, Figure 9 shows a case where the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 are maintained at a low level L during the period prior to the conversion point PP.

[0259] In this case, among the multiple stages included in the output control unit SCTR1, the stage that receives the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4, which are maintained at a low level L during the period prior to the transition point PP, can output a pull-up control signal having a gate-on level, for example, a low level L.

[0260] For example, as shown in Figure 9, the first to fourth pull-up control signals PUS1 to PUS4 may have a low level L.

[0261] In contrast, a stage that receives a first control clock signal CCLK1, a second control clock signal CCLK2, a third control clock signal CCLK3, and a fourth control clock signal CCLK4 having high-level H pulses during the period after the transition point PP can output a pull-up control signal having a gate-off level, for example, a high-level H pulse.

[0262] For example, as shown in Figure 9, the 5th to 8th pull-up control signals PUS5 to PUS8 may have high-level H pulses.

[0263] In this case, as described above, among the multiple scan stages included in the scan drive unit connected to the output control unit SCTR1, the scan stage to which the first to fourth pull-up control signals PUS1 to PUS4 are applied can output a gate signal (scan signal) having a gate-on level pulse, and the scan stage to which the fifth to eighth pull-up control signals PUS5 to PUS8 are applied can output a gate signal (scan signal) that is maintained at the gate-off level.

[0264] For a more detailed explanation of this, please refer to Figures 10 through 14 below.

[0265] Figure 10 is a block diagram showing an example of a scan drive unit included in the gate drive unit of Figure 5.

[0266] For example, the scan drive unit SDV shown in Figure 10 could be any one of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 included in the gate drive unit 120 described with reference to Figure 5. That is, the scan drive unit SDV shown in Figure 10 could be a scan drive unit whose output level of the gate signal (scan signal) is controlled by the output control unit SCTR1 included in the gate drive unit 120.

[0267] On the other hand, for the sake of explanation, Figure 10 shows the 32 gate stages GST1 to GST32 included in the scan drive unit SDV and the multiple gate signals GATE1 to GATE32 output from them. Here, as mentioned above, the scan drive unit SDV in Figure 10 is one of the first scan drive unit SDV1, the second scan drive unit SDV2, and the fourth scan drive unit SDV4 as explained with reference to Figure 5. Therefore, the multiple gate signals GATE1 to GATE32 shown in Figure 10 may correspond to multiple first scan signals SCAN1 output from the first scan drive unit SDV1, multiple second scan signals SCAN2 output from the second scan drive unit SDV2, or multiple fourth scan signals SCAN4 output from the fourth scan drive unit SDV4. For example, the pixel circuit configuration shown in Figure 3 can be changed in various ways. For example, a pixel may be configured to be controlled by one or more scan signals, two or more scan signals, or three or more scan signals, but is not limited to this. From this perspective, for example, multiple gate signals GATE1 to GATE32 may correspond to one or more of one or more scan signals. For example, multiple gate signals GATE1 to GATE32 may correspond to one scan signal that is not supplied during the second display period DP2, but are not limited to this. For example, multiple gate signals GATE1 to GATE32 may correspond to one scan signal that is maintained at the gate-off level during the second display period DP2, but are not limited to this.

[0268] Referring to Figures 6a and 10, the scan drive unit SDV can include multiple gate stage groups GSG1 to GSG4. Each of the multiple gate stage groups GSG1 to GSG4 can include multiple gate stages. For example, the multiple gate stages GST1 to GST32 included in the scan drive unit SDV can be divided into multiple gate stage groups GSG1 to GSG4. As an example, as mentioned above, if the multiple stages STG1 to STG4 of the output control unit STCR1 are formed in units of eight horizontal lines, then the multiple gate stage groups GSG1 to GSG4 can be formed in units of eight horizontal lines, and each can include eight gate stages.

[0269] For example, the first gate stage group GSG1 includes gate stages GST1 to GST8 from the 1st to the 8th; the second gate stage group GSG2 includes gate stages GST9 to GST16 from the 9th to the 16th; the third gate stage group GSG3 includes gate stages GST17 to GST24 from the 17th to the 24th; and the fourth gate stage group GSG4 includes gate stages GST25 to GST32 from the 25th to the 32nd.

[0270] In one embodiment, multiple gate stages included in each of the multiple gate stage groups GSG1 to GSG4 can receive the same pull-up control signal and the same pull-down control signal.

[0271] For example, the first gate stage group GSG1 receives a first pull-up control signal PUS1 and a first pull-down control signal PDS1 provided from the first stage STG1 of the output control unit SCTR1, the second gate stage group GSG2 receives a second pull-up control signal PUS2 and a second pull-down control signal PDS2 provided from the second stage STG2 of the output control unit SCTR1, the third gate stage group GSG3 receives a third pull-up control signal PUS3 and a third pull-down control signal PDS3 provided from the third stage STG3 of the output control unit SCTR1, and the fourth gate stage group GSG4 can receive a fourth pull-up control signal PUS4 and a fourth pull-down control signal PDS4 provided from the fourth stage STG4 of the output control unit SCTR1.

[0272] As a result, the plurality of gate stages included in each of the gate stage groups GSG1 to GSG4 can receive the same pull-up control signal and pull-down control signal.

[0273] The plurality of gate stages GST1 to GST32 included in the plurality of gate stage groups GSG1 to GSG4 are cascade-connected and are respectively connected to the corresponding gate lines GL1 to GL32, and can output gate signals GATE1 to GATE32 to the corresponding gate lines.

[0274] In one embodiment, each of the plurality of gate stages GST1 to GST32 included in the plurality of gate stage groups GSG1 to GSG4 can control the output signal levels of the gate signals GATE1 to GATE32 output to the corresponding gate lines GL1 to GL32 based on the pull-up control signal and the pull-down control signal provided to the corresponding gate stage group.

[0275] For example, when the pull-up control signal is at the gate-on level and the pull-down control signal is at the gate-off level, the plurality of gate stages included in the corresponding gate stage group output a gate signal having a pulse at the gate-on level. When the pull-up control signal is at the gate-off level and the pull-down control signal is at the gate-on level, the gate signal output from the plurality of gate stages included in the corresponding gate stage group may have a gate-off level.

[0276] In one embodiment, the plurality of gate stages GST1 to GST32 included in the scan driver SDV may have substantially the same configuration except for the input signals. Accordingly, hereinafter, for convenience of explanation, when describing the plurality of gate stages GST1 to GST32 included in the scan driver SDV, the configuration and driving method of the stages included in the scan driver SDV will be described based on the first gate stage GST1.

[0277] FIG. 11 is a circuit diagram showing an example of the first gate stage included in the scan driver of FIG. 10.

[0278] FIG. 12 is a waveform diagram for explaining an example of the driving of the scan driver of FIG. 10.

[0279] Referring to FIGS. 10 and 11, the first gate stage GST1 may include a gate signal generation unit SRO that controls the voltage level of the output node PN, and a masking unit MSK that controls the signal level of the first gate signal GATE1 based on the voltage of the output node PN, the first pull-up control signal PUS1, and the first pull-down control signal PDS1.

[0280] The gate signal generator SRO can receive a gate start signal GVST as an input signal through a first gate input terminal 1101, a first gate clock signal GCLK1 through a second gate input terminal 1102, be connected to a first power supply VGH through a first power supply input terminal 1103, and be connected to a second power supply VGL through a second power supply input terminal 1104. Based on the gate start signal GVST, the first gate clock signal GCLK1, the first power supply VGH, and the second power supply VGL, the gate signal generator SRO can control the voltage level of the output node PN.

[0281] The masking unit MSK can receive a first pull-up control signal PUS1 through a first masking input terminal 1105, for example, a first masking input terminal 1105 connected to the second output terminal 726 of the first output unit OUT1 included in the first stage STG1 of the output control unit SCTR1, and can receive a first pull-down control signal PDS1 through a second masking input terminal 1106, for example, a second masking input terminal 1106 connected to the third output terminal 727 of the first output unit OUT1 included in the first stage STG1 of the output control unit SCTR1. Based on the signal levels of the first pull-up control signal PUS1 and the first pull-down control signal PDS1, the masking unit MSK can output the voltage of the output node PN or the voltage of the second power supply VGL as a first gate signal GATE1 through the gate output terminal 1108.

[0282] More specifically, the gate signal generator SRO of the first gate stage GST1 may include first to sixth scan transistors ST1 to ST6, a first scan capacitor SC1, a second scan capacitor SC2, and a third scan capacitor SC3. Depending on the embodiment, the gate signal generator SRO may further include a first scan bridge voltage transistor STbv1. However, depending on the design, the first scan bridge voltage transistor STbv1 may be omitted.

[0283] The first scan transistor ST1 is connected between the first gate input terminal 1101 and the first scan control node SN1 and may include a gate electrode connected to the second gate input terminal 1102. In one embodiment, the first scan transistor ST1 may include, as a dual-gate structure, first and second scan subtransistors ST1a and ST1b connected in series with each other.

[0284] The second scan transistor ST2 is connected between the first power input terminal 1103 and the second scan control node SN2 and may include a gate electrode connected to the first gate input terminal 1101. In one embodiment, the second scan transistor ST2 may include, for example, third and fourth scan subtransistors ST2a and ST2b connected in series with each other as a dual-gate structure.

[0285] The third scan transistor ST3 is connected between the second gate input terminal 1102 and the fourth scan control node SN4 and may include a gate electrode connected to the second scan control node SN2. In one embodiment, the third scan transistor ST3 may include, for example, fifth and sixth scan subtransistors ST3a and ST3b connected in series with each other as a dual-gate structure.

[0286] The fourth scan transistor ST4 is connected between the first power input terminal 1103 and the fourth scan control node SN4 and may include a gate electrode connected to the first scan control node SN1. In one embodiment, the fourth scan transistor ST4 may include, for example, seventh and eighth scan subtransistors ST4a and ST4b connected in series as a dual-gate structure. While it has been shown that all scan transistors ST1 through ST4 have a dual-gate structure, the invention is not limited thereto. For example, at least one or each of the first scan transistors ST1 through ST4 may have a single-gate structure, or they may have a triple-gate structure in which three scan subtransistors are connected in series, but the invention is not limited thereto.

[0287] The fifth scan transistor ST5 is connected between the second power input terminal 1104 and the output node PN and may include a gate electrode connected to the third scan control node SN3. For example, the gate electrode of the fifth scan transistor ST5 connected to the third scan control node SN3 may be connected to the first scan control node SN1 via the first scan bridge voltage transistor STbv1.

[0288] Here, the first scan bridge voltage transistor STbv1 is connected between the first scan control node SN1 and the third scan control node SN3 and includes a gate electrode connected to the second power input terminal 1104, so that the first scan bridge voltage transistor STbv1 can always remain in the turned-on state. As a result, the voltage at the first scan control node SN1 and the voltage at the third scan control node SN3 can have substantially the same value.

[0289] As a result, the fifth scan transistor ST5 is turned on when the voltage at the third scan control node SN3 or the voltage at the first scan control node SN1 is at the gate-on level, for example, a low level, thereby electrically connecting the second power supply input terminal 1104 and the output node PN. Consequently, during the interval in which the fifth scan transistor ST5 is turned on, the voltage at the output node PN may be at the gate-on level, for example, a low level.

[0290] The sixth scan transistor ST6 is connected between the first power input terminal 1103 and the output node PN and may include a gate electrode connected to the fourth scan control node SN4.

[0291] This allows the sixth scan transistor ST6 to be turned on when the voltage at the fourth scan control node SN4 is at the gate-on level, for example, a low level, thereby electrically connecting the first power input terminal 1103 to the output node PN. As a result, during the period when the sixth scan transistor ST6 is turned on, the voltage at the output node PN may be at the gate-off level, for example, a high level.

[0292] The first scan capacitor SC1 may be connected between the second gate input terminal 1102 and the second scan control node CN2. The second scan capacitor SC2 may be connected between the third scan control node SN3 and the output node PN, and the third scan capacitor SC3 may be connected between the fourth scan control node SN4 and the first power input terminal 1103.

[0293] The masking section MSK may include a first masking transistor PT1 and a second masking transistor PT2.

[0294] The first masking transistor PT1 may include a gate electrode connected between the output node PN and the gate output terminal 1108, and connected to the first masking input terminal 1105, which is provided with a first pull-up control signal PUS1.

[0295] The first masking transistor PT1 is turned on when the first pull-up control signal PUS1 has a gate-on level, for example, a low level, and can electrically connect the output node PN and the gate output terminal 1108. When the first masking transistor PT1 is turned on, the voltage of the output node PN can be output to the first gate wiring GL1 through the gate output terminal 1108 as the first gate signal GATE1.

[0296] The second masking transistor PT2 can include a gate electrode connected between the second power input terminal 1104 and the gate output terminal 1108 and connected to the second masking input terminal 1106 to which the first pull-down control signal PDS1 is provided.

[0297] The second masking transistor PT2 is turned on when the first pull-down control signal PDS1 has a gate-on level, for example, a low level, and can electrically connect the second power input terminal 1104 and the gate output terminal 1108. When the second masking transistor PT2 is turned on, the second power supply VGL, that is, the voltage of the low level L, can be output to the first gate wiring GL1 through the gate output terminal 1108 as the first gate signal GATE2.

[0298] More specifically, referring further to FIG. 12, for the plurality of gate stage groups GSG1 to GSG4 included in the scan driving unit SDV, when the first pull-up control signal PUS1 and the second pull-up control signal PUS2 applied to the first gate stage group GSG1 and the second gate stage group GSG2 have a gate-off level, for example, a pulse of the high level H, each of the plurality of gate stages included in the first gate stage group GSG1 and the second gate stage group GSG2, for example, the first to sixteenth gate stages GST1 to GST16, can output gate signals GATE1 to GATE16 that are maintained at a gate-off level, for example, a low level L, based on the corresponding pull-up control signal.

[0299] In contrast, if the third pull-up control signal PUS3 and the fourth pull-up control signal PUS4 applied to the third gate stage group GSG3 and the fourth gate stage group GSG4 have a gate-on level, for example, a low level L, then each of the gate stages included in the third gate stage group GSG3 and the fourth gate stage group GSG4, for example, the 17th to 32nd gate stages GST17 to GST32, can output gate signals GATE17 to GATE32 having a gate-on level, for example, a high level H pulse, based on the corresponding pull-up control signal. For example, depending on the type of transistor connected to the first gate line GL1, the gate-off levels from the first gate stage GST1 to the 16th gate stage GST16 may be high level H, and the gate-on levels may be low level L, but are not limited to this.

[0300] On the other hand, Figure 12 only shows the multiple pull-up control signals PUS1 to PUS4 applied to the multiple gate stage groups GSG1 to GSG4, but as mentioned above, each of the multiple pull-down control signals PDS1 to PDS4 applied to the multiple gate stage groups GSG1 to GSG4 may have a phase opposite to that of the corresponding pull-up control signal.

[0301] In the embodiment, the first gate stage GST1 described with reference to Figure 11 is a circuit that outputs a first gate signal GATE1 having a high-level H pulse as the gate-on level, and may be, but is not limited to, a plurality of scan stages SST11 to SST1n included in the first scan drive unit SDV1 described with reference to Figure 5, and / or a plurality of scan stages SST41 to SST4n included in the fourth scan drive unit SDV4.

[0302] Figure 13 is a circuit diagram showing another example of the first gate stage included in the scan drive unit of Figure 10.

[0303] Figure 14 is a waveform diagram illustrating another example of the drive of the scan drive unit shown in Figure 10.

[0304] On the other hand, the first gate stage GST1_1 in Figure 13 shows a modified embodiment of the first gate stage GST1 described with reference to Figure 11 in relation to the gate signal generation unit SRO_1.

[0305] Referring to Figures 10 and 13, the first gate stage GST1_1 may include a gate signal generator SRO_1 that controls the voltage level of the output node PN, and a masking unit MSK_1 that controls the signal level of the first gate signal GATE1 based on the voltage of the output node PN, a first pull-up control signal PUS1, and a first pull-down control signal PDS1.

[0306] The gate signal generator SRO_1 receives a gate start signal GVST as an input signal through the first gate input terminal 1301, a second gate clock signal GCLK2 through the second gate input terminal 1302, a first gate clock signal GCLK1 through the third gate input terminal 1303, and is connected to the first power supply VGH through the first power supply input terminal 1304 and the second power supply VGL through the second power supply input terminal 1305. Based on the gate start signal GVST, the first gate clock signal GCLK1, the second gate clock signal GCLK2, the first power supply VGH, and the second power supply VGL, the gate signal generator SRO_1 can control the voltage level of the output node PN.

[0307] The masking unit MSK_1 can receive the first pull-up control signal PUS1 through the first masking input terminal 1306 and the first pull-down control signal PDS1 through the second masking input terminal 1307. Based on the signal levels of the first pull-up control signal PUS1 and the first pull-down control signal PDS1, the masking unit MSK can output the voltage of the output node PN or the voltage of the first power supply VGH as the first gate signal GATE1 through the gate output terminal 1308.

[0308] More specifically, the gate signal generation unit SRO_1 of the first gate stage GST1_1 may include the 7th to 13th scan transistors ST7 to ST13, the 4th scan capacitor SC4, and the 5th scan capacitor SC5. Depending on the embodiment, the gate signal generation unit SRO_1 may further include the second scan bridge voltage transistor STbv2. For example, depending on the design, the second scan bridge voltage transistor STbv2 may be omitted.

[0309] The seventh scan transistor ST7 is connected between the first gate input terminal 1301 and the fifth scan control node SN5 and may include a gate electrode connected to the second gate input terminal 1302. In one embodiment, the seventh scan transistor ST7 may include, for example, ninth and tenth scan subtransistors ST7a and ST7b connected in series with each other as a dual-gate structure.

[0310] The eighth scan transistor ST8 is connected between the fifth scan control node SN5 and the sixth scan control node SN6 and may include a gate electrode connected to the third gate input terminal 1303.

[0311] The ninth scan transistor ST9 is connected between the sixth scan control node SN6 and the first power input terminal 1304 and may include a gate electrode connected to the eighth scan control node SN8.

[0312] The 10th scan transistor ST10 is connected between the 2nd power input terminal 1305 and the 8th scan control node SN8 and may include a gate electrode connected to the 2nd gate input terminal.

[0313] The 11th scan transistor ST11 is connected between the second gate input terminal 1302 and the 8th scan control node SN8 and may include a gate electrode connected to the 5th scan control node SN5.

[0314] The 12th scan transistor ST12 may include a gate electrode connected between the third gate input terminal 1303 and the output node PN, and connected to the 7th scan control node SN7. For example, the gate electrode of the 12th scan transistor ST12 connected to the 7th scan control node SN7 may be connected to the 5th scan control node SN5 via the second scan bridge voltage transistor STbv2.

[0315] Here, the second scanbridge voltage transistor STbv2 is connected between the fifth scan control node SN5 and the seventh scan control node SN7 and includes a gate electrode connected to the second power input terminal 1305, so that the second scanbridge voltage transistor STbv2 can always remain turned on. As a result, the voltage at the fifth scan control node SN5 and the voltage at the seventh scan control node SN7 can have substantially the same value.

[0316] As a result, the 12th scan transistor ST12 is turned on when the voltage at the 7th scan control node SN7 or the voltage at the 5th scan control node SN5 is at the gate-on level, for example, a low level, and the 3rd gate input terminal 1303 and the output node PN are electrically connected. As a result, the voltage at the output node PN may be at the gate-on level, for example, a low level, due to the first gate clock signal GCLK1 which is at a low level during the interval in which the 12th scan transistor ST12 is turned on.

[0317] The 13th scan transistor ST13 is connected between the first power input terminal 1304 and the output node PN and may include a gate electrode connected to the 8th scan control node SN8.

[0318] This allows the 13th scan transistor ST13 to be turned on when the voltage at the 8th scan control node SN8 is at the gate-on level, for example, a low level, thereby electrically connecting the first power input terminal 1304 and the output node PN. As a result, during the interval in which the 13th scan transistor ST13 is turned on, the voltage at the output node PN may be at the gate-off level, for example, a high level.

[0319] Furthermore, the masking section MSK_1 may include a first masking transistor PT1 and a second masking transistor PT2.

[0320] The first masking transistor PT1 may include a gate electrode connected between the output node PN and the gate output terminal 1308, and connected to the first masking input terminal 1306, to which a first pull-up control signal PUS1 is provided.

[0321] The first masking transistor PT1 is turned on when the first pull-up control signal PUS1 is at a gate-on level, for example, a low level, and can electrically connect the output node PN and the gate output terminal 1308. When the first masking transistor PT1 is turned on, the voltage at the output node PN can be output as the first gate signal GATE1 through the gate output terminal 1308 to the first gate wiring GL1.

[0322] The second masking transistor PT2 may include a gate electrode connected between the first power input terminal 1304 and the gate output terminal 1308, and connected to the second masking input terminal 1307, which is provided with the first pull-down control signal PDS1.

[0323] The second masking transistor PT2 is turned on when the first pull-down control signal PDS1 has a gate-on level, for example, a low level, and can electrically connect the first power supply input terminal 1304 and the gate output terminal 1308. When the second masking transistor PT2 is turned on, the first power supply VGH, i.e., a high-level H voltage, can be output as the first gate signal GATE1 through the gate output terminal 1308 to the first gate wiring GL1.

[0324] More specifically, referring further to Figure 14, if the first pull-up control signal PUS1 and the second pull-up control signal PUS2 applied to the first gate stage group GSG1 and the second gate stage group GSG2, respectively, have gate-off level pulses, for example, high level H, then each of the gate stages included in the first gate stage group GSG1 and the second gate stage group GSG2, for example, the first to sixteenth gate stages GST1 to GST16, can output gate signals GATE1 to GATE16 that are maintained at a gate-off level, for example, low level L, based on the corresponding pull-up control signals.

[0325] In contrast, if the third pull-up control signal PUS3 and the fourth pull-up control signal PUS4 applied to the third gate stage group GSG3 and the fourth gate stage group GSG4 have a gate-on level, for example, a low level L, then each of the gate stages included in the third gate stage group GSG3 and the fourth gate stage group GSG4, for example, the 17th to 32nd gate stages GST17 to GST32, can output gate signals GATE17 to GATE32 having a gate-on level, for example, a high level H pulse, based on the corresponding pull-up control signal.

[0326] On the other hand, Figure 14 only shows the multiple pull-up control signals PUS1 to PUS4 applied to the multiple gate stage groups GSG1 to GSG4, but as mentioned above, each of the multiple pull-down control signals PDS1 to PDS4 applied to the multiple gate stage groups GSG1 to GSG4 may have a phase opposite to that of the corresponding pull-up control signal.

[0327] In the embodiment, the first gate stage GST1_1 described with reference to Figure 13 is a circuit that outputs a first gate signal GATE1 having a low-level L pulse as the gate-on level, and may be, but is not limited to, a plurality of scan stages SST21~SST2n included in the second scan drive unit SDV2 described with reference to Figure 5.

[0328] Figure 15 is a block diagram showing another example of the gate drive unit shown in Figure 5.

[0329] On the other hand, the gate drive unit 1520 shown in Figure 15 represents a modified embodiment of the gate drive unit 620, which includes the output control unit SCTR1 described with reference to Figure 6a in relation to the connection relationship of the multiple control clock signals CCLK1, CCLK2, CCLK3, and CCLK4 connected to the output control unit SCTR2. For the sake of clarity, redundant explanations will not be repeated.

[0330] On the other hand, Figure 15 shows only the output control unit SCTR2 in relation to the various configurations included in the gate drive unit 1520, and shows eight stages STG1 to STG8 among the multiple stages included in the output control unit SCTR2, as well as multiple pull-up control signals PUS1 to PUS8 and multiple pull-down control signals PDS1 to PDS8 output from them.

[0331] On the other hand, although the light emission drive unit EDV included in the gate drive unit 1520 is not shown in Figure 15, as mentioned above, the output control unit SCTR2 can receive light emission signals from multiple light emission stages included in the light emission drive unit EDV.

[0332] Referring to Figure 15, the gate drive unit 1520 according to one embodiment of this specification may include an output control unit SCTR2.

[0333] The output control unit SCTR2 may include multiple stages STG1 to STG8. These multiple stages STG1 to STG8 can output multiple pull-up control signals PUS1 to PUS8 and multiple pull-down control signals PDS1 to PDS8 based on multiple clock signals CLK1 and CLK2 and multiple control clock signals CCLK1, CCLK2, CCLK3, and CCLK4. Here, the multiple stages STG1 to STG8 may have substantially the same configuration.

[0334] In one embodiment, the multiple stages STG1 to STG8 included in the output control unit SCTR2 may be formed in units of at least two horizontal lines. For example, as shown in Figure 15, the multiple stages STG1 to STG8 may be formed in units of eight horizontal lines. In this way, in the embodiment shown in Figure 15, each of the multiple stages STG1 to STG8 included in the output control unit SCTR2 can commonly control eight scan stages formed in units of eight horizontal lines from among the multiple scan stages included in the scan drive unit.

[0335] Each of the multiple stages STG1 to STG8 may include carry sections CRY1 to CRY8 for outputting carry signals CR1 to CR8, and output sections OUT1 to OUT8 for outputting pull-up control signals PUS1 to PUS8 and pull-down control signals PDS1 to PDS8.

[0336] The carry signals CR1 to CR8, output through the output terminals of each of the multiple carry units CRY1 to CRY8, can be provided to the output units OUT1 to OUT8 of the corresponding stage.

[0337] Furthermore, each of the multiple output units OUT1 to OUT8 can receive one of several control clock signals, for example, a first control clock signal CCLK1, a second control clock signal CCLK2, a third control clock signal CCLK3, and a fourth control clock signal CCLK4.

[0338] In one embodiment, the output units included in the i-th stage (where i is an integer greater than 0) and the i+2 stage receive the first control clock signal CCLK1, the output units included in the i+1-th stage and the i+3-th stage receive the second control clock signal CCLK2, the output units included in the i+4-th stage and the i+6-th stage receive the third control clock signal CCLK3, and the output units included in the i+5-th stage and the i+7-th stage receive the fourth control clock signal CCLK4. For example, the order of stages configured to receive the same control clock signal can be changed in various ways. For example, they may be configured to receive the same control clock signal every two stages, but are not limited to this.

[0339] For example, the first output unit OUT1 and the third output unit OUT3 can receive the first control clock signal CCLK1, the second output unit OUT2 and the fourth output unit OUT4 can receive the second control clock signal CCLK2, the fifth output unit OUT5 and the seventh output unit OUT7 can receive the third control clock signal CCLK3, and the sixth output unit OUT6 and the eighth output unit OUT8 can receive the fourth control clock signal CCLK4.

[0340] In one embodiment, the signal level of at least one of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled by the drive mode. For example, the signal levels of the first control clock signal CCLK1, the second control clock signal CCLK2, the third control clock signal CCLK3, and the fourth control clock signal CCLK4 can be controlled independently. This allows the signal levels of multiple pull-up control signals PUS1 to PUS8 and multiple pull-down control signals PDS1 to PDS8 output from multiple output units OUT1 to OUT8 to be controlled.

[0341] On the other hand, the first carry unit CRY1 included in the first stage STG1 can receive the light emission start signal EVST, which is substantially similar to what was explained with reference to Figure 6b.

[0342] Figure 16 is a block diagram showing yet another example of the gate drive unit in Figure 5.

[0343] Figure 17 is a waveform diagram showing an example of a control clock signal provided to the gate drive unit in Figure 16.

[0344] On the other hand, the gate drive unit 1620 shown in Figure 16 represents a modified embodiment of the gate drive unit 620, which includes the output control unit SCTR1 described with reference to Figure 6a in relation to the connection relationship between the output control unit SCTR3 and the light-emitting drive unit EDV, and the multiple control clock signals CCLK1 to CCLK8 connected to the output control unit SCTR3 and their connection relationships. For the sake of clarity, redundant explanations will not be repeated.

[0345] On the other hand, Figure 16 shows only the light emission drive unit EDV and the output control unit SCTR3, in relation to the various configurations included in the gate drive unit 1620. Also, for the sake of explanation, Figure 15 shows 32 stages EST1 to EST32 among the multiple light emission stages included in the light emission drive unit EDV and multiple light emission control signals EM1 to EM32 output from them, as well as 8 stages STG1 to STG8 among the multiple stages included in the output control unit SCTR3 and multiple pull-up control signals PUS1 to PUS8 and multiple pull-down control signals PDS1 to PDS8 output from them.

[0346] Referring to Figure 16, the gate drive unit 1620 according to one embodiment of this specification may include a light-emitting drive unit EDV and an output control unit SCTR3.

[0347] The output control unit SCTR3 may include multiple stages STG1 to STG8. These multiple stages STG1 to STG8 can output multiple pull-up control signals PUS1 to PUS8 and multiple pull-down control signals PDS1 to PDS8 based on multiple clock signals CLK1 and CLK2 and multiple control clock signals CCLK1 to CCLK8. Here, the multiple stages STG1 to STG8 may have substantially the same configuration.

[0348] In one embodiment, the multiple stages STG1 to STG8 included in the output control unit SCTR3 can be formed in units of at least two horizontal lines. For example, as shown in Figure 16, the multiple stages STG1 to STG8 can be formed in units of four horizontal lines. In this way, in the embodiment of Figure 16, each of the multiple stages STG1 to STG8 included in the output control unit SCTR3 can commonly control four scan stages formed in units of four horizontal lines from among the multiple scan stages included in the scan drive unit.

[0349] Each of the multiple stages STG1 to STG8 may include carry sections CRY1 to CRY8 for outputting carry signals CR1 to CR8, and output sections OUT1 to OUT8 for outputting pull-up control signals PUS1 to PUS8 and pull-down control signals PDS1 to PDS8.

[0350] Each of the multiple carry units CRY1 to CRY8 included in the multiple stages STG1 to STG8 can receive a light emission control signal from the light emission drive unit EDV.

[0351] In one embodiment, the k-th stage (where k is an integer greater than 0) can receive the light emission control signal output from the 4k-3 light emission stage. For example, the first carry unit CRY1 included in the first stage STG1 receives the first light emission control signal EM1 output from the first light emission stage EST1, the second carry unit CRY2 included in the second stage STG2 receives the fifth light emission control signal EM5 output from the fifth light emission stage EST5, the third carry unit CRY3 included in the third stage STG3 receives the ninth light emission control signal EM9 output from the ninth light emission stage EST9, the fourth carry unit CRY4 included in the fourth stage STG4 receives the thirteenth light emission control signal EM13 output from the thirteenth light emission stage EST13, and the fifth stage S The fifth carry unit CRY5 included in TG5 can receive the 17th light emission control signal EM17 output from the 17th light emission stage EST17; the sixth carry unit CRY6 included in the sixth stage STG6 can receive the 21st light emission control signal EM21 output from the 21st light emission stage EST21; the seventh carry unit CRY7 included in the seventh stage STG7 can receive the 25th light emission control signal EM25 output from the 25th light emission stage EST25; and the eighth carry unit CRY8 included in the eighth stage STG8 can receive the 29th light emission control signal EM29 output from the 29th light emission stage EST29. For example, the kth stage (where k is an integer greater than 0) can receive a light emission control signal output from any one of the 4k-3 to 4k-1 light emission stages, but is not limited to this.

[0352] In this way, each of the multiple stages STG1 to STG8 controls four scan stages formed in units of four horizontal lines, so that each of the multiple carry units CRY1 to CRY8 included in each of the multiple stages STG1 to STG8 can receive a light emission control signal from one of the four light emission stages formed in units of four horizontal lines.

[0353] On the other hand, as substantially similar to what is described with reference to Figure 6b, the first carry unit CRY1 included in the first stage STG1 can also receive the light emission start signal EVST. In this case, for the remaining stages excluding the first stage STG1, the l-th stage (where l is an integer greater than 1) can receive the light emission control signal output from the fourth (l-1) light emission stage. For example, for the remaining stages excluding the first stage STG1, the l-th stage can receive the light emission control signal output from any one of the 4th (l-1) to 4l-1 light emission stages, but is not limited to this.

[0354] The carry signals CR1 to CR8, output through the output terminals of each of the multiple carry units CRY1 to CRY8, can be provided to the output units OUT1 to OUT8 of the corresponding stage.

[0355] Furthermore, each of the multiple output units OUT1 to OUT8 can receive one of the multiple control clock signals CCLK1 to CCKL8.

[0356] In one embodiment, the output unit included in the i-th stage (where i is an integer greater than 0) receives the first control clock signal CCLK1, the output unit included in the i+1-th stage receives the second control clock signal CCLK2, the output unit included in the i+2-th stage receives the third control clock signal CCLK3, the output unit included in the i+3-th stage receives the fourth control clock signal CCLK4, the output unit included in the i+4-th stage receives the fifth control clock signal CCLK5, the output unit included in the i+5-th stage receives the sixth control clock signal CCLK6, the output unit included in the i+6-th stage receives the seventh control clock signal CCLK7, and the output unit included in the i+7-th stage receives the eighth control clock signal CCLK8. For example, the output units included in each stage can receive different signals from the first control clock signal CCLK1 to the eighth control clock signal CCLK8, but are not limited to this.

[0357] For example, the first output unit OUT1 can receive the first control clock signal CCLK1, the second output unit OUT2 can receive the second control clock signal CCLK2, the third output unit OUT3 can receive the third control clock signal CCLK3, the fourth output unit OUT4 can receive the fourth control clock signal CCLK4, the fifth output unit OUT5 can receive the fifth control clock signal CCLK5, the sixth output unit OUT6 can receive the sixth control clock signal CCLK6, the seventh output unit OUT7 can receive the seventh control clock signal CCLK7, and the eighth output unit OUT8 can receive the eighth control clock signal CCLK8.

[0358] Multiple control clock signals CCLK1 to CCLK8 may have the same period and pulse width, and their phases may not overlap.

[0359] For example, referring further to Figure 17, as mentioned above, when the gate drive unit 1620 is driven in the second mode and multiple control clock signals CCLK1 to CCLK8 perform toggle operation, the second control clock signal CCLK2 is set to a signal shifted by approximately 1 / 4 period from the first control clock signal CCLK1, the third control clock signal CCLK3 is set to a signal shifted by approximately 1 / 4 period from the second control clock signal CCLK2, and the fourth control clock signal CCLK4 is set to a signal shifted by approximately 1 / 4 period from the third control clock signal CCLK3. The signals may be set to shifted signals, with the fifth control clock signal CCLK5 being set to a signal shifted by approximately 1 / 4 period from the fourth control clock signal CCLK4, the sixth control clock signal CCLK6 being set to a signal shifted by approximately 1 / 4 period from the fifth control clock signal CCLK5, the seventh control clock signal CCLK7 being set to a signal shifted by approximately 1 / 4 period from the sixth control clock signal CCLK6, and the eighth control clock signal CCLK8 being set to a signal shifted by approximately 1 / 4 period from the seventh control clock signal CCLK7.

[0360] That is, the first control clock signal CCLK1 and the fifth control clock signal CCLK5 may have substantially the same waveform with a difference of only one period, the second control clock signal CCLK2 and the sixth control clock signal CCLK6 may have substantially the same waveform with a difference of only one period, the third control clock signal CCLK3 and the seventh control clock signal CCLK7 may have substantially the same waveform with a difference of only one period, and the fourth control clock signal CCLK4 and the eighth control clock signal CCLK8 may have substantially the same waveform with a difference of only one period. For example, each control clock signal may be set to a signal that is shifted by approximately 1 / 4 cycle from the other control clock signals, but is not limited thereto. For example, each control clock signal and the other control clock signals may be adjacent control clock signals or separated control clock signals, but is not limited thereto.

[0361] In one embodiment, the signal level of at least one of the multiple control clock signals CCLK1 to CCLK8 can be controlled by the drive mode. For example, the signal levels of the multiple control clock signals CCLK1 to CCLK8 can be controlled independently.

[0362] This allows for the control of the signal levels of multiple pull-up control signals PUS1-PUS8 and multiple pull-down control signals PDS1-PDS8 output from multiple output units OUT1-OUT8.

[0363] Figure 18 is a block diagram showing yet another example of the gate drive unit in Figure 5.

[0364] Figure 19 is a waveform diagram showing an example of a control clock signal provided to the gate drive unit in Figure 18.

[0365] On the other hand, the gate drive unit 1820 shown in Figure 18 represents a modified embodiment of the gate drive unit 1620, which includes the output control unit SCTR3 described with reference to Figure 16 in relation to the connection relationship of the multiple control clock signals CCLK1 to CCLK8 connected to the output control unit SCTR4. For the sake of convenience, redundant explanations will not be repeated.

[0366] On the other hand, Figure 18 shows only the output control unit SCTR4 in relation to the various configurations included in the gate drive unit 1820, and shows 16 stages STG1 to STG16 among the multiple stages included in the output control unit SCTR4, and multiple pull-up control signals PUS1 to PUS16 and multiple pull-down control signals PDS1 to PDS16 output from them.

[0367] On the other hand, although the light-emitting drive unit EDV included in the gate drive unit 1820 is not shown in Figure 18, as mentioned above, the output control unit SCTR4 can receive light-emitting signals from multiple light-emitting stages included in the light-emitting drive unit EDV.

[0368] Referring to Figure 18, the gate drive unit 1820 according to one embodiment of this specification may include an output control unit SCTR4.

[0369] The output control unit SCTR4 may include multiple stages STG1 to STG16. These multiple stages STG1 to STG16 can output multiple pull-up control signals PUS1 to PUS16 and multiple pull-down control signals PDS1 to PDS16 based on multiple clock signals CLK1, CLK2 and multiple control clock signals CCLK1 to CCLK8. Here, the multiple stages STG1 to STG16 may have substantially the same configuration.

[0370] In one embodiment, the multiple stages STG1 to STG16 included in the output control unit SCTR4 may be formed in units of at least two horizontal lines. For example, as shown in Figure 18, the multiple stages STG1 to STG16 may be formed in units of four horizontal lines. In this way, in the embodiment shown in Figure 18, each of the multiple stages STG1 to STG16 included in the output control unit SCTR4 can commonly control four scan stages formed in units of four horizontal lines from among the multiple scan stages included in the scan drive unit.

[0371] Each of the multiple stages STG1 to STG16 may include carry sections CRY1 to CRY16 for outputting carry signals CR1 to CR16, and output sections OUT1 to OUT16 for outputting pull-up control signals PUS1 to PUS16 and pull-down control signals PDS1 to PDS16.

[0372] The carry signals CR1 to CR16, output through the output terminals of each of the multiple carry units CRY1 to CRY16, can be provided to the output units OUT1 to OUT16 of the corresponding stage.

[0373] Furthermore, each of the multiple output units OUT1 to OUT16 can receive one of the multiple control clock signals CCLK1 to CCLK8.

[0374] In one embodiment, the output units included in the i-th stage (where i is an integer greater than 0) and the i+2 stage receive the first control clock signal CCLK1, the output units included in the i+1-th stage and the i+3-th stage receive the second control clock signal CCLK2, the output units included in the i+4-th stage and the i+6-th stage receive the third control clock signal CCLK3, the output units included in the i+5-th stage and the i+7-th stage receive the fourth control clock signal CCLK4, the output units included in the i+8-th stage and the i+10-th stage receive the fifth control clock signal CCLK5, the output units included in the i+9-th stage and the i+11-th stage receive the sixth control clock signal CCLK6, the output units included in the i+12-th stage and the i+14-th stage receive the seventh control clock signal CCLK7, and the output units included in the i+13-th stage and the i+15-th stage receive the eighth control clock signal CCLK8. For example, the output sections included in each of the two stages may, but are not limited to, receive the same control clock signal. For example, the order of stages configured to receive the same control clock signal may, but are not limited to, be changed in various ways.

[0375] For example, the first output unit OUT1 and the third output unit OUT3 can receive the first control clock signal CCLK1, the second output unit OUT2 and the fourth output unit OUT4 can receive the second control clock signal CCLK2, the fifth output unit OUT5 and the seventh output unit OUT7 can receive the third control clock signal CCLK3, and the sixth output unit OUT6 and the eighth output unit OUT8 can receive the fourth control clock signal CCLK4. In addition, the ninth output unit OUT9 and the eleventh output unit OUT11 can receive the fifth control clock signal CCLK5, the tenth output unit OUT10 and the twelfth output unit OUT12 can receive the sixth control clock signal CCLK6, the thirteenth output unit OUT13 and the fifteenth output unit OUT15 can receive the seventh control clock signal CCLK7, and the fourteenth output unit OUT14 and the sixteenth output unit OUT16 can receive the eighth control clock signal CCLK8.

[0376] In one embodiment, the signal level of at least one of the first control clock signal CCLK1, second control clock signal CCLK2, third control clock signal CCLK3, fourth control clock signal CCLK4, fifth control clock signal CCLK5, sixth control clock signal CCLK6, seventh control clock signal CCLK7, and eighth control clock signal CCLK8 can be controlled by the drive mode. For example, the signal levels of the first control clock signal CCLK1, second control clock signal CCLK2, third control clock signal CCLK3, fourth control clock signal CCLK4, fifth control clock signal CCLK5, sixth control clock signal CCLK6, seventh control clock signal CCLK7, and eighth control clock signal CCLK8 can be controlled independently.

[0377] Multiple control clock signals CCLK1 to CCLK8 may have the same period and pulse width, and their phases may not overlap.

[0378] For example, referring further to Figure 19, as mentioned above, when the gate drive unit 1820 is driven in the second mode and multiple control clock signals CCLK1 to CCLK8 perform toggle operation, the second control clock signal CCLK2 is set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1, the third control clock signal CCLK3 is set to a signal shifted by approximately 1 / 2 period from the second control clock signal CCLK2, and the fourth control clock signal CCLK4 is set to a signal shifted by approximately 1 / 2 period from the third control clock signal CCLK3. The signals may be set to shifted signals, with the fifth control clock signal CCLK5 being set to a signal shifted by approximately 1 / 2 period from the fourth control clock signal CCLK4, the sixth control clock signal CCLK6 being set to a signal shifted by approximately 1 / 2 period from the fifth control clock signal CCLK5, the seventh control clock signal CCLK7 being set to a signal shifted by approximately 1 / 2 period from the sixth control clock signal CCLK6, and the eighth control clock signal CCLK8 being set to a signal shifted by approximately 1 / 2 period from the seventh control clock signal CCLK7.

[0379] That is, the first control clock signal CCLK1, the third control clock signal CCLK3, the fifth control clock signal CCLK5, and the seventh control clock signal CCLK7 are set to have a difference of a multiple of one period and have substantially the same waveform, and the second control clock signal CCLK2, the fourth control clock signal CCLK4, the sixth control clock signal CCLK6, and the eighth control clock signal CCLK8 may have substantially the same waveform when set to have a difference of a multiple of one period.

[0380] In one embodiment, the signal level of at least one of the multiple control clock signals CCLK1 to CCLK8 can be controlled by the drive mode. For example, the signal levels of the multiple control clock signals CCLK1 to CCLK8 can be controlled independently.

[0381] This allows for the control of the signal levels of multiple pull-up control signals PUS1 to PUS16 and multiple pull-down control signals PDS1 to PDS16 output from multiple output units OUT1 to OUT16.

[0382] On the other hand, the first carry unit CRY1 included in the first stage STG1 can also receive the light emission start signal EVST, which is substantially similar to what was explained with reference to Figure 6b.

[0383] Figure 20 is a block diagram showing yet another example of the gate drive unit in Figure 5.

[0384] Figure 21 is a waveform diagram showing an example of a control clock signal provided to the gate drive unit in Figure 20.

[0385] On the other hand, the gate drive unit 2020 shown in Figure 20 represents a modified embodiment of the gate drive unit 1620, which includes the output control unit SCTR3 described with reference to Figure 16 in relation to the multiple control clock signals CCLK1 to CCLK6 connected to the output control unit SCTR5 and their connection relationships. For the sake of clarity, redundant explanations will not be repeated.

[0386] On the other hand, Figure 20 shows only the output control unit SCTR5 in relation to the various configurations included in the gate drive unit 2020, and shows six of the multiple stages included in the output control unit SCTR5, STG1 to STG6, and multiple pull-up control signals PUS1 to PUS6 and multiple pull-down control signals PDS1 to PDS6 output from them.

[0387] On the other hand, although the light emission drive unit EDV included in the gate drive unit 2020 is not shown in Figure 20, as mentioned above, the output control unit SCTR5 can receive light emission signals from multiple light emission stages included in the light emission drive unit EDV.

[0388] Referring to Figure 20, the gate drive unit 2020 according to one embodiment of this specification may include an output control unit SCTR5.

[0389] The output control unit SCTR5 may include multiple stages STG1 to STG6. These multiple stages STG1 to STG6 can output multiple pull-up control signals PUS1 to PUS6 and multiple pull-down control signals PDS1 to PDS6 based on multiple clock signals CLK1 and CLK2 and multiple control clock signals CCLK1 to CCLK6. Here, the multiple stages STG1 to STG6 may have substantially the same configuration.

[0390] In one embodiment, the multiple stages STG1 to STG6 included in the output control unit SCTR5 may be formed in units of at least two horizontal lines. For example, as shown in Figure 20, the multiple stages STG1 to STG6 may be formed in units of four horizontal lines. In this way, in the embodiment of Figure 20, each of the multiple stages STG1 to STG6 included in the output control unit SCTR5 can commonly control four scan stages formed in units of four horizontal lines from among the multiple scan stages included in the scan drive unit.

[0391] Each of the multiple stages STG1 to STG6 may include carry sections CRY1 to CRY6 for outputting carry signals CR1 to CR6, and output sections OUT1 to OUT6 for outputting pull-up control signals PUS1 to PUS6 and pull-down control signals PDS1 to PDS6.

[0392] The carry signals CR1 to CR6, output through the output terminals of each of the multiple carry units CRY1 to CRY6, can be provided to the output units OUT1 to OUT6 of the corresponding stage.

[0393] Furthermore, each of the multiple output units OUT1 to OUT6 can receive one of the multiple control clock signals CCLK1 to CCLK6.

[0394] In one embodiment, the output unit included in the i-th stage (where i is an integer greater than 0) receives the first control clock signal CCLK1, the output unit included in the i+1-th stage receives the second control clock signal CCLK2, the output unit included in the i+2-th stage receives the third control clock signal CCLK3, the output unit included in the i+3-th stage receives the fourth control clock signal CCLK4, the output unit included in the i+4-th stage receives the fifth control clock signal CCLK5, and the output unit included in the i+5-th stage receives the sixth control clock signal CCLK6. For example, the output units included in each stage can receive different signals from the first control clock signal CCLK1 to the sixth control clock signal CCLK6, but are not limited to this.

[0395] For example, the first output unit OUT1 can receive the first control clock signal CCLK1, the second output unit OUT2 can receive the second control clock signal CCLK2, the third output unit OUT3 can receive the third control clock signal CCLK3, the fourth output unit OUT4 can receive the fourth control clock signal CCLK4, the fifth output unit OUT5 can receive the fifth control clock signal CCLK5, and the sixth output unit OUT6 can receive the sixth control clock signal CCLK6.

[0396] In one embodiment, the signal level of at least one of the multiple control clock signals CCLK1 to CCLK6 can be controlled by the drive mode. For example, the signal levels of the multiple control clock signals CCLK1 to CCLK6 can be controlled independently.

[0397] Multiple control clock signals CCLK1 to CCLK6 may have the same period and pulse width, and their phases may not overlap.

[0398] For example, referring further to Figure 21, as described above, when the gate drive unit 2020 is driven in the second mode and multiple control clock signals CCLK1 to CCLK6 perform a toggle operation, the second control clock signal CCLK2 may be set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1, the third control clock signal CCLK3 may be set to a signal shifted by approximately 1 / 2 period from the second control clock signal CCLK2, the fourth control clock signal CCLK4 may be set to a signal shifted by approximately 1 / 2 period from the third control clock signal CCLK3, the fifth control clock signal CCLK5 may be set to a signal shifted by approximately 1 / 2 period from the fourth control clock signal CCLK4, and the sixth control clock signal CCLK6 may be set to a signal shifted by approximately 1 / 2 period from the fifth control clock signal CCLK5. For example, the phase shift between adjacent control clock signals is not limited to 1 / 2 cycle, but may be a variety of values ​​such as 1 / 6 cycle, 1 / 4 cycle, 1 cycle, etc., but is not limited to these. For example, control clock signals whose phase has been shifted by approximately 1 / 2 period may be adjacent signals or non-adjacent signals, but are not limited to this.

[0399] That is, the first control clock signal CCLK1, the third control clock signal CCLK3, and the fifth control clock signal CCLK5 are set to have substantially the same waveform with a difference of a multiple of one period, and the second control clock signal CCLK2, the fourth control clock signal CCLK4, and the sixth control clock signal CCLK6 may have substantially the same waveform with a difference of a multiple of one period.

[0400] In one embodiment, the signal level of at least one of the multiple control clock signals CCLK1 to CCLK6 can be controlled by the drive mode. For example, the signal levels of the multiple control clock signals CCLK1 to CCLK6 can be controlled independently.

[0401] This allows for the control of the signal levels of multiple pull-up control signals PUS1-PUS6 and multiple pull-down control signals PDS1-PDS6 output from multiple output units OUT1-OUT6.

[0402] On the other hand, the first carry unit CRY1 included in the first stage STG1 can also receive the light emission start signal EVST, which is substantially similar to what was explained with reference to Figure 6b.

[0403] Figure 22 is a block diagram showing yet another example of the gate drive unit in Figure 5.

[0404] Figure 23 is a waveform diagram showing an example of a control clock signal provided to the gate drive unit in Figure 22.

[0405] On the other hand, the gate drive unit 2220 shown in Figure 22 represents a modified embodiment of the gate drive unit 620, which includes the output control unit SCTR1 described with reference to Figure 6a in relation to the connection relationship between the output control unit SCTR6 and the light-emitting drive unit EDV, and the multiple control clock signals CCLK1 to CCLK10 connected to the output control unit SCTR6 and their connection relationships. For the sake of clarity, redundant explanations will not be repeated.

[0406] On the other hand, Figure 22 shows only the output control unit SCTR6 in relation to the various configurations included in the gate drive unit 2220, and shows 10 stages STG1 to STG10 among the multiple stages included in the output control unit SCTR6, and multiple pull-up control signals PUS1 to PUS10 and multiple pull-down control signals PDS1 to PDS10 output from them.

[0407] Referring to Figure 22, the gate drive unit 2220 according to one embodiment of this specification may include an output control unit SCTR6.

[0408] The output control unit SCTR6 may include multiple stages STG1 to STG10. These multiple stages STG1 to STG10 can output multiple pull-up control signals PUS1 to PUS10 and multiple pull-down control signals PDS1 to PDS10 based on multiple clock signals CLK1, CLK2 and multiple control clock signals CCLK1 to CCLK10. Here, the multiple stages STG1 to STG10 may have substantially the same configuration.

[0409] In one embodiment, the multiple stages STG1 to STG10 included in the output control unit SCTR6 may be formed in units of at least two horizontal lines. For example, as shown in Figure 22, the multiple stages STG1 to STG10 may be formed in units of two horizontal lines. In this way, in the embodiment of Figure 22, each of the multiple stages STG1 to STG10 included in the output control unit SCTR6 can commonly control two scan stages formed in units of two horizontal lines from among the multiple scan stages included in the scan drive unit.

[0410] Each of the multiple stages STG1 to STG10 may include carry sections CRY1 to CRY10 for outputting carry signals CR1 to CR10, and output sections OUT1 to OUT10 for outputting pull-up control signals PUS1 to PUS10 and pull-down control signals PDS1 to PDS10.

[0411] Each of the multiple carry units CRY1 to CRY10 included in the multiple stages STG1 to STG10 can receive a light emission control signal from the light emission drive unit EDV.

[0412] In one embodiment, the k-th stage (where k is an integer greater than 0) can receive the light emission control signal output from the 2k-1 light emission stage. For example, the first carry unit CRY1 included in the first stage STG1 receives the first light emission control signal EM1 output from the first light emission stage EST1, the second carry unit CRY2 included in the second stage STG2 receives the third light emission control signal EM3 output from the third light emission stage EST3, the third carry unit CRY3 included in the third stage STG3 receives the fifth light emission control signal EM5 output from the fifth light emission stage EST5, the fourth carry unit CRY4 included in the fourth stage STG4 receives the seventh light emission control signal EM7 output from the seventh light emission stage EST7, the fifth carry unit CRY5 included in the fifth stage STG5 receives the ninth light emission control signal EM9 output from the ninth light emission stage EST9, and the sixth stage STG6 includes The sixth carry unit CRY6 receives the 11th light emission control signal EM11 output from the 11th light emission stage EST11, the seventh carry unit CRY7 included in the seventh stage STG7 receives the 13th light emission control signal EM13 output from the 13th light emission stage EST13, the eighth carry unit CRY8 included in the eighth stage STG8 receives the 15th light emission control signal EM15 output from the 15th light emission stage EST15, the ninth carry unit CRY9 included in the ninth stage STG9 receives the 17th light emission control signal EM17 output from the 17th light emission stage EST17, and the tenth carry unit CRY10 included in the tenth stage STG10 receives the 19th light emission control signal EM19 output from the 19th light emission stage EST19.

[0413] In this way, each of the multiple stages STG1 to STG10 controls two scan stages formed in units of two horizontal lines, so that each of the multiple carry units CRY1 to CRY10 included in each of the multiple stages STG1 to STG10 can receive a light emission control signal from one of the two light emission stages formed in units of two horizontal lines.

[0414] On the other hand, as substantially similar to what is described with reference to Figure 6b, the first carry unit CRY1 included in the first stage STG1 can also receive the light emission start signal EVST. In this case, for the remaining stages excluding the first stage STG1, the lth stage (where l is an integer greater than 1) can receive the light emission control signal output from the second (l-1) light emission stage.

[0415] The carry signals CR1 to CR10, output through the output terminals of each of the multiple carry units CRY1 to CRY10, can be provided to the output units OUT1 to OUT10 of the corresponding stage.

[0416] Furthermore, each of the multiple output units OUT1 to OUT10 can receive one of the multiple control clock signals CCLK1 to CCKL10.

[0417] In one embodiment, the output unit included in the i-th stage (where i is an integer greater than 0) receives the first control clock signal CCLK1, the output unit included in the i+1-th stage receives the second control clock signal CCLK2, the output unit included in the i+2-th stage receives the third control clock signal CCLK3, the output unit included in the i+3-th stage receives the fourth control clock signal CCLK4, the output unit included in the i+4-th stage receives the fifth control clock signal CCLK5, the output unit included in the i+5-th stage receives the sixth control clock signal CCLK6, the output unit included in the i+6-th stage receives the seventh control clock signal CCLK7, the output unit included in the i+7-th stage receives the eighth control clock signal CCLK8, the output unit included in the i+8-th stage receives the ninth control clock signal CCLK9, and the output unit included in the i+9-th stage receives the tenth control clock signal CCLK10. For example, the order of the stages and the order of the control clock signals can be changed in various ways.

[0418] For example, the first output unit OUT1 can receive the first control clock signal CCLK1, the second output unit OUT2 can receive the second control clock signal CCLK2, the third output unit OUT3 can receive the third control clock signal CCLK3, the fourth output unit OUT4 can receive the fourth control clock signal CCLK4, the fifth output unit OUT5 can receive the fifth control clock signal CCLK5, the sixth output unit OUT6 can receive the sixth control clock signal CCLK6, the seventh output unit OUT7 can receive the seventh control clock signal CCLK7, the eighth output unit OUT8 can receive the eighth control clock signal CCLK8, the ninth output unit OUT9 can receive the ninth control clock signal CCLK9, and the tenth output unit OUT10 can receive the tenth control clock signal CCLK10.

[0419] Multiple control clock signals CCLK1 to CCLK10 may have the same period and pulse width, and their phases may not overlap.

[0420] For example, referring further to Figure 23, as mentioned above, when the gate drive unit 2220 is driven in the second mode and multiple control clock signals CCLK1 to CCLK10 perform toggle operation, the second control clock signal CCLK2 is set to a signal shifted by approximately 1 / 2 period from the first control clock signal CCLK1, the third control clock signal CCLK3 is set to a signal shifted by approximately 1 / 2 period from the second control clock signal CCLK2, the fourth control clock signal CCLK4 is set to a signal shifted by approximately 1 / 2 period from the third control clock signal CCLK3, and the fifth control clock signal CCLK5 is set to a signal shifted by approximately 1 / 2 period from the fourth control clock signal CCLK4. The signals may be set to shifted signals, with the 6th control clock signal CCLK6 being set to a signal shifted by approximately 1 / 2 period from the 5th control clock signal CCLK5, the 7th control clock signal CCLK7 being set to a signal shifted by approximately 1 / 2 period from the 6th control clock signal CCLK6, the 8th control clock signal CCLK8 being set to a signal shifted by approximately 1 / 2 period from the 7th control clock signal CCLK7, the 9th control clock signal CCLK9 ​​being set to a signal shifted by approximately 1 / 2 period from the 8th control clock signal CCLK8, and the 10th control clock signal CCLK10 being set to a signal shifted by approximately 1 / 2 period from the 9th control clock signal CCLK9.

[0421] That is, the first control clock signal CCLK1, the third control clock signal CCLK3, the fifth control clock signal CCLK5, the seventh control clock signal CCLK7, and the ninth control clock signal CCLK9 ​​are set to have a difference of a multiple of one period and have substantially the same waveform, and the second control clock signal CCLK2, the fourth control clock signal CCLK4, the sixth control clock signal CCLK6, the eighth control clock signal CCLK8, and the tenth control clock signal CCLK10 may have substantially the same waveform when set to have a difference of a multiple of one period.

[0422] In one embodiment, the signal level of at least one of the multiple control clock signals CCLK1 to CCLK10 can be controlled by the drive mode. For example, the signal levels of the multiple control clock signals CCLK1 to CCLK10 can be controlled independently.

[0423] This allows for the control of the signal levels of multiple pull-up control signals PUS1 to PUS10 and multiple pull-down control signals PDS1 to PDS10 output from multiple output units OUT1 to OUT10.

[0424] Figure 24 is a block diagram showing a gate drive unit according to one embodiment of this specification.

[0425] Figure 25 is a circuit diagram showing an example of the first selection stage of the voltage selection unit included in the gate drive unit of Figure 24.

[0426] Figures 26a to 26c are waveform diagrams illustrating an example of driving the first selection stage in Figure 25.

[0427] On the other hand, the gate drive unit 2420 shown in Figure 24 is a modified embodiment in relation to the voltage selection unit VSEL. Therefore, for the sake of clarity, redundant explanations will not be repeated.

[0428] On the other hand, Figures 26a to 26c show various signals input for driving the pixel PX, as explained with reference to Figure 3, along with the pull-up control signal PUS1 and the bias voltage Vobs1, in order to explain the operation of the voltage selector VSEL.

[0429] Referring to Figure 24, the gate drive unit 2420 according to one embodiment of this specification may include an output control unit SCTR and a voltage selection unit VSEL.

[0430] Depending on the embodiment, the output control unit SCTR may be embodied in any one of the following: output control unit SCTR1 described with reference to Figure 6a, output control unit SCTR2 described with reference to Figure 15, output control unit SCTR3 described with reference to Figure 16, output control unit SCTR4 described with reference to Figure 18, output control unit SCTR5 described with reference to Figure 20, and output control unit SCTR6 described with reference to Figure 22. That is, each of the multiple stages STG1 to STG3 included in the output control unit SCTR can output pull-up control signals PUS1 to PUS3 and pull-down control signals PDS1 to PDS3.

[0431] The voltage selector VSEL may include multiple selection stages VSG1 to VSG3. These multiple selection stages VSG1 to VSG3 can output multiple bias voltages Vobs1 to Vobs3 based on multiple pull-up control signals PUS1 to PUS4, multiple pull-down control signals PDS1 to PDS4, a first voltage V1, and a second voltage V2.

[0432] In one embodiment, the multiple selection stages VSG1 to VSG3 included in the voltage selection unit VSEL can be cascaded.

[0433] For example, the second selection stage VSG2 may be cascaded to the first selection stage VSG1, and the third selection stage VSG3 may be connected to the second selection stage VSG2. Here, multiple selection stages VSG1 to VSG3 may have substantially the same configuration.

[0434] In one embodiment, each of the multiple selection stages VSG1 to VSG3 can output one of the first voltage V1 and the second voltage V2 as a bias voltage Vbos1 to Vobs3 based on the pull-up control signals PUS1 to PUS3 and the pull-down control signals PDS1 to PDS3 provided to the selection stage.

[0435] More specifically, referring further to Figure 25, and using the first selection stage VSG1 as a reference among the multiple selection stages VSG1 to VSG3, the first selection stage VSG1 can receive the first pull-up control signal PUS1 through the first selection input terminal 2501, for example, the first selection input terminal 2501 which is connected to the second output terminal 726 of the first output unit OUT1 included in the first stage STG1 of the output control unit SCTR1, and can receive the first pull-down control signal PDS1 through the second selection input terminal 2502, for example, the second selection input terminal 2502 which is connected to the third output terminal 727 of the first output unit OUT1 included in the first stage STG1 of the output control unit SCTR1.

[0436] The first selection stage VSG1 can output a first bias voltage Vobs1, which is either a first voltage V1 supplied from the first voltage terminal 2508 or a second voltage V2 supplied from the second voltage terminal 2509, based on the signal levels of the first pull-up control signal PUS1 and the first pull-down control signal PDS1.

[0437] For this purpose, the first selection stage VSG1 may include a first selection transistor VT1 and a second selection transistor VT2. In one embodiment, the first selection stage VSG1 may further include an auxiliary capacitor VC connected between the first selection input terminal 2501 and the first voltage terminal 2508.

[0438] The first selection transistor VT1 may include a gate electrode connected between the first voltage terminal 2508 and the voltage output terminal 2503, and connected to the first selection input terminal 2501, to which the first pull-up control signal PUS1 is provided.

[0439] The first selection transistor VT1 is turned on when the first pull-up control signal PUS1 is at a gate-on level, for example, a low level, and can output the first voltage V1 provided from the first voltage terminal 2508 to the voltage output terminal 2503. That is, when the first selection transistor VT1 is turned on, the first bias voltage Vobs1 may have a voltage level equal to the first voltage V1.

[0440] The second selection transistor VT2 may include a gate electrode connected between the second voltage terminal 2509 and the voltage output terminal 2503, and connected to the second selection input terminal 2502, which is provided with the first pull-down control signal PDS1.

[0441] The second selection transistor VT2 is turned on when the first pull-down control signal PDS1 has a gate-on level, for example, a low level, and can output a second voltage V2 provided from the second voltage terminal 2509 to the voltage output terminal 2503. That is, when the second selection transistor VT2 is turned on, the first bias voltage Vobs1 may have a voltage level equal to the second voltage V2.

[0442] In one embodiment, the voltage levels of the first voltage V1 and the second voltage V2 may be different. For example, as mentioned above, the bias voltage Vobs is a voltage for controlling the drive transistor DT included in the pixel PX to an on-bias state, and both the first voltage V1 and the second voltage V2 have positive voltage levels, and the voltage level of the first voltage V1 may be higher than the voltage level of the second voltage V2.

[0443] Referring more specifically to Figures 26a and 26b, as shown in Figure 26a, during the first display period DP1, for example, when the output control unit SCTR is driven in the first mode and the first pull-up control signal PUS1 has a low level L which is the gate-on level, the first selected transistor VT1 may be turned on by the low-level L first pull-up control signal PUS1, and the second selected transistor VT2 may be turned off by the high-level H first pull-down control signal PDS1.

[0444] As a result, the first selection stage VSG1 outputs a first bias voltage Vobs1 of the first voltage V1 through the voltage output terminal 2503, and the first bias voltage Vobs1 of the first voltage V1 can be supplied to the drive transistor DT of the pixel PX by the seventh switching transistor M7, which is turned on in the section where the third scan signal SCAN3 has a gate-on level, for example, a low level L.

[0445] Furthermore, as shown in Figure 26b, during the second display period DP2, for example, when the output control unit SCTR is driven in the second mode and the first pull-up control signal PUS1 has a high-level H pulse that is at least partially gate-off level, the second selected transistor VT2 may be turned on by the first pull-down control signal PDS1 having a low-level L pulse, and the first selected transistor VT1 may be turned off by the first pull-up control signal PUS1 having a high-level H pulse during the same period.

[0446] As a result, the first selection stage VSG1 outputs a first bias voltage Vobs1 of the second voltage V2 through the voltage output terminal 2503, and the first bias voltage Vobs1 of the second voltage V2 can be supplied to the drive transistor DT of the pixel PX by the seventh switching transistor M7, which is turned on in the section where the third scan signal SCAN3 has a gate-on level, for example, a low level L.

[0447] Here, when the display device 100 controls the drive frequency for each sub-display area of ​​the display area AA, a change in the drive frequency may cause a change in brightness for each sub-display area due to the difference in the characteristics of the threshold voltage (Vth) of the drive transistor DT.

[0448] As a result, when the gate drive unit 2420 according to one embodiment of this specification controls the drive frequency for each sub-display area of ​​the display area AA, the voltage level of the bias voltage Vobs for the threshold voltage shift of the drive transistor DT is controlled differently for the first display period DP1 and the second display period DP2, for example, the first mode and the second mode, thereby improving the variation in the threshold voltage characteristics of the drive transistor DT due to changes in the drive frequency. As a result, even if the drive frequency is controlled differently for each sub-display area of ​​the display area AA, the display quality does not deteriorate.

[0449] In the embodiment, in order to apply the first bias voltage Vobs1 of the second voltage V2 to the pixel PX through the seventh switching transistor M7, which is turned on during the interval in which the third scan signal SCAN3 has a gate-on level, the high-level H pulse of the first pull-up control signal PUS1 may superimpose at least a portion of the low-level L pulse of the third scan signal SCAN3. For example, the high-level H pulse of the first pull-up control signal PUS1 may superimpose all of the two low-level L pulses contained in the third scan signal SCAN3.

[0450] However, it is not limited to this, and referring to Figure 26c, the high-level H pulse of the first pull-up control signal PUS1 may be superimposed on one of the two low-level L pulses included in the third scan signal SCAN3. In this case, during some sections of the second display period DP2, the first bias voltage Vobs1 of the second voltage V2 may be supplied to the pixel PX, and during other sections, the first bias voltage Vobs1 of the first voltage V1 may be supplied to the pixel PX. In this way, the average voltage level of the bias voltage Vobs applied to the pixel PX can be controlled by adjusting the pulse width of the high-level H pulse of the first pull-up control signal PUS1.

[0451] On the other hand, as mentioned above, the output control unit SCTR included in the gate drive unit 2420 shown in Figure 24 can be embodied in any one of the following: output control unit SCTR1 described with reference to Figure 6a, output control unit SCTR2 described with reference to Figure 15, output control unit SCTR3 described with reference to Figure 16, output control unit SCTR4 described with reference to Figure 18, output control unit SCTR5 described with reference to Figure 20, and output control unit SCTR6 described with reference to Figure 22. As a result, the pull-up control signals PUS1 to PUS3 and pull-down control signals PDS1 to PDS3 output from each of the multiple stages STG1 to STG3 of the output control unit SCTR are formed in units of at least two horizontal lines, so that each of the multiple selection stages VSG1 to VSG3 included in the voltage selection unit VSEL can provide bias voltages Vobs1 to Vobs3 to multiple pixels PX formed in units of at least two horizontal lines corresponding to the output control unit SCTR.

[0452] Figure 27 is a waveform diagram illustrating another example of pixel driving in Figure 3.

[0453] For example, the waveform diagram shown in Figure 27 illustrates a modified version of the waveform diagram described with reference to Figure 26b.

[0454] Referring to Figures 3, 24, and 27, as described above, during the second display period DP2, for example, during the period when the output control unit SCTR is driven in the second mode and the first pull-up control signal PUS1 has a high-level H pulse that is gate-off level for at least a portion of the interval, the first bias voltage Vobs1 of the second voltage V2 output from the first selection stage VSG1 can be supplied to the pixel PX.

[0455] However, in some cases, even if the first bias voltage Vobs1 is supplied to the pixel PX, for example, the drive transistor DT, the degree of threshold voltage shift may not be sufficient. In this case, the hysteresis characteristics may not be improved.

[0456] In one embodiment, during the second display period DP2, the second scan signal SCAN2 supplied to the second scan wiring SL2 may have a gate-on level pulse, for example, a low level L, and the data signal Vdata supplied to the data wiring DL may have a parking voltage Vpobs, where the parking voltage Vpobs may have a voltage level corresponding to the bias voltage Vobs.

[0457] As a result, during the second display period DP2, a data signal Vdata with a parking voltage Vpobs is supplied to the first electrode of the drive transistor DT, for example, the source electrode, through the first switching transistor M1 which is turned on by the second scan signal SCAN2, so that the drive transistor DT has an on-bias state, and the hysteresis characteristics can be more effectively improved.

[0458] As described above, in the case of a gate drive unit and a display device including the same according to one embodiment of this specification, the gate drive unit may include an output control unit for controlling the output level of the gate signal output from the scan drive unit.

[0459] As a result, the gate drive unit and the display device including it according to one embodiment of this specification are not limited to a fixed area, but can freely divide the display area in accordance with the displayed image and control the drive frequency for each area. As a result, power consumption can be improved because the drive frequency is controlled in accordance with the display area.

[0460] Furthermore, the gate drive unit according to one embodiment of this specification does not include a separate control unit for controlling the signal level of the gate signals output from the multiple scan drive units, but instead uses an output control unit that is commonly connected to the multiple scan drive units to control the signal level of the gate signals. Therefore, the size of the bezel area in which the gate drive unit is located can be minimized.

[0461] Furthermore, the gate drive unit according to one embodiment of this specification may include a voltage selection unit for controlling the voltage level of the bias voltage for controlling the on-bias state of the pixels according to the drive frequency for each display area. This prevents a decrease in display quality even if the drive frequency is controlled differently for each sub-display area of ​​the display area.

[0462] The gate drive unit according to the embodiments of this specification can be described as follows.

[0463] An embodiment of the present invention may include a light-emitting drive unit comprising a plurality of light-emitting stages connected in cascade and outputting a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals, and an output control unit comprising a plurality of stages connected in cascade and outputting a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light-emitting control signal from the plurality of light-emitting control signals, at least one clock signal from the plurality of clock signals, a first power supply and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, a first power supply and a second power supply.

[0464] According to other features of this specification, the gate drive unit may further include a scan drive unit which includes a plurality of gate stages connected in cascade and output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, and a plurality of pull-up control signals and a plurality of pull-down control signals.

[0465] According to other features of this specification, the signal levels of multiple gate signals can be controlled based on multiple pull-up control signals and multiple pull-down control signals.

[0466] According to other features of this specification, each of the multiple pull-up control signals and each of the multiple pull-down control signals may have opposite phases.

[0467] According to other features of this specification, each of the multiple control clock signals may have a waveform that is toggling between gate-on and gate-off levels or maintained at the gate-on level.

[0468] According to other features of this specification, the scan drive unit may output a gate signal having a gate-on pulse in a section in which at least one control clock signal has a gate-on level, and the scan drive unit may output a gate signal that is maintained at a gate-off level in a section in which at least one control clock signal toggles between a gate-on level and a gate-off level.

[0469] According to another feature of this specification, the gate stages are divided into gate stage groups, and each of the gate stage groups can receive the same pull-up control signal from among multiple pull-up control signals and the same pull-down control signal from among multiple pull-down control signals.

[0470] According to other features of this specification, the carry section may include a first transistor having a gate electrode connected between a first input terminal to which an illumination control signal is provided and a first control node, and connected to a second input terminal to which at least one clock signal is provided; a second transistor having a gate electrode connected between a second control node and a first power input terminal to which the voltage of a first power supply is supplied, and connected to the first input terminal; a third transistor having a gate electrode connected between a second input terminal and a first QB node, and connected to the second control node; a fourth transistor having a gate electrode connected between a first power input terminal and a first QB node, and connected to the first control node; a fifth transistor having a gate electrode connected between a second power input terminal to which the voltage of a second power supply is supplied and a first output terminal to which a carry signal is output, and connected to a first Q node; a sixth transistor having a gate electrode connected between a first power input terminal and a first output terminal, and connected to a first QB node; a first bridge voltage transistor having a gate electrode connected between a first control node and a first Q node, and connected to a second power input terminal; and a first capacitor connected between a second input terminal and a second control node.

[0471] According to other features of this specification, the carry section may further include a second capacitor connected between the first Q node and the first output terminal, and a third capacitor connected between the first QB node and the first power input terminal.

[0472] According to other features of this specification, the output section includes a seventh transistor with a gate electrode connected between a third input terminal to which a carry signal is provided and a third control node, and connected to a fourth input terminal to which at least one control clock signal is provided; an eighth transistor with a gate electrode connected between a fourth control node and a first power input terminal to which the voltage of the first power supply is supplied, and connected to a third input terminal; a ninth transistor with a gate electrode connected between a fourth input terminal and a second QB node, and connected to a fourth control node; and a tenth transistor with a gate electrode connected between a first power input terminal and a second QB node, and connected to a third control node. The circuit includes an 11th transistor with a gate electrode connected to the 2nd Q node and connected between the 2nd power supply input terminal to which the voltage of the 2nd power supply is supplied and the 2nd output terminal to which a pull-up control signal is output, and a 12th transistor with a gate electrode connected to the 2nd QB node and connected between the 1st power supply input terminal and the 2nd output terminal, and a 2nd bridge voltage transistor with a gate electrode connected to the 2nd power supply input terminal and connected between the 3rd control node and the 2nd Q node, and a 4th capacitor connected between the 4th input terminal and the 4th control node, and a pull-down control signal may be output through the 3rd output terminal connected to the 2nd QB node.

[0473] According to other features of this specification, the output section may further include a fifth capacitor connected between the second Q node and the second output terminal, and a sixth capacitor connected between the second QB node and the first power input terminal.

[0474] According to other features of this specification, each of the multiple gate stages may include a gate signal generation unit that controls the voltage of an output node based on a gate start signal, multiple gate clock signals, a first power supply and a second power supply, and a masking unit that controls the signal level of a gate signal based on a pull-up control signal and a pull-down control signal.

[0475] According to other features of this specification, the masking section may include a first masking transistor connected between the output node and the gate output terminal from which the gate signal is output, and including a gate electrode that receives a pull-up control signal, and a second masking transistor connected between the gate output terminal and the first power supply input terminal to which the voltage of the first power supply is supplied, or between the gate output terminal and the second power supply input terminal to which the voltage of the second power supply is supplied, and including a gate electrode that receives a pull-down control signal.

[0476] According to other features of this specification, the gate drive unit may further include a voltage selection unit which includes a plurality of selection stages that are cascaded and output a plurality of bias voltages based on a plurality of pull-up control signals, a plurality of pull-down control signals, a first voltage, and a second voltage having a different voltage level from the first voltage.

[0477] According to other features of this specification, based on a plurality of pull-up control signals and a plurality of pull-down control signals, a plurality of bias voltages may have the voltage level of a first voltage or the voltage level of a second voltage.

[0478] According to other features of this specification, the voltage selector may include a first selector transistor connected between a first voltage terminal to which a first voltage is supplied and a voltage output terminal to which a bias voltage is output, and including a gate electrode that receives a pull-up control signal, and a second selector transistor connected between the voltage output terminal and a second voltage terminal to which a second voltage is supplied, and including a gate electrode that receives a pull-down control signal.

[0479] An embodiment of the gate drive unit according to this specification may include an output control unit including a plurality of stages connected in cascade and outputting a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply, and a scan drive unit including a plurality of gate stages connected in cascade and outputting a plurality of gate signals based on a gate start signal, a plurality of gate clock signals and a plurality of pull-up control signals and a plurality of pull-down control signals. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light emission control signal from a plurality of light emission control signals, at least one clock signal from a plurality of clock signals, a first power supply and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from a plurality of control clock signals, a first power supply and a second power supply.

[0480] The display devices according to the embodiments of this specification can be described as follows.

[0481] An embodiment of the Specified Information includes a display panel containing a plurality of pixels, a scan drive unit that outputs a plurality of gate signals to the plurality of pixels, a light-emitting drive unit that outputs a plurality of light-emitting control signals to the plurality of pixels, and an output control unit that includes a plurality of stages that output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light-emitting control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the plurality of stages may include a carry unit that outputs a carry signal based on at least one light-emitting control signal from the plurality of light-emitting control signals, at least one clock signal from the plurality of clock signals, a first power supply, and a second power supply, and an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, a first power supply, and a second power supply.

[0482] According to other features of this specification, the signal levels of multiple gate signals can be controlled based on multiple pull-up control signals and multiple pull-down control signals.

[0483] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. A light-emitting drive unit including a plurality of cascaded light-emitting stages, wherein the plurality of light-emitting stages output a plurality of light-emitting control signals based on a light-emitting start signal and a plurality of light-emitting clock signals, An output control unit including a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. A scan drive unit including a plurality of cascaded gate stages, wherein the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, a plurality of pull-up control signals, and a plurality of pull-down control signals. Includes, Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and A gate drive unit including an output unit that outputs the pull-up control signal and the pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply and the second power supply.

2. The gate drive unit according to claim 1, wherein the signal levels of the plurality of gate signals are controlled based on the plurality of pull-up control signals and the plurality of pull-down control signals.

3. The gate drive unit according to claim 2, wherein each of the plurality of pull-up control signals and each of the plurality of pull-down control signals have opposite phases to each other.

4. The gate drive unit according to claim 1, wherein each of the plurality of control clock signals has a waveform that toggles between a gate-on level and a gate-off level or is maintained at a gate-on level.

5. In the interval where at least one control clock signal has a gate-on level, the scan drive unit outputs the gate signal having a gate-on level pulse. The gate drive unit according to claim 4, wherein, in the interval in which the at least one control clock signal toggles between a gate-on level and a gate-off level, the scan drive unit outputs the gate signal which is maintained at the gate-off level.

6. The aforementioned multiple gate stages are divided into multiple gate stage groups, The gate drive unit according to claim 1, wherein each of the plurality of gate stage groups receives the same pull-up control signal from the plurality of pull-up control signals and receives the same pull-down control signal from the plurality of pull-down control signals.

7. The aforementioned carrying section is, A first transistor including a gate electrode connected between a first input terminal to which the light emission control signal is provided and a first control node, and connected to a second input terminal to which at least one clock signal is provided, A second transistor, which includes a gate electrode connected to the first input terminal and connected to the first input terminal, is connected between the second control node and the first power supply input terminal to which the voltage of the first power supply is supplied. A third transistor including a gate electrode connected between the second input terminal and the first QB node and connected to the second control node, A fourth transistor, including a gate electrode connected between the first power input terminal and the first QB node and connected to the first control node, A fifth transistor, including a gate electrode connected to the first Q node, is connected between the second power input terminal to which the voltage of the second power supply is supplied and the first output terminal to which the carry signal is output. A sixth transistor, including a gate electrode connected between the first power input terminal and the first output terminal and connected to the first QB node, A first bridge voltage transistor, which includes a gate electrode connected between the first control node and the first Q node and connected to the second power input terminal, and The gate drive unit according to claim 1, further comprising a first capacitor connected between the second input terminal and the second control node.

8. The aforementioned carrying section is, A second capacitor connected between the first Q node and the first output terminal, and The gate drive unit according to claim 7, further comprising a third capacitor connected between the first QB node and the first power input terminal.

9. The output unit is, A seventh transistor including a gate electrode connected between the third input terminal to which the carry signal is provided and the third control node, and connected to the fourth input terminal to which at least one control clock signal is provided, An eighth transistor, including a gate electrode connected between the fourth control node and the first power input terminal to which the voltage of the first power supply is supplied, and which is connected to the third input terminal, A ninth transistor, which includes a gate electrode connected between the fourth input terminal and the second QB node and connected to the fourth control node, A tenth transistor, including a gate electrode connected between the first power input terminal and the second QB node and connected to the third control node, An eleventh transistor, including a gate electrode connected to the second Q node, is connected between the second power input terminal to which the voltage of the second power supply is supplied and the second output terminal to which the pull-up control signal is output. A twelfth transistor, including a gate electrode connected between the first power input terminal and the second output terminal and connected to the second QB node, A second bridge voltage transistor, which includes a gate electrode connected between the third control node and the second Q node and connected to the second power input terminal, and It includes a fourth capacitor connected between the fourth input terminal and the fourth control node, The gate drive unit according to claim 1, wherein the pull-down control signal is output through a third output terminal connected to the second QB node.

10. The output unit is, A fifth capacitor connected between the second Q node and the second output terminal, and The gate drive unit according to claim 9, further comprising a sixth capacitor connected between the second QB node and the first power input terminal.

11. Each of the aforementioned multiple gate stages is A gate signal generation unit that controls the voltage of the output node based on the gate start signal, the plurality of gate clock signals, the first power supply and the second power supply, and The gate drive unit according to claim 1, further comprising a masking unit that controls the signal level of the gate signal based on the pull-up control signal and the pull-down control signal.

12. The aforementioned masking portion is A first masking transistor, which includes a gate electrode that receives the pull-up control signal, is connected between the output node and the gate output terminal to which the gate signal is output, and The gate drive unit according to claim 11, further comprising a second masking transistor connected between the gate output terminal and a first power input terminal to which the voltage of the first power supply is supplied, or between the gate output terminal and a second power input terminal to which the voltage of the second power supply is supplied, and including a gate electrode that receives the pull-down control signal.

13. The gate drive unit according to claim 1, further comprising a voltage selection unit including a plurality of cascaded selection stages, wherein the plurality of selection stages are configured to output a plurality of bias voltages based on a plurality of pull-up control signals, a plurality of pull-down control signals, a first voltage, and a second voltage having a voltage level different from the first voltage, wherein the plurality of bias voltages are voltages supplied to the drive transistor of a pixel to control the drive transistor of the pixel in an on-bias state.

14. The gate drive unit according to claim 13, wherein, based on the plurality of pull-up control signals and the plurality of pull-down control signals, the plurality of bias voltages have the voltage level of the first voltage or the voltage level of the second voltage.

15. The aforementioned voltage selection unit is A first selection transistor, which includes a gate electrode that receives the pull-up control signal, is connected between a first voltage terminal to which the first voltage is supplied and a voltage output terminal to which the bias voltage is output, and The gate drive unit according to claim 13, further comprising a second selection transistor connected between the voltage output terminal and the second voltage terminal to which the second voltage is supplied, and including a gate electrode that receives the pull-down control signal.

16. An output control unit including a plurality of cascaded stages, wherein the plurality of stages output a plurality of pull-up control signals and a plurality of pull-down control signals based on a plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply and a second power supply having a lower voltage level than the first power supply, and A scan drive unit including a plurality of cascaded gate stages, wherein the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, a plurality of pull-up control signals, and a plurality of pull-down control signals, Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and A gate drive unit including an output unit that outputs a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply and the second power supply.

17. Display panel containing multiple pixels, A scan drive unit that outputs multiple gate signals to the multiple pixels, A light-emitting drive unit that outputs multiple light-emitting control signals to the multiple pixels, and The output control unit includes a plurality of stages that output a plurality of pull-up control signals and a plurality of pull-down control signals based on the plurality of light emission control signals, a plurality of clock signals, a plurality of control clock signals, a first power supply, and a second power supply having a lower voltage level than the first power supply. Each of the aforementioned multiple stages is A carry unit that outputs a carry signal based on at least one of the plurality of light emission control signals, at least one clock signal from the plurality of clock signals, the first power supply and the second power supply, and The output unit includes outputting a pull-up control signal and a pull-down control signal based on the carry signal, at least one control clock signal from the plurality of control clock signals, the first power supply, and the second power supply. A display device in which the scan drive unit includes a plurality of cascaded gate stages, the plurality of gate stages output a plurality of gate signals based on a gate start signal, a plurality of gate clock signals, a plurality of pull-up control signals, and a plurality of pull-down control signals.

18. The display device according to claim 17, wherein each of the plurality of pull-up control signals and each of the plurality of pull-down control signals have opposite phases to each other.

19. The display area of ​​the aforementioned display panel is divided into a plurality of sub-display areas. The display device according to claim 17, wherein the scan drive unit outputs gate signals that are different from each other according to the plurality of sub-display areas.

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