Semiconductor equipment
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2024-02-15
- Publication Date
- 2026-08-07
Smart Images

Figure 0007902350000001 
Figure 0007902350000002 
Figure 0007902350000003
Abstract
Description
[Technical Field]
[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]
[0002] In semiconductor devices having Schottky barrier diodes, there is a need to improve their characteristics. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Publication No. 2023-45865 [Overview of the Initiative] [Problems that the invention aims to solve]
[0004] Embodiments of the present invention provide a semiconductor device capable of improving its characteristics. [Means for solving the problem]
[0005] According to one embodiment, the semiconductor device comprises a first electrode, a second electrode, a first semiconductor portion of a first conductivity type provided between the first electrode and the second electrode, a second semiconductor portion of a second conductivity type, a fourth semiconductor portion of a first conductivity type, and a third electrode. The first semiconductor portion includes a first subregion, a second subregion adjacent to the first subregion in a second direction intersecting a first direction toward the second electrode, a third subregion adjacent to the first subregion in the first direction, a fourth subregion adjacent to the second subregion in a third direction intersecting a plane including the first and second directions, a fifth subregion adjacent to the fourth subregion in the first direction and in Schottky contact with the second electrode, and a sixth subregion adjacent to the second subregion in the first direction and adjacent to the fourth subregion in the third direction, and having a higher impurity concentration of the first conductivity type than the first impurity concentration of the first conductivity type in the first, second, third, fourth, and fifth subregions. The second semiconductor portion is provided between the sixth subregion and the second electrode and is adjacent to the third subregion in the second direction. The fourth semiconductor portion is provided between the second semiconductor portion and the second electrode and is electrically connected to the second electrode. The third electrode is provided so as to face the third partial region and the second semiconductor portion via the first insulating portion. [Brief explanation of the drawing]
[0006] [Figure 1] A schematic perspective view illustrating an example of a semiconductor device according to this embodiment. [Figure 2] A diagram showing a part of the semiconductor device in Figure 1. [Figure 3] A diagram showing a part of the semiconductor device in Figure 1. [Figure 4] A diagram showing a part of the semiconductor device in Figure 1. [Figure 5] A diagram showing a part of the semiconductor device in Figure 1. [Figure 6] Figure 1 shows an example of a side view of a semiconductor device. [Modes for carrying out the invention]
[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each figure, elements similar to those described above with respect to the previously presented figures are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.
[0008] FIG. 1 is a schematic perspective view schematically showing an example of a semiconductor device 100. FIGS. 2 to 5 are views showing a part of the semiconductor device 100 of FIG. 1. FIG. 2 is a view showing a semiconductor part 110 which is a part of the semiconductor device 100. FIG. 3 is a view showing a semiconductor part 120 which is a part of the semiconductor device 100. FIG. 4 is a view showing a semiconductor part 130 which is a part of the semiconductor device 100. FIG. 5 is a view showing a semiconductor part 140 which is a part of the semiconductor device 100. FIG. 6 is a view showing an example of a side surface of the semiconductor device 100 of FIG. 1.
[0009] The semiconductor device 100 includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor part 11, a second semiconductor part 12, a third semiconductor part 13, and a fourth semiconductor part 14. The semiconductor device 100 may include a fifth semiconductor part 15, a silicide layer 16, and a first insulating part 41. The first semiconductor part 11, the second semiconductor part 12, the third semiconductor part 13, and the fourth semiconductor part 14 contain SiC. The first semiconductor part 11, the second semiconductor part 12, the third semiconductor part 13, and the fourth semiconductor part 14 may contain at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC. These semiconductor parts contain crystals. These semiconductor parts may contain silicon. These semiconductor parts may contain a compound semiconductor containing Ga.
[0010] The direction from the first electrode 51 to the second electrode 52 is defined as the first direction D1. One direction perpendicular to the first direction D1 is defined as the second direction D2. The direction perpendicular to the first direction D1 and the second direction D2 is defined as the third direction D3.
[0011] Figures 2 to 5 show the semiconductor device 100 divided along the third direction D3 into a semiconductor portion 110, a semiconductor portion 120, a semiconductor portion 130, and a semiconductor portion 140. Hereinafter, the semiconductor device 100 will be described with reference to FIGS. 1 to 5. In FIGS. 2 to 5, illustration of a fifth semiconductor portion 15 and a first electrode 51, which will be described later, is omitted.
[0012] The first semiconductor portion 11 is provided between a first electrode 51 and a second electrode 52. The first semiconductor portion 11 has a first conductivity type. The first conductivity type is, for example, an n-type.
[0013] The first semiconductor portion 11 includes a first partial region 11a, a second partial region 11b aligned with the first partial region 11a in a second direction intersecting a first direction D1 from the first electrode 51 toward the second electrode 52, a third partial region 11c aligned with the first partial region 11a in the first direction D1, a fourth partial region 11d aligned with the second partial region 11b in a third direction intersecting a plane including the first direction D1 and a second direction D2, a fifth partial region 11e aligned with the fourth partial region 11d in the first direction D1 and in Schottky contact with the second electrode 52, a sixth partial region 11f aligned with the second partial region 11b in the first direction D1, aligned with the fourth partial region 11d in the third direction D3, and having an impurity concentration of the first conductivity type higher than the first impurity concentration of the first conductivity type in the first partial region 11a, the second partial region 11b, the third partial region 11c, the fourth partial region 11d, and the fifth partial region 11e. In the first partial region 11a, the second partial region 11b, the third partial region 11c, the fourth partial region 11d, the fifth partial region 11e, and the sixth partial region 11f, the boundaries may be clear or unclear. The above-mentioned plane extends in the first direction D1 and extends in the second direction D2.
[0014] For example, the first partial region 11a, the second partial region 11b, the third partial region 11c, the fourth partial region 11d, and the fifth partial region 11e are n-regions. The sixth partial region 11f is, for example, n +This is a region. The sixth partial region 11f includes the first stepped portion 11fa. In this embodiment, as shown in Figures 1, 6, etc., the first stepped portion 11fa is formed in a stepped shape relative to the second semiconductor portion 12 in a plane including the first direction D1 and the second direction D2.
[0015] The portion where the fifth partial region 11e and the second electrode 52 make Schottky contact functions as a Schottky barrier diode (SBD). As shown in Figure 1, the second electrode 52 may include a first electrode portion 52a and a second electrode portion 52b. At least a portion of the first electrode portion 52a is provided between the sixth partial region 11f and the second electrode portion 52b in the first direction D1. The first electrode portion 52a may include, for example, Ti. The second electrode portion 52b may include, for example, a metal such as Al.
[0016] The second semiconductor portion 12 is provided between the sixth partial region 11f and the second electrode 52. The second semiconductor portion 12 is aligned with the third partial region 11c in the second direction D2. In this embodiment, the second semiconductor portion 12 is provided on the sixth partial region 11f. Furthermore, in this embodiment, a part of the second semiconductor portion 12 is also provided on the second partial region 11b. The second semiconductor portion 12 is of the second conductivity type. The second conductivity type is, for example, p-type. Note that if the first conductivity type is p-type, the second conductivity type will be n-type. The second semiconductor portion 12 is, for example, p + This is a region. The sixth subregion 11f is located directly below the second semiconductor portion 12.
[0017] As shown in Figures 1 and 6, the second semiconductor portion 12 includes a second stepped portion 12a. In this embodiment, the second stepped portion 12a is formed in a stepped shape relative to the sixth partial region 11f in a plane including the first direction D1 and the second direction D2. In this plane, the second stepped portion 12a and the first stepped portion 11fa face each other. The boundary between the first stepped portion 11fa and the second stepped portion 12a may be clear or unclear.
[0018] The third semiconductor portion 13 is provided between the second semiconductor portion 12 and the second electrode 52. The direction from the third partial region 11c to the third semiconductor portion 13 is along the second direction D2. In this embodiment, the third semiconductor portion 13 is provided on the second semiconductor portion 12. The third semiconductor portion 13 is of the second conductivity type. In this embodiment, it is of the p-type. The impurity concentration of the second conductivity type in the third semiconductor portion 13 is higher than the impurity concentration of the second conductivity type in the second semiconductor portion 12. The third semiconductor portion 13 is, for example, p ++ This is a region. A portion of the third semiconductor portion 13 is electrically connected to the second electrode 52. For example, the third semiconductor portion 13 makes ohmic contact with the second electrode 52. The position where the third semiconductor portion 13 is provided can be determined rationally based on the cell pitch, area, and positional relationship, and for example, it can be provided at the position shown in Figure 1. By providing the third semiconductor portion 13 at the position shown in Figure 1, the photolithography process for providing the third semiconductor portion 13 can be shared with the process for the sixth partial region 11f.
[0019] The fourth semiconductor portion 14 is provided between the third semiconductor portion 13 and the second electrode 52. The fourth semiconductor portion 14 is electrically connected to the second electrode 52. In this embodiment, the fourth semiconductor portion 14 is provided on the second semiconductor portion 12 and on the third semiconductor portion 13. The direction from the third partial region 11c to the fourth semiconductor portion 14 is along the second direction D2. The fourth semiconductor portion 14 is of the first conductivity type. In this embodiment, the first conductivity type is n-type. The impurity concentration of the first conductivity type in the fourth semiconductor portion 14 is higher than the impurity concentration of the first conductivity type in the first semiconductor portion 11. The fourth semiconductor portion 14 is, for example, n ++ This is the region. A portion of the fourth semiconductor part 14 is electrically connected to the second electrode 52. For example, the fourth semiconductor part 14 makes ohmic contact with the second electrode 52.
[0020] The direction from the first partial region 11a to the third electrode 53 is along the first direction D1. A first insulating portion 41 is provided around the third electrode 53. A portion of the first insulating portion 41 is provided between the third partial region 11c and the third electrode 53. The first insulating portion 41 includes, for example, SiO2.
[0021] For example, as shown in Figure 2, a silicide layer 16 is provided on the semiconductor device 100. At least a portion of the silicide layer 16 is provided between the second semiconductor portion 12 and the second electrode 52 in the first direction D1. At least a portion of the silicide layer 16 is provided facing the fourth semiconductor portion 14 in the second direction D2. In this embodiment, the silicide layer 16 is provided on the upper surface of the third semiconductor portion 13 and on the side surface of the fourth semiconductor portion 14.
[0022] As shown in Figure 1, the semiconductor device 100 may further include a first insulating portion 41. The first insulating portion 41 includes a first insulating region 41a. At least a portion of the first insulating region 41a is provided between the third partial region 11c and the third electrode 53. A portion of the first insulating portion 41 may be provided between the fourth semiconductor portion 14 and the third electrode 53.
[0023] A portion of the third electrode 53 is provided on the upper surface of the silicide layer 16. On the upper surface of the fourth semiconductor portion 14, a portion of the third electrode 53 is electrically connected to the fourth semiconductor portion 14 via the first insulating portion 41.
[0024] Furthermore, as shown in Figure 6, for example, an insulating portion 17 may be provided between the fourth semiconductor portion 14, the first insulating portion 41, and the second electrode 52.
[0025] The fifth semiconductor portion 15 is provided between the first electrode 51 and the first semiconductor portion 11 in the first direction D1. The concentration of the fifth impurity of the first conductivity type in the fifth semiconductor portion 15 is higher than the concentration of the first impurity in the first semiconductor portion 11. The fifth semiconductor portion 15 may correspond to, for example, at least one of a buffer layer and a substrate. A low-resistance electrical connection is obtained.
[0026] In the semiconductor device 100, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential referenced to the potential of the second electrode 52. The first electrode 51 functions as, for example, a drain electrode. The second electrode 52 functions as, for example, a source electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 100 is, for example, a transistor. Alternatively, the semiconductor device 100 may be, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) incorporating a Schottky barrier diode.
[0027] In the semiconductor device 100, adjacent to the second subregion 11b, the third subregion 11c, and the fifth subregion 11e, n + A sixth sub-region 11f of the region is provided. The sixth sub-region 11f is p + It is located directly beneath the second semiconductor region 12. The sixth partial region 11f functions, for example, as a current diffusion layer.
[0028] The third sub-region 11c corresponds, for example, to a JFET (Junction Field Effect Transistor) region. In the case of a semiconductor device in which the sixth sub-region 11f is located directly below the third sub-region 11c, the oxide film electric field increases. Therefore, measures to address avalanche breakdown resistance and other issues become necessary by narrowing the width W1 in the second direction D2 of the third sub-region 11c or by increasing the thickness of the oxide film. In contrast, in this embodiment, the sixth sub-region 11f is not located directly below the third sub-region 11c. Therefore, the semiconductor device 100 can suppress the increase in the oxide film electric field without taking the measures described above.
[0029] Furthermore, as shown in Figure 1, the third sub-region 11c and the sixth sub-region 11f are spaced apart by a width W2 in the second direction D2. The width W2 is a finite distance. Here, if the width W2 is 0, that is, if the third sub-region 11c and the sixth sub-region 11f are in contact in the second direction D2, the breakdown voltage of the semiconductor device is determined based on the electric field concentrated in region A1. In this case, the breakdown voltage is strongly affected by the variation in the width W1 of the third sub-region 11c in the second direction D2. In the semiconductor device 100 of this embodiment, since the third sub-region 11c and the sixth sub-region 11f are spaced apart by providing a width W2, avalanche breakdown can be induced in the first stepped portion 11fa and the second stepped portion 12a. As a result, the semiconductor device 100 can stably reduce its avalanche breakdown voltage.
[0030] The fifth sub-region 11e corresponds, for example, to a Schottky region. In the case of a semiconductor device in which a sixth sub-region 11f is provided directly below the fifth sub-region 11e, the electric field of the Schottky junction increases. To suppress this increase in the electric field, for example, it is necessary to narrow the width W3 of the sixth sub-region 11f in the second direction. In this embodiment, since a sixth sub-region 11f is not provided directly below the fifth sub-region 11e, the semiconductor device 100 can suppress the increase in the electric field of the Schottky junction.
[0031] In the semiconductor device 100, the SBD current can be broadened along the third direction D3 without increasing the oxide film electric field. Furthermore, the sixth partial region 11f appropriately reduces the breakdown voltage of the second stepped portion 12a (see Figure 1) of the second semiconductor portion 12. For example, the avalanche withstand capability of the semiconductor device 100 can be improved.
[0032] Furthermore, in the semiconductor device 100, the first stepped portion 11fa of the sixth partial region 11f and the second stepped portion 12a of the second semiconductor portion 12 can improve the spread of the avalanche current. As a result, the semiconductor device 100 can more easily exhibit an improved avalanche withstand capability.
[0033] In the semiconductor device 100, a sixth partial region 11f is provided directly below the second semiconductor part 12. When manufacturing the second semiconductor part 12 and the sixth partial region 11f, a mask for implanting impurities can be shared. Thereby, in the semiconductor device 100, the sixth partial region 11f can be easily provided in the semiconductor device 100.
[0034] As shown in FIG. 1 and the like, the fourth semiconductor part 14 may include a high-concentration region 14p and a low-concentration region 14q. A part of the high-concentration region 14p is provided between the low-concentration region 14q and the silicide layer 16. The impurity concentration of the first conductivity type in the high-concentration region 14p is higher than the impurity concentration of the first conductivity type in the low-concentration region 14q. The high-concentration region 14p is, for example, an n ++ region. The low-concentration region 14q is, for example, an n + region.
[0035] In an embodiment, for example, the impurity of the first conductivity type includes at least one selected from the group consisting of N, P, and As. For example, the impurity of the second conductivity type includes at least one selected from the group consisting of B, Al, and Ga.
[0036] In one example, the concentration of the impurity of the first conductivity type in the first semiconductor part 11 is, for example, 1×10 14 cm -3 or more and 1×10 17 cm -3 or less. In one example, the concentration of the impurity of the second conductivity type in the second semiconductor part 12 is, for example, 1×10 16 / cm -3 or more and 1×10 20 cm -3 or less. In one example, the concentration of the impurity of the second conductivity type in the third semiconductor part 13 is, for example, 1×10 19 cm -3 or more and 1×10 21 cm -3 or less. In one example, the concentration of the impurity of the first conductivity type in the fourth semiconductor part 14 is, for example, 1×10 19 cm -3 or more and 1×10 21cm -3 The following applies: In one example, the concentration of the first conductivity type impurity in the fifth semiconductor section 15 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 18 cm -3 The following applies. The impurity concentration mentioned above may, for example, be substantially equivalent to the carrier concentration.
[0037] In the embodiment, information regarding length and thickness is obtained by electron microscopy observation or the like. Information regarding the composition of the material is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy) or the like.
[0038] The embodiments include the following aspects:
[0039] (Note 1) First electrode and, The second electrode and A first semiconductor portion of a first conductivity type is provided between the first electrode and the second electrode, and the first semiconductor portion is The first subregion and, In a second direction that intersects with the first direction moving from the first electrode to the second electrode, a second subregion is adjacent to the first subregion, A third subregion adjacent to the first subregion in the aforementioned first direction, In a third direction intersecting the plane including the first and second directions, a fourth subregion is adjacent to the second subregion, A fifth subregion is aligned with the fourth subregion in the first direction and is in Schottky contact with the second electrode, A sixth subregion that is aligned with the second subregion in the first direction, aligned with the fourth subregion in the third direction, and has a higher impurity concentration of the first conductivity type than the first impurity concentration of the first conductivity type in the first subregion, second subregion, third subregion, fourth subregion, and fifth subregion, The semiconductor part includes, A second semiconductor portion having a second conductivity type is provided between the sixth subregion and the second electrode, and is aligned with the third subregion in the second direction. A fourth semiconductor portion of the first conductivity type is provided between the second semiconductor portion and the second electrode and is electrically connected to the second electrode, A third electrode is provided so as to face the third partial region and the second semiconductor portion via the first insulating portion, A semiconductor device equipped with [the necessary components].
[0040] (Note 2) The semiconductor device according to Appendix 1, further comprising a third semiconductor portion of a second conductivity type provided between the second semiconductor portion and the second electrode, wherein the direction from the third partial region to the third semiconductor portion is along the second direction.
[0041] (Note 3) The first insulating portion is further provided, At least a portion of the first insulating portion is provided between the third partial region and the third electrode, as described in Appendix 1, for the semiconductor device.
[0042] (Note 4) The impurity concentration of the first conductivity type in the fourth semiconductor portion is higher than the impurity concentration of the first impurity. The semiconductor device according to Appendix 2 or 3, wherein the impurity concentration of the second conductivity type in the third semiconductor portion is higher than the impurity concentration of the second conductivity type in the second semiconductor portion.
[0043] (Note 5) Furthermore, it is equipped with a silicide layer, A portion of the silicide layer is provided between the second semiconductor portion and the second electrode in the first direction, and is provided opposite the fourth semiconductor portion in the second direction, as described in any one of the appendices 1 to 4, the semiconductor device described in any one of appendices 1 to 4.
[0044] (Note 6) The fourth semiconductor portion includes a high-concentration region and a low-concentration region. A portion of the high-concentration region is provided between the low-concentration region and the silicide layer in the second direction. The semiconductor device according to any one of the appendices 1 to 5, wherein the impurity concentration of the first conductivity type in the high-concentration region is higher than the impurity concentration of the first conductivity type in the low-concentration region.
[0045] (Note 7) The semiconductor device according to any one of appendices 1 to 6, wherein the sixth sub-region includes a first stepped portion formed in a stepped manner relative to the second semiconductor portion in a plane including the first direction and the second direction.
[0046] (Note 8) The semiconductor device according to any one of the appendices 1 to 7, wherein the second semiconductor portion includes a second stepped portion formed in a stepped manner with respect to the sixth partial region in a plane including the first direction and the second direction.
[0047] (Note 9) The sixth partial region includes a first stepped portion formed in a stepped manner relative to the second semiconductor portion in a plane including the first direction and the second direction, The second semiconductor portion includes a second stepped portion formed in a stepped manner relative to the sixth partial region in a plane including the first direction and the second direction, A semiconductor device according to any one of the appendices 1 to 8, wherein the first stepped portion and the second stepped portion are facing each other.
[0048] (Note 10) A semiconductor device according to any one of the appendices 2 to 9, wherein a part of the third semiconductor portion and a part of the fourth semiconductor portion make ohmic contact with the second electrode.
[0049] (Note 11) The second electrode includes a first electrode portion and a second electrode portion, The semiconductor device according to any one of appendices 1 to 10, wherein the first electrode portion is provided between the fifth sub-region and the second electrode portion in the first direction.
[0050] (Note 12) The semiconductor device according to Appendix 11, wherein at least a portion of the first electrode portion is provided between the sixth portion region and the second electrode portion in the first direction.
[0051] (Note 13) The first electrode portion is a semiconductor device as described in Appendix 11, comprising Ti.
[0052] (Note 14) The second electrode portion is a semiconductor device as described in Appendix 11, comprising Al.
[0053] (Note 15) The fifth semiconductor portion of the first conductivity type is further comprising: The fifth semiconductor portion is provided between the first electrode and the first semiconductor portion in the first direction, The semiconductor device according to any one of the appendices 1 to 14, wherein the impurity concentration of the first conductivity type in the fifth semiconductor portion is higher than the first impurity concentration.
[0054] (Note 16) The semiconductor device according to any one of the appendices 2 to 15, wherein the first semiconductor part, the second semiconductor part, the third semiconductor part, and the fourth semiconductor part include SiC.
[0055] According to the embodiment, a semiconductor device with improved characteristics can be provided.
[0056] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configuration of each element, such as electrodes, semiconductor parts, and insulating parts, included in a semiconductor device is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.
[0057] Furthermore, combinations of two or more elements from any of the specific examples, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.
[0058] Furthermore, all semiconductor devices that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.
[0059] Furthermore, within the scope of the concept of the present invention, a person skilled in the art could conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of the present invention.
[0060] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]
[0061] 11...First semiconductor part, 11a...First partial region, 11b...Second partial region, 11c...Third partial region, 11d...Fourth partial region, 11e...Fifth partial region, 11f...Sixth partial region, 11fa...First stepped portion, 12...Second semiconductor part, 12a...Second stepped portion, 13...Third semiconductor part, 14...Fourth semiconductor part, 14p...High concentration region, 14q...Low concentration region, 15...Fifth semiconductor part, 16...Silicide layer, 17...Insulating portion, 41...First insulating portion, 51...First electrode, 52...Second electrode, 52a...First electrode portion, 52b...Second electrode portion, 53...Third electrode, 100...Semiconductor device, 110,120,130,140...Semiconductor parts
Claims
1. First electrode and The second electrode and A first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, and the first semiconductor portion is The first subregion and, A second subregion that is adjacent to the first subregion in a second direction that intersects with the first direction moving from the first electrode to the second electrode, A third subregion adjacent to the first subregion in the first direction, In the third direction intersecting the first and second directions, a fourth subregion is adjacent to the second subregion, A fifth sub-region is aligned with the fourth sub-region in the first direction and is in Schottky contact with the second electrode, A sixth subregion which is aligned with the second subregion in the first direction and with the fourth subregion in the third direction, and which has a higher impurity concentration of the first conductivity type than the first impurity concentration of the first conductivity type in the first subregion, second subregion, third subregion, fourth subregion, and fifth subregion, The first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, A second semiconductor portion having a second conductivity type is provided between the sixth partial region and the second electrode, and is aligned with the third partial region in the second direction. A fourth semiconductor portion of the first conductivity type is provided between the second semiconductor portion and the second electrode and is electrically connected to the second electrode, A third electrode is provided so as to face the third partial region and the second semiconductor portion via the first insulating portion, Equipped with, The semiconductor device wherein the sixth sub-region includes a first stepped portion formed in a stepped manner relative to the second semiconductor portion in a plane where the first direction and the second direction intersect.
2. First electrode and The second electrode and A first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, and the first semiconductor portion is The first subregion and, A second subregion that is adjacent to the first subregion in a second direction that intersects with the first direction moving from the first electrode to the second electrode, A third subregion adjacent to the first subregion in the first direction, In the third direction intersecting the first and second directions, a fourth subregion is adjacent to the second subregion, A fifth sub-region is aligned with the fourth sub-region in the first direction and is in Schottky contact with the second electrode, A sixth subregion which is aligned with the second subregion in the first direction and with the fourth subregion in the third direction, and which has a higher impurity concentration of the first conductivity type than the first impurity concentration of the first conductivity type in the first subregion, second subregion, third subregion, fourth subregion, and fifth subregion, The first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, A second semiconductor portion having a second conductivity type is provided between the sixth partial region and the second electrode, and is aligned with the third partial region in the second direction. A fourth semiconductor portion of the first conductivity type is provided between the second semiconductor portion and the second electrode and is electrically connected to the second electrode, A third electrode is provided so as to face the third partial region and the second semiconductor portion via the first insulating portion, Equipped with, The semiconductor device includes a second stepped portion formed in a stepped manner relative to the sixth partial region in a plane where the first direction and the second direction intersect.
3. First electrode and The second electrode and A first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, and the first semiconductor portion is The first subregion and, A second subregion that is adjacent to the first subregion in a second direction that intersects with the first direction moving from the first electrode to the second electrode, A third subregion adjacent to the first subregion in the first direction, In the third direction intersecting the first and second directions, a fourth subregion is adjacent to the second subregion, A fifth sub-region is aligned with the fourth sub-region in the first direction and is in Schottky contact with the second electrode, A sixth subregion which is aligned with the second subregion in the first direction and with the fourth subregion in the third direction, and which has a higher impurity concentration of the first conductivity type than the first impurity concentration of the first conductivity type in the first subregion, second subregion, third subregion, fourth subregion, and fifth subregion, The first semiconductor portion having a first conductivity type is provided between the first electrode and the second electrode, A second semiconductor portion having a second conductivity type is provided between the sixth partial region and the second electrode, and is aligned with the third partial region in the second direction. A fourth semiconductor portion of the first conductivity type is provided between the second semiconductor portion and the second electrode and is electrically connected to the second electrode, A third electrode is provided so as to face the third partial region and the second semiconductor portion via the first insulating portion, Equipped with, The sixth partial region includes a first stepped portion formed in a stepped manner relative to the second semiconductor portion in a plane where the first direction and the second direction intersect, The second semiconductor portion includes a second stepped portion formed in a stepped manner relative to the sixth partial region in a plane where the first direction and the second direction intersect, A semiconductor device in which the first stepped portion and the second stepped portion are facing each other.
4. The semiconductor device according to any one of claims 1 to 3, further comprising a third semiconductor portion of a second conductivity type provided between the second semiconductor portion and the second electrode, wherein the direction from the third partial region to the third semiconductor portion is along the second direction.
5. The impurity concentration of the first conductivity type in the fourth semiconductor portion is higher than the first impurity concentration. The semiconductor device according to claim 4, wherein the impurity concentration of the second conductivity type in the third semiconductor portion is higher than the impurity concentration of the second conductivity type in the second semiconductor portion.
6. Furthermore, it has a silicide layer, A portion of the silicide layer is provided between the second semiconductor portion and the second electrode in the first direction, and is provided opposite the fourth semiconductor portion in the second direction, according to any one of claims 1 to 3, the semiconductor device according to any one of claims 1 to 3.
7. The fourth semiconductor portion includes a high-concentration region and a low-concentration region. A portion of the high-concentration region is provided between the low-concentration region and the silicide layer in the second direction. The semiconductor device according to claim 6, wherein the impurity concentration of the first conductivity type in the high-concentration region is higher than the impurity concentration of the first conductivity type in the low-concentration region.
8. The semiconductor device according to claim 4, wherein a part of the third semiconductor portion and a part of the fourth semiconductor portion are in ohmic contact with the second electrode.
9. The semiconductor device according to claim 4, wherein the first semiconductor portion, the second semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion include SiC.
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