Indication device

Abstract

This method effectively utilizes the space present in areas where pixel electrodes are not formed. [Solution] The device comprises a semiconductor layer, a first insulating layer on the semiconductor layer, a gate electrode and a first conductive layer on the first insulating layer, a second insulating layer on the gate electrode and the first conductive layer, a source electrode, a drain electrode and a second conductive layer on the second insulating layer, a third insulating layer on the source electrode, the drain electrode and the second conductive layer, a first electrode and a third conductive layer on the third insulating layer, a planarization film covering the end of the first electrode, an electroluminescent layer on the first electrode, and a second electrode on the electroluminescent layer and the planarization film, wherein the second electrode is electrically connected to the third conductive layer via an opening provided in the planarization film, and the opening overlaps the first conductive layer, the second conductive layer and the third conductive layer.

Description

Technical Field

[0001] The technical field relates to light-emitting devices, display devices (such as EL display devices and liquid crystal display devices), semiconductor devices, etc. and so on.

Background Art

[0002] Patent Document 1 discloses a light-emitting device in which a pixel electrode is disposed on a wiring used in a pixel circuit via an insulating layer. and so on.

Prior Art Documents

Patent Documents

[0003]

Patent Document ①

Summary of the Invention

Problems to be Solved by the Invention

[0004] When adopting a structure such as that of Patent Document 1, the conductive layer in contact with the insulating layer is only the pixel electrode. Therefore, there is a space where a conductive layer can be disposed in a region where the pixel electrode is not formed. and so on.

[0005] Therefore, the first problem is to effectively utilize the space existing in the region where the pixel electrode is not formed. and so on.

[0006] Another problem is to reduce the parasitic capacitance formed at the intersection of wirings.

[0007] Note that the invention disclosed below is satisfactory if it can solve either the first problem or the second problem. and so on.

Means for Solving the Problems

[0008] In the region where pixel electrodes are not formed, auxiliary wiring (auxiliary electrodes), one transistor and other The first problem is solved by forming connecting wires, capacitive electrodes, etc., that connect to the transistor. It can be solved.

[0009] On the other hand, when the first wiring and the second wiring intersect, the first wiring has a first opening A second opening is provided for the second wiring.

[0010] Then, the first opening and the second opening are positioned at the intersection of the first wiring and the second wiring. Furthermore, by ensuring that part or all of the first opening does not overlap with the second opening This can solve the second problem.

[0011] For example, a semiconductor layer, a first insulating layer on the semiconductor layer, and a gate on the first insulating layer. An electrode and a first conductive layer, and a second insulating layer on the gate electrode and on the first conductive layer, The source electrode, drain electrode, and second conductive layer on the second insulating layer, and the source electrode A third insulating layer on the drain electrode and the second conductive layer, and the third insulating layer The upper first electrode and third conductive layer, the planarizing film covering the end of the first electrode, and the first An electroluminescent layer on the electrode, and on the electroluminescent layer and the The device has a second electrode on the planarization film, and the second electrode has an opening provided in the planarization film. The third conductive layer is electrically connected via a portion, and the opening is connected to the first conductive layer The present invention provides a light-emitting device characterized by overlapping a layer, the second conductive layer, and the third conductive layer. It is possible.

[0012] For example, a gate electrode and a first conductive layer, and on the gate electrode and on the first conductive layer a first insulating layer, a semiconductor layer and a second conductive layer on the first insulating layer, and source electrodes and drain electrodes, a second insulating layer on the source electrodes, on the drain electrodes, and on the second conductive layer, a first electrode and a third conductive layer on the second insulating layer, and a planarization film covering an end portion of the first electrode, an electroluminescence layer on the first electrode, and a second electrode on the electroluminescence layer and on the planarization film, and the second electrode is electrically connected to the third conductive layer through an opening provided in the planarization film, and the opening overlaps with the first conductive layer, the second conductive layer, and the third conductive layer, and a light-emitting device can be provided.

[0013] In the above light-emitting device, one of the first conductive layer or the second conductive layer is a dummy electrode and the other of the first conductive layer or the second conductive layer is preferably a wiring.

[0014] In the above light-emitting device, one of the first conductive layer or the second conductive layer is a first dummy electrode and the other of the first conductive layer or the second conductive layer is preferably a second dummy electrode.

[0015] In the above light-emitting device, one of the first conductive layer or the second conductive layer is a first wiring and the other of the first conductive layer or the second conductive layer is a second wiring, and the opening is preferably provided at an intersection of the first wiring and the second wiring.

[0016] In the above light-emitting device, a first opening is provided in the first conductive layer, and the first opening is preferably provided inside the opening.​

[0017] In the above-described light-emitting device, the second conductive layer is provided with a second opening, It is preferable that the opening in 2 is located on the inside of the aforementioned opening.

[0018] In the above-described light-emitting device, the first conductive layer is provided with a first opening, The conductive layer 2 is provided with a second opening, and the first opening and the second opening Preferably, it is provided on the inside of the opening.

[0019] In the above-described light-emitting device, the first conductive layer is the same layer as the gate electrode, and the second The conductive layer is the same as the source electrode and drain electrode, and the third conductive layer is the It is preferable that the electrode is in the same layer as the first electrode.

[0020] For example, it includes first and second transistors, first to third wiring, and pixel electrodes. The first and second transistors are transistors with an inverse staggered structure, and the The source or drain of the first transistor is electrically connected to the wiring of 1. The gate of the first transistor is electrically connected to the second wiring. Furthermore, the third wiring has either the source or the drain of the second transistor electrically connected to it. It is connected to the source or drain of the second transistor, and the pixel electrode has The other side is electrically connected, and the other side of the source or drain of the first transistor is connected to The gate of the second transistor and the electrical connection wiring in the same layer as the pixel electrode are electrically connected. A display device characterized by being connected to a device can be provided.

[0021] In the above-mentioned display device, a capacitive element is provided, and the gate electrode of the second transistor is the It is used as one electrode of the capacitance element, and the third wiring is used as the other electrode of the capacitance element. It would be preferable if it could be used for both the extreme and extreme functions.

[0022] The above-mentioned display device has a conductive layer in the same layer as the pixel electrode, and the conductive layer is the third Overlapping with the wiring, the conductive layer is electrically connected to the gate electrode of the second transistor. It would be preferable if it were.

[0023] In the above-described display device, the conductive layer is located inside the opening provided in the third wiring. Preferably, it is electrically connected to the gate electrode of the second transistor.

[0024] For example, it has a transistor and first and second wirings, and the first wiring is the transistor The second wiring is electrically connected to either the source or drain of the transistor, The first wiring is electrically connected to the gate of the transistor, and the first wiring is connected to the first opening The second wiring has a second opening, and the first and second openings are the It is provided at the intersection of wiring 1 and wiring 2, and at the intersection, the first The present invention provides a semiconductor device characterized in that the opening has a region that does not overlap with the second opening. It is possible.

[0025] For example, it has a transistor, first to third wirings, and a capacitive element, and the first wiring is , electrically connected to either the source or drain of the transistor, the second The wiring is electrically connected to the gate of the transistor, and the third wiring is the It is electrically connected to one electrode of the capacitive element, and is the source or slave of the transistor. The other side of the capacitor element and the other electrode of the capacitor element are electrically connected, and the first wiring The first has an opening, the third wiring has a third opening, and the first and the third The opening is provided at the intersection of the first wiring and the third wiring, and at the intersection Furthermore, the first opening has a region that does not overlap with the third opening. We can provide semiconductor devices.

[0026] For example, it has a transistor, first to third wirings, and a capacitive element, and the first wiring is , electrically connected to either the source or drain of the transistor, the second The wiring is electrically connected to the gate of the transistor, and the third wiring is the It is electrically connected to one electrode of the capacitive element, and is the source or slave of the transistor. The other side of the capacitor element and the other electrode of the capacitor element are electrically connected, and the first wiring The first has an opening, the second wiring has a second opening, and the third wiring has a third The first wiring has an opening, and the first and second openings have a fourth opening. , provided at the first intersection of the first wiring and the second wiring, the third and the The fourth opening is provided at the second intersection of the first wiring and the third wiring, In the first intersection, the first opening has a region that does not overlap with the second opening. At the second intersection, the third opening has a region that does not overlap with the fourth opening. A semiconductor device characterized by having [this feature] can be provided.

[0027] In this specification, dummy electrodes (electrically isolated electrodes, floating electrodes) This refers to an electrode that is electrically floating (not supplied with current or voltage). It tastes good.

[0028] Furthermore, in this specification, a dummy semiconductor layer (an electrically isolated semiconductor layer, a floating layer) is used. A semiconductor layer is an electrically floating state in which no current or voltage is supplied. This refers to the semiconductor layer of the material.

[0029] Furthermore, in this specification, "A and B are in the same layer" means "A and B were formed in the same process." This means that "A and B were formed from the same material."

[0030] For example, "A and B were formed in the same process" or "A and B were formed from the same material." This means that a predetermined film (starting film) was pattern-processed to form A and B.

[0031] Furthermore, pattern processing involves, for example, forming a mask on a predetermined film (starting film) and using the mask. This means processing a predetermined film (starting film) into a predetermined shape and removing the mask, etc.

[0032] Therefore, "A and B were formed in the same process" or "A and B were formed from the same material" This concept includes the idea that "A and B were formed using the same starting film."

[0033] As another example, using printing methods (inkjet printing, letterpress printing, etc.), A and B can be... When forming, "A and B were formed in the same process" or "A and B were formed from the same material." "Ta" means that the printing was done so that both A and B form a pattern. [Effects of the Invention]

[0034] By solving the first problem, the space present in the region where pixel electrodes are not formed can be addressed. The space can be used effectively.

[0035] By solving the second problem, parasitic capacitance formed at the intersections of wiring can be reduced. It is possible. [Brief explanation of the drawing]

[0036] [Figure 1] An example of a light-emitting device. [Figure 2] An example of a light-emitting device. [Figure 3] An example of a light-emitting device. [Figure 4] An example of a light-emitting device. [Figure 5] An example of a light-emitting device. [Figure 6] An example of a light-emitting device. [Figure 7] An example of a light-emitting device. [Figure 8] An example of a light-emitting device. [Figure 9] An example of a light-emitting device. [Figure 10] An example of a light-emitting device. [Figure 11] An example of a light-emitting device. [Figure 12] An example of a light-emitting device. [Figure 13] An example of a light-emitting device. [Figure 14] An example of a light-emitting device. [Figure 15] An example of a light-emitting device. [Figure 16] An example of a light-emitting device. [Figure 17] An example of a light-emitting device. [Figure 18] An example of a light-emitting device. [Figure 19] An example of a light-emitting device. [Figure 20] An example of a light-emitting device. [Figure 21] An example of a light-emitting device. [Figure 22] An example of a light-emitting device. [Figure 23] An example of a light-emitting device. [Figure 24] An example of a light-emitting device. [Figure 25] An example of a light-emitting device. [Figure 26] An example of a light-emitting device. [Figure 27] An example of a light-emitting device. [Figure 28] An example of a light-emitting device. [Figure 29] An example of a light-emitting device. [Figure 30] An example of a light-emitting device. [Figure 31] An example of a semiconductor device. [Figure 32] An example of a semiconductor device. [Modes for carrying out the invention]

[0037] The embodiments will be described in detail with reference to the drawings.

[0038] However, the form and details may be modified in various ways without departing from the spirit of the invention. This will be easily understood by those skilled in the art.

[0039] Therefore, the scope of the invention is not to be interpreted as being limited to the contents of the embodiments described below. do not have.

[0040] In the configuration described below, the same part or parts having similar functions are the same The same symbols are used across different drawings, and explanations of their repetition are omitted.

[0041] Furthermore, the following embodiments can be implemented by combining some or all of them as appropriate.

[0042] (Embodiment 1) Figure 1 shows an example of a light-emitting device.

[0043] A semiconductor layer 1110 is formed on a substrate 1050 having an insulating surface.

[0044] An insulating layer 1111 is formed on the semiconductor layer 1110.

[0045] The semiconductor layer 1110 has at least a channel formation region, a source region, and a drain region. do.

[0046] The insulating layer 1111 corresponds to the gate insulating film of the transistor 1100.

[0047] A conductive layer 1112 is formed on the insulating layer 1111.

[0048] The conductive layer 1112 corresponds to the gate electrode of the transistor 1100 and has a channel formation region and They are formed in overlapping positions.

[0049] An insulating layer 1113 is formed on the conductive layer 1112.

[0050] The insulating layer 1113 corresponds to the interlayer insulating film.

[0051] A conductive layer 1114 and a conductive layer 1115 are formed on the insulating layer 1113.

[0052] The conductive layer 1114 corresponds to either the source electrode or the drain electrode of the transistor 1100. do.

[0053] Furthermore, the conductive layer 1114 is formed in the insulating layer 1111 and the insulating layer 1113 Electrically connected to either the source region or the drain region of the semiconductor layer via a hole. ru.

[0054] The conductive layer 1115 corresponds to either the source electrode or the drain electrode of the transistor 1100. do.

[0055] Furthermore, the conductive layer 1115 is formed in the insulating layer 1111 and the insulating layer 1113 Electrically connected to the source region or drain region of the semiconductor layer via a hole. ru.

[0056] An insulating layer 1120 is formed on the conductive layer 1114 and the conductive layer 1115.

[0057] The insulating layer 1120 corresponds to the interlayer insulating film.

[0058] A conductive layer 1211 and a conductive layer 1212 are formed on the insulating layer 1120.

[0059] The conductive layer 1211 corresponds to the first electrode (pixel electrode, lower electrode) of the light-emitting element.

[0060] The conductive layer 1211 is transmitted to the conductive layer 11 through a contact hole formed in the insulating layer 1120. It is electrically connected to 15.

[0061] The conductive layer 1212 corresponds to the second electrode (counter electrode, upper electrode) of the light-emitting element. It is electrically connected to 230 and functions as auxiliary wiring (auxiliary electrodes) for the conductive layer 1230.

[0062] Furthermore, in order to reduce the number of steps, conductive layer 1211 and conductive layer 1212 are formed in the same step. This is preferable. In other words, it is preferable that the conductive layer 1211 and the conductive layer 1212 are the same layer.

[0063] Of course, the conductive layer 1211 and the conductive layer 1212 may be formed using different processes.

[0064] An insulating layer 1130 is formed on the conductive layer 1211 and the conductive layer 1212.

[0065] The insulating layer 1130 corresponds to the partition layer.

[0066] The insulating layer 1130 has openings to expose a portion of the surface of the conductive layer 1211, and conductive An opening is provided to expose a portion of the surface of layer 1212.

[0067] In other words, the insulating layer 1130 covers the edges of the conductive layer 1211 and the edges of the conductive layer 1212. Yes, they are.

[0068] On the conductive layer 1211 and the insulating layer 1130, there is an electroluminescent layer 1220 ( An EL layer (electroluminescent layer) is formed.

[0069] On the electroluminescent layer 1220, on the insulating layer 1130, and on the conductive layer 1212 A conductive layer 1230 is formed thereon.

[0070] In other words, the conductive layer 1230 is provided with an opening (contact hole) in the insulating layer 1130. It is electrically connected to the conductive layer 1212 via this.

[0071] The conductive layer 1230 corresponds to the second electrode (counter electrode, upper electrode) of the light-emitting element.

[0072] By using the configuration shown in Figure 1, the conductive layer 1211 is formed in the region where it is not formed. The conductive layer 1212 can be used as auxiliary wiring for the conductive layer 1230.

[0073] Therefore, the space in areas where pixel electrodes are not formed can be effectively utilized.

[0074] Note that in Figure 1, the transistor 1100 provided on the substrate 1050 is a top gate. Although a bottom-gate TFT is shown in the diagram, transistor 1100 can also be used as a bottom-gate TFT. Alternatively, transistors formed using silicon wafers, SOI substrates, etc., may also be used.

[0075] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0076] (Embodiment 2) We will now explain the case where a planarized membrane is used as the partition layer.

[0077] A planarized film is an insulating film that has a flat surface.

[0078] A typical example of a planarized film is one formed by extruding a liquid raw material onto a substrate and then curing it. It is an insulating film, etc.

[0079] Examples of insulating films formed by extruding liquid raw materials onto a substrate and then curing them include organic It contains insulating films, etc.

[0080] Examples of organic insulating films include polyimide films, acrylic films, and siloxane films.

[0081] Because organic insulating films are made from liquid raw materials, the higher the height of the structure formed in the lower layer of the film, the greater the effect. The distance between the structure and the membrane surface becomes shorter.

[0082] Therefore, the higher the height of the structure formed in the lower layer of the membrane, the greater the gap between the bottom and surface of the opening. The distance will be shortened.

[0083] Note that instead of a planarization film, CMP (Chemical Mechanical Po An insulating film or the like may be used, whose surface has been planarized by polishing (such as lishing).

[0084] The polished surface of the insulating film creates an insulating film with a surface that reflects the irregularities of the underlying structure. The surface is flattened and formed by polishing after the material has been processed, and therefore liquid raw materials are used. The resulting insulating film has a shape similar to that of the film itself.

[0085] Therefore, an example of a configuration in which the bottom surface of the opening is raised is shown in Figures 2 and 3.

[0086] Figure 2 shows the configuration in Figure 1 with the addition of a conductive layer 1300.

[0087] To reduce the number of processes, the conductive layer 1300 is made using the same process as the gate electrode of the transistor 1100. It is preferable that the conductive layer is formed from [the material].

[0088] Figure 3 shows the configuration in Figure 1 with the addition of a conductive layer 1400.

[0089] To reduce the number of processes, the conductive layer 1400 is used for the source electrode and drain of the transistor 1100. It is preferable that the conductive layer is formed in the same process as the electrode.

[0090] The conductive layer 1300 or conductive layer 1400 is, for example, used in wiring or dummy electrodes for a light-emitting device. These include electrically isolated electrodes, floating electrodes, etc.

[0091] Examples of wiring used in light-emitting devices include gate wiring, capacitive wiring, signal lines, power lines, and power lines. Disconnected wires, etc., can be used.

[0092] Dummy electrodes (electrically isolated electrodes, floating electrodes) are used in light-emitting devices. It is an electrode that is electrically isolated from the wiring or electrodes.

[0093] Then, the conductive layer 1300 or the conductive layer 1400 connects the conductive layer 1212 and the conductive layer 1230. It is formed in a position that overlaps with the opening provided in the insulating layer 1130 for electrical connection. ru.

[0094] Furthermore, at least the edge (end, outer circumference) of the opening overlaps with the conductive layer 1300 or the conductive layer 1400. It is sufficient if it is formed in the correct position.

[0095] As described above, by placing the conductive layer in a position that overlaps with the opening, the conductive layer 1230 This can reduce the probability of the wire breaking.

[0096] In other words, by providing a conductive layer below the opening, the bottom surface of the opening is raised, so the opening The step at the opening becomes smaller.

[0097] Furthermore, reducing the step difference at the opening reduces the probability of the conductive layer 1230 breaking. It is possible.

[0098] Note that in Figures 2 and 3, a dummy semiconductor layer (electrically isolated) is placed at a position overlapping with the opening. When semiconductor layers (floating semiconductor layers) are arranged, the probability of the conductive layer 1230 breaking is good. It is preferable because it reduces the risk.

[0099] It is preferable that the dummy semiconductor layer be formed using the same process as the semiconductor layer of the transistor. stomach.

[0100] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0101] (Embodiment 3) Figure 4 shows an example of a configuration in which both conductive layer 1300 and conductive layer 1400 are added to Figure 1. In Figure 4, a planarization membrane is used as the partition layer.

[0102] To reduce the number of processes, the conductive layer 1300 is made using the same process as the gate electrode of the transistor 1100. It is preferable that the conductive layer is formed from [the material].

[0103] To reduce the number of processes, the conductive layer 1400 is used for the source electrode and drain of the transistor 1100. It is preferable that the conductive layer is formed in the same process as the electrode.

[0104] As shown in Figure 4, by having both conductive layer 1300 and conductive layer 1400, as shown in Figure 2, This is preferable because it reduces the probability of the conductive layer 1230 breaking compared to Figure 3.

[0105] The conductive layer 1300 or conductive layer 1400 is, for example, used in wiring or dummy electrodes for a light-emitting device. These include electrically isolated electrodes, floating electrodes, etc.

[0106] Examples of wiring used in light-emitting devices include gate wiring, capacitive wiring, signal lines, power lines, and power lines. Disconnected wires, etc., can be used.

[0107] Dummy electrodes (electrically isolated electrodes, floating electrodes) are used in light-emitting devices. It is an electrode that is electrically isolated from the wiring or electrodes.

[0108] For example, in a configuration where an opening is provided at the intersection of two wires, the conductive layer 1300 is the first wire Corresponding to this, the conductive layer 1400 corresponds to the second wiring.

[0109] For example, in a configuration where one wire, a dummy electrode, and an opening are superimposed, the conductive layer 1300 is the wire Alternatively, one of the dummy electrodes corresponds to the conductive layer 1400, which corresponds to the wiring or the other of the dummy electrodes. .

[0110] For example, in a configuration in which two dummy electrodes and an opening are superimposed, the conductive layer 1300 is the first dummy - Corresponding to the electrode, the conductive layer 1400 corresponds to the second dummy electrode.

[0111] Note that in Figure 4, a dummy semiconductor layer (an electrically isolated semiconductor) is placed at the position overlapping with the opening. By arranging layers (floating semiconductor layer), the probability of the conductive layer 1230 breaking is further reduced. Therefore, it is preferable.

[0112] It is preferable that the dummy semiconductor layer be formed using the same process as the semiconductor layer of the transistor. stomach.

[0113] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0114] (Embodiment 4) When using a planarization film as a partition layer, in order to reduce the probability of disconnection in the light-emitting region, A dummy electrode or dummy semiconductor layer may be placed beneath the pixel electrode.

[0115] Of course, both dummy electrodes and dummy semiconductor layers may be placed beneath the pixel electrodes.

[0116] It is preferable that the dummy semiconductor layer be formed using the same process as the semiconductor layer of the transistor. stomach.

[0117] It is preferable that the dummy electrode be formed in the same process as the gate electrode of the transistor. .

[0118] The dummy electrode is formed in the same process as the source and drain electrodes of the transistor. It is preferable to do so.

[0119] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0120] (Embodiment 5) Figures 5, 6, and 7 show a channel-etched TFT, a type of TFT with an inverse staggered structure. An example of a light-emitting device is shown.

[0121] Figure 5 is a circuit diagram of the pixel circuit used in the light-emitting device shown in Figures 6 and 7.

[0122] The pixel circuit shown in Figure 5 consists of transistor Tr1, transistor Tr2, wiring G, wiring S, It has wiring V and light-emitting element EL (EL element).

[0123] Transistor Tr1 has the function of controlling the conduction and non-conductivity of transistor Tr2.

[0124] Transistor Tr1 is sometimes called a switching transistor.

[0125] Transistor Tr2 has the function of controlling the current supplied to the light-emitting element EL.

[0126] Transistor Tr2 is sometimes called a driver transistor.

[0127] Wiring G corresponds to, for example, a gate wire.

[0128] The gate wire is electrically connected to the gate of transistor Tr1, and transistor Tr1 It has the function of supplying signals to control conductivity and non-conductivity.

[0129] Wiring S corresponds to, for example, a signal line.

[0130] The signal line has the function of supplying video signals.

[0131] Wiring V corresponds to, for example, a power line.

[0132] Power lines have the function of supplying current or voltage.

[0133] Wiring G is electrically connected to the gate of transistor Tr1.

[0134] Wiring S is electrically connected to either the source or the drain of transistor Tr1.

[0135] Wiring V is electrically connected to either the source or the drain of transistor Tr2.

[0136] The light-emitting element EL is electrically connected to the source or the other drain of transistor Tr2. Yes, they are.

[0137] The source or drain of transistor Tr1, and the gate of transistor Tr2, They are electrically connected.

[0138] The cross-sectional view of section AB in Figure 6 corresponds to Figure 7(A).

[0139] Furthermore, Figure 7(A) corresponds to the cross-sectional view of transistor Tr2 in Figure 5.

[0140] The cross-sectional view of the CD section in Figure 6 corresponds to Figure 7(B).

[0141] Furthermore, Figure 7(B) shows the source or drain of transistor Tr1 in Figure 5 and the other side of the transistor. This corresponds to the cross-sectional view of the connection point between ZISTA Tr2 and the gate.

[0142] The cross-sectional view of section EF in Figure 6 corresponds to Figure 7(C).

[0143] Furthermore, Figure 7(C) corresponds to the cross-sectional view of transistor Tr1 in Figure 5.

[0144] Furthermore, in Figures 6 and 7, a conductive layer 101 is placed on the substrate 50 having an insulating surface, and a conductive layer 101 is placed on the substrate 50 having an insulating surface. Layer 102 is formed.

[0145] The conductive layer 101 corresponds to the gate electrode of transistor Tr2.

[0146] Furthermore, the conductive layer 101 is connected to the source or drain of transistor Tr1. It also functions as part of the connecting wiring for electrically connecting to the gate of Tr2.

[0147] The conductive layer 102 corresponds to the gate electrode of transistor Tr1.

[0148] Furthermore, the conductive layer 102 also functions as a wiring G (gate wire).

[0149] An insulating layer 200 is formed on the conductive layer 101 and the conductive layer 102.

[0150] The insulating layer 200 functions as a gate insulating film for transistor Tr1, and transistor T It has the function of being a gate insulating film of r2.

[0151] A semiconductor layer 301 and a semiconductor layer 302 are formed on the insulating layer 200.

[0152] Semiconductor layer 301 corresponds to the semiconductor layer of transistor Tr2.

[0153] Semiconductor layer 302 corresponds to the semiconductor layer of transistor Tr1.

[0154] A conductive layer 401 and a conductive layer 402 are formed on the semiconductor layer 301.

[0155] The conductive layer 401 corresponds to either the source electrode or the drain electrode of the transistor Tr2. .

[0156] Furthermore, the conductive layer 401 also functions as a connection wire to the conductive layer 601, which is the pixel electrode. ru.

[0157] The conductive layer 402 corresponds to either the source electrode or the drain electrode of the transistor Tr2. .

[0158] Furthermore, the conductive layer 402 also functions as wiring V (power line).

[0159] A conductive layer 403 and a conductive layer 404 are formed on the semiconductor layer 302.

[0160] The conductive layer 403 corresponds to either the source electrode or the drain electrode of the transistor Tr1. .

[0161] Furthermore, the conductive layer 403 is connected to the source or drain of transistor Tr1. It also functions as part of the connecting wiring for electrically connecting to the gate of Tr2.

[0162] The conductive layer 404 corresponds to the source electrode or the other of the drain electrode of transistor Tr1. .

[0163] Furthermore, the conductive layer 404 also functions as wiring S (signal line).

[0164] An insulating layer is placed on conductive layer 401, conductive layer 402, conductive layer 403, and conductive layer 404. 500 is formed.

[0165] The insulating layer 500 corresponds to the interlayer insulating film.

[0166] A conductive layer 601 and a conductive layer 602 are formed on the insulating layer 500.

[0167] The conductive layer 601 corresponds to the first electrode (pixel electrode, lower electrode) of the light-emitting element.

[0168] The conductive layer 601 is connected to the conductive layer 401 through contact holes formed in the insulating layer 500. They are electrically connected.

[0169] The conductive layer 602 is connected to the source or drain of transistor Tr1 and the other side of transistor Tr It functions as part of the connecting wiring for electrically connecting the two gates.

[0170] The conductive layer 602 is transmitted to the conductive layer 4 through the first contact hole formed in the insulating layer 500. A second component electrically connected to 03 and formed in the insulating layer 200 and the insulating layer 500 It is electrically connected to the conductive layer 101 via a tact hole.

[0171] As shown in Figure 6, the longitudinal direction of the region where the upper and lower conductive layers overlap and the contact hose By making the longitudinal direction of the ring parallel to the contact hole, the area of ​​the contact hole can be increased. It is preferable because it is possible.

[0172] Therefore, in Figure 6, the longitudinal direction of the first contact hole and the longitudinal direction of the second contact hole The directions intersect.

[0173] To reduce the number of processes, the first and second contact holes are manufactured in the same process. It is preferable to form the conductive layer 601 and the conductive layer 602 in the same process.

[0174] For example, the source or drain of transistor Tr1 and the gate of transistor Tr2 If we try to bring the conductive layer 403 into contact with the conductive layer 101 in order to electrically connect them, After forming the insulating layer 200 but before forming the insulating layer 500, the contact hole fabrication process It will take some time.

[0175] On the other hand, as shown in Figures 6 and 7, the conductive layer 602 is the source or drain of transistor Tr1. As part of the connecting wiring for electrically connecting the other end of the circuit to the gate of transistor Tr2 By using this method, after forming the insulating layer 200 and before forming the insulating layer 500, The process of creating contact holes becomes unnecessary.

[0176] In other words, the structure in Figures 6 and 7 consists of a first contact hole and a second contact hole. Because it is a structure that can be formed at the same time, after forming the insulating layer 200, This structure eliminates the need to perform a contact hole creation process before forming the 500. ru.

[0177] Therefore, the structures shown in Figures 6 and 7 are designed to reduce the contact hole fabrication process by one step. It can be said that this is the case.

[0178] An insulating layer 700 is formed on the conductive layer 601 and the conductive layer 602.

[0179] The insulating layer 700 corresponds to the partition layer.

[0180] The insulating layer 700 is provided with openings to expose a portion of the surface of the conductive layer 601. Yes, they are.

[0181] In other words, the insulating layer 700 covers the edges of the conductive layer 601.

[0182] On the conductive layer 601 and the insulating layer 700, there is an electroluminescent layer 801 (EL layer). A field-emitting layer is formed.

[0183] A conductive layer 900 is formed on the electroluminescent layer 801 and the insulating layer 700. It is being done.

[0184] The conductive layer 900 corresponds to the second electrode (counter electrode, upper electrode) of the light-emitting element.

[0185] As described above, by using the conductive layer 602 as a connecting wire, the number of manufacturing steps can be reduced. It can be made into a structure.

[0186] Furthermore, since the conductive layer 602 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0187] In this embodiment, a channel-etched TFT is used, but a channel-stopped TFT can also be used. good.

[0188] Furthermore, the light-emitting element in this embodiment can be replaced with other display elements (liquid crystal elements, electrophoretic elements, etc.). You can.

[0189] In other words, this embodiment is applicable to display devices in general.

[0190] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0191] (Embodiment 6) Figures 5 to 7 show an example of a configuration with added capacitive elements, as shown in Figures 8 to 9.

[0192] Figure 8 corresponds to the circuit diagram of the pixel circuit in Figure 9.

[0193] Figure 8 shows an example in which a capacitive element C is added to Figure 5.

[0194] One terminal (one electrode) of the capacitive element C is electrically connected to the gate of transistor Tr2. It continues.

[0195] The other terminal (the other electrode) of the capacitive element C is electrically connected to the wiring V (power line). ru.

[0196] In this embodiment, one electrode of the capacitor element C and the gate electrode of the transistor Tr2 are shared.

[0197] Also, the other electrode of the capacitor element C and the wiring V (power supply line) are shared.

[0198] Here, FIG. 9 shows a configuration in which the conductive layer 101 extends below the conductive layer 402 in FIG. 6.

[0199] By making one electrode of the capacitor element C and the gate electrode of the transistor Tr2 shared, and also making the other electrode of the capacitor element C and the wiring V (power supply line) shared, a capacitor element can be manufactured without reducing the aperture ratio.

[0200] Note that the light-emitting element of this embodiment may be replaced with other display elements (liquid crystal elements, electrophoretic elements, etc.).

[0201] That is, this embodiment is applicable to display devices in general.

[0202] Part or all of the configuration described in this embodiment can be implemented in appropriate combination with part or all of the configuration described in other embodiments.

[0203] (Embodiment 7) A configuration for increasing the capacitance of the capacitor element is shown in FIG. 10.

[0204] FIG. 10(A) shows a configuration in which a conductive layer 603 is added to FIG. 9.

[0205] FIG. 10(B) corresponds to the cross-sectional view of the G-H cross-section of FIG. 10(A).

[0206] Note that the circuit diagram of the pixel circuit in FIG. 10 is as shown in FIG. 8.

[0207] The conductive layer 603 constitutes part of the other electrode of the capacitive element C.

[0208] If the conductive layer 603 is formed in the same process as the conductive layer 601 which serves as the pixel electrode, the number of steps will not increase. Sautéing is preferable.

[0209] The conductive layer 603 communicates with the conductive layer 402 through contact holes provided in the insulating layer 500. They are electrically connected.

[0210] Furthermore, in order to reduce the contact resistance between the conductive layer 603 and the conductive layer 402, contact holes are provided. It is preferable to have multiple options.

[0211] By using the above configuration, the width of the other electrode of the capacitive element C can be increased. This allows us to increase the capacitance of the capacitive element C.

[0212] Furthermore, since the conductive layer 603 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0213] In addition, in Figure 10, the conductive layer 403 and the conductive layer 101 may be in direct contact.

[0214] Furthermore, the light-emitting element in this embodiment can be replaced with other display elements (liquid crystal elements, electrophoretic elements, etc.). You can.

[0215] In other words, this embodiment is applicable to display devices in general.

[0216] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0217] (Embodiment 8) The configuration for increasing the capacitance of the capacitive element is shown in FIG. 11.

[0218] FIG. 11(A) shows a configuration in which a conductive layer 604 is added in FIG. 9.

[0219] FIG. 11(B) corresponds to a cross-sectional view of the I-J cross section of FIG. 11(A).

[0220] Note that the circuit diagram of the pixel circuit in FIG. 11 is as shown in FIG. 8.

[0221] The conductive layer 604 constitutes a part of one electrode of the capacitive element C.

[0222] Forming the conductive layer 604 in the same process as the conductive layer 601 serving as the pixel electrode is preferable because the number of processes does not increase.

[0223] The conductive layer 604 is electrically connected to the conductive layer 101 through contact holes provided in the insulating layer 200 and the insulating layer 500.

[0224] [[ID=`32]]Note that it is preferable to provide a plurality of contact holes in order to reduce the contact resistance between the conductive layer 604 and the conductive layer 101.

[0225] With the above configuration, since the other electrode of the capacitive element C is sandwiched by one electrode of the capacitive element, the capacitance of the capacitive element C can be increased.

[0226] Also, when the area of the conductive layer 604 in FIG. 11 is the same as the area of the conductive layer 603 in FIG. 10, in FIG. 11, since the other terminal (the other electrode) of the capacitive element C is sandwiched by one terminal (one electrode) of the capacitive element, the capacitance of the capacitive element C in FIG. 11 is larger than the capacitance of the capacitive element C in FIG. 10. [[ID=``45]]

[0227] Furthermore, since the conductive layer 604 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0228] In addition, in Figure 11, the conductive layer 403 and the conductive layer 101 may be in direct contact.

[0229] Furthermore, the light-emitting element in this embodiment can be replaced with other display elements (liquid crystal elements, electrophoretic elements, etc.). You can.

[0230] In other words, this embodiment is applicable to display devices in general.

[0231] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0232] (Embodiment 9) Figure 12 shows a configuration for increasing the capacitance of a capacitive element.

[0233] Figure 12(A) shows the configuration in which the conductive layer 604 is added to Figure 9.

[0234] Figure 12(B) corresponds to the cross-sectional view of the I2-J2 section in Figure 12(A).

[0235] The circuit diagram for the pixel circuit in Figure 12 is shown in Figure 8.

[0236] The conductive layer 604 constitutes a part of one electrode of the capacitive element C.

[0237] If the conductive layer 604 is formed in the same process as the conductive layer 601 which serves as the pixel electrode, the number of steps will not increase. Sautéing is preferable.

[0238] The conductive layer 604 is connected to the insulating layer 200 and the insulating layer 500 via contact holes. It is electrically connected to the conductive layer 101.

[0239] Here, in Figure 12, an opening is provided in the conductive layer 402 (wiring V (power line)). ru.

[0240] Furthermore, in Figure 12, contact holes are provided in the insulating layer 200 and the insulating layer 500. It is located inside the opening provided in the conductive layer 402 (wiring V (power line)).

[0241] In other words, conductive layer 604 and conductive layer 101 are located inside the opening provided in conductive layer 402. They are electrically connected.

[0242] Furthermore, in order to reduce the contact resistance between the conductive layer 604 and the conductive layer 101, contact holes are provided. It is preferable to have multiple options.

[0243] Furthermore, if multiple contact holes are provided in the insulating layer 200 and the insulating layer 500, the conductive layer It is preferable to provide multiple openings in 402 that correspond to multiple contact holes.

[0244] By using the above configuration, the other electrode of the capacitive element C is connected to one electrode of the capacitive element. Because the structure involves sandwiching the element between poles, the capacitance of the capacitive element C can be increased.

[0245] Furthermore, in Figure 12, an opening is provided in the conductive layer 402 (wiring V (power line)). Therefore, the size of the conductive layer 604 can be reduced compared to Figure 11.

[0246] Therefore, Figure 12 allows for a larger aperture ratio compared to Figure 11.

[0247] Furthermore, since the conductive layer 604 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0248] In addition, in Figure 12, the conductive layer 403 and the conductive layer 101 may be in direct contact.

[0249] Furthermore, the light-emitting element of this embodiment can be replaced with other display elements (liquid crystal elements, electrophoretic elements, etc.). You can.

[0250] In other words, this embodiment is applicable to display devices in general.

[0251] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0252] (Embodiment 10) When using a TFT with an inverse staggered structure, the second electrode of the light-emitting element (counter electrode, upper It is more preferable to provide auxiliary wiring (auxiliary electrodes) for the electrodes.

[0253] For example, Figure 13 illustrates a configuration in which a conductive layer 605 is added to the one in Figure 6.

[0254] Figure 13(B) corresponds to the cross-sectional view of the KL section in Figure 13(A).

[0255] The conductive layer 605 functions as auxiliary wiring for the conductive layer 900, which becomes the second electrode of the light-emitting element. To possess.

[0256] The conductive layer 605 conducts through openings (contact holes) provided in the insulating layer 700. It is electrically connected to layer 900.

[0257] Note that the conductive layer 605 in Figure 13 has a shape with multiple openings (lattice-like, mesh-like). be.

[0258] In Figure 13, a configuration was shown in which one pixel electrode was placed in one aperture, A structure in which multiple pixel electrodes are arranged in the aperture is also possible.

[0259] Furthermore, when a planarized film is used as the insulating layer 700, the openings provided in the insulating layer 700 ( The contact holes are formed in a position that overlaps with the conductive layer 102 (wiring G (gate wire)). Therefore, the probability of the conductive layer 900 breaking can be reduced.

[0260] Furthermore, a dummy semiconductor layer (electrically) formed in the same process as the semiconductor layer used in the transistor. An isolated semiconductor layer (floating semiconductor layer) is connected to an opening (corner) provided in the insulating layer 700. By positioning it in a location that overlaps with the contact hole, the probability of the conductive layer 900 breaking is reduced. It can be reduced.

[0261] Furthermore, since the conductive layer 605 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0262] In addition, in Figure 13, the conductive layer 403 and the conductive layer 101 may be in direct contact.

[0263] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0264] (Embodiment 11) In Figure 13, the position overlaps with the opening (contact hole) provided in the insulating layer 700. Figure 14 shows a configuration in which a conductive layer 405 is placed.

[0265] The conductive layer 405 is a dummy electrode (an electrically isolated electrode, a floating electrode).

[0266] The conductive layer 405 is formed in the same process as the source and drain electrodes used in the transistor. This is preferable because it does not increase the number of steps involved.

[0267] By providing the conductive layer 405, the probability of the conductive layer 900 breaking can be reduced. Cut.

[0268] Furthermore, a dummy semiconductor layer (electrically) formed in the same process as the semiconductor layer used in the transistor. An isolated semiconductor layer (floating semiconductor layer) is connected to an opening (corner) provided in the insulating layer 700. By positioning it in a location that overlaps with the contact hole, the probability of the conductive layer 900 breaking is reduced. It can be reduced.

[0269] Furthermore, since the conductive layer 605 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0270] In addition, in Figure 14, the conductive layer 403 and the conductive layer 101 may be in direct contact.

[0271] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0272] (Embodiment 12) Figures 15 and 16 show the openings (contact holes) provided in the insulating layer 700 in Figure 13. This configuration involves placing the wires at the intersections of the wires.

[0273] Figure 15 shows the conductive layer 102 corresponding to wiring G (gate wire) and the conductive layer corresponding to wiring V (power line). The configuration includes an opening (contact hole) at the intersection with the electrical layer 402.

[0274] Figure 16 shows the conductive layer 102 corresponding to wiring G (gate wire) and the conductive layer corresponding to wiring S (signal wire). The configuration includes an opening (contact hole) at the intersection with the electrical layer 404.

[0275] Figures 15 and 16 show that the probability of the conductive layer 900 breaking is reduced compared to Figure 13. Cut.

[0276] Furthermore, a dummy semiconductor layer (electrically) formed in the same process as the semiconductor layer used in the transistor. An isolated semiconductor layer (floating semiconductor layer) is connected to an opening (corner) provided in the insulating layer 700. By positioning it in a location that overlaps with the contact hole, the probability of the conductive layer 900 breaking is reduced. It can be reduced.

[0277] Furthermore, since the conductive layer 605 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0278] Furthermore, even if the conductive layer 403 and the conductive layer 101 are in direct contact as shown in Figures 15 and 16... good.

[0279] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0280] (Embodiment 13) Figures 17 and 18 show the openings (contact holes) provided in the insulating layer 700 in Figure 13. This configuration involves placing the conductive layer 404 (wiring) in a position that overlaps with it.

[0281] When a planarized film is used as the insulating layer 700, the opening (contact hole) is made of conductive layer 40 By arranging it in a position that overlaps with 4 (wiring), the conductive layer 900 is less likely to break. The rate can be reduced.

[0282] Figure 18 shows the opening (contact hole) provided in the insulating layer 700 in Figure 17 and The configuration involves placing a conductive layer 103 in an overlapping position.

[0283] Figure 17(B) is a cross-sectional view of the OP section in Figure 17(A).

[0284] Furthermore, Figure 18(B) is a cross-sectional view of the QR section in Figure 18(A).

[0285] The conductive layer 103 is a dummy electrode (an electrically isolated electrode, a floating electrode).

[0286] If the conductive layer 103 is formed using the same process as the gate electrode used in the transistor, the number of process steps will increase. It is preferable because it does not do so.

[0287] By providing the conductive layer 103, the probability of the conductive layer 900 breaking can be reduced. Cut.

[0288] Furthermore, a dummy semiconductor layer (electrically) formed in the same process as the semiconductor layer used in the transistor. An isolated semiconductor layer (floating semiconductor layer) is connected to an opening (corner) provided in the insulating layer 700. By positioning it in a location that overlaps with the contact hole, the probability of the conductive layer 900 breaking is reduced. It can be reduced.

[0289] Furthermore, since the conductive layer 605 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0290] Furthermore, even if the conductive layer 403 and the conductive layer 101 are in direct contact as shown in Figures 17 and 18... good.

[0291] Furthermore, in this embodiment, the openings (contact holes) provided in the insulating layer 700 and Although the conductive layer 103 was placed on top of the conductive layer 404, it may also be placed on top of the conductive layer 402. .

[0292] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0293] (Embodiment 14) Figures 19 and 20 show the openings (contact holes) provided in the insulating layer 700 in Figure 13. The structure is such that the conductive layer 104 and the conductive layer 406 are placed in superimposition with the conductive layer 104.

[0294] The conductive layer 104 is a dummy electrode (an electrically isolated electrode, a floating electrode).

[0295] If the conductive layer 104 is formed using the same process as the gate electrode used in the transistor, the number of process steps will increase. It is preferable because it does not do so.

[0296] By providing the conductive layer 104, the probability of the conductive layer 900 breaking can be reduced. Cut.

[0297] The conductive layer 406 is a dummy electrode (an electrically isolated electrode, a floating electrode).

[0298] The conductive layer 406 is formed in the same process as the source and drain electrodes used in the transistor. This is preferable because it does not increase the number of steps involved.

[0299] By providing the conductive layer 406, the probability of the conductive layer 900 breaking can be reduced. Cut.

[0300] In this embodiment, both conductive layer 104 and conductive layer 406 were formed, but conductive layer 1 Alternatively, the configuration may consist of forming only one of the 04 or the conductive layer 406.

[0301] Furthermore, if a notch is provided in the pixel electrode as shown in Figure 20, and a dummy electrode is placed in the notch, Compared to Figure 19, the area of ​​the pixel electrodes can be increased, thus improving the aperture ratio. It is possible.

[0302] Furthermore, a dummy semiconductor layer (electrically) formed in the same process as the semiconductor layer used in the transistor. An isolated semiconductor layer (floating semiconductor layer) is connected to an opening (corner) provided in the insulating layer 700. By positioning it in a location that overlaps with the contact hole, the probability of the conductive layer 900 breaking is reduced. It can be reduced.

[0303] Alternatively, a dummy semiconductor layer may be formed without creating dummy electrodes.

[0304] Furthermore, since the conductive layer 605 is formed in a space where there are no pixel electrodes, the pixel electrodes It allows for the effective use of non-existent space.

[0305] Furthermore, even if the conductive layer 403 and the conductive layer 101 are in direct contact as shown in Figures 19 and 20... good.

[0306] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0307] (Embodiment 15) The shape of the conductive layer 605 is not limited to a shape having multiple openings (lattice-like, mesh-like). It can be made into various shapes.

[0308] For example, as shown in Figure 21, a linear shape along the conductive layer 102 (wiring G (gate wire)) and You can.

[0309] For example, as shown in Figure 22, the conductive layer 404 (wiring S (signal line)) is made linear. You can.

[0310] Of course, it may also be in the form of a linear shape along the conductive layer 402 (wiring V (power line)).

[0311] Multiple conductive layers 605 may be provided.

[0312] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0313] (Embodiment 16) When multiple openings (contact holes) are formed in the insulating layer 700, the conductive layer 60 This is preferable because it ensures a reliable electrical connection between 5 and the conductive layer 900.

[0314] In this case, multiple types of formation positions described across multiple other embodiments are combined. They may be carried out together (for example, by creating a first opening in a position that overlaps with wiring G (gate wire)). (And, for example, a second opening is provided in a position that overlaps with the wiring V (power line).)

[0315] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0316] (Embodiment 17) Any type of circuit can be applied to the pixel circuit of a light-emitting device.

[0317] For example, Figure 23 shows an example of a pixel circuit for a light-emitting device.

[0318] Figure 23 shows the circuit in Figure 5 with transistor Tr3, wiring G2, and wiring R added. be.

[0319] Transistor Tr3 is called a reset transistor or erase transistor. It is also said.

[0320] Wiring G2 has the function of supplying a signal that controls the conduction and non-conductivity of transistor Tr3. .

[0321] Wiring R corresponds to the reset line (erase line).

[0322] The reset line (erase line) supplies a signal to reset the voltage held in the pixel circuit. It has the function of doing so.

[0323] The gate of transistor Tr3 is electrically connected to wiring G2.

[0324] Either the source or the drain of transistor Tr3 is electrically connected to the wiring R.

[0325] The source or drain of transistor Tr3 is connected to the gate of transistor Tr2. They are directly connected.

[0326] Note that in Figure 23, wiring R and wiring V may be shared.

[0327] That is, in Figure 23, without providing wiring R, the source or drain of transistor Tr3 One side may be electrically connected to wiring V.

[0328] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0329] (Embodiment 18) Any type of circuit can be applied to the pixel circuit of a light-emitting device.

[0330] For example, Figure 24 shows an example of a pixel circuit in a light-emitting device.

[0331] The pixel circuit of the light-emitting device shown in Figure 24 consists of transistors Tr1 to Tr6, Wire S (signal wire), wiring G1~Wiring G3 (gate wire), wiring R (reset wire), wiring V (electrical wire) It has a power source, a capacitive element C1, a capacitive element C2, and a light-emitting element EL (EL element).

[0332] Transistors Tr1 to Tr6 are n-channel type transistors, but they are p-channel type transistors. Either a 1 / 2-type transistor or a 1 / 2-type transistor will work.

[0333] The wiring S is then electrically connected to either the source or the drain of transistor Tr1. It is being done.

[0334] Wiring G1 connects the gate of transistor Tr2 and the gate of transistor Tr5 to the electrical They are directly connected.

[0335] Wiring G2 connects the gate of transistor Tr1, the gate of transistor Tr4, and a capacitive element. One terminal (one electrode) of sub-C2 is electrically connected to [the other component].

[0336] Wiring G3 is electrically connected to the gate of transistor Tr6.

[0337] Wiring R is electrically connected to either the source or the drain of transistor Tr6. .

[0338] Wiring V connects either the source or drain of transistor Tr2 to one side of capacitive element C1. It is electrically connected to the terminal (one of the electrodes).

[0339] The light-emitting element EL is electrically connected to either the source or the drain of transistor Tr5. It is.

[0340] The other terminal (other electrode) of the capacitive element C1 and the source or slave of the transistor Tr6 The other side of the gate, the gate of transistor Tr3, and the source or drain of transistor Tr4. One end of the capacitor is electrically connected to the other terminal (the other electrode) of the capacitive element C2.

[0341] The other of the source or drain of transistor Tr1, and the source or drain of transistor Tr2 The other drain is electrically connected to either the source or the drain of transistor Tr3. It is being done.

[0342] The other of the source or drain of transistor Tr3, and the source or drain of transistor Tr4 The other end of the drain is electrically connected to the other end of the source or drain of transistor Tr5. It is being done.

[0343] The operation of the circuit in Figure 24 will be explained.

[0344] During the first period (reset period), wiring G3 is selected, and transistor Tr6 is led. The pixel circuit is reset to the normal state.

[0345] Note that wiring G1 and wiring G2 are not selected during the first period.

[0346] During the second period (writing period), wiring G2 is selected, and transistor Tr1, When transistor Tr4 becomes conductive, the video signal is written from wiring S.

[0347] Furthermore, wiring G1 and wiring G3 will not be selected during the second period.

[0348] In the third period (display period), wiring G1 is selected, and transistor Tr2, Current is supplied from the wiring V to the light-emitting element EL via transistors 3 and 5. .

[0349] Furthermore, wiring G2 and wiring G3 will not be selected during the third period.

[0350] In short, the process involves repeatedly selecting wiring G3, wiring G2, and wiring G1 in sequence.

[0351] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0352] (Embodiment 19) Any type of circuit can be applied to the pixel circuit of a light-emitting device.

[0353] For example, Figure 25 shows an example of a pixel circuit in a light-emitting device.

[0354] The pixel circuit of the light-emitting device shown in Figure 25 consists of transistors Tr1 to Tr6, Line S (signal line), wiring G1 to wiring G3 (gate lines), wiring V1 to wiring V2 (power lines), capacity It has a quantitative element C and a light-emitting element EL (EL element).

[0355] Then, wiring S is electrically connected to either the source or the drain of transistor Tr1. It is being done.

[0356] Wiring G1 connects the gate of transistor Tr1 and the gate of transistor Tr2 to the electrical They are directly connected.

[0357] Wiring G2 connects the gate of transistor Tr4 and the gate of transistor Tr5 to the electrical They are directly connected.

[0358] Wiring G3 is electrically connected to the gate of transistor Tr6.

[0359] Wiring V1 is electrically connected to either the source or the drain of transistor Tr3. ru.

[0360] Wiring V2 connects either the source or drain of transistor Tr5 to transistor Tr6 It is electrically connected to either the source or the drain of the device.

[0361] Note that if transistors Tr1 to Tr6 are all p-channel type transistors In this case, the first voltage applied to wiring V1 is higher than the second voltage applied to wiring V2. ru.

[0362] For example, if the first voltage is Vdd (a voltage higher than the reference potential) and the second voltage is Vss (a voltage higher than the reference potential) (A voltage lower than the quasi-potential.)

[0363] On the other hand, in the case where transistors Tr1 to Tr6 are all n-channel type transistors In this case, the first voltage applied to wiring V1 is lower than the second voltage applied to wiring V2. ru.

[0364] For example, if the first voltage is Vss (a voltage lower than the reference potential) and the second voltage is Vdd (a voltage lower than the reference potential) (This is a voltage higher than the quasi-potential.)

[0365] The light-emitting element EL is connected to either the source or drain of transistor Tr4, and transistor T It is electrically connected to the other side of the source or drain of r6.

[0366] The other of the source or drain of transistor Tr1, and the source or drain of transistor Tr5 The other end of the drain and one terminal (one electrode) of the capacitive element C are electrically connected. ru.

[0367] Either the source or drain of transistor Tr2, and the gate of transistor Tr3, The other terminal (the other electrode) of the capacitive element C is electrically connected to it.

[0368] The other of the source or drain of transistor Tr2, and the source or The other end of the drain is electrically connected to the other end of the source or drain of transistor Tr4. It is being done.

[0369] The operation of the circuit shown in Figure 25 will be explained below.

[0370] In the first period, wiring G1 and wiring G3 are selected, and transistor Tr1, Set transistors Tr2 and Tr6 to a conductive state.

[0371] Therefore, it is preferable that wiring G1 and wiring G3 are electrically connected.

[0372] Note that wiring G2 will not be selected during the first period.

[0373] In the second period, wiring G2 is selected, and transistors Tr4 and Tr5 This will be displayed as a conductive state.

[0374] Furthermore, wiring G1 and wiring G3 will not be selected during the second period.

[0375] When performing the above operations, the following configuration is preferable for simplifying the circuit.

[0376] Wiring G1 and G3 are electrically connected to the first terminal, and wiring G2 is electrically connected to the second terminal. Connect to it.

[0377] Then, the input signal is input directly to either the first terminal or the second terminal, and the first terminal Alternatively, the other terminal of the second terminal may be used to input an inverted signal of the input signal.

[0378] In this case, the input terminal for inputting the input signal and one of the first terminal or the second terminal are Electrically connected, the input terminal and the other of the first or second terminal are connected via an inverter circuit. By electrically connecting them, the circuit can be simplified, which is preferable.

[0379] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0380] (Embodiment 20) A configuration that effectively utilizes the space in the area outside the pixel where pixel electrodes are not formed. Here is an example.

[0381] Figure 26 is a modified version of Figure 4.

[0382] In Figure 26, the conductive layer 1212 is made of FPC1700 (Flexible Printed Circuit). It is used as a connecting wire between the ED circuit and the conductive layer 1230.

[0383] That is, current or voltage is transmitted from the FPC 1700 to the conductive layer 1230 via the conductive layer 1212. It will be supplied.

[0384] Furthermore, the conductive layer 1212 and the conductive layer 1230 are electrically connected at the end of the insulating layer 1130. It is being done.

[0385] The edges of the insulating layer 1130 are located outside the pixel area.

[0386] Furthermore, an opening is provided on the outside of the pixel portion, and the conductive layer 1212 is connected through the opening on the outside of the pixel portion. The conductive layer 1230 may be electrically connected to it.

[0387] Furthermore, a sealing material 1500 is provided between the end of the insulating layer 1130 and the mounting portion of the FPC 1700. It is placed there.

[0388] A sealing body 1600 is provided on the sealing material 1500.

[0389] As the sealing material, resin sealant, glass frit, etc., can be used.

[0390] The encapsulant is a substrate (for example, a glass substrate, a metal substrate, a plastic substrate, etc.), and the encapsulant is a substrate. Cans or similar containers can be used.

[0391] Furthermore, conductive layers 1300 and 1400 are arranged beneath conductive layer 1212.

[0392] To reduce the number of processes, the conductive layer 1300 is formed in the same process as the gate electrode of the transistor. It is preferable that the conductive layer is made of a material that is conductive.

[0393] To reduce the number of manufacturing steps, the conductive layer 1400 is connected to the source and drain electrodes of the transistor. It is preferable that the conductive layer is formed in the same process.

[0394] The conductive layer 1300 or conductive layer 1400 is, for example, used in wiring or dummy electrodes for a light-emitting device. These include electrically isolated electrodes, floating electrodes, etc.

[0395] Dummy electrodes (electrically isolated electrodes, floating electrodes) are used in light-emitting devices. It is an electrode that is electrically isolated from the wiring or electrodes.

[0396] Furthermore, if the insulating layer 1130 is a planarized film, the conductive layer 1300 and the conductive layer 1400 are insulated. When placed in a position that overlaps with the edge of layer 1130, the conductive layer 12 at the edge of the insulating layer 1130 This is preferable because it reduces the probability of the 30 wire breaking.

[0397] Furthermore, in the region between the end of the insulating layer 1130 and the mounting portion of the FPC 1700, By stacking layer 1300, conductive layer 1400, and conductive layer 1212, conductive layer 121 Since no irregularities are formed in the lower layer of 2, disconnection of the conductive layer 1212 can be prevented.

[0398] In addition, in Figure 26, a dummy semiconductor layer (electrical) is placed at a position that overlaps with the edge of the insulating layer 1130. When an isolated semiconductor layer (a floating semiconductor layer) is placed, the conductive layer 1230 becomes disconnected. This is preferable because it further reduces the probability of that happening.

[0399] It is preferable that the dummy semiconductor layer be formed using the same process as the semiconductor layer of the transistor. stomach.

[0400] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0401] (Embodiment 21) Figure 27 shows that in Figure 26, conductive layer 1212 and conductive layer 1400 are connected via a contact hole. This configuration involves electrical connections.

[0402] Figure 28 shows that in Figure 27, conductive layer 1300 and conductive layer 1400 are connected via a contact hole. This configuration involves electrical connections.

[0403] With the configuration shown in Figure 27, the conductive layer 1400 can be used as auxiliary wiring.

[0404] As shown in the configuration in Figure 28, conductive layers 1300 and 1400 are used as auxiliary wiring. It is possible.

[0405] Furthermore, it is preferable that the contact holes be located close to the edge of the insulating layer 1130. .

[0406] In other words, by bringing the edge of the insulating layer 1130 and the contact hole close together, conductivity is improved. Since the distance over which only one layer of layer 1212 is used as a connecting wire is shortened, conductive layer 1230 and F This can reduce the resistance present between the PC1700s.

[0407] Therefore, one contact hole is provided between the end of the sealing material 1500 and the end of the insulating layer 1130. It is preferable to provide multiple of these.

[0408] Furthermore, it is preferable to provide the contact holes in a location close to the mounting area of ​​the FPC1700. It's nice.

[0409] In other words, by bringing the mounting portion and contact hole of the FPC1700 closer together, Since the distance over which only one layer of conductive layer 1212 is used as wiring is shortened, conductive layer 1230 and F This can reduce the resistance present between the PC1700s.

[0410] Therefore, one or more contact holes are provided in a position that overlaps with the mounting portion of the FPC1700. It is preferable to provide several of them.

[0411] Furthermore, the FPC1700 and the conductive layer 1212 are made of a resin containing conductive particles (for example, anisotropic conductive It is fixed using a membrane or the like.

[0412] Here, the mounting portion of the FPC1700 is given a textured surface to ensure secure fastening.

[0413] Therefore, one or more contact holes are provided in a position that overlaps with the mounting portion of the FPC1700. Providing multiple connections is also preferable from the standpoint of ensuring secure adhesion between the FPC1700 and the conductive layer 1212. stomach.

[0414] From the perspective of ensuring more reliable adhesion between FPC1700 and conductive layer 1212, FPC1 It is preferable to provide multiple contact holes in positions that overlap with the mounting portion of 700.

[0415] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0416] (Embodiment 22) Deformation of a contact structure that electrically connects a conductive layer below a partition layer with a conductive layer above a partition layer. Here is an example.

[0417] In Figures 29 and 30, a conductive layer 4002 is formed on the substrate 4001.

[0418] To reduce the number of processes, the conductive layer 4002 is formed in the same process as the gate electrode of the transistor. It is preferable.

[0419] An insulating layer 4003 is formed on the conductive layer 4002.

[0420] A conductive layer 4004 is formed on the insulating layer 4003.

[0421] To reduce the number of manufacturing steps, the conductive layer 4004 is the same as the source and drain electrodes of the transistor. It is preferable to form it in a single step.

[0422] An insulating layer 4005 is formed on the conductive layer 4004.

[0423] A conductive layer 4006 is formed on the insulating layer 4005.

[0424] To reduce the number of steps involved, it is preferable to form the conductive layer 4006 in the same process as the pixel electrode.

[0425] An insulating layer 4007 is formed on the conductive layer 4006.

[0426] The insulating layer 4007 corresponds to the partition layer and is formed using a planarized film.

[0427] A conductive layer 4008 is formed on the insulating layer 4007.

[0428] The conductive layer 4008 corresponds to the upper electrode of the light-emitting element.

[0429] Furthermore, the insulating layer 4007 is provided with openings.

[0430] Furthermore, the conductive layer 4002 and the conductive layer 4004 are connected to the openings provided in the insulating layer 4007. Because they are arranged in an overlapping manner, in the opening provided in the insulating layer 4007 The conductive layer 4008 reduces the probability of disconnection.

[0431] Here, Figure 29(A) shows an example in which an opening is provided in the conductive layer 4004.

[0432] The openings in the conductive layer 4004 overlap with the openings in the insulating layer 4007. It is arranged in a circular pattern.

[0433] In Figure 29(A), the opening provided in the conductive layer 4004 is provided in the insulating layer 4007. It is smaller than the opening provided and is located inside the opening in the insulating layer 4007. .

[0434] By using the configuration shown in Figure 29(A), the openings provided in the insulating layer 4007 Because irregularities are created on the inside, the contact area between conductive layer 4006 and conductive layer 4008 is increased. It is possible.

[0435] By increasing the contact area between conductive layer 4006 and conductive layer 4008, conductive layer 40 The contact resistance between 06 and the conductive layer 4008 is reduced.

[0436] Furthermore, since it is sufficient to create irregularities on the inside of the openings provided in the insulating layer 4007, conductivity is achieved. A portion of the opening in layer 4004 protrudes from the opening in insulating layer 4007. It's okay to do so.

[0437] In other words, the openings provided in the insulating layer 4007 are provided in at least the conductive layer 4004. It has a region that overlaps with the outer periphery of the opening.

[0438] Figure 29(B) shows an example in which an opening is provided in the conductive layer 4002.

[0439] The openings in the conductive layer 4002 overlap with the openings in the insulating layer 4007. It is arranged in a circular pattern.

[0440] In Figure 29(B), the opening provided in the conductive layer 4002 is provided in the insulating layer 4007. It is smaller than the opening provided and is located inside the opening in the insulating layer 4007. .

[0441] By using the configuration shown in Figure 29(B), the openings provided in the insulating layer 4007 Because irregularities are created on the inside, the contact area between conductive layer 4006 and conductive layer 4008 is increased. It is possible.

[0442] By increasing the contact area between conductive layer 4006 and conductive layer 4008, conductive layer 40 The contact resistance between 06 and the conductive layer 4008 is reduced.

[0443] Furthermore, since it is sufficient to create irregularities on the inside of the openings provided in the insulating layer 4007, conductivity is achieved. A portion of the opening in layer 4002 protrudes from the opening in insulating layer 4007. It's okay to do so.

[0444] In other words, the openings provided in the insulating layer 4007 are provided in at least the conductive layer 4002. It has a region that overlaps with the outer periphery of the opening.

[0445] Figure 29(C) shows an example in which openings are provided in the conductive layer 4002 and the conductive layer 4004.

[0446] The openings provided in the conductive layer 4002 and the conductive layer 4004 are provided in the insulating layer 4007. It is positioned to overlap with the opening.

[0447] In Figure 29(C), the openings provided in conductive layer 4002 and conductive layer 4004 are insulated Smaller than the opening provided in the edge layer 4007, and within the opening provided in the insulating layer 4007 It is positioned to the side.

[0448] By using the configuration shown in Figure 29(C), the openings provided in the insulating layer 4007 Because irregularities are created on the inside, the contact area between conductive layer 4006 and conductive layer 4008 is increased. It is possible.

[0449] By increasing the contact area between conductive layer 4006 and conductive layer 4008, conductive layer 40 The contact resistance between 06 and the conductive layer 4008 is reduced.

[0450] Furthermore, since it is sufficient to create irregularities on the inside of the openings provided in the insulating layer 4007, conductivity is achieved. A portion of the openings provided in layer 4002 and conductive layer 4004 is provided in insulating layer 4007. It's okay if it sticks out of the opening.

[0451] In other words, the opening provided in the insulating layer 4007 is at least connected to the conductive layer 4002 and the conductive layer It has regions that overlap with the outer periphery of the openings provided in layer 4004.

[0452] On the other hand, from the standpoint of preventing disconnection of the conductive layer 4008, as shown in Figure 29(C), insulation An opening in the conductive layer 4004 is placed inside an opening in the layer 4007, and In addition, an opening provided in conductive layer 4002 is placed inside the opening provided in conductive layer 4004. It is preferable to place it there.

[0453] In other words, the openings in the insulating layer 4007 are smaller than the openings in the conductive layer 4004. The openings provided in the conductive layer 4004 are larger, and the openings provided in the conductive layer 4002 are larger. Make it larger than the department.

[0454] The above configuration creates a stepped shape, thus reducing the probability of the conductive layer 4008 breaking. It is possible.

[0455] Furthermore, Figure 30(A) shows a modified example of Figure 29(C).

[0456] In Figure 30(A), an opening 4009 is provided in the insulating layer 4007, and the conductive layer An opening 4010 is provided in 4004, and an opening 4011 is provided in the conductive layer 4002. It's being kicked.

[0457] Furthermore, part or all of the opening 4010 is positioned so as not to overlap with the opening 4011. It is being done.

[0458] By using the configuration shown in Figure 30(A), the number of bumps and ridges can be increased, as shown in Figure 29(A ) and (B) can reduce contact resistance.

[0459] By using the configuration shown in Figure 30(A), the opening 4010 and the opening are located within the opening 4009. If the region where part 4011 overlaps (the region with a deep groove) is not formed, or if the opening 4009 is not formed This reduces the area of ​​the region where openings 4010 and 4011 overlap (the region with a deep groove). Therefore, the probability of the conductive layer 4008 breaking can be reduced.

[0460] The conductive layer 4002 or conductive layer 4004 is, for example, used in wiring or dummy electrodes for a light-emitting device. These include electrically isolated electrodes, floating electrodes, etc.

[0461] Examples of wiring used in light-emitting devices include gate wiring, capacitive wiring, signal lines, power lines, and power lines. Disconnected wires, etc., can be used.

[0462] Dummy electrodes (electrically isolated electrodes, floating electrodes) are used in light-emitting devices. It is an electrode that is electrically isolated from the wiring or electrodes.

[0463] Furthermore, a dummy semiconductor layer (electrically) is placed in a position that overlaps with the opening provided in the insulating layer 4007. When isolated semiconductor layers (floating semiconductor layers) are placed, the conductive layer 4008 becomes disconnected. This is preferable because the probability is further reduced.

[0464] It is preferable that the dummy semiconductor layer be formed using the same process as the semiconductor layer of the transistor. stomach.

[0465] Furthermore, when an opening in the insulating layer 4007 is provided at the intersection of the wiring (conductive layer 400 In the case where both 2 and the conductive layer 4004 are wiring, Figure 30(A) is particularly preferred. .

[0466] Here, Figure 30(B) shows that the opening provided in the insulating layer 4007 is provided at the intersection of the wiring. In this case, Figure 30(A) is shown as the case where it is adopted.

[0467] Parasitic capacitance occurs at the intersection of wires, but it is the area where the two wires overlap. It occurs in the region.

[0468] Therefore, as shown in Figures 30(A) and 30(B), the opening 4010 and the opening 4011 are By staggering their placement, the conductive layer 4002 (first wiring) and the conductive layer at the intersection The area of ​​the region where 4004 (the second wiring) and the other wiring overlap is reduced.

[0469] Therefore, parasitic capacitance at wiring intersections can be reduced.

[0470] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0471] (Embodiment 23) The technical concept of reducing parasitic capacitance at wiring intersections is applicable to semiconductor devices in general. be.

[0472] Semiconductor devices include all devices that have transistors, such as light-emitting devices and liquid crystal display devices. These include components such as storage devices, memory devices, CPUs, and RFID.

[0473] Figure 31 shows an example of a semiconductor device.

[0474] Figure 31(A) shows a cross-sectional view of the wiring intersection, and Figure 31(B) shows a top view of the wiring intersection. It is showing.

[0475] In other words, a conductive layer 4002 is formed on the substrate 4001.

[0476] The conductive layer 4002 corresponds to the first wiring.

[0477] To reduce the number of processes, the conductive layer 4002 is formed in the same process as the gate electrode of the transistor. It is preferable.

[0478] An insulating layer 4003 is formed on the conductive layer 4002.

[0479] A conductive layer 4004 is formed on the insulating layer 4003.

[0480] The conductive layer 4004 corresponds to the second wiring.

[0481] To reduce the number of manufacturing steps, the conductive layer 4004 is the same as the source and drain electrodes of the transistor. It is preferable to form it in a single step.

[0482] An insulating layer 4005 is formed on the conductive layer 4004.

[0483] Parasitic capacitance occurs at the intersection of wires, but it is the area where the two wires overlap. It occurs in the region.

[0484] Therefore, openings 4010 and 4011 are positioned offset from each other as shown in Figure 31. Therefore, at the intersection, conductive layer 4002 (first wiring) and conductive layer 4004 (second wiring) The area of ​​the region where the two overlap decreases.

[0485] Therefore, parasitic capacitance at wiring intersections can be reduced.

[0486] Furthermore, since the area of ​​the region where the wires overlap each other should be reduced, at the intersection... , the region where opening 4010 and opening 4011 overlap, and opening 4010 and opening 4011 It is acceptable to have both areas where and do not overlap, and areas where both exist.

[0487] Figure 32 shows examples of semiconductor devices other than light-emitting devices.

[0488] Figure 32(A) shows an example of a pixel circuit in a liquid crystal display device.

[0489] The circuit in Figure 32(A) consists of a transistor Tr, a capacitance element C, a liquid crystal element LC, and wiring G (G It has wiring S (signal line) and wiring CL (capacitance line).

[0490] Wiring G is electrically connected to the gate of transistor Tr.

[0491] Wiring S is electrically connected to either the source or the drain of transistor Tr.

[0492] The wiring CL is electrically connected to one terminal (one electrode) of the capacitive element C.

[0493] The other terminal of the source or drain of the transistor Tr and the other terminal of the capacitive element C (the other terminal The pole and the liquid crystal element (LC) are electrically connected.

[0494] Here, in Figure 32(A), there are two wiring combinations to which the configuration in Figure 31 can be applied, and For example, there are wiring G and wiring S, wiring G and wiring CL, etc.

[0495] Furthermore, in order to reduce the number of steps, the wiring S is connected to the source and drain electrodes of the transistor Tr. It is preferable to form them in the same process.

[0496] Furthermore, in order to reduce the number of processes, wiring G and wiring CL are the same as the gate electrode of transistor Tr. It is preferable to form it during the process.

[0497] Figure 32(B) shows an example of a cell circuit of a memory device.

[0498] Figure 32(B) shows an example of DRAM.

[0499] The circuit in Figure 32(B) consists of a transistor Tr, a capacitive element C, wiring W (word line), and wiring B. It has (bit lines) and wiring CL (capacitance lines).

[0500] Wiring W is electrically connected to the gate of transistor Tr.

[0501] Wiring B is electrically connected to either the source or the drain of transistor Tr.

[0502] The wiring CL is electrically connected to one terminal (one electrode) of the capacitive element C.

[0503] The other terminal of the source or drain of the transistor Tr and the other terminal of the capacitive element C (the other terminal The poles are electrically connected.

[0504] Here, in Figure 32(B), there are two wiring combinations to which the configuration in Figure 31 can be applied, and For example, there are wiring G and wiring S, wiring G and wiring CL, etc.

[0505] Furthermore, in order to reduce the number of steps, the wiring S is connected to the source and drain electrodes of the transistor Tr. It is preferable to form them in the same process.

[0506] Furthermore, in order to reduce the number of processes, wiring G and wiring CL are the same as the gate electrode of transistor Tr. It is preferable to form it during the process.

[0507] An example of a configuration based on Figures 31 and 32 is shown below.

[0508] Configuration A includes at least a transistor, a first wiring, and a second wiring. .

[0509] The first wiring has a first opening and is electrically connected to the gate of the transistor. .

[0510] The second wiring has a second opening and supplies electricity to either the source or the drain of the transistor. They are directly connected.

[0511] The second wiring is formed on or below the first wiring via an insulating layer. It intersects with the first wiring.

[0512] The first opening and the second opening are partly or entirely connected to the intersection of the first wiring and the second wiring. They are positioned in overlapping locations. That is, the first opening and the second opening protrude from the intersection. It's okay to do so.

[0513] The first opening and the second opening have regions that do not overlap at their intersection.

[0514] However, in order to reduce the parasitic capacity, the first and second openings must be completely at the intersection. A non-overlapping configuration is most preferable.

[0515] Configuration B includes at least a transistor, a first wiring, a second wiring, and a third wiring It has a wire and a capacitive element.

[0516] The first wiring has a first opening and is electrically connected to the gate of the transistor. .

[0517] The second wire is electrically connected to either the source or the drain of the transistor.

[0518] The third wiring has a third opening and is electrically connected to one terminal (one electrode) of the capacitive element. It is connected.

[0519] The other terminal (the other electrode) of the transistor's source or drain and the other terminal (the other electrode) of the capacitive element They are electrically connected.

[0520] The third wiring is formed on or below the first wiring via an insulating layer. It intersects with the first wiring.

[0521] The first opening and the third opening are partly or entirely connected to the intersection of the first wiring and the third wiring. They are positioned in overlapping locations. That is, the first opening and the third opening protrude from the intersection. It's okay to do so.

[0522] The first and third openings have regions that do not overlap at their intersection.

[0523] However, in order to reduce the parasitic capacity, the first and third openings must be completely closed at the intersection. A non-overlapping configuration is most preferable.

[0524] Furthermore, configurations A and B may be combined.

[0525] Furthermore, the transistors, capacitive elements, wiring, etc. described in this embodiment may differ from those in other embodiments. The described configuration can be applied.

[0526] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0527] (Embodiment 24) The materials used in each layer will be explained.

[0528] The substrates used include glass substrates, quartz substrates, metal substrates (such as stainless steel substrates), semiconductor substrates, etc. These are possible, but not limited to them.

[0529] A base insulating film may be formed on the substrate.

[0530] The insulating layer can be made of any material that has insulating properties. For example, Mechanical insulating films (silicon oxide film, silicon nitride film, silicon oxide film containing nitrogen, nitrogen containing oxygen) Silicon oxide film, aluminum nitride film, aluminum oxide film, hafnium oxide film), organic insulating film Edge films (polyimide films, acrylic films, siloxane films, etc.) can be used, but are not limited to these. It is not specified. The insulating layer may be a single-layer or multi-layer structure.

[0531] Furthermore, impurities such as alkali metals used in the light-emitting element can enter the transistor. To prevent this, all insulating layers below the partition layer (interlayer insulating film, gate insulating film, etc.) are made of inorganic insulating material. It is preferable to form a film.

[0532] The conductive layer can be made of any material that is conductive. For example, A Aluminum film, titanium film, molybdenum film, tungsten film, gold film, silver film, copper film, donor source Silicon films containing elements or acceptor elements, films made of various alloys, transparent conductive films ( Materials such as tin oxide can be used, but are not limited to these. The conductive layer is a single layer. It can be either a structural or layered structure.

[0533] The semiconductor layer can be made from any semiconductor material. It can also contain silicon. Semiconductor films, oxide semiconductor films, organic semiconductor films, etc. can be used, but are not limited to these. It is not possible. The semiconductor layer can be a single-layer structure or a multilayer structure. In the case of TFTs, element isolation is The formed semiconductor film (island-shaped semiconductor film) becomes the semiconductor layer. Transistors formed using an SOI substrate Distors are included in TFTs. Transits formed using silicon wafers In the case of STA, the silicon wafer itself corresponds to the semiconductor layer.

[0534] Furthermore, donor elements or acceptor elements are provided in the source and drain regions of the semiconductor layer. It is preferable to include it because it can lower the resistance of the source and drain regions. stomach.

[0535] Examples of semiconductor films containing silicon include silicon (Si) and silicon germanium (S). Examples include iGe (iGe) and silicon carbide (SiC), but are not limited to these.

[0536] The oxide semiconductor preferably contains indium (In) or zinc (Zn). It is particularly preferable to include both In and Zn.

[0537] Furthermore, stabilizers are used to reduce variations in the electrical characteristics of transistors using oxide semiconductors. As risers, gallium (Ga), tin (Sn), hafnium (Hf), and aluminum are used. It is preferable that the material contains (Al) or one or more selected from lanthanides.

[0538] Lanthanides include lanthanum (La), cerium (Ce), and praseodymium (Pr). Neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd) Terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (E) These include r), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0539] For example, as oxide semiconductors of a monochemical metal, indium oxide, tin oxide, zinc oxide, etc. It can be used.

[0540] Furthermore, for example, as oxide semiconductors of binary metals, In-Zn oxides and Sn-Zn oxides are used. Oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides Oxides, In-Ga-based oxides, etc., can be used.

[0541] Furthermore, for example, as an oxide semiconductor of a ternary metal, In-Ga-Zn oxide (IGZ (Also written as O), In-Sn-Zn oxides, Sn-Ga-Zn oxides, In-Al -Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce- Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Z n-based oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides Oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​acids Alkaloids, Al-Ga-Zn oxides, Sn-Al-Zn oxides, etc., can be used.

[0542] Furthermore, for example, as an oxide semiconductor of a quaternary metal, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al -Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc. You can use it.

[0543] For example, an In-Ga-Zn oxide contains In, Ga, and Zn. This refers to oxides, and the ratio of In, Ga, and Zn is not specified. Other metal elements may also be included.

[0544] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn acids with an atomic ratio of Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) Oxides or oxides with a similar composition can be used.

[0545] Alternatively, In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn Zn=2:1:3 (=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1: In-Sn-Zn oxides with an atomic ratio of 5 (=1 / 4:1 / 8:5 / 8) and their compositions in the vicinity. Oxides may also be used.

[0546] However, this is not limited to these, and includes the required semiconductor characteristics (mobility, threshold, variability, etc.). A suitable composition should be used depending on the requirements. Furthermore, in order to obtain the desired semiconductor properties, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to make it appropriate.

[0547] The semiconductor layer can be either a single crystal or a non-single crystal.

[0548] In the case of non-single crystals, they can be amorphous or polycrystalline. Furthermore, there may be crystalline parts within the amorphous material. Structures including this are also acceptable. However, since amorphous materials have many defects, non-amorphous materials are preferred. .

[0549] Furthermore, when forming a transistor with an inverse staggered structure, the space between the semiconductor layer and the source electrode, Furthermore, a donor element or an acceptor element is contained between the semiconductor layer and the drain electrode, respectively. An impurity semiconductor layer (buffer layer) may be interposed.

[0550] Furthermore, donor elements for silicon-containing semiconductors include, for example, phosphorus, and silicon-containing Examples of acceptor elements in semiconductors include boron.

[0551] When forming an organic EL element, the electroluminescent layer contains at least an organic compound. The light-emitting unit has a light-emitting layer.

[0552] When forming an organic EL element, the light-emitting unit includes an electron injection layer and an electron transport layer in addition to the light-emitting layer. It may also have a hole injection layer, a hole transport layer, etc.

[0553] Furthermore, when forming an organic EL element, multiple light-emitting units and multiple light-emitting units are used Brightness can be improved by having a structure that includes multiple charge generation layers. .

[0554] The charge generation layer can be made of metal, oxide conductor, or a layered structure of metal oxide and organic compound. A mixture of a specific oxide and an organic compound can be used.

[0555] As a charge generation layer, a layered structure of metal oxide and organic compound, and When a mixture of these is used, when a voltage is applied, holes are injected in the cathode direction and electricity is injected in the anode direction. It is suitable because it allows for the injection of the child.

[0556] Suitable metal oxides for use in the charge generation layer include vanadium oxide, niobium oxide, and tantalum oxide. chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, rhenium oxide, etc. It is a transition metal oxide.

[0557] Furthermore, as organic compounds used in the charge generation layer, amine compounds (especially arylamines) Transition metal oxides can be obtained by using compounds such as carbazole derivatives, aromatic hydrocarbons, and Alq. It is preferable because it forms a charge transfer complex.

[0558] When forming an inorganic EL element, the electroluminescent layer must contain at least an inorganic compound. The light-emitting unit has a light-emitting layer.

[0559] Furthermore, it is preferable to sandwich the light-emitting layer containing an inorganic compound between a pair of dielectric layers.

[0560] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0561] (Embodiment 25) This document presents an example of a method for fabricating a light-emitting device with a top-gate type TFT.

[0562] First, a semiconductor film is formed on the substrate, and then the semiconductor film is patterned to form island-shaped semiconductor layers. do.

[0563] A semiconductor film may be formed after an underlying insulating film is formed on the substrate surface.

[0564] Additionally, island-shaped dummy semiconductor layers may be formed when patterning the semiconductor film.

[0565] Next, a gate insulating film is formed on the semiconductor layer.

[0566] Next, a conductive film is formed on the gate insulating film, and the conductive film is patterned to form the gate electrode and wiring. This forms island-shaped dummy electrodes, etc.

[0567] Furthermore, pattern processing involves, for example, forming a mask on a predetermined film (starting film) and using the mask. This means processing a predetermined film (starting film) into a predetermined shape and removing the mask, etc.

[0568] Next, donor elements or acceptor elements are added to the semiconductor layer as needed.

[0569] Next, a first interlayer insulating film is formed on the gate electrode.

[0570] Next, contact holes are formed in the first interlayer insulating film and the gate insulating film.

[0571] Next, a conductive film is formed on the first interlayer insulating film, and the conductive film is patterned to form a source electrode. This forms drain electrodes, wiring, island-shaped dummy electrodes, etc.

[0572] Next, a second interlayer insulating film is formed on the source electrode and the drain electrode.

[0573] Next, contact holes are formed in the second interlayer insulating film.

[0574] Next, a conductive film is formed on the second interlayer insulating film, and the conductive film is patterned to form the first electrode. To form auxiliary wiring, etc.

[0575] Next, a planarization film is formed on the first electrode and the auxiliary wiring.

[0576] Next, openings are formed in the planarized film.

[0577] Furthermore, if the planarization film is photosensitive, the aperture can be formed by exposing and developing the planarization film. It is possible.

[0578] If the planarization film is non-photosensitive, openings can be formed by pattern processing. can.

[0579] Next, an electroluminescent layer is formed on the first electrode.

[0580] Next, a second electrode is formed on the electroluminescent layer, on the planarization film, and on the auxiliary wiring. To accomplish.

[0581] Furthermore, when forming the electroluminescent layer and the second electrode using a vapor deposition method, By using a mask, an electroluminescent layer of a predetermined shape and a second electrode can be formed. It is possible to form this.

[0582] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0583] (Embodiment 26) This document presents an example of a method for fabricating a light-emitting device having a bottom-gate type TFT.

[0584] In this embodiment, an example of a light-emitting device having a channel-etched TFT with an inverse staggered structure is provided. show.

[0585] First, a conductive film is formed on the substrate, and the conductive film is patterned to form gate electrodes, wiring, and island shapes. Dummy electrodes, etc., are formed.

[0586] A conductive film may be formed after an underlying insulating film is formed on the substrate surface.

[0587] Next, a gate insulating film is formed on the gate electrode.

[0588] The conductive layer of the same layer as the source electrode and drain electrode, and the conductive layer of the same layer as the gate electrode, directly When connecting, contact holes are formed in the gate insulating film.

[0589] On the other hand, when forming the connecting wiring which is formed in the same process as the first electrode (pixel electrode), The process of forming contact holes in the insulating film becomes unnecessary.

[0590] Next, a semiconductor film is formed on the gate insulating film, and the semiconductor film is patterned to form island-shaped semiconductors. It forms layers.

[0591] Furthermore, an impurity semiconductor film containing a donor element or an acceptor element is formed on the semiconductor film. Then, the semiconductor film and the impurity semiconductor film are patterned to form island-shaped semiconductor layers and island-shaped impurity semiconductor layers. A conductive layer may be formed.

[0592] Additionally, island-shaped dummy semiconductor layers may be formed when patterning the semiconductor film.

[0593] Furthermore, when patterning the impurity semiconductor film, island-shaped dummy impurity semiconductor layers are formed. You can.

[0594] Next, a conductive film is formed on the semiconductor layer and the gate insulating film, and the conductive film is patterned. Source electrodes, drain electrodes, wiring, island-shaped dummy electrodes, etc. are formed.

[0595] Furthermore, if an impurity semiconductor layer is formed, the impurity semiconductor between the source electrode and the drain electrode will be The body layer is etched and removed.

[0596] Furthermore, the process of patterning the conductive film, or the gap between the source electrode and the drain electrode The process of etching and removing the pure semiconductor layer between the source electrode and the drain electrode The surface of the semiconductor layer is etched.

[0597] Next, an interlayer insulating film is formed on the source electrode and the drain electrode.

[0598] Next, a first contact hole is formed in the interlayer insulating film, and the interlayer insulating film and gate insulating film are formed. A second contact hole is formed in the marginal film.

[0599] To reduce the number of steps, the first and second contact holes are formed simultaneously. It is preferable to do so.

[0600] Next, a conductive film is formed on the interlayer insulating film, and the conductive film is patterned to form the first electrode and connection wiring. Forms wires, auxiliary wiring, capacitive electrodes, etc.

[0601] Next, a planarization film is formed on the first electrode and the auxiliary wiring.

[0602] Next, openings are formed in the planarized film.

[0603] Furthermore, if the planarization film is photosensitive, the aperture can be formed by exposing and developing the planarization film. It is possible.

[0604] If the planarization film is non-photosensitive, openings can be formed by pattern processing. can.

[0605] Next, an electroluminescent layer is formed on the first electrode.

[0606] Next, a second electrode is formed on the electroluminescent layer, on the planarization film, and on the auxiliary wiring. To accomplish.

[0607] Furthermore, when forming the electroluminescent layer and the second electrode using a vapor deposition method, By using a mask, an electroluminescent layer of a predetermined shape and a second electrode can be formed. It is possible to form this.

[0608] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate.

[0609] (Embodiment 27) The light-emitting device and semiconductor device described in other embodiments are, for example, mounted on the display unit of an electronic device. It is possible to do so.

[0610] Electronic devices include televisions, computers, cameras, telephones (landlines, mobile phones), and mobile phones. While there are other types of terminals, such as band terminals, this list is not limited to these.

[0611] Some or all of the configurations described in this embodiment may be the same as the configurations described in other embodiments. It can be implemented in part or in whole, or in any combination as appropriate. [Explanation of Symbols]

[0612] 50 circuit boards 101 Conductive layer 102 Conductive layer 103 Conductive layer 104 Conductive layer 200 Insulating layer 301 Semiconductor layer 302 Semiconductor layer 401 Conductive layer 402 Conductive layer 403 Conductive layer 404 Conductive layer 405 Conductive layer 406 Conductive layer 500 Insulating layer 601 Conductive layer 602 Conductive layer 603 Conductive layer 604 Conductive layer 605 Conductive layer 700 Insulating layer 801 Electroluminescent layer 900 conductive layer 1050 circuit board 1100 transistors 1110 Semiconductor layer 1111 Insulating layer 1112 Conductive layer 1113 Insulating layer 1114 Conductive layer 1115 Conductive layer 1120 Insulating layer 1130 Insulating layer 1211 Conductive layer 1212 Conductive layer 1220 Electroluminescent layer 1230 Conductive layer 1300 conductive layer 1400 conductive layer 1500 sealing material 1600 Sealed body 1700 FPC 4001 circuit board 4002 Conductive layer 4003 Insulating layer 4004 Conductive layer 4005 Insulating layer 4006 Conductive layer 4007 Insulating layer 4008 Conductive layer 4009 Opening 4010 Opening 4011 Opening Tr Transistor Tr1 Transistor Tr2 transistor Tr3 transistor Tr4 transistor Tr5 transistor Tr6 transistor C Capacitive element C1 Capacitive element C2 Capacitive element S wiring R wiring V wiring V1 Wiring V2 wiring G wiring G1 Wiring G2 Wiring G3 Wiring CL wiring B Wiring W wiring EL light-emitting element LC liquid crystal element

Claims

1. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region, in a display device.

2. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. The wiring comprises a fourth conductive layer located in the same layer as the gate electrode of the first transistor, and a fifth conductive layer located in the same layer as one of the source electrode and drain electrode of the first transistor, in the display device.

3. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. In a plan view, the channel length direction of the first transistor is along the first direction, A display device in which, in a plan view, the channel length direction of the second transistor is aligned with the second direction.

4. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. It has a sixth conductive layer that functions as a gate wire and is electrically connected to the first transistor, A display device wherein the second opening overlaps with the sixth conductive layer.

5. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. The wiring comprises a fourth conductive layer located in the same layer as the gate electrode of the first transistor, and a fifth conductive layer located in the same layer as one of the source electrode and drain electrode of the first transistor. In a plan view, the channel length direction of the first transistor is along the first direction, A display device in which, in a plan view, the channel length direction of the second transistor is aligned with the second direction.

6. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. The wiring comprises a fourth conductive layer located in the same layer as the gate electrode of the first transistor, and a fifth conductive layer located in the same layer as one of the source electrode and drain electrode of the first transistor. It has a sixth conductive layer that functions as a gate wire and is electrically connected to the first transistor, A display device wherein the second opening overlaps with the sixth conductive layer.

7. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. In a plan view, the channel length direction of the first transistor is along the first direction, In a plan view, the channel length direction of the second transistor is along the second direction, It has a sixth conductive layer that functions as a gate wire and is electrically connected to the first transistor, A display device wherein the second opening overlaps with the sixth conductive layer.

8. A light-emitting element having a first electrode, an EL layer having a region located above the first electrode, and a second electrode having a region located above the EL layer, An insulating layer having a region covering the end of the first electrode, a first opening, and a second opening, and functioning as a partition layer, The aforementioned second electrode has electrically connected wiring, In a plan view, the wiring is a display device having a first region extending in a first direction, a second region extending in the first direction, a third region located between the first region and the second region and extending in a second direction that intersects the first direction so as to connect the first region and the second region, and a fourth region located between the first region and the second region and extending in a second direction so as to connect the first region and the second region, A first conductive layer having the function of the first electrode, The present invention comprises a second conductive layer having the function of a second electrode, The second conductive layer has a portion that overlaps with the first opening and a portion that overlaps with the second opening. In a plan view, the first conductive layer is positioned inside the portion enclosed by the first to fourth regions. In a plan view, the second conductive layer has a region that overlaps with the first conductive layer via the EL layer in the portion that overlaps with the first opening, In a plan view, the wiring has an overlap with the second opening in the third region. The second conductive layer is electrically connected to the wiring through the second opening. In a plan view, the second conductive layer does not have a portion in contact with the wiring in the portion that overlaps with the fourth region. A first transistor having a function for controlling the current supplied to the light-emitting element, A second transistor has one of its source and drain electrodes electrically connected to a signal line, and the other of its source and drain electrodes electrically connected to the first transistor. The wiring comprises a fourth conductive layer located in the same layer as the gate electrode of the first transistor, and a fifth conductive layer located in the same layer as one of the source electrode and drain electrode of the first transistor. In a plan view, the channel length direction of the first transistor is along the first direction, In a plan view, the channel length direction of the second transistor is along the second direction, It has a sixth conductive layer that functions as a gate wire and is electrically connected to the first transistor, A display device wherein the second opening overlaps with the sixth conductive layer.

9. In any one of claims 1 to 8, A display device in which, in a plan view, the first electrodes of a plurality of light-emitting elements are arranged inside the portion enclosed by the first to fourth regions.

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