Driver circuit

Abstract

A driver circuit according to the present invention comprises: a first-stage inverter circuit group (1) having M inverter circuits (11) to (1M) connected in series between a power source potential node and a ground potential node; a capacitor element group (40) corresponding to each of the M inverter circuits (11) to (1M) in the first-stage inverter circuit group (1) and having M capacitor elements (401) to (40M) connected in series between a power source potential node VDD and a ground potential node VSS; second to (M-1)th stage inverter circuit groups (2) to (M-1) which have one less inverter circuit than the number of inverter circuits in the preceding inverter circuit group, are connected without connecting a capacitor element between the output nodes of two inverter circuits in the preceding inverter circuit group, and in which input nodes are connected to the source node of the NMOS of the inverter circuit on the ground potential node side in the preceding inverter circuit group; and an Mth stage inverter circuit (M) which is connected without connecting a capacitor element between the output nodes of two inverter circuits (M-1)1, (M-1)2 in the (M-1)th stage inverter circuit group (M-1), and in which input nodes are connected to the source node of the NMOS of the inverter circuit (M-1)1.

Description

[Technical Field]

[0001] This disclosure relates to a House of Cards (HoC) type driver circuit using an inverter circuit made of CMOS (Complementary Metal Oxide Semiconductor). [Background technology]

[0002] Non-patent document 1 describes a CMOS power amplifier that generates high voltage using MOS transistors with low breakdown voltages. The power amplifier described in Non-Patent Document 1 has a three-stage HoC (High-End Cubic) configuration using inverter circuits made of CMOS, and all inverter circuits are connected in parallel with capacitive elements. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] LG Salem et al. “A Recursive Switched-Capacitor House-of-Cards Power Amplifier” IEEE Journal of Solid-State Circuits, vol. 52, no. 7, July 2017. PP1719-1738 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The power amplifier described in Non-Patent Document 1 has capacitive elements connected in parallel to each inverter circuit for all inverter circuits that have an HoC (Hospital of Cups) configuration, which results in a larger power amplifier circuit. As circuits become larger, the influence of parasitic capacitance in the wiring connecting inverter circuits increases, leading to the problem of longer rise and fall times in the output voltage of power amplifiers.

[0005] This disclosure aims to solve the above-mentioned problems and to provide a driver circuit with faster rise and fall times for the output voltage. [Means for solving the problem]

[0006] The driver circuit according to this disclosure comprises a first-stage inverter circuit group having M inverter circuits composed of PMOS and NMOS connected in series between a power supply potential node and a ground potential node, and M capacitive elements corresponding to each of the M inverter circuits in the first-stage inverter circuit group, connected in series between the power supply potential node and the ground potential node. Furthermore, the capacitance value of the m-th position capacitive element, which is positioned from the 1st to the Mth position, is the larger of either (m-1) times the parasitic capacitance value of the PMOS or (Mm) times the parasitic capacitance value of the NMOS. The number of capacitor elements and the inverter circuit composed of PMOS and NMOS is one less than the number of inverter circuits in the preceding inverter circuit group, and between the output nodes of the two inverter circuits in the preceding inverter circuit group Connect Furthermore, between the second to M-1 stage inverter circuit group, where the input node is connected to the source node of the PMOS of the inverter circuit on the ground potential node side in the preceding inverter circuit group, and the output nodes of the two inverter circuits in the M-1 stage inverter circuit group Connect The system includes an inverter circuit consisting of M-stage PMOS and NMOS transistors, where the input node is connected to the source node of the PMOS transistor in the inverter circuit on the ground potential node side of the M-1 stage inverter circuit group. [Effects of the Invention]

[0007] According to this disclosure, in an inverter circuit composed of subsequent PMOS and NMOS transistors, when no capacitive elements are connected between the output nodes of the two inverter circuits in the preceding inverter circuit group, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits. This configuration allows for faster rise and fall times in the output voltage of the driver circuit. [Brief explanation of the drawing]

[0008] [Figure 1] This is a diagram showing the driver circuit according to Embodiment 1. [Figure 2] This is a conceptual plan view showing the arrangement relationship between the capacitive element, the first-stage inverter circuit, and the input signal line in the driver circuit according to Embodiment 1. [Figure 3] This figure shows the operating state when the PMOS transistor of the inverter circuit is turned on in the driver circuit according to Embodiment 1. [Figure 4] This figure shows the operating state when the NMOS transistor of the inverter circuit is turned on in the driver circuit according to Embodiment 1. [Figure 5] This is a diagram showing the driver circuit according to Embodiment 2. [Figure 6] This figure shows the operating state when the PMOS transistor of the inverter circuit is turned on in the driver circuit according to Embodiment 2. [Figure 7] This figure shows the operating state when the NMOS transistor of the inverter circuit is turned on in the driver circuit according to Embodiment 2. [Figure 8] This is a diagram showing the driver circuit according to Embodiment 3. [Modes for carrying out the invention]

[0009] Embodiment 1. The driver circuit according to Embodiment 1 will be explained using Figures 1 to 4. The driver circuit according to Embodiment 1 is a driver circuit with a three-stage HoC (High-of-Climate) configuration using an inverter circuit made of CMOS. The driver circuit according to Embodiment 1 comprises a first-stage inverter circuit group 1, a second-stage inverter circuit group 2, a third-stage inverter circuit 3, and a capacitive element group 40.

[0010] First, we will explain the inverter circuits that make up each of the inverter circuit groups 1 to 3. As shown in Figure 1, the inverter circuit is a complementary CMOS inverter circuit consisting of a P-type MOS transistor (hereinafter abbreviated as PMOS) and an N-type MOS transistor (hereinafter abbreviated as NMOS) connected in series.

[0011] The drain electrode of the PMOS is electrically connected to the drain electrode of the NMOS, and this is electrically connected to the output node (output terminal) of the inverter circuit. The gate electrode of the PMOS and the gate electrode of the NMOS are electrically connected, and this is electrically connected to the input node (input terminal) of the inverter circuit. The source electrode of the PMOS is electrically connected to the source node (source terminal) of the PMOS in the inverter circuit. The source electrode of the NMOS is electrically connected to the source node (source terminal) of the NMOS in the inverter circuit.

[0012] PMOS and NMOS are formed and integrated on the surface of a semiconductor substrate using generally known semiconductor manufacturing techniques. In the following explanation, the inverter circuit corresponding to each stage will be matched with the sign of each stage, and in each stage, the ground potential node V SS The lowest-ranking inverter circuit, or the first-ranked one, located on the side, is the power supply potential node V. DD Numbers are assigned sequentially as subscripts.

[0013] For example, in the first stage inverter circuit group 1, the inverter circuit positioned in the first position is designated as 11, and the inverter circuit positioned in the third position, which is the highest position, is designated as 13. The inverter circuits in the second-stage inverter circuit group 2 and the third-stage inverter circuit group 3 are similarly denoted by reference numerals. Furthermore, in inverter circuits, PMOS is denoted with the subscript P, and NMOS with the subscript N. For example, the PMOS in inverter circuit 11 is 1 1P And NMOS is 1 1N It is expressed as follows.

[0014] The first-stage inverter circuit group 1 has three inverter circuits 11 to 13 connected in series between the power supply potential node V DD and the ground potential node V SS . In the inverter circuits 11 to 13, the source nodes of the PMOSs are on the power supply potential node V DD side, and the source nodes of the NMOSs are on the ground potential node V SS side and are connected in series.

[0015] That is, the source node of the NMOS of the inverter circuit 11 arranged in the first position is connected to the ground potential node V SS . The source node of the NMOS of the inverter circuit 12 arranged in the second position is connected to the source node of the PMOS of the inverter circuit 11. The source node of the NMOS of the inverter circuit 13 arranged in the third position is connected to the source node of the PMOS of the inverter circuit 12. The source node of the PMOS of the inverter circuit 13 arranged in the third position is connected to the power supply potential node V DD .[[ID=​​​​​​​​​​​​​SS Assuming the potential is 0V, the input signals input to each of the input terminals In1 to In3 are the signals shown in Figure 1.

[0018] In other words, the input signal input to the first input terminal In1 is a signal with a high level of 1V and a low level of 0V. The input signal input to the second input terminal In2 is a signal with a high level of 2V and a low level of 1V. The input signal input to the third input terminal In3 is a signal with a high level of 3V and a low level of 2V.

[0019] The second-stage inverter circuit group 2 has two inverter circuits 21 and 22, which is one less than the number of inverter circuits 11 to 13 in the first-stage inverter circuit group 1. The two inverter circuits 21 and 22 are connected in series. The two inverter circuits 21 and 22 are each connected to the ground potential node V. SS Starting from the side, the ground potential node V in the first stage inverter circuit group 1, which is the preceding stage. SS In a state where no capacitive element is connected between the output nodes of two adjacent inverter circuits connected in order from side to side, the source node of the PMOS is at the power supply potential node V of the two inverter circuits. DD The output node of the inverter circuit connected to the side has an NMOS source node at the ground potential node V of the two inverter circuits. SS It is electrically connected to the output node of the inverter circuit connected to the side.

[0020] In other words, the NMOS source node of the inverter circuit 21, which is located at the lowest position, i.e., the first position, is electrically connected to the output node of the inverter circuit 11, which is located at the first position in the first stage inverter circuit group 1. The PMOS source node of inverter circuit 21 is electrically connected to the output node of inverter circuit 12, which is located in the second position in the first stage inverter circuit group 1.

[0021] The source node of the NMOS inverter circuit 22, which is positioned at the top, i.e., second position, is electrically connected to the output node of the inverter circuit 12, which is positioned second position in the first stage inverter circuit group 1. The PMOS source node of inverter circuit 22 is electrically connected to the output node of inverter circuit 13, which is located in the third position, the highest position in the first stage inverter circuit group 1.

[0022] The input nodes of the two inverter circuits 21 and 22 are connected to the ground potential node V in the preceding first-stage inverter circuit group 1. SS The inverter circuits on the side are electrically connected to the source node of the PMOS of the inverter circuit in the first stage inverter circuit group 1. In other words, the input node of inverter circuit 21 is electrically connected to the PMOS source node of inverter circuit 11 and the NMOS source node of inverter circuit 12 of the first stage inverter circuit group 1. The input node of inverter circuit 22 is electrically connected to the PMOS source node of inverter circuit 12 and the NMOS source node of inverter circuit 13 of the first stage inverter circuit group 1.

[0023] In the third-stage inverter circuit 3, when no capacitive elements are connected between it and the output nodes of the two inverter circuits 21 and 22 in the second-stage inverter circuit group 2, the source node of the PMOS is at the power supply potential node V. DD The output node of the inverter circuit 22 connected to the side is connected, and the source node of the NMOS is at ground potential node V. SS It is connected to the output node of the inverter circuit 21 that is connected to the side. The input node of inverter circuit 3 is electrically connected to the PMOS source node of inverter circuit 21 and the NMOS source node of inverter circuit 22 in the second stage inverter circuit group 2. The output node of inverter circuit 3 is electrically connected to the output terminal Out by the output signal line 6.

[0024] The first-stage inverter circuit group 1, the second-stage inverter circuit group 2, and the third-stage inverter circuit 3 are formed vertically on the surface of the semiconductor substrate, with an insulating layer in between, in the order of the first, second, and third stages.

[0025] Inverter circuits 21 and 22 in the second-stage inverter circuit group 2 and inverter circuit 3 in the third-stage inverter circuit are connected between the output nodes of adjacent inverter circuits in the preceding inverter circuit group when no capacitive elements are connected. This allows for a shorter length of circuit wiring connecting the inverter circuits and reduces parasitic capacitance in the circuit wiring. As a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0026] Each of the capacitive element groups 40 corresponds to one of the three inverter circuits 11-13 in the first stage inverter circuit group 1, and is connected between the PMOS source node and the NMOS source node of the corresponding inverter circuits 11-13, and the power supply potential node V DD and ground potential node V SS It has three capacitive elements 401 to 403 connected in series between them.

[0027] The three capacitive elements 401-403 connected in series are at the power supply potential node V DD and ground potential node V SS It has the function of dividing the voltage between the two points into three parts. Power supply potential node V DD The potential applied to is V DD (For example, 3V) and ground potential node V SS If we set this to 0V, the potential at the connection point where the capacitive element 401, which is positioned in the first position, and the capacitive element 402, which is positioned in the second position, are connected is V DD / 3 (for example, 1V), the potential at the connection point where the second-position capacitive element 402 and the third-position capacitive element 403 are connected is 2·V. DD It becomes / 3 (for example, 2V).

[0028] Furthermore, the three capacitive elements 401-403, each holding a charge, control the PMOS 3 of inverter circuits 21, 22, and 3 in the second-stage inverter circuit group 2. 1P and NMOS3 1N It has the function of charging the gate electrode. The capacitive element 403, positioned in the third position (highest), is used when an L-level potential is input to each of the input terminals In1 to In3, and the PMOS of each inverter circuit is turned on (hereinafter abbreviated as "when the PMOS is turned on"), and the PMOS 2 of the inverter circuit 22, which is positioned in the second position (highest) of the second stage inverter circuit group 2, is used. 2P A negative voltage is applied between the gate electrode and source electrode of the PMOS2 in the inverter circuit 22. 2P Charge the gate electrode.

[0029] At the same time, the capacitive element 403 is connected to the PMOS 3 of the third stage inverter circuit 3. 1P A negative voltage is applied between the gate electrode and source electrode of the PMOS 3 in the inverter circuit 3. 1P Charge the gate electrode. Therefore, the capacitance value of the capacitive element 403 is the parasitic capacitance between the gate electrode and source electrode of the PMOS, C. P Therefore, PMOS2 2P and PMOS3 1P To turn it on, double the C P It's done that way.

[0030] As a result, the PMOS1 of inverter circuits 11-13 in the first stage inverter circuit group 1 1P ~1 3P When it turns ON, the PMOS2 in inverter circuit 22, which is located in the second position in the second stage inverter circuit group 2, 2P and the PMOS3 of the third stage inverter circuit 3 1P It is turned on. Therefore, the power supply potential node V is connected to the output terminal Out. DD The potential V applied to it DD (For example, 3V) is output.

[0031] The capacitive element 402, positioned in the second position (middle position), controls the PMOS in the inverter circuit 21, which is positioned in the first position in the second stage inverter circuit group 2, when the PMOS is turned on. 1P A negative voltage is applied between the gate electrode and source electrode of the PMOS2 in the inverter circuit 22. 1P Charge the gate electrode. Therefore, the capacitance value of the capacitive element 402 is PMOS2 1P To turn it on, C P The capacity value is required.

[0032] Furthermore, the capacitive element 402, positioned in the second position, is used when a high-level potential is input to each of the input terminals In1 to In3, and the NMOS of each inverter circuit is turned on (hereinafter abbreviated as "when the NMOS is turned on"), and the NMOS 2 of the inverter circuit 22, positioned in the second position of the second stage inverter circuit group 2, is turned on. 2N In the inverter circuit 22, a positive voltage is applied between the gate electrode and source electrode of the NMOS2 2N Charge the gate electrode.

[0033] Therefore, the capacitance value of the capacitive element 402 is the parasitic capacitance between the gate electrode and source electrode of the NMOS, C. N Therefore, NMOS2 2N To turn it on, C N The capacity value is required. Therefore, the capacitance value of the capacitive element 402 is C P or C N The capacity value is set to the larger of the two values.

[0034] The capacitive element 401, which is positioned in the first position (lowest position), is the NMOS2 in the inverter circuit 21, which is positioned in the first position (lowest position) in the second stage inverter circuit group 2, when the NMOS is turned on. 1N Charge the gate electrode. At the same time, the capacitive element 401 is the NMOS 3 of the third stage inverter circuit 3. 1NCharge the gate electrode. Therefore, the capacitance value of the capacitive element 401 is NMOS2 1N and NMOS3 1N To turn it on, double the C N It's done that way.

[0035] As a result, the NMOS1 of inverter circuits 11-13 in the first stage inverter circuit group 1 1N ~1 3N When it turns ON, the NMOS2 in inverter circuit 21, which is located in the first position in the second stage inverter circuit group 2, 1N and the NMOS3 of the third stage inverter circuit 3 1N It is turned on. Therefore, the output terminal Out is at ground potential node V. SS It is connected to ground (e.g., 0V).

[0036] Thus, the capacitance value of the third (highest) capacitive element 403 is doubled. P The capacitance value of the second (middle) position of the capacitance element 402 is set to C P or C N The capacitance value of the larger of the two values, the capacitance element 401 located in the first (lowest) position, is set to twice the C N Therefore, even if inverter circuit 21 is connected to the output node of inverter circuit 11 and the output node of inverter circuit 12, inverter circuit 22 is connected to the output node of inverter circuit 12 and the output node of inverter circuit 13, and inverter circuit 3 is connected to the output node of inverter circuit 21 and the output node of inverter circuit 22, without connecting any capacitive elements, the inverter circuits constituting inverter circuit groups 1 to 3 will operate quickly and complementaryly, whether the PMOS is turned on or the NMOS is turned on.

[0037] As a result, depending on the H and L levels input to each of the input terminals In1 to In3, the output terminal Out can output signals with fast rise and fall times and output voltages exceeding the withstand voltage of the PMOS and NMOS, such as 0V and 3V.

[0038] Furthermore, since the outputs of inverter circuits 11-13 in the first-stage inverter circuit group 1 are connected to capacitive elements 401-403 via PMOS or NMOS that constitute inverter circuits 11-13, a properly divided voltage is supplied between the PMOS source nodes and NMOS source nodes in inverter circuits 21, 22 and the third-stage inverter circuit 3 in the second-stage inverter circuit group 2, without the need to add capacitive elements between the PMOS source nodes and NMOS source nodes.

[0039] The capacitive element group 40 is modularized together with the first-stage inverter circuit group 1 to the third-stage inverter circuit group 3. Each of the capacitive elements 401 to 403 is composed of parallel metal plates, and the two electrodes (metal plates) have a long side and a short side. Capacitive elements 401 to 403 are positioned directly above each of the input signal lines 501 to 503, with an insulating layer in between, so that their short sides are perpendicular to the wiring direction of the input signal lines 501 to 503 and their long sides are parallel to the wiring direction of the input signal lines 501 to 503.

[0040] The arrangement of capacitive elements 401-403 and inverter circuits 11-13 of the first-stage inverter circuit group 1 will be explained using Figure 2. Figure 2 is a conceptual plan view that representatively shows the arrangement of the capacitive element 401, the inverter circuit 11, and the input signal line 501. The arrangement of capacitive elements 402 and 403 and the input signal lines 502 and 503 of inverter circuits 12 and 13 is the same as the arrangement of capacitive element 401, inverter circuit 11, and input signal line 501.

[0041] PMOS1 1P and NMOS1 1N Each has a comb-shaped gate electrode, and the gate electrode is electrically connected to the input signal line 50 via the input node of the inverter circuit 11. The wiring direction of the input signal line 50 is perpendicular to that of the gate electrode. PMOS11P The source electrode is formed in a comb shape and is electrically connected at one end to the P-side wiring layer (circuit wiring) via the source node of the PMOS of the inverter circuit 11. The P-side wiring layer is routed in parallel with the input signal line 50.

[0042] PMOS1 1P The drain electrode is positioned opposite the source electrode with the gate electrode in between, and is electrically connected to the output wiring layer via the output node of the inverter circuit 11. The wiring direction of the output wiring layer is opposite to that of the input signal line 50, and is positioned in a straight line with the input signal line 50.

[0043] NMOS1 1N The source electrode is formed in a comb shape and is electrically connected at the other end to the N-side wiring layer (circuit wiring) via the source node of the NMOS inverter circuit of the inverter circuit 11. The N-side wiring layer is routed parallel to the input signal line 50. NMOS1 1N The drain electrode is positioned opposite the source electrode with the gate electrode in between, and is electrically connected to the output wiring layer via the output node of the inverter circuit 11.

[0044] The input signal line 50, the output wiring layer, the P-side wiring layer, and the N-side wiring layer are formed on the surface of the semiconductor substrate by patterning the same layer of conductive material. The input signal line 50, the P-side wiring layer, and the N-side wiring layer are arranged in parallel. The capacitive element 401 is electrically insulated from the input signal line 501, the P-side wiring layer, and the N-side wiring layer, and is positioned between the P-side wiring layer and the N-side wiring layer.

[0045] The longer side of the capacitive element 401 is parallel to the input signal line 501, and its shorter side is located inside the outer edges of the P-side wiring layer and the N-side wiring layer. One electrode of the capacitive element 401 is electrically connected directly above the P-side wiring layer. The other electrode of the capacitive element 401 is electrically connected directly above the N-side wiring layer.

[0046] The length of the shorter side of each of the capacitive elements 401 to 403, indicated by W in Figure 2, is less than or equal to the distance between the source nodes of the PMOS and NMOS in the inverter circuit. Furthermore, the length of the longer side of each of the capacitive elements 401 to 403, indicated by L in Figure 2, is no more than five times the length of the shorter side.

[0047] The size of the electrodes in the capacitive elements 401 to 403 is such that the length of the short side W is less than or equal to the distance between the PMOS source node and the NMOS source node of the inverter circuit, and the length of the long side L is less than or equal to 5 times the length of the short side. As a result, the parasitic capacitance between the input signal lines 501 to 503 is small, and consequently, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0048] The capacitive element group 40 may be integrated together with the first-stage inverter circuit group 1 to the third-stage inverter circuit group 3 on the surface of the semiconductor substrate. In this case, each of the capacitive elements 401 to 403 is formed directly above each of the input signal lines 501 to 503 with an insulating layer in between, and is composed of electrodes made of a pair of conductive layers with an insulating layer interposed between them. Furthermore, each of the capacitive elements 401 to 403 is positioned between the P-side wiring layer and the N-side wiring layer such that the length of its short side W is less than or equal to the distance between the source nodes of the PMOS and NMOS in the inverter circuit, and the length of its long side L is less than or equal to five times the length of its short side.

[0049] Next, the operation of the driver circuit according to Embodiment 1 will be described. Power supply potential node V DD The potential applied to the ground potential node V is set to 3V. SS Let this voltage be 0V. The input signal input to the first input terminal In1 is a signal with a high level of 1V and a low level of 0V, the input signal input to the second input terminal In2 is a signal with a high level of 2V and a low level of 1V, and the input signal input to the third input terminal In3 is a signal with a high level of 3V and a low level of 2V.

[0050] First, we will explain the case where an input signal with a potential of L is input to each of the input terminals In1 to In3, using Figure 3. The low level potential of the input signal controls the PMOS 1 of inverter circuits 11-13 in the first stage inverter circuit group 1. 1P ~1 3P On, NMOS1 1N ~1 3N It is off.

[0051] Power supply potential node V DD and ground potential node V SS The potential states are as follows, depending on the charge held by each of the capacitive elements 401 to 403 that divide the voltage between them into three parts. In other words, the input node of the inverter circuit 22, which is positioned second in the second stage of the inverter circuit group 2, is set to 2V, which is the potential at the connection point between the capacitive element 403 and the capacitive element 402, due to the charge held by the capacitive element 403. PMOS1 of inverter circuit 13, which is positioned in the third position (highest position) in the first stage inverter circuit group 1 3P When this is turned on, the PMOS2 of the inverter circuit 22 2P It turns on.

[0052] The input node of the inverter circuit 21, which is positioned first in the second stage of the inverter circuit group 2, is set to 1V, which is the potential at the connection point between the capacitive element 402 and the capacitive element 401, due to the charge held by the capacitive element 402. PMOS1 of inverter circuit 12, which is positioned in the second position in the first stage inverter circuit group 1 2P When this is turned on, the PMOS2 of the inverter circuit 21 1P It turns on.

[0053] The input node of the third-stage inverter circuit 3 is the PMOS 1 of the inverter circuit 12, which is located in the second position in the first-stage inverter circuit group 1. 2PWhen it is turned on, the potential at the connection point between the capacitor element 403 and the capacitor element 402 becomes 2V due to the charge held by the capacitor element 403. PMOS1 of the inverter circuit 13 arranged in the third position in the first-stage inverter circuit group 1 3P and PMOS2 of the inverter circuit 22 2P When it is turned on, PMOS3 of the inverter circuit 3 1P is turned on.

[0054] PMOS1 of the inverter circuits 11 to 13 in the first-stage inverter circuit group 1 1P ~1 3P and PMOS2 of the inverter circuits 21 and 22 in the second-stage inverter circuit group 2 1P 、2 2P and PMOS3 of the third-stage inverter circuit 3 1P are turned on, and the potential in the circuit wiring connecting the inverter circuits becomes as follows as shown in FIG. 3.

[0055] That is, as shown by the solid line A1 in FIG. 3, from the power supply potential node V DD (one electrode of the capacitor element 403 arranged in the third position (highest position)), through the circuit wiring connecting the power supply potential node V DD to the source node of the PMOS of the inverter circuit 13 arranged in the third position (highest position) in the first-stage inverter circuit group 1, the circuit wiring connecting the output node of the inverter circuit 13 to the source node of the PMOS of the inverter circuit 22 arranged in the second position (highest position) in the second-stage inverter circuit group 2, the circuit wiring connecting the inverter circuit 22 to the source node of the PMOS of the third-stage inverter circuit 3, and the circuit wiring connecting the output node of the inverter circuit 3 to the output terminal Out, the potential of the path leading to the output terminal Out is 3V.

[0056] As shown by the dashed line B1 in Figure 3, the potential of the path from the other electrode of the capacitive element 403 located in the third position to the input node of the inverter circuit 22, via the circuit wiring connecting the other electrode of the capacitive element 403 to one electrode of the capacitive element 402 located in the second position, and the circuit wiring connecting the other electrode of the capacitive element 403 to the input node of the inverter circuit 22 located in the second position in the second stage inverter circuit group 2, is 2V. PMOS2 of inverter circuit 22 2P It turns on.

[0057] As shown by the dashed line B1 in Figure 3, the potential of the path from the other electrode of the capacitive element 403 to the source node of the NMOS in the inverter circuit 13, via the circuit wiring connecting the other electrode of the capacitive element 403 and the source node of the NMOS in the inverter circuit 13, is 2V.

[0058] Furthermore, as shown by the dashed line B1 in Figure 3, the potential of the path from the other electrode of the capacitive element 403 to the input node of the inverter circuit 3, via the circuit wiring connecting the other electrode of the capacitive element 403 to the source node of the PMOS of the inverter circuit 12 located in the second position in the first stage inverter circuit group 1, the circuit wiring connecting the output node of the inverter circuit 12 to the source node of the PMOS of the inverter circuit 21 located in the first position in the second stage inverter circuit group 2, and the circuit wiring connecting the output node of the inverter circuit 21 to the input node of the third stage inverter circuit 3, is 2V. PMOS3 of inverter circuit 3 1P It turns on.

[0059] As shown by the dashed line B1 in Figure 3, the potential of the path from the output node of inverter circuit 12 to the source node of the NMOS of inverter circuit 22 via the circuit wiring connecting the output node of inverter circuit 12 and the source node of the NMOS of inverter circuit 22 is 2V. NMOS2 of inverter circuit 22 2N It is off.

[0060] As shown by the dashed line B1 in Figure 3, the potential of the circuit wiring connecting the output node of inverter circuit 12 and the PMOS source node of inverter circuit 21, and the circuit wiring connecting the output node of inverter circuit 21 and the NMOS source node of inverter circuit 3, to the NMOS source node of inverter circuit 3 is 2V. NMOS3 of inverter circuit 3 1N It is off.

[0061] Furthermore, as shown by the dashed line C1 in Figure 3, the potential of the path from the other electrode of the capacitive element 402 positioned in the second position to the input node of the inverter circuit 21, via the circuit wiring connecting the other electrode of the capacitive element 402 to one electrode of the capacitive element 401 positioned in the first position, and the circuit wiring connecting the other electrode of the capacitive element 402 to the input node of the inverter circuit 21 positioned in the first position in the second stage inverter circuit group 2, is 1V. PMOS2 of inverter circuit 22 1P It turns on.

[0062] As shown by the dashed line C1 in Figure 3, the potential of the path from the other electrode of the capacitive element 402 to the source node of the NMOS in the inverter circuit 21, via the circuit wiring connecting the other electrode of the capacitive element 402 to the source node of the PMOS in the inverter circuit 11, and the circuit wiring connecting the output node of the inverter circuit 11 to the source node of the NMOS in the inverter circuit 21, is 1V. NMOS2 of inverter circuit 21 1N It is off. The source node of the NMOS in the inverter circuit 11 is 0V, as shown by the dashed line D1 in Figure 3.

[0063] Next, we will explain the case where an input signal with a high potential is input to each of the input terminals In1 to In3, using Figure 4. The H level potential of the input signal controls the NMOS1 of inverter circuits 11-13 in the first stage inverter circuit group 1. 1N ~1 3N On, PMOS1 1P ~13P It is off.

[0064] Power supply potential node V DD and ground potential node V SS The potential states are as follows, depending on the charge held by each of the capacitive elements 401 to 403 that divide the voltage between them into three parts. In other words, the input node of the inverter circuit 21, which is positioned in the first position (lowest position) in the second stage inverter circuit group 2, is set to 1V, which is the potential at the connection point between the capacitive element 402 and the capacitive element 401, due to the charge held by the capacitive element 402. NMOS1 of inverter circuit 11, which is positioned as the first (lowest) in the first stage inverter circuit group 1 1N When it is turned on, the NMOS2 of the inverter circuit 21 1N It turns on.

[0065] The input node of the inverter circuit 22, which is positioned second in the second stage of the inverter circuit group 2, is set to 2V, which is the potential at the connection point between the capacitive element 403 and the capacitive element 402, due to the charge held by the capacitive element 403. NMOS1 of inverter circuit 12, which is positioned in the second position in the first stage inverter circuit group 1 2N When it is turned on, the NMOS2 of the inverter circuit 22 2N It turns on.

[0066] The input node of the third-stage inverter circuit 3 is the NMOS1 of the inverter circuit 12, which is located in the second position in the first-stage inverter circuit group 1. 2N When the switch is turned on, the charge held by the capacitive element 402 causes the potential at the connection point between the capacitive element 402 and the capacitive element 401 to be 1V. NMOS1 of inverter circuit 11, which is positioned in the first position in the first stage inverter circuit group 1 1N and NMOS 21 of inverter circuit 21 2N When it is turned on, the NMOS3 of inverter circuit 3 1N It turns on.

[0067] NMOS1 of inverter circuits 11-13 in the first stage inverter circuit group 1 1N ~1 3N , the NMOS2 of inverter circuits 21 and 22 in the second stage inverter circuit group 2 1N , 2 2N , the NMOS3 of the third stage inverter circuit 3 1N When the inverter is turned on, the potential in the circuit wiring connecting the inverter circuits becomes as follows, as shown in Figure 4.

[0068] That is, as shown by the dashed line D2 in Figure 4, the ground potential node V SS (One electrode of the capacitive element 401, which is positioned in the first position (lowest position)) is at ground potential node V SS The following are electrically connected: the circuit wiring connecting the NMOS source node of inverter circuit 11, which is positioned first (highest) in the first stage inverter circuit group 1; the circuit wiring connecting the output node of inverter circuit 11 to the NMOS source node of inverter circuit 21, which is positioned first (lowest) in the second stage inverter circuit group 2; the circuit wiring connecting the output node of inverter circuit 21 to the NMOS source node of inverter circuit 3, and the circuit wiring connecting the output node of inverter circuit 3 to the output terminal Out. SS The potential in the path from the output terminal Out is 0V.

[0069] As shown by the dashed line C2 in Figure 4, the potential of the path from the other electrode of the capacitive element 402 positioned in the second position to the input node of the inverter circuit 21, via the circuit wiring connecting the other electrode of the capacitive element 402 to one electrode of the capacitive element 401 positioned in the first position, and the circuit wiring connecting the other electrode of the capacitive element 402 to the input node of the inverter circuit 21 positioned in the first position in the second stage inverter circuit group 2, is 1V. NMOS2 of inverter circuit 21 1N It turns on. PMOS2 of inverter circuit 21 1P It is off.

[0070] As shown by the dashed line C2 in Figure 4, the potential of the path from the other electrode of the capacitive element 402 to the input node of the inverter circuit 3, via the circuit wiring connecting the other electrode of the capacitive element 402 and the source node of the NMOS of the inverter circuit 12, and the circuit wiring connecting the output node of the inverter circuit 12 and the input node of the inverter circuit 3, is 1V. NMOS3 of inverter circuit 3 1N It turns on. PMOS3 of inverter circuit 21 1P It is off.

[0071] As shown by the dashed line C2 in Figure 4, the potential of the path from the other electrode of the capacitive element 402 to the source node of the PMOS of the inverter circuit 21, via the circuit wiring connecting the other electrode of the capacitive element 402 and the source node of the NMOS of the inverter circuit 12, and the circuit wiring connecting the output node of the inverter circuit 12 and the source node of the PMOS of the inverter circuit 21, is 1V. As shown by the dashed line C2 in Figure 4, the potential of the path from the output node of inverter circuit 12 to the source node of the NMOS transistor in inverter circuit 22 via the circuit wiring connecting the output node of inverter circuit 12 to the source node of the NMOS transistor in inverter circuit 22 is 1V.

[0072] As shown by the dashed line B2 in Figure 4, the potential of the path from the other electrode of the capacitive element 403 located in the third position to the input node of the inverter circuit 22, via the circuit wiring connecting the other electrode of the capacitive element 403 to one electrode of the capacitive element 402 located in the second position, and the circuit wiring connecting the other electrode of the capacitive element 403 to the input node of the inverter circuit 22 located in the second position in the second stage inverter circuit group 2, is 2V. NMOS2 of inverter circuit 22 2N It turns on. PMOS2 of inverter circuit 22 2P It is off.

[0073] As shown by the dashed line B2 in Figure 4, the potential of the path from the other electrode of the capacitive element 403 to the source node of the PMOS of the inverter circuit 12, which is located in the second position in the first stage inverter circuit group 1, via the circuit wiring connecting the other electrode of the capacitive element 403 to the source node of the PMOS of the inverter circuit 12, is 2V.

[0074] As shown by the dashed line B2 in Figure 4, the potential of the path from the other electrode of the capacitive element 403 to the source node of the NMOS in the inverter circuit 13, via the circuit wiring connecting the other electrode of the capacitive element 403 and the source node of the NMOS in the inverter circuit 13, is 2V. The source node of the PMOS in inverter circuit 13 is 3V, as shown by the solid line A2 in Figure 4.

[0075] The driver circuit according to Embodiment 1 is a three-stage driver circuit using an inverter circuit made of CMOS, where the power supply potential node V DD and ground potential node V SS A first-stage inverter circuit group 1 has three inverter circuits 11-13 connected in series between it and the power supply potential node V, which is connected between the PMOS source node and the NMOS source node of each of the three inverter circuits 11-13. DD and ground potential node V SSA group of capacitive elements 40 having three capacitive elements 401 to 403 connected in series between the first and second positions of an inverter circuit 11 and an inverter circuit 12, and a first-position inverter circuit 21, which is located in the first position and is connected without any capacitive elements between the output node of the first-position inverter circuit 11 and the output node of the second-position inverter circuit 12, and a group of capacitive elements 40 having three capacitive elements 401 to 403 connected in series between the first and second positions of an inverter circuit 11 and an inverter circuit 12, which is located in the first position and has an input node electrically connected to the PMOS source node of the inverter circuit 11 and the NMOS source node of the inverter circuit 12, and a group of capacitive elements 40 having three capacitive elements 401 to 403 connected in series between the first and second positions of an inverter circuit 11, and an inverter circuit 21, which is located in the first position and has an input node electrically connected to the PMOS source node of the inverter circuit 11 and the NMOS source node of the inverter circuit 12, and a group of capacitive elements 40 having three capacitive elements 401 to 403 connected in series between the first and second positions of an inverter circuit 12, and an inverter circuit 21, which is located in the first position and is connected without any capacitive elements between the output node of the first-position inverter circuit 11 and the output node of the second-position inverter circuit 12, and an inverter circuit 21, which is located in the first position and has an input node electrically connected to the PMOS source node of the inverter circuit 11 and the NMOS source node of the The driver circuit includes a second-stage inverter circuit group 2 having an inverter circuit 22 positioned in the second position and electrically connected to the NMOS source node of the driver circuit 13, and a third-stage inverter circuit 3 connected between the output node of inverter circuit 21 and the output node of inverter circuit 22 without connecting any capacitive elements, and whose input nodes are electrically connected to the PMOS source node of inverter circuit 21 and the NMOS source node of inverter circuit 22. As a result, the number of capacitive elements can be reduced, the length of the circuit wiring connecting the inverter circuits can be shortened, and parasitic capacitance occurring in the circuit wiring can be reduced, thereby speeding up the rise and fall times of the output voltage of the driver circuit.

[0076] Furthermore, in the driver circuit according to Embodiment 1, the capacitance value of the capacitive element 401 placed in the first position is the parasitic capacitance C of the NMOS. N The capacitance value of the second-position capacitance element 402, twice the capacitance value of the first element, is the parasitic capacitance C of the PMOS. P Or the parasitic capacitance C of an NMOS N The capacitance value of the PMOS is the larger of the two values, and the capacitance value of the third-position capacitance element 403 is the parasitic capacitance C. P Since the capacitance value is set to twice that of the original, the inverter circuits constituting inverter circuit groups 1 to 3 operate quickly and complementaryly, whether the PMOS or NMOS is turned on.

[0077] Furthermore, in the driver circuit according to Embodiment 1, the length of the short side of the electrodes of the capacitive elements 401 to 403 in the capacitive element group 40 is set to be less than or equal to the distance between the PMOS source node and the NMOS source node of the inverter circuit, and the length of the long side is set to be 5 times or less the length of the short side. As a result, the parasitic capacitance between the capacitive elements 401 to 403 and the input signal lines 501 to 503 is small, and consequently, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0078] Embodiment 2. The driver circuit according to Embodiment 2 will be described with reference to Figures 5 to 7. The driver circuit according to Embodiment 2 differs from the driver circuit according to Embodiment 1 in that it is an M-stage HoC-type driver circuit, whereas the driver circuit according to Embodiment 1 is a 3-stage HoC-type driver circuit. All other aspects are the same. M is a natural number greater than or equal to 4. In Figures 5 to 7, the same reference numerals as those used in Figures 1 to 4 indicate the same or corresponding parts.

[0079] The driver circuit according to Embodiment 2 is basically constructed using the same approach as the driver circuit according to Embodiment 1, and consists of M inverter circuits 11-1 as the first stage (initial stage) inverter circuit group 1. M This driver circuit has an M-stage HoC configuration, consisting of M-stage inverter circuit groups, each with one fewer inverter circuit than the preceding inverter circuit group. Note that the M-stage (final stage) inverter circuit group M is a single inverter circuit M.

[0080] As shown in Figure 5, the driver circuit according to Embodiment 2 comprises a first-stage inverter circuit group 1, a middle-stage inverter circuit group 2 to the (M-1)th stage inverter circuit group M-1, and a final-stage M-stage inverter circuit M and a capacitive element group 40. The first stage inverter circuit group 1 is at power supply potential node V. DD and ground potential node Vss M inverter circuits 11-1 connected in series between them M It holds.

[0081] Power supply potential node V DD The potential is such that the first stage inverter circuit group 1 has M inverter circuits 11~1 M Therefore, if the withstand voltage of the PMOS and NMOS constituting the inverter circuit is set to 1V each, then MV is M times 1V. Ground potential node V ss The potential is the ground potential, which is 0V.

[0082] From inverter circuit 11 to inverter circuit 1 M Each input node connects from the corresponding input terminal In1 to input terminal In M Each from input signal line 501 to input signal line 50 M They are electrically connected by this. From inverter circuit 11 to inverter circuit 1 M Each input node has input terminal In1 to input terminal In M Each input signal is input to it.

[0083] Input terminals In1~In M Each input signal has the same amplitude, the same phase, and is a DC level that is voltage-offset in order from the first input terminal In1, which is connected to the input node of the inverter circuit 11, which is positioned in the first position.

[0084] In other words, the input signal input to input terminal In1, which is positioned as the first (lowest) input terminal, is a signal with a potential of 0V at the low level and a potential of 1V at the high level. The input signal input to the second input terminal, In2, has a low-level potential of 1V, which is the same as the high-level potential of the input signal input to input terminal In1. The potential difference is the same as the potential difference of the input signal input to input terminal In1, and the high-level potential is 2V.

[0085] Similarly, the input signals input to the input terminal In, located from the 3rd position onwards (M-1st position), have a potential difference of 1V, and are signals whose potential is lower than the H level of the input signal input to the input terminal In located in the preceding position. Input terminal In, located in position M (highest position) M The input signal that is input to the device is a signal with a low level potential of (M-1)V and a high level potential of MV.

[0086] Each of the capacitive element group 40 is one of the M inverter circuits 11-1 in the first stage inverter circuit group 1. M Each corresponds to a corresponding inverter circuit 11-1 M It is connected between the PMOS source node and the NMOS source node, and the power supply potential node V DD and ground potential node V SS M capacitive elements 401-40 are connected in series between them. M It holds.

[0087] M capacitive elements 401-40 connected in series M Power supply potential node V DD and ground potential node V SS It has the function of dividing the voltage between and by M. The potential at the connection point where the first-position capacitive element 401 and the second-position capacitive element 402 are connected is V DD -V DD (M-1) / M(=V DD In Embodiment 1, the voltage is 1V, which is the same as the potential of the H level of the input signal input to the input terminal In1, which is located in the first position, and the potential of the L level of the input signal input to the input terminal In2, which is located in the second position.

[0088] In other words, the potential at the connection point where adjacent capacitive elements 40 are connected is the same as the potential of the H level input signal input to the lower input terminal In and the potential of the L level input signal input to the upper input terminal In.

[0089] Capacitive element 40 located at position M MCapacitive element 40 positioned at (M-1) M-1 The potential at the connection point where they are connected is V DD ―V DD / M(=V DD (M-1) / M) is the same as the potential of the H level of the input signal input to input terminal In1, which is located at position M-1, and the potential of the L level of the input signal input to input terminal In2, which is located at position M.

[0090] Also, M capacitive elements 401-40 M Each of these components has the function of charging the gate electrodes of the PMOS or NMOS transistors in the inverter circuits of the (M-1)th stage inverter circuit group M-1 and the Mth stage inverter circuit M, respectively, using the charge they each hold.

[0091] Multiple inverter circuits are connected in series in each of the inverter circuit groups, from the second stage (M-1) to the (M-1) stage (M-1). In each of the inverter circuit groups 2 to M-1 in the middle section, multiple inverter circuits are at ground potential node V. SS Starting from the side, the ground potential node V in the preceding inverter circuit group. SS In a state where no capacitive elements are connected between the output nodes of two adjacent inverter circuits connected in order from side to side, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, and the source node of the NMOS is electrically connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits. In each of the intermediate inverter circuit groups 2 to M-1, the input nodes of multiple inverter circuits are connected sequentially to the PMOS source nodes of the inverter circuits in the preceding inverter circuit group, starting from the inverter circuit on the ground potential node side in the preceding inverter circuit group.

[0092] In other words, the second stage inverter circuit group 2 consists of (M-1) inverter circuits 21-2 M-1 It holds. The inverter circuit 21, which is positioned at the lowest level, i.e., in the first position, is electrically connected to the output node of the inverter circuit 11, which is positioned in the first position in the first stage inverter circuit group 1, and the output node of the inverter circuit 12, which is positioned in the second position, without connecting any capacitive elements. The input node of inverter circuit 21 is electrically connected to the PMOS source node of inverter circuit 11 and the NMOS source node of inverter circuit 12 of the first stage inverter circuit group 1.

[0093] The inverter circuit 22, positioned in the second position, is electrically connected to the output node of the inverter circuit 12, positioned in the second position in the first stage inverter circuit group 1, and the output node of the inverter circuit 13, positioned in the third position, without connecting any capacitive elements. The input node of inverter circuit 22 is electrically connected to the PMOS source node of inverter circuit 12 and the NMOS source node of inverter circuit 13 of the first stage inverter circuit group 1.

[0094] Inverter circuits 22-2 are placed in the 3rd place and below (M-1)th place (highest rank). M-1 Similarly, the output nodes of adjacent inverter circuits in the first-stage inverter circuit group 1 are electrically connected without any capacitive elements being connected. Inverter circuits 23-2 are placed in the 3rd place and below (M-1) position. M-1 The input node is similarly electrically connected to the PMOS source node of the lower-level inverter circuit and the NMOS source node of the upper-level inverter circuit in the adjacent inverter circuits of the first-stage inverter circuit group 1.

[0095] Inverter circuit 2 located in position (M-1) M-1 This is the inverter circuit 1 located in the (M-1) position within the first stage inverter circuit group 1. M-1 The output node and the inverter circuit 1 located at position M M It is electrically connected to the output node without any capacitive elements connected to it. Inverter circuit 2 located in position (M-1) M-1 The input node is the inverter circuit 1 located in the (M-1) position in the first stage inverter circuit group 1. M-1 Inverter circuit 1 located at the source node and Mth position of the PMOS M It is electrically connected to the source node of the NMOS.

[0096] The third stage inverter circuit group 3 consists of (M-2) inverter circuits 31-3 N-2 It holds. The inverter circuit 31, which is positioned at the lowest level, i.e., in the first position, is electrically connected to the output node of the inverter circuit 21, which is positioned in the first position in the second stage of the inverter circuit group 2, and the output node of the inverter circuit 22, which is positioned in the second position, without connecting any capacitive elements. The input node of inverter circuit 31 is electrically connected to the PMOS source node of inverter circuit 21 and the NMOS source node of inverter circuit 22 of the second-stage inverter circuit group 2.

[0097] The inverter circuit 32, positioned in the second position, is electrically connected to the output node of the inverter circuit 22, positioned in the second position in the second stage inverter circuit group 2, and the output node of the inverter circuit 23, positioned in the third position, without connecting any capacitive elements. The input node of inverter circuit 32 is electrically connected to the PMOS source node of inverter circuit 22 and the NMOS source node of inverter circuit 23 of the second stage inverter circuit group 2.

[0098] Inverter circuits 32-3 are placed in the 3rd to 2nd (M-2) positions (highest rank). M-2 Similarly, the output nodes of adjacent inverter circuits in the second stage inverter circuit group 2 are electrically connected without any capacitive elements connected. Inverter circuits 33-3 are placed in the 3rd position and below (M-2nd position). M-2The input node is similarly electrically connected to the PMOS source node of the lower-level inverter circuit and the NMOS source node of the upper-level inverter circuit in the adjacent inverter circuit group 2 of the second stage inverter circuit group.

[0099] Inverter circuit 3 located in position (M-2) M-2 This is the inverter circuit 2 located in the (M-2) position within the second stage inverter circuit group 2. M-2 The output node and inverter circuit 1 located at position (M-1) M-1 It is electrically connected to the output node without any capacitive elements connected to it. Inverter circuit 3 located in position (M-2) M-2 The input node is the inverter circuit 2 located in the (M-2) position in the second stage inverter circuit group 2. M-2 Inverter circuit 1 located at the source node and (M-1) position of the PMOS M-1 It is electrically connected to the source node of the NMOS.

[0100] Regarding the inverter circuit group M-2 from the 4th stage inverter circuit group 4 to the (M-1) stage inverter circuit group M-2 Similar to the second-stage inverter circuit group 2 and the third-stage inverter circuit group 3, multiple inverter circuits are connected between the output nodes of adjacent inverter circuits in the preceding inverter circuit group without connecting any capacitive elements.

[0101] The input nodes of the (M-1) stage inverter circuit group M-2, starting from the 4th stage inverter circuit group 4, are electrically connected to the PMOS source nodes of the lower-level inverter circuits and the NMOS source nodes of the higher-level inverter circuits in the adjacent inverter circuits of the preceding inverter circuit group, similar to the connection between the 2nd stage inverter circuit group 2 and the 3rd stage inverter circuit group 3.

[0102] The M-stage inverter circuit M is electrically connected to the (M-1)-stage inverter circuit group M-1, with no capacitive elements connected between the output node of inverter circuit (M-1)1, which is positioned in the first position (lowest), and the output node of inverter circuit (M-1)2, which is positioned in the second position (highest). The input node of the M-stage inverter circuit M is electrically connected to the PMOS source node of inverter circuit (M-1)1 and the NMOS source node of inverter circuit (M-1)2 of the (M-1)-stage inverter circuit group M-1.

[0103] The first-stage inverter circuit group 1, the second-stage inverter circuit group 2, the third-stage inverter circuit group 3, ..., the (M-1)-stage inverter circuit group, and the M-stage inverter circuit are formed vertically on the surface of the semiconductor substrate in the order of first stage, second stage, third stage, ..., (M-1)-stage, and M-stage, with an insulating layer in between.

[0104] Capacitive element 40 located at position M (highest position) M When the PMOS is turned on, the inverter circuit 2 located in the M-1 position (highest position) of the second stage inverter circuit group 2 is... M-1 PMOS2 in M-1P The gate electrode, inverter circuit 3, is positioned at the top of the inverter circuit group 3~M-1 from the 3rd stage to the M-1 stage. M-2 PMOS3 in (M-1)2 M-2P ~(M-1) 2P PMOSM in the M-stage inverter circuit M of the gate electrode. 1P Charge the gate electrode. Therefore, the capacitive element 40 is positioned at the Mth position. M The capacitance value is PMOS2 M-1P From PMOSM 1P To turn it on, (M-1) times C P It's done that way.

[0105] As a result, inverter circuits 11-1 in the first stage inverter circuit group 1 M PMOS1 1P ~1 MPWhen it is turned on, Inverter circuit 3 is located at the top of the inverter circuit group 2~M-1 from the 2nd stage to the M-1 stage. M-1 PMOS3 in (M-1)2 M-1P ~(M-1) 2P and PMOSM in the M-stage inverter circuit M 1P It is turned on. Therefore, the power supply potential node V is connected to the output terminal Out. DD The potential V applied to it DD (For example, NV) is output.

[0106] Capacitive element 40 positioned at M-1 M-1 When the PMOS is turned on, the inverter circuit 2 located in the M-2 position (one position below the highest) in the second stage inverter circuit group 2 is the inverter circuit 2. M-2 PMOS2 in M-2P The gate electrode, inverter circuit 3, is located one level below the top level in the inverter circuit group 3~M-1 from the 3rd stage to the M-1 stage. M-2 PMOS2 in (M-2)1 M-2P ~(M-1) 1P Charge the gate electrode. Therefore, the capacitive element 40 is positioned at position M-1. M-1 The capacitance value is PMOS2 M-2P From PMOSM-1 1P To turn it on, (M-2) times C P It is necessary.

[0107] Capacitive element 40 positioned at M-1 M-1 When the NMOS is turned on, the inverter circuit 2 is located in the M-1 position (highest position) of the second stage inverter circuit group 2. M-1 NMOS2 M-1N Charge the gate electrode. Therefore, the capacitive element 40 is positioned at position M-1. M-1 The capacitance value is NMOS2 M-1N To turn it on, C N It is necessary. Therefore, capacitive element 40M-1 The capacity value is (M-2)C P or C N The capacity value is set to the larger of the two values.

[0108] Capacitive element 40 positioned from M-2 to 2nd position M-2 ~402 is a capacitive element 40 located at position M-2 to position 2 in order to charge the gate electrode of the PMOS in the inverter circuit located one position lower in order when the PMOS is turned on. M-2 The capacity values ​​of ~402 are (M-3) times C in order. P From C P It is necessary. When the PMOS is turned on, the m-th position capacitive element 40 is located from the M-2 position to the 2nd position. m The capacity value is (m-1) times C P It requires.

[0109] Capacitive element 40 positioned from M-2 to 2nd position M-2 ~402 is a capacitive element 40 located at position M-2 to position 2 in order to charge the gate electrode of the NMOS in the inverter circuit which is arranged sequentially in the same position when the NMOS is turned on. M-2 The capacity values ​​for ~402 are in order of doubling C N From (M-3) times C N It is necessary. When the NMOS is turned on, the m-th position capacitive element 40 is located from the M-2 position to the 2nd position. m The capacity value is (Mm) times C N It is necessary. Therefore, the m-th position capacitive element 40 is positioned from the M-2 position to the 2nd position. m The capacitance value is (m-1)C P Or (Mm)C N The capacity value is set to the larger of the two values.

[0110] The capacitance element 401, which is positioned in first place (last place), is used when turning on the NMOS. In the inverter circuit 21, which is positioned as the first (lowest) in the second stage inverter circuit group 2, NMOS2 1N The gate electrode, the NMOS3 in the inverter circuit 31~(M-1)1 located at the lowest level in the inverter circuit group 3~M-1 from the 3rd stage to the M-1 stage. 1N ~(M-1) 1N The gate electrode, the M-stage inverter circuit M, is an NMOSM 1N Charge the gate electrode. Therefore, the capacitive element 40 is positioned at the Mth position. M The capacitance value is NMOS2 1N From NMOSM 1N To turn it on, (M-1) times C N It's done that way.

[0111] As a result, inverter circuits 11-1 in the first stage inverter circuit group 1 M NMOS1 1N ~1 MN When it turns ON, the NMOS2 in inverter circuit 21, which is located in the first position in the inverter circuit group 2~M-1 from the second stage to the M-1 stage 1N ~(M-1) 1N and the NMOSM of the M-stage inverter circuit M 1N It is turned on. Therefore, the output terminal Out is at ground potential node V. SS It is connected to ground (e.g., 0V).

[0112] In short, in the driver circuit according to Embodiment 2, in the first stage inverter circuit group 1, the ground potential node V ss The inverter circuit 11 to which the NMOS source node is electrically connected is designated as the first position, and the power supply potential node V DD Inverter circuit 1 to which the PMOS source node is electrically connected. M If we consider this to be the Mth position, then the mth position capacitive element 40 is located from the 1st position to the Mth position. m The capacitance value is (m-1)C P Or (Mm)C N The capacity value is set to the larger of the following two values. m ranges from 1 to M.

[0113] Thus, the capacitance elements 401-40 are arranged from the 1st to the Mth position. M By setting the capacitance value, even if each inverter circuit in the inverter circuit groups 2 to M from the second stage to the M stage is connected without connecting capacitive elements between the output nodes of adjacent inverter circuits in the preceding inverter circuit group, the inverter circuits constituting inverter circuit groups 1 to M will operate quickly and complementaryly, whether the PMOS is turned on or the NMOS is turned on.

[0114] As a result, input terminal In1~In M Depending on the H and L levels input to each, the output terminal Out can output signals with fast rise and fall times and output voltages exceeding the withstand voltage of the PMOS and NMOS, such as 0V and NV.

[0115] The group of capacitive elements 40 is modularized or integrated in the same manner as in Embodiment 1. Capacitive elements 401-40 in the capacitive element group 40 M The length of the shorter side of each electrode is, as in Embodiment 1, less than or equal to the distance between the PMOS source node and the NMOS source node of the inverter circuit. Also, capacitive elements 401~40 M The length of the longer side of each electrode is no more than five times the length of the shorter side.

[0116] Capacitive elements 401-40 M The size of the electrodes in this circuit is such that the length of the short side is less than or equal to the distance between the source nodes of the PMOS and NMOS in the inverter circuit, and the length of the long side is less than or equal to 5 times the length of the short side, so input signal lines 501~50 M The parasitic capacitance between the two is small, and as a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0117] Next, the operation of the driver circuit according to Embodiment 2 will be described. First, input terminals In1~InM The case where an input signal with an L-level potential is input to each of them will be explained using Figure 6. The potential of the input signal at the L level determines the inverter circuits 11-1 in the first stage inverter circuit group 1. M PMOS1 1P ~1 MP On, NMOS1 1N ~1 MN It is off.

[0118] Power supply potential node V DD and ground potential node V SS Capacitive elements 401-40 divide the voltage between them by M. M Depending on the charge each element holds, the potential states are as follows: To avoid complexity and redundancy in the explanation, the names of the components will be omitted and explained using symbols. For example, "Power supply potential node V DD and the inverter circuit 1 positioned at the top of the first stage inverter circuit group 1 M The circuit wiring connecting the source node of the PMOS is "V DD -1 M It will be described as the "source node of the PMOS."

[0119] As shown by the solid line A3 in Figure 6, V DD (40 M From one of the electrodes, V DD -1 M PMOS source node, 1 M Output node-2 M-1 PMOS source node, 2 M-1 Output node-2 M-2 The potential of the path from the source node of the PMOS, ..., output node of M-12, to the output terminal Out via the source node of the PMOS of M, output node of M, and Out is MV.

[0120] 40 M From the other electrode, 40 M The other electrode -40 M-1 One electrode, 40 M The other electrode -1M The source node of the NMOS and 1 M-1 The PMOS source node and 2 M-1 Input node, 1 M-1 Output node-2 M-1 The source node of the NMOS and 2 M-2 The PMOS source node and 3 M-2 Input node, 2 M-2 Output node-3 M-2 The source node of the NMOS and 3 M-3 The PMOS source node and 4 M-3 The path from the input node of M, ..., the output node of (M-2)2 to the NMOS source node of 32 and the PMOS source node of 31, and the input node of M, the output node of 31 and the NMOS source node of M is (M-1)V.

[0121] As shown by the dashed line B3 in Figure 6, the path from the other electrode of 403 to the other electrode of 403 - one electrode of 402, the other electrode of 403 - the NMOS source node of 13, the PMOS source node of 12, and the input node of 22, the output node of 12 - the NMOS source node of 22, the PMOS source node of 21, and the input node of 3, and the output node of 21 - the NMOS source node of 31 is 2V.

[0122] As shown by the dashed line C3 in Figure 6, the path from the other electrode of 402 to the other electrode of 402 - one electrode of 401, the other electrode of 402 - the NMOS source node of 12 and the PMOS source node of 11 and the input node of 21, the output node of 11 - the NMOS source node of 21 is 1V. The source node of the 11 NMOS transistors is at 0V, as shown by the dashed line D3 in Figure 6. Given the potential relationship described above, all PMOS transistors will be on and all NMOS transistors will be off.

[0123] Next, input terminal In1~In M The case where an input signal with a potential of H level is input to each of them will be explained using Figure 7. Due to the potential of the H level of the input signal, the NMOSs 1 M ~1 MN in the first-stage inverter circuit group 1 are on, and the PMOSs 1 1P ~1 MP are off. The voltage between the power supply potential node V DD and the ground potential node V SS is divided by the capacitive elements 401~40 M , and the potential states are as follows according to the charges held by each of them.

[0124] As shown by the two-dot chain line D4 in FIG. 7, the output terminal Out is at the ground potential, that is, 0V, through the source node of the NMOS of V SS -11, the output node of 11, the source node of the NMOS of -21, the output node of 21, the source node of the NMOS of -31, the output node of 31, the source node of the NMOS of -41, ···, the output node of (M - 1)1, the source node of the NMOS of -M1, and the output node of M1 to the ground potential node V SS (one electrode of the capacitive element 401 arranged at the first position (the lowest position)).

[0125] As shown by the one-dot chain line C4 in FIG. 7, the path from the other electrode of 402 to the other electrode of 402, the one electrode of 401, the source node of the NMOS of 12, the source node of the PMOS of 11, the input node of 21, the output node of 12, the source node of the NMOS of -22, the source node of the PMOS of 21, the input node of 31, the output node of 22, the source node of the NMOS of -32, the source node of the PMOS of 31, the input node of 41, ···, the output node of (M - 2)2, the source node of the NMOS of -(M - 1)2, the source node of the PMOS of (M - 1)1, the input node of M, and the source node of the PMOS of (M - 1)2, the output node of (M - 1)2 is 1V.

[0126] ​​​​​​​​​​​​​​​​​​​​As shown by the dashed line B4 in FIG. 7, from the other electrode of 403, the paths from the other electrode of 403 - one electrode of 402, the source node of 13 NMOSs, the source node of 12 PMOSs, the 22 input nodes, the 13 output nodes - the source node of 23 NMOSs, the source node of 22 PMOSs, the 32 input nodes, the 23 output nodes - the source node of 33 NMOSs, the source node of 32 PMOSs, the 42 input nodes, ···, the output node of (M - 2)3 - the source node of (M - 1)3 NMOSs, the source node of (M - 1)2 PMOSs are 2V.

[0127] As shown by the partial long - dashed - double - dotted line F4 in FIG. 40 M-1 from the other electrode of, 40 M-1 from the other electrode of - 40 M-2 one electrode of and the source node of 1 M-2 NMOSs and the source node of 1 M-1 PMOSs and the 2 M-2 input nodes, the 1 M-1 output nodes - 2 M-1 NMOSs and the source node of 2 M-2 PMOSs and the 3 M-2 input nodes, the 2 M-1 output nodes - 3 M-2 The path at the source node of the PMOSs is (M - 2)V.

[0128] As shown by the partial triple - dot - dashed line E4 in FIG. 7, from the other electrode of 40 M from the other electrode of, 40 M from the other electrode of - 40 M-1 one electrode of and the source node of 1 M NMOSs and the source node of 1 M-1 PMOSs and the 2 M-1 input nodes, the 1 M output nodes - 2 M-1 The path at the source node of the PMOSs is (M - 1)V. The source node of 11 NMOSs is MV as shown by the solid line A4 in FIG. 7. Due to the above potential relationship, all PMOSs are off and all NMOSs are on.

[0129] The driver circuit according to Embodiment 2 is an M-stage driver circuit using an inverter circuit made of CMOS, where the power supply potential node V DD and ground potential node V SS M inverter circuits 11-1 connected in series between them M A first-stage inverter circuit group 1 having and M inverter circuits 11-1 M Inverter circuits 11-1 correspond to each. M It is connected between the PMOS source node and the NMOS source node, and the power supply potential node V DD and ground potential node V SS M capacitive elements 401-40 are connected in series between them. MA group of capacitive elements 40 having such elements, and the number of inverter circuits is one less than the number of inverter circuits in the preceding inverter circuit group, and in a state where no capacitive elements are connected between the output nodes of two inverter circuits that are connected adjacently in order from the ground potential node side in the preceding inverter circuit group, the source node of the PMOS is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the source node of the NMOS is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input nodes are connected in order from the inverter circuit on the ground potential node side in the preceding inverter circuit group to the source node of the PMOS of the inverter circuit in the preceding inverter circuit group, in the second to (M-1) stage inverter circuit group 2~( In the M-1) and M-stage inverter circuit M, where no capacitive elements are connected between the output node of inverter circuit (M-1)1 and the output node of inverter circuit (M-1)2, which are arranged in the (M-1)-stage inverter circuit group (M-1), the source node of the PMOS is connected to the output node of inverter circuit (M-1)2, the source node of the NMOS is connected to the output node of inverter circuit (M-1)1, and the input node is electrically connected to the source node of the PMOS of inverter circuit (M-1)1 and the source node of the NMOS of inverter circuit (M-1)2, the number of capacitive elements can be reduced, the length of the circuit wiring connecting the inverter circuits can be shortened, and the parasitic capacitance occurring in the circuit wiring can be reduced, resulting in faster rise and fall times for the output voltage of the driver circuit.

[0130] Furthermore, in the driver circuit according to Embodiment 2, the capacitance value of the m-th position capacitance element, which is located in the first to M positions of the capacitance element group 40, is set to the larger of (m-1) times the parasitic capacitance value of the PMOS and (Mm) times the parasitic capacitance value of the NMOS. Therefore, whether the PMOS is turned on or the NMOS is turned on, the inverter circuits constituting inverter circuit groups 1 to 3 operate quickly and complementaryly.

[0131] Furthermore, the driver circuit according to Embodiment 2 includes capacitive elements 401 to 40 in the group of capacitive elements 40M In this configuration, the length of the short side of the electrode was set to be less than or equal to the distance between the source node of the PMOS and the source node of the NMOS in the inverter circuit, and the length of the long side was set to be less than or equal to 5 times the length of the short side, so the capacitive elements 401~40 M and input signal lines 501~50 M The parasitic capacitance between the two is small, and as a result, the rise and fall times of the output voltage output from the output node of the inverter circuit 3 can be shortened.

[0132] Embodiment 3. The driver circuit according to Embodiment 3 will be explained with reference to Figure 8. The driver circuit according to Embodiment 3 is a driver circuit that uses two of the driver circuits according to Embodiment 1 or Embodiment 2, and obtains twice the output voltage amplitude by differential operation of the two driver circuits.

[0133] The first driver circuit 100 is either the driver circuit according to Embodiment 1 or the driver circuit according to Embodiment 2. The second driver circuit 200 is either the driver circuit according to Embodiment 1 or the driver circuit according to Embodiment 2, and has the same configuration as the first driver circuit 100.

[0134] V1 is output as a high-level potential and V2 as a low-level potential from the output terminal Out of the first driver circuit 100. The output terminal Out of the second driver circuit 200 also outputs V1 as a high-level potential and V2 as a low-level potential, and these potentials are output with a 180-degree phase shift via the 180-degree phase shift circuit 200A. The L level potential is the ground potential, and the H level potential is 3V when using the driver circuit according to Embodiment 1, and MV when using the driver circuit according to Embodiment 2.

[0135] The output terminal Out of the first driver circuit 100 is electrically connected to the gate electrode of the amplification NMOS transistor 300 that constitutes the amplification circuit. The output terminal Out of the second driver circuit 200 is electrically connected to the source electrode of the amplification NMOS transistor 300 via the 180-degree phase shift circuit 200A. The drain electrode of the amplification NMOS transistor 300 is electrically connected to the output terminal Out1, and the power supply potential node V is connected via the resistor element 400. D It is electrically connected to it.

[0136] When V1 is applied as a high-level potential from the output terminal Out of the first driver circuit 100 to the gate electrode of the amplification NMOS transistor 300, V2, which is shifted by 180 degrees in phase, is simultaneously applied to the source electrode of the amplification NMOS transistor 300. Therefore, the potential difference between the gate electrode and the source electrode is 2(V1-V2), and an output voltage of 2(V1-V2) is obtained from the drain electrode of the amplification NMOS transistor 300. Note that the power supply potential node V D The potential applied to it is 2(V1-V2).

[0137] The potential difference between the gate electrode and source electrode of the amplification NMOS transistor 300 is 6V when using the driver circuit according to Embodiment 1, and 2 × MV when using the driver circuit according to Embodiment 2.

[0138] The driver circuit according to Embodiment 3 has the same effects as the driver circuit according to Embodiment 1 or Embodiment 2, and can also obtain twice the output voltage compared to the driver circuit according to Embodiment 1 or Embodiment 2.

[0139] Furthermore, it is possible to freely combine the embodiments, modify any component of each embodiment, or omit any component in each embodiment. [Industrial applicability]

[0140] The driver circuit described herein is suitable for a driver circuit that uses an inverter circuit made of CMOS manufactured using a semiconductor process and outputs a voltage higher than the breakdown voltage of PMOS and NMOS. [Explanation of symbols]

[0141] 1. First stage inverter circuit group, 11-13-1 M Inverter circuit, 2nd stage inverter circuit group, 21, 22~2 M-1 Inverter circuit, 3rd stage inverter circuit (group), 3, 31, 32~3 M-1 , 3 M Inverter circuit, MM stage inverter circuit, 40 capacitive element group, 401~403~40 M Capacitive elements, 501~503~50 M Input signal line, 100 first driver circuit, 200 second driver circuit, 300 MOS transistor for amplification.

Claims

1. The first stage of inverter circuits comprises M inverter circuits, each consisting of a PMOS and an NMOS transistor, each having an input node, an output node, a PMOS source node, and an NMOS source node. These M inverter circuits are connected in series between a power supply potential node and a ground potential node, with the first inverter circuit having an NMOS source node electrically connected to the ground potential node, and the Mth inverter circuit having a PMOS source node electrically connected to the power supply potential node, with the PMOS source nodes electrically connected to the NMOS source nodes in that order. Input signals with the same amplitude, the same phase, and DC levels, which are equivoltage offset in the order from the first inverter circuit to the Mth inverter circuit, are input to the input node of each inverter circuit. Each of the M inverter circuits in the first stage inverter circuit group corresponds to one of the M inverter circuits, and the M capacitor elements are connected between the PMOS source node and the NMOS source node of the corresponding inverter circuit, and are connected in series between the power supply potential node and the ground potential node, and the capacitance value of the m-th capacitor element, which is arranged from the 1st to the Mth position, is the larger of the capacitance value of (m-1) times the parasitic capacitance value of the PMOS and the capacitance value of (M-m) times the parasitic capacitance value of the NMOS, The inverter circuit group from the second stage to the M-1 stage has multiple inverter circuits, each composed of PMOS and NMOS transistors, each having an input node, an output node, a PMOS source node, and an NMOS source node, the number of such inverter circuits is one less than the number of inverter circuits in the preceding inverter circuit group, the multiple inverter circuits are connected in series, and each of the multiple inverter circuits is connected in order from the ground potential node side, without any capacitive elements connected between it and the output nodes of two inverter circuits that are connected adjacently in order from the ground potential node side in the preceding inverter circuit group, the PMOS source node is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the NMOS source node is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input nodes are connected in order from the inverter circuit on the ground potential node side in the preceding inverter circuit group to the PMOS source node of the inverter circuit in the preceding inverter circuit group, The M-stage inverter circuit is composed of PMOS and NMOS transistors, and has an input node, an output node, a PMOS source node, and an NMOS source node, and in a state where no capacitive elements are connected between the output nodes of the two inverter circuits in the M-1 stage inverter circuit group, the PMOS source node is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the NMOS source node is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node is connected to the PMOS source node of the inverter circuit on the ground potential node side in the M-1 stage inverter circuit group, A driver circuit equipped with the following features.

2. The driver circuit according to claim 1, wherein in each of the M capacitive elements, the length of the short side of the electrode is less than or equal to the distance between the source node of the PMOS and the source node of the NMOS of the inverter circuit, and the length of the long side is less than or equal to five times the length of the short side.

3. The first stage of inverter circuits comprises M inverter circuits, each consisting of a PMOS and an NMOS transistor, each having an input node, an output node, a PMOS source node, and an NMOS source node. These M inverter circuits are connected in series between a power supply potential node and a ground potential node, with the PMOS source node facing the power supply potential node. The input signals, which have the same amplitude, the same phase, and DC levels, are input to the input nodes of each inverter circuit, with equivoltage offsets in the order from the inverter circuit connected to the ground potential node to the inverter circuit connected to the power supply potential node. A group of capacitive elements having M capacitive elements, each corresponding to one of the M inverter circuits in the first stage inverter circuit group, connected between the PMOS source node and the NMOS source node of the corresponding inverter circuit, connected in series between the power supply potential node and the ground potential node, with the length of the short side of each electrode being less than or equal to the distance between the PMOS source node and the NMOS source node of the inverter circuit, and the length of the long side being less than or equal to five times the length of the short side, The inverter circuit group from the second stage to the M-1 stage has multiple inverter circuits, each composed of PMOS and NMOS transistors, each having an input node, an output node, a PMOS source node, and an NMOS source node, the number of such inverter circuits is one less than the number of inverter circuits in the preceding inverter circuit group, the multiple inverter circuits are connected in series, and each of the multiple inverter circuits is connected in order from the ground potential node side, without any capacitive elements connected between it and the output nodes of two inverter circuits that are connected adjacently in order from the ground potential node side in the preceding inverter circuit group, the PMOS source node is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the NMOS source node is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input nodes are connected in order from the inverter circuit on the ground potential node side in the preceding inverter circuit group to the PMOS source node of the inverter circuit in the preceding inverter circuit group, The M-stage inverter circuit comprises a PMOS and an NMOS transistor, having an input node, an output node, a PMOS source node, and an NMOS source node, wherein, in a state where no capacitive elements are connected between the output nodes of the two inverter circuits in the M-1 stage inverter circuit group, the PMOS source node is connected to the output node of the inverter circuit connected to the power supply potential node side of the two inverter circuits, the NMOS source node is connected to the output node of the inverter circuit connected to the ground potential node side of the two inverter circuits, and the input node is connected to the PMOS source node of the inverter circuit on the ground potential node side in the M-1 stage inverter circuit group, In the aforementioned first-stage inverter circuit group, if the inverter circuit in which the source node of an NMOS is electrically connected to the ground potential node is designated as the first position, and the inverter circuit in which the source node of a PMOS is electrically connected to the power potential node is designated as the Mth position, The capacitance value of the m-th position capacitance element, which is located in the group of capacitance elements from the 1st to the Mth position, is the larger of the capacitance value that is (m-1) times the parasitic capacitance value of the PMOS and the capacitance value that is (M-m) times the parasitic capacitance value of the NMOS. Driver circuit.

4. A first driver circuit comprising the driver circuit described in claim 1 or claim 3, A second driver circuit comprising the driver circuit described in claim 1 or claim 3, An amplifying MOS transistor is provided, in which the drain electrode is connected to the power supply potential node and the output node, the output voltage from the first driver circuit is applied to the gate electrode, and the output voltage from the second driver circuit is applied to the source electrode at a voltage that is 180 degrees out of phase with the output voltage from the first driver circuit. A driver circuit equipped with the following features.

Images