Display board and method for manufacturing the same, display device

Abstract

To provide a display substrate which optimizes the layout of a line structure and is advantageous for achieving narrow frame design of a display panel.SOLUTION: A display substrate includes a base substrate including a display region and a peripheral region, and a gate scan driving circuit, a light-emitting control scan driving circuit, and a first power line that are sequentially arranged, the gate scan driving circuit includes a first stabilizing capacitor, a first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scan driving circuit, a second electrode plate of the first stabilizing capacitor is electrically connected to the first power line; and the light-emitting control scan driving circuit includes a second stabilizing capacitor, a first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal of the light-emitting control scan driving circuit, a second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, the second electrode plate of the second stabilizing capacitor includes a first part and a second part, and an organic insulation layer is provided between the first part and the second part along the direction vertical to the base substrate.SELECTED DRAWING: Figure 5C

Description

Technical Field

[0001] Cross-reference to Related Applications This application claims the priority of Chinese Patent Application No. 202010889271.2, filed on August 28, 2020, and the entire content disclosed in the above Chinese Patent Application is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0003] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines intersecting with the gate lines. The driving of the gate lines can be realized by an integrated driving circuit to be bound. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array), thereby driving the gate lines. For example, a GOA including a plurality of cascaded shift register units can be adopted to provide a switch state voltage signal (scanning signal) to a plurality of rows of gate lines of the pixel array, so that, for example, a plurality of rows of gate lines are controlled to be sequentially turned on, and a data signal is provided to the pixel units of the corresponding row in the pixel array by the data lines, thereby forming a gradation voltage required for the gray scale of the displayed image in each pixel unit, and further displaying an image of one frame.

Summary of the Invention

Means for Solving the Problems

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the light emission control scanning drive circuit further includes a third stabilizing capacitor and a first connection portion, wherein a first electrode plate of the third stabilizing capacitor is electrically connected to the first connection portion, a second electrode plate of the third stabilizing capacitor is electrically connected to a first power line, and the second electrode plate of the third stabilizing capacitor includes a first portion and a second portion, and has an organic insulating layer between the first portion and the second portion in a direction perpendicular to the base substrate.

[0006] For example, in a display board according to at least one embodiment of the present disclosure, the light emission control scanning drive circuit includes a plurality of cascaded light emission control shift register units, each light emission control shift register unit includes a plurality of transistors, a plurality of capacitors, and a plurality of connection parts, the plurality of transistors include: a first transistor whose gate is connected to a first clock signal line, whose first electrode is connected to a first node, and whose second electrode is connected to an input terminal; a second transistor whose gate is connected to the first node, whose first electrode is connected to a second node, and whose second electrode is connected to the first clock signal line, thereby receiving the first clock signal; a third transistor whose gate is connected to a first clock signal line, whose first electrode is connected to a second node, and whose second electrode is connected to a second power line, thereby receiving a second voltage; and a third transistor whose first electrode is connected to a second clock signal line, and whose second electrode is connected to a third node. The plurality of capacitors include a sixth transistor having a gate connected to the second clock signal line, receiving the second clock signal, with a first electrode connected to the third node and a second electrode connected to the fourth node, a ninth transistor having a gate connected to the fourth node, receiving the third voltage with a first electrode connected to the third power line, and a second electrode connected to the output terminal, and a tenth transistor receiving the second voltage with a first electrode connected to the second power line, and a second electrode connected to the output terminal, and the plurality of capacitors include a first capacitor with a second electrode connected to the third node, a third capacitor with a first electrode connected to the fourth node, receiving the third voltage with a second electrode connected to the third power line, a third stabilizing capacitor with a first electrode plate connected to the first node and a second electrode plate electrically connected to the first power line, and a second stabilizing capacitor with a first electrode plate connected to the output terminal of the light emission control scanning drive circuit and a second electrode plate electrically connected to the first power line,The plurality of connection parts include the first connection part and the third connection part, the first connection part includes the first node, and the third connection part is connected to the output terminal of the light emission control scanning drive circuit.

[0007] For example, in a display board according to at least one embodiment of the present disclosure, the gate scanning drive circuit further includes a first scanning capacitor, and the ratio of the first stabilizing capacitor to the first scanning capacitor satisfies the following relation. GH1 / EH1 <C24 / C21<GH1 / EH2

[0008] However, C21 represents the first scanning capacitor, C24 represents the first stabilizing capacitor, GH1 is the duration of the active level of the gate scanning signal output by the gate scanning drive circuit in one frame, EH1 is the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame, and EH2 is the duration of the inactive level of the light emission control scanning drive circuit in one frame time.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the ratio of the second stabilizing capacitor to the second capacitor of the light emission control scanning drive circuit satisfies the following relation. GH1 / EH1 <C6 / C2<GH1 / EH2

[0010] However, C6 represents the second stabilizing capacitor, C2 represents the second capacitor of the light emission control scanning drive circuit, GH1 is the duration of the active level of the gate scanning signal output by the gate scanning drive circuit in one frame, EH1 is the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame, and EH2 is the duration of the inactive level of the light emission control scanning drive circuit in one frame time.

[0011] For example, in a display board according to at least one embodiment of the present disclosure, the ratio of the first stabilizing capacitor to the first scanning capacitor also satisfies the following relation. GOL / GOW <C24 / C21<GH1 / EH2

[0012] However, GOL / GOW is the aspect ratio of the output transistor of the gate scanning drive circuit.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, if the light emission control scanning drive circuit includes a second capacitor, the ratio of the second stabilizing capacitor to the second capacitor of the light emission control scanning drive circuit satisfies the following relational expression. End of Life / End of Life <C6 / C2<GH1 / EH2

[0014] However, EOL / EOW is the aspect ratio of the output transistor of the light emission control scanning drive circuit.

[0015] For example, in a display board according to at least one embodiment of the present disclosure, the ratio of the first stabilizing capacitor to the first scanning capacitor also satisfies the following relation. (GSW / GSL) / (GOW / GOL) <C24 / C21<GH1 / EH2

[0016] However, GOW / GOL is the width-to-length ratio of the output transistors of the gate scanning drive circuit, and GSW / GSL is the width-to-length ratio of any one of the switch transistors of the gate scanning drive circuit.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the ratio of the second stabilizing capacitor to the second capacitor of the light emission control scanning drive circuit satisfies the following relation. (ESW / ESL) / (EOW / EOL) <C6 / C2<GH1 / EH2

[0018] However, EOW / EOL is the width-to-length ratio of the output transistors of the light emission control scanning drive circuit, and ESW / ESL is the width-to-length ratio of any one of the switch transistors of the light emission control scanning drive circuit.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the light emission control scanning drive circuit further includes a fourth stabilizing capacitor and a second connection portion, wherein a first electrode plate of the fourth stabilizing capacitor is electrically connected to the second connection portion, a second electrode plate of the fourth stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the fourth stabilizing capacitor includes a first portion and a second portion, and has an organic insulating layer between the first portion and the second portion in a direction perpendicular to the base substrate.

[0020] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of capacitors further include a fourth stabilizing capacitor, the first electrode plate of the fourth stabilizing capacitor is connected to the second node, the second electrode plate of the fourth stabilizing capacitor is electrically connected to the first power line, and the plurality of connections further include a second connection, the second connection includes the second node.

[0021] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of transistors further include an 11th transistor, the gate of the 6th transistor being connected to the second electrode of the 11th transistor, the first electrode of the 1st capacitor being connected to the second electrode of the 11th transistor, the gate of the 11th transistor receiving the second voltage by being connected to the second power line, and the first electrode of the 11th transistor being connected to the second node; and a 12th transistor, the gate of the 10th transistor being connected to the second electrode of the 12th transistor, the first electrode of the 2nd capacitor being connected to the second electrode of the 12th transistor, the gate of the 12th transistor receiving the second voltage by being connected to the second power line, and the first electrode of the 12th transistor being connected to the first node.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame is greater than the duration of the active level of the gate scanning signal output by the gate scanning drive circuit in one frame.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, a first portion of the second electrode plate of the second stabilizer capacitor is located on a first blocking layer, a second portion of the second electrode plate of the second stabilizer capacitor is located on a second blocking layer, the first blocking layer and the second blocking layer are sequentially provided on one side of the light emission control scanning drive circuit away from the base substrate, the first blocking layer covers at least one transistor in the light emission control scanning drive circuit, the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control scanning drive circuit, the second blocking layer is further provided on one side of the gate scanning drive circuit away from the base substrate, and the second blocking layer covers at least one transistor in the gate scanning drive circuit.

[0024] For example, in a display substrate according to at least one embodiment of the present disclosure, a first portion of the second electrode plate of the third stabilizing capacitor is located on a first blocking layer, a second portion of the second electrode plate of the third stabilizing capacitor is located on a second blocking layer, the light emission control scanning drive circuit further includes a fourth stabilizing capacitor, a first portion of the second electrode plate of the fourth stabilizing capacitor is located on the first blocking layer, a second portion of the second electrode plate of the fourth stabilizing capacitor is located on the second blocking layer, the first blocking layer and the second blocking layer are sequentially provided on one side of the light emission control scanning drive circuit away from the base substrate, the first blocking layer covers at least one transistor in the light emission control scanning drive circuit, the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control scanning drive circuit, the second blocking layer is further provided on one side of the gate scanning drive circuit away from the base substrate, and the second blocking layer covers at least one transistor in the gate scanning drive circuit.

[0025] For example, in a display board according to at least one embodiment of the present disclosure, the first blocking layer and the second blocking layer receive a first voltage by being connected to the first power line.

[0026] For example, in a display substrate according to at least one embodiment of the present disclosure, for each of the light emission control shift register units, the first blocking layer covers at least one transistor in the light emission control shift register unit, and the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control shift register unit.

[0027] For example, in a display substrate according to at least one embodiment of the present disclosure, the light emission control scanning drive circuit further includes a second power line or a third scanning line extending along a first direction, the display substrate further includes a first power line extending along the first direction, a positive projection of the second power line or the third scanning line onto the base substrate is located between a positive projection of a transistor included in the light emission control scanning drive circuit onto the base substrate and a positive projection of the gate scanning drive circuit onto the base substrate, and a positive projection of the first power line onto the base substrate is located on a side where a positive projection of the light emission control scanning drive circuit onto the base substrate is away from the display area.

[0028] For example, in a display substrate according to at least one embodiment of the present disclosure, the second power line, the third scanning line, and the first power line are located on a side away from the second blocking layer of the first blocking layer along a direction perpendicular to the base substrate.

[0029] For example, in a display substrate according to at least one embodiment of the present disclosure, a boundary where a positive projection of the first blocking layer onto the light emission control scanning drive circuit is close to one side of the display area is located on a side where a positive projection of the second power line or the third scanning line onto the base substrate is away from the display area, and a positive projection of a boundary of the first blocking layer on a side away from the display area onto the base substrate overlaps with a positive projection of the first power line onto the base substrate.

[0030] For example, in a display substrate according to at least one embodiment of the present disclosure, the light emission control scanning drive circuit includes a plurality of output transistors and is configured to output the light emission control signal to the light emission control transistors of the display area one line at a time, and the orthographic projection of the boundary on one side of the first shielding layer adjacent to the display area onto the base substrate is such that the plurality of output transistors are located between the orthographic projection onto the base substrate and the orthographic projection onto the base substrate of the second power line or the third scanning line.

[0031] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projection onto the base substrate of one boundary of the second shielding layer adjacent to the display area coincides with the orthographic projection onto the base substrate of the gate scanning drive circuit, and the orthographic projection onto the base substrate of one boundary of the second shielding layer away from the display area coincides with the orthographic projection onto the base substrate of the first power line.

[0032] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projection of the boundary on one side of the second shielding layer adjacent to the display area onto the base substrate coincides with the orthographic projection of the output transistor that outputs the gate scanning signal in the gate scanning drive circuit onto the base substrate, or the orthographic projection of the boundary on one side of the second shielding layer adjacent to the display area onto the base substrate coincides with the orthographic projection of the gate scanning drive circuit onto the base substrate on one side adjacent to the display area.

[0033] For example, in a display board according to at least one embodiment of the present disclosure, the absolute value of the second voltage provided by the second power line is greater than the absolute value of the first voltage provided by the first power line.

[0034] For example, in a display substrate according to at least one embodiment of the present disclosure, corresponding to each light emission control shift register unit, the first blocking layer includes a plurality of periodically arranged first apertures, and the second blocking layer includes a plurality of periodically arranged second apertures, so that the first blocking layer and the second blocking layer each cover at least some of the transistors of the light emission control shift register unit.

[0035] For example, in a display substrate according to at least one embodiment of the present disclosure, the density range of the first aperture is 10% to 50%, and the density range of the second aperture is 10% to 50%.

[0036] For example, in a display substrate according to at least one embodiment of the present disclosure, the shapes of the first and second openings are rectangular, and the dimensional range of the first and second openings is 10 μm × 10 μm to 20 μm × 20 μm.

[0037] For example, in a display substrate according to at least one embodiment of the present disclosure, corresponding to each light emission control shift register unit, the first blocking layer includes a plurality of non-periodically arranged first apertures, and the second blocking layer includes a plurality of non-periodically arranged second apertures, so that the first blocking layer and the second blocking layer cover at least some of the transistors of the light emission control shift register unit, respectively.

[0038] For example, in a display substrate according to at least one embodiment of the present disclosure, the density range of the first aperture is 10% to 25%, and the density range of the second aperture is 10% to 25%.

[0039] For example, in a display substrate according to at least one embodiment of the present disclosure, the dimensions of the first aperture and the dimensions of the second aperture have a positive correlation with the area of ​​the corresponding transistor.

[0040] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthographic projections of the periphery of the first opening and the periphery of the second opening onto the base substrate do not overlap.

[0041] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projection of the periphery of the first opening onto the base substrate and the orthogonal projection of the periphery of the second opening onto the base substrate are provided alternately.

[0042] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first planarization layer and a second planarization layer, wherein the first planarization layer is located on one side of the first barrier layer away from the second barrier layer in a direction perpendicular to the base substrate, and the second planarization layer is located between the first barrier layer and the second barrier layer in a direction perpendicular to the base substrate, and the second planarization layer is the organic insulating layer.

[0043] For example, in a display substrate according to at least one embodiment of the present disclosure, the second blocking layer is connected to the first blocking layer by a plurality of via holes penetrating the second planarization layer, the light emission control scanning drive circuit includes a plurality of cascaded light emission control shift register units, each light emission control shift register unit includes a plurality of transistors, and for each light emission control shift register unit, the first blocking layer covers at least one transistor in the light emission control shift register unit, and the second blocking layer covers at least one transistor from a plurality of transistors other than the at least one transistor in the light emission control shift register unit, and corresponding to each light emission control shift register unit, the first blocking layer includes a plurality of periodically arranged first apertures, and the second blocking layer includes a plurality of periodically arranged second apertures, so that the first blocking layer and the second blocking layer each cover at least some of the transistors in the light emission control shift register unit, and along a second direction perpendicular to the first direction, the plurality of via holes are located between the first apertures and the second apertures.

[0044] For example, in a display substrate according to at least one embodiment of the present disclosure, the via hole shape is circular or rectangular, and the via hole diameter range is 3 μm to 5 μm.

[0045] For example, a display substrate according to at least one embodiment of the present disclosure further includes a support layer, the support layer being located on one side of the second barrier layer away from the first barrier layer, and the orthographic projection of the support layer onto the base substrate overlaps with the orthographic projection onto the base substrate of the periphery of a row of via holes away from the display area in the plurality of via holes.

[0046] For example, a display substrate according to at least one embodiment of the present disclosure further includes a semiconductor layer arranged sequentially between the base substrate and the first insulating layer in a direction perpendicular to the base substrate, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, and a fourth insulating layer, wherein the semiconductor layer includes the active layers of the plurality of transistors, the first conductive layer includes the gates of the plurality of transistors and the first electrodes of the plurality of capacitors, the second conductive layer includes the second electrodes of the plurality of capacitors, and the third conductive layer includes the plurality of connection portions, the first clock signal line, the second clock signal line, the second power line, and the third power line.

[0047] For example, in a display substrate according to at least one embodiment of the present disclosure, the first blocking layer and the second blocking layer each form a plurality of stabilizing capacitors between themselves and the third conductive layer, the first blocking layer and the second blocking layer each serve as the second electrode plates of the plurality of stabilizing capacitors, and the first electrode plate of the plurality of stabilizing capacitors is the third conductive layer.

[0048] For example, in a display substrate according to at least one embodiment of the present disclosure, the portion of the first shielding layer away from the display area includes a first portion and a second portion located on one side of the first planarization layer away from the base substrate, and the portion of the second shielding layer away from the display area includes a first portion and a second portion located on one side of the second planarization layer away from the base substrate.

[0049] For example, in a display substrate according to at least one embodiment of the present disclosure, the first power line includes a portion of the third conductive layer away from the display area, a first portion of the first shielding layer, and a first portion of the second shielding layer, and the portion of the third conductive layer away from the display area and the first portion of the first shielding layer are in direct contact with the first portion of the second shielding layer.

[0050] For example, in a display substrate according to at least one embodiment of the present disclosure, the angle range between the second portion of the first barrier layer and the third conductive layer is 20° to 30°, and the angle range between the second portion of the second barrier layer and the third conductive layer is 25° to 40°.

[0051] For example, in a display substrate according to at least one embodiment of the present disclosure, the first planarization layer and the second planarization layer further include a groove provided between the light emission control scanning drive circuit and the gate scanning drive circuit, the first planarization layer includes a first portion located on one side of the groove away from the display area and covering the light emission control scanning drive circuit and a second portion covering the gate scanning drive circuit, and the second planarization layer located on one side of the groove away from the display area and covering the light emission control scanning drive circuit. The second planarization layer comprises a first portion and a second portion covering the gate scanning drive circuit, wherein the orthographic projection of the first boundary adjacent to the display area onto the base substrate falls within the orthographic projection of the first portion of the second planarization layer onto the base substrate, and the orthographic projection of the first portion of the second planarization layer onto the base substrate falls within the orthographic projection of the first portion of the first planarization layer onto the base substrate, and the second planarization layer extends from the region corresponding to the light emission control scanning drive circuit to the region corresponding to the gate scanning drive circuit and covers the groove.

[0052] For example, in a display substrate according to at least one embodiment of the present disclosure, the width B along the second direction perpendicular to the first direction of the orthographic projection of the second barrier layer covering the groove onto the base substrate is expressed by the following formula: B=A+k1×P1+k2×Q1+k3×P2+k4×Q2 P1 = d1 × tan(c1) P2 = d2 × tan(c2)

[0053] However, A represents the width of the orthographic projection of the groove onto the base substrate along the second direction, P1 represents the width of the orthographic projection of the first gradient portion of the second barrier layer onto the base substrate, Q1 represents the width of the orthographic projection of the first platform of the second barrier layer onto the base substrate, P2 represents the width of the orthographic projection of the second gradient portion of the second barrier layer onto the base substrate, Q2 represents the width of the orthographic projection of the second platform of the second barrier layer onto the base substrate, d1 represents the thickness of the first planarization layer, d2 represents the thickness of the second planarization layer, c1 represents the gradient angle of the first planarization layer, c2 represents the gradient angle of the second planarization layer, and k1, k2, k3, and k4 are coefficients, however 1 <k1≦2、1<k2≦2、1<k3≦2、1<k4≦2である。

[0054] For example, in a display substrate according to at least one embodiment of the present disclosure, the angle range between the first blocking layer and the second blocking layer at a position adjacent to the groove of the first blocking layer is 25° to 40°.

[0055] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fifth insulating layer and a sixth insulating layer, wherein the fifth insulating layer is located between the first barrier layer and the third conductive layer in a direction perpendicular to the base substrate, and the sixth insulating layer is located between the second barrier layer and the third conductive layer in a direction perpendicular to the base substrate.

[0056] For example, in a display substrate according to at least one embodiment of the present disclosure, the fifth insulating layer includes the first planarization layer, and the sixth insulating layer includes the first planarization layer and the second planarization layer.

[0057] For example, in a display substrate according to at least one embodiment of the present disclosure, the thickness range of the first planarization layer and the second planarization layer is 1.0 μm to 2.0 μm, respectively.

[0058] For example, a display substrate according to at least one embodiment of the present disclosure includes a first portion located in the display area and a second portion located on one side away from the base substrate, wherein the orthographic projection of the boundary of the first portion adjacent to the peripheral area onto the base substrate is such that the gate scanning drive circuit partially overlaps with the orthographic projection onto the base substrate, and the orthographic projection of the second portion onto the base substrate is such that the pixel definition layer partially overlaps with the orthographic projection onto the base substrate of the second aperture of the second barrier layer, a cathode layer located on one side away from the base substrate, a first packaging layer located on one side away from the base substrate, a second packaging layer located on one side away from the base substrate, and a third packaging layer located on one side away from the base substrate.

[0059] For example, in a display substrate according to at least one embodiment of the present disclosure, the distance range between the boundary where the first barrier layer separates from the display area and the boundary where the third packaging layer separates from the display area is 95 μm to 105 μm.

[0060] For example, a display substrate according to at least one embodiment of the present disclosure further includes a touch structure located on one side away from the base substrate where the third packaging layer is located.

[0061] For example, in a display substrate according to at least one embodiment of the present disclosure, the touch structure includes a plurality of touch wirings connected to a touch driving electrode and a touch sensing electrode, the touch driving electrode and the touch sensing electrode portions are located in the display area, and the orthographic projection of the first shielding layer and the second shielding layer onto the base substrate at least partially overlaps with the orthographic projection of the touch wiring onto the base substrate.

[0062] For example, in a display substrate according to at least one embodiment of the present disclosure, the display substrate further includes a first planarization layer and a second planarization layer, the first planarization layer and the second planarization layer further include a groove provided between the light emission control scanning drive circuit and the gate scanning drive circuit, and the orthographic projection of at least a portion of the touch wiring onto the base substrate enters the groove.

[0063] For example, in a display substrate according to at least one embodiment of the present disclosure, the first shielding layer further includes a third portion, the orthographic projection of the third portion onto the base substrate overlaps with and contacts the orthographic projection of the signal lines of the gate scanning drive circuit onto the base substrate.

[0064] The signal lines of the gate scanning drive circuit are configured to provide a clock signal to the gate scanning drive circuit.

[0065] At least one embodiment of the present disclosure further provides a light emission control scanning drive circuit comprising a plurality of cascaded light emission control shift register units, each light emission control shift register unit comprising a plurality of transistors, a plurality of capacitors, a plurality of connectors, a first cutoff layer, and a second cutoff layer, wherein the first cutoff layer is located between the plurality of connectors and the second cutoff layer, and the plurality of transistors include: a first transistor whose gate is connected to a first clock signal line, receiving a first clock signal, having a first electrode connected to a first node and a second electrode connected to an input terminal; a second transistor whose gate is connected to the first node, having a first electrode connected to a second node and a second electrode connected to the first clock signal line, receiving the first clock signal; and a third transistor whose gate is connected to a first clock signal line, having a first electrode connected to a second node and receiving a second voltage, having a second electrode connected to a second power line. , a fourth transistor whose gate is connected to the second clock signal line and receives the second clock signal, its first electrode is connected to the first node and its second electrode is connected to the second electrode of the fifth transistor, a fifth transistor whose gate is connected to the second node and its first electrode is connected to the third power line and receives the third voltage, a sixth transistor whose gate is connected to the second electrode of the eleventh transistor and its first electrode is connected to the second clock signal line and receives the second clock signal, its second electrode is connected to the third node, a seventh transistor whose gate is connected to the second clock signal line and receives the second clock signal, its first electrode is connected to the third node and its second electrode is connected to the fourth node, an eighth transistor whose gate is connected to the first node and its first electrode is connected to the fourth node and its second electrode is connected to the third power line and receives the third voltage,The plurality of capacitors include a ninth transistor whose second electrode is connected to the output terminal, a tenth transistor whose gate is connected to the second electrode of a twelfth transistor and whose first electrode is connected to the second power line, thereby receiving the second voltage, and whose second electrode is connected to the output terminal, an eleventh transistor whose gate is connected to the second power line, thereby receiving the second voltage, and whose first electrode is connected to the second node, and a twelfth transistor whose gate is connected to the second power line, thereby receiving the second voltage, and whose first electrode is connected to the first node, and the plurality of capacitors include a first capacitor whose first electrode is connected to the second electrode of the eleventh transistor and whose second electrode is connected to the third node, a second capacitor whose first electrode is connected to the second electrode of the twelfth transistor and whose second electrode is connected to the second clock signal line, thereby receiving the second clock signal, a third capacitor whose first electrode is connected to the fourth node and whose second electrode is connected to the third power line, thereby receiving the third voltage, and a first electrode plate connected to the first node The circuit includes a third stabilizing capacitor in which the second electrode plate is electrically connected to the first power line, a fourth stabilizing capacitor in which the first electrode plate is connected to the second node and the second electrode plate is electrically connected to the first power line, and a second stabilizing capacitor in which the first electrode plate is connected to the output terminal and the second electrode plate is electrically connected to the first power line, wherein the plurality of connection parts include a first connection part, a second connection part, and a third connection part, the first connection part includes the first node, the second connection part includes the second node, and the third connection part is the light emission control scanning drive circuit The second stabilizing capacitor is connected to the output terminal, the first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal, the second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the second stabilizing capacitor includes a first portion and a second portion, with an organic insulating layer between the first portion and the second portion along a direction perpendicular to the base substrate, the first electrode plate of the third stabilizing capacitor is electrically connected to the first connection portion, the second electrode plate of the third stabilizing capacitor is electrically connected to the first power line, andThe second electrode plate of the third stabilizing capacitor includes a first portion and a second portion, and has an organic insulating layer between the first portion and the second portion along a direction perpendicular to the base substrate; the first electrode plate of the fourth stabilizing capacitor is electrically connected to the second connection portion; the second electrode plate of the fourth stabilizing capacitor is electrically connected to the first power line; and the second electrode plate of the fourth stabilizing capacitor includes a first portion and a second portion, and has an organic insulating layer between the first portion and the second portion along a direction perpendicular to the base substrate.

[0066] At least one embodiment of the present disclosure further provides a display device including a display substrate according to any one embodiment of the present disclosure.

[0067] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, providing a base substrate, and forming a gate scanning drive circuit, a light emission control scanning drive circuit, and a first power line on the base substrate, wherein the output terminal of the gate scanning drive circuit is electrically connected to at least one data writing transistor in the display area, the data writing transistor is configured to control the writing of a data signal in response to the gate scanning signal, the output terminal of the light emission control scanning drive circuit is electrically connected to at least one light emission control transistor in the display area, the light emission control transistor is configured to control the emission of light from a light-emitting element in response to the light emission control signal, and the first power line is connected to at least one light emission in the display area The gate scanning drive circuit is electrically connected to the cathode of the optical element, and the gate scanning drive circuit includes a first stabilizing capacitor, the first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scanning drive circuit, and the second electrode plate of the first stabilizing capacitor is electrically connected to the first power line, and the light emission control scanning drive circuit includes a second stabilizing capacitor, the first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal of the light emission control scanning drive circuit, and the second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the second stabilizing capacitor includes a first portion and a second portion, and has an organic insulating layer between the first portion and the second portion along a direction perpendicular to the base substrate.

[0068] To more clearly explain the technical concept of the embodiments of the present invention, the accompanying drawings of these embodiments are briefly introduced below. It is obvious that the accompanying drawings in the following description relate only to some embodiments of the present invention and do not limit the present invention. [Brief explanation of the drawing]

[0069] [Figure 1A] This is a schematic diagram of the overall circuit structure of the display panel. [Figure 1B] This is a circuit diagram of the pixel circuit of the 7T1C. [Figure 1C]This is a circuit diagram of the light emission control shift register unit. [Figure 1D] Figure 1C shows the signal timing diagram during operation of the light emission control shift register unit. [Figure 1E] Figure 1C is a schematic diagram of the layout of the light emission control shift register unit on the display board. [Figure 1F] This is a schematic diagram of a gate scanning shift register unit according to at least one embodiment of the present disclosure. [Figure 1G] This is a schematic layout diagram of a gate scanning shift register unit on a display board according to at least one embodiment of the present disclosure. [Figure 2A] Figure 1C is a schematic diagram of the layout of the light emission control shift register unit 105 on the display board. [Figure 2B] This is a schematic diagram of a first barrier layer relating to at least one embodiment of the present disclosure. [Figure 2C] This is a schematic diagram of a second barrier layer relating to at least one embodiment of the present disclosure. [Figure 2D] Figure 2A is a perspective view of the light emission control shift register unit 105. [Figure 2E] Figure 2D is a schematic diagram of the second cutoff layer of the light emission control shift register unit 105 shown. [Figure 2F] Figure 2D is a schematic diagram of the first cutoff layer of the light emission control shift register unit 105 shown. [Figure 3A] Figure 1C is a schematic diagram of another layout of the light emission control shift register unit 105 on the display board. [Figure 3B] This is a schematic diagram of another first barrier layer relating to at least one embodiment of the present disclosure. [Figure 3C] This is a schematic diagram of another second barrier layer relating to at least one embodiment of the present disclosure. [Figure 4] This is a cross-sectional view of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] This is a schematic diagram of another display board relating to at least one embodiment of the present disclosure. [Figure 5B] This is a cross-sectional view of the display board in Figure 5A, along the AA' and BB' directions. [Figure 5C] This is a schematic diagram of a light emission control shift register unit according to at least one embodiment of the present disclosure. [Figure 5D] This is a schematic diagram of a gate scanning shift register unit according to at least one embodiment of the present disclosure. [Figure 5E] This diagram shows the connection relationship between a light emission control shift register unit and a pixel circuit according to at least one embodiment of the present disclosure. [Figure 6] This is a cross-sectional view of another display substrate according to at least one embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a light emission controlled scanning drive circuit according to at least one embodiment of the present disclosure. [Figure 8] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Figure 9] This is a flowchart of a method for manufacturing a display board according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0070] To further clarify the object, technical proposal and advantages of the embodiments of the present invention, the technical proposal of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It will be clear that the embodiments described are some embodiments of the present invention, and not all embodiments. Any other embodiments that a person skilled in the art can obtain without creative work based on the embodiments of the present invention described are all within the scope of protection of the present invention.

[0071] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by those skilled in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but merely distinguish different components. Similarly, similar terms such as “one,” “1,” and “the said” do not imply a quantitative limitation, but indicate the presence of at least one. Similar terms such as “includes” and “contains” mean that the element or object preceding the term includes the element or object listed after the term, and their equivalents, but do not exclude other elements or objects. Similar terms such as “connected” and “connected to one another” are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. Terms such as “up,” “down,” “left,” and “right” merely indicate relative positions, and such relative positions may change if the absolute position of the subject changes.

[0072] The present disclosure will be described below by some specific embodiments. In order to maintain clarity and brevity in the following description of embodiments of the present invention, detailed descriptions of known functions and known components may be omitted. When any component of any embodiment of the present invention appears in one or more accompanying drawings, that component is represented by the same reference numeral in each accompanying drawing.

[0073] Figure 1A is a schematic diagram of the overall circuit structure of the display panel. For example, as shown in Figure 1A, 101 represents the entire outer frame of the display panel, and the display panel includes a display area (i.e., a pixel array area) 102 and a peripheral area 106 located around the display area 102, the display area including an array of pixel units 103, and the peripheral area 106 including a scan drive shift register unit 104, the cascade-connected scan drive shift register units 104 which constitute a gate scan drive circuit (Gate GOA) used to provide, for example, a gate scan signal that is shifted row by row to the array of pixel units 103 in the display area 102 of the display panel 101. This peripheral region 106 further includes a light emission control shift register unit 105, and a plurality of cascaded light emission control shift register units 105 constitute a light emission control scanning drive circuit (EM GOA) and are used to provide light emission control signals, for example, that are shifted one row at a time, to pixel units 103 arranged in an array in the display area 102 of the display panel 101, that is, to output a gate scanning drive circuit for light emission control signals.

[0074] As shown in Figure 1A, data lines DL1-DLN (where N is an integer greater than 1) connected to the data drive chip IC penetrate the display area 102 vertically, providing data signals to the array-arranged pixel units 103. Gate lines GL1-GLM (where M is an integer greater than 1) connected to the scan drive shift register unit 104 and the light emission control shift register unit 105 penetrate the display area 102 horizontally, providing gate scan signals and light emission control signals to the array-arranged pixel units 103. For example, each pixel unit 103 may include a pixel circuit having a circuit structure such as 7T1C, 7T2C, 8T2C, or 4T1C within this field, and a light-emitting element. The pixel circuit operates by controlling data signals transmitted by data lines, gate scan signals transmitted by gate lines, and light emission control signals, thereby driving the light emission of the light-emitting element and realizing operations such as display. This light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0075] Figure 1B is a circuit diagram of the pixel circuit of 7T1C. As shown in Figure 1D, this pixel circuit includes a drive transistor M1, a data writing transistor M2, a compensation transistor M3, a storage capacitor Cst, light emission control transistors M4 / M5, and reset transistors M6 / M7, and further includes a drive node S1, a data writing node S2, a compensation node S3, and a light emission control node S4. For example, the gate of the data writing transistor M2 is connected to a gate line GLm (where m is an integer greater than 0 and less than or equal to M), thereby receiving a gate scanning signal provided by the gate scanning drive circuit, and the gates of the light emission control transistors M4 / M5 are connected to light emission control signal lines EM1 and EM2, respectively (for example, these light emission control signal lines are gate lines), thereby receiving light emission control signals provided by the light emission control scanning drive circuit, and thus driving the emission of light from the light-emitting element LE. The specific connection relationships and operating principles of this pixel circuit may be described in reference to the design of this art and are omitted here.

[0076] Figure 1C is a circuit diagram of the light emission control shift register unit. Figure 1D is a signal timing diagram of the light emission control shift register unit during operation as shown in Figure 1C. Below, we will briefly introduce the operation process of this light emission control shift register unit by linking Figures 1C and 1D.

[0077] As shown in Figure 1C, this light emission control shift register unit 105 includes 12 transistors (1st transistor T1, 2nd transistor T2, 3rd transistor T3, 4th transistor T4, 5th transistor T5, 6th transistor T6, 7th transistor T7, 8th transistor T8, output transistor T9 (also called 9th transistor), 10th transistor T10 (also called output transistor), 11th transistor T11 and 12th transistor T12) and 3 capacitors (1st capacitor C1, 2nd capacitor C2 and 3rd capacitor C3). For example, when multiple light emission control shift register units 105 are cascaded, the second electrode of the first transistor T1 in the first stage light emission control shift register unit 105 is connected to the input terminal EI, and the input terminal EI is connected to the trigger signal line ESTV, thereby configuring it to receive a trigger signal as an input signal. The second electrode of the first transistor T1 in each of the other stages of light emission control shift register units 105 is electrically connected to the output terminal of the preceding light emission control shift register unit 105, so that it receives the output signal output by the output terminal EOUT of the preceding light emission control shift register unit 105 and uses it as an input signal, thereby realizing a shift output, and providing a light emission control signal that shifts, for example, one row at a time, to the pixel units 103 arranged in an array in the display area 102 of the display panel 101.

[0078] As shown in Figures 1C and 1D, this light-emitting control shift register unit further includes a first clock signal terminal CK and a second clock signal terminal CB, where ECK represents the first clock signal line and ECB represents the second clock signal line. For example, the first clock signal is received by connecting the first clock signal terminal CK to the first clock signal line ECK or the second clock signal line ECB. For example, when the first clock signal terminal CK is connected to the first clock signal line ECK, the first clock signal line ECK provides the first clock signal, and when the first clock signal terminal CK is connected to the second clock signal line ECB, the second clock signal line ECB provides the first clock signal. Specifically, this depends on the actual situation, and the embodiments of this disclosure are not limited thereto. Similarly, the second clock signal is received by connecting the second clock signal terminal CB to the second clock signal line ECB or the first clock signal line ECK. In the following example, the first clock signal is received by connecting the first clock signal terminal CK to the first clock signal line ECK, and the second clock signal is received by connecting the second clock signal terminal CB to the second clock signal line ECB. However, the embodiments of this disclosure are not limited thereto. For example, the first and second clock signals may be pulse signals with a duty cycle greater than 50%, and there may be, for example, a half-period difference between them. VGL represents the second power line and the second voltage provided by the second power line, VGH represents the third power line and the third voltage provided by the third power line, and the third voltage may be greater than the second voltage, for example, the third voltage being a DC high level and the second voltage being a DC low level. N1, N2, N3, and N4 represent the first node, second node, third node, and fourth node in the schematic circuit diagram, respectively.

[0079] As shown in Figures 1C and 1D, the gate of the first transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line ECK), so it receives the first clock signal, the second electrode of the first transistor T1 is connected to the input terminal EI, and the first electrode of the first transistor T1 is connected to the first node N1. For example, if this light emission control shift register unit is the first stage light emission control shift register unit, the input terminal EI is connected to the trigger signal line ESTV so it receives the trigger signal, and if this light emission control shift register unit is a light emission control shift register unit of any other stage other than the first stage, the input terminal EI is connected to the output terminal EOUT of the preceding light emission control shift register unit.

[0080] The gate of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first clock signal terminal CK, thereby receiving the first clock signal.

[0081] The gate of the third transistor T3 is connected to the first clock signal terminal CK, allowing it to receive the first clock signal. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the second power line VGL, allowing it to receive the second voltage.

[0082] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (for example, the second clock signal terminal CB is connected to the second clock signal line ECB), thereby receiving the second clock signal. The first electrode of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.

[0083] The gate of the fifth transistor T5 is connected to the second node N2, and the first electrode of the fifth transistor T5 is connected to the third power line VGH, thereby receiving the third voltage.

[0084] The gate of the sixth transistor T6 is connected to the second electrode of the eleventh transistor T11, and the first electrode of the sixth transistor T6 is connected to the second clock signal terminal CB, thereby receiving the second clock signal, and the second electrode of the sixth transistor T6 is connected to the third node N3.

[0085] The first electrode of the first capacitor C1 is connected to the second electrode of the eleventh transistor T11, and the second electrode of the first capacitor C2 is connected to the third node N3.

[0086] The gate of the seventh transistor T7 is connected to the second clock signal terminal CB, thereby receiving the second clock signal. The first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0087] The gate of the 8th transistor T8 is connected to the 1st node N1, the 1st electrode of the 8th transistor T8 is connected to the 4th node N4, and the 2nd electrode of the 8th transistor T8 is connected to the 3rd power line VGH, thereby receiving the 3rd voltage.

[0088] The gate of output transistor T9 is connected to the fourth node N4, and the first electrode of output transistor T9 is connected to the third power line VGH, thereby receiving the third voltage, and the second electrode of output transistor T9 is connected to the output terminal EOUT.

[0089] The first electrode of the third capacitor C3 is connected to the fourth node N4, and the second electrode of the third capacitor C3 is connected to the third power line VGH, thereby receiving the third voltage.

[0090] The gate of the 10th transistor T10 is connected to the second electrode of the 12th transistor T12, and the first electrode of the 10th transistor T10 is connected to the second power line VGL, thereby receiving the second voltage, and the second electrode of the 10th transistor T10 is connected to the output terminal EOUT.

[0091] The first electrode of the second capacitor C2 is connected to the second electrode of the 12th transistor T12, and the second electrode of the second capacitor C2 is connected to the second clock signal terminal CB, thereby receiving the second clock signal.

[0092] The gate of the 11th transistor T11 is connected to the second power line VGL, thereby receiving the second voltage, and the first electrode of the 11th transistor T11 is connected to the second node N2.

[0093] The gate of the 12th transistor T12 is connected to the second power line VGL, thereby receiving the second voltage, and the first electrode of the 12th transistor T12 is connected to the first node N1.

[0094] The transistors in the light emission control shift register unit 105 shown in Figure 1C are all described as P-type transistors, meaning that each transistor turns on when its gate receives a low level (on level) and turns off when it receives a high level (off level). In this case, the first electrode of the transistor may be the source electrode, and the second electrode of the transistor may be the drain electrode.

[0095] This light emission control shift register unit includes, but is not limited to, the arrangement shown in Figure 1C. For example, the light emission control shift register unit 105 does not necessarily include T11 and T12, and a transistor having the same function as T11 or T12 may be provided at the position of the N3 or N4 node. Each transistor may be an N-type transistor, or a mixture of P-type and N-type transistors may be used, and the port polarity of the selected type of transistor should be connected according to the port polarity of the corresponding transistor in the embodiment of this disclosure.

[0096] It should be explained that the transistors used in this light-emitting control shift register unit may be thin-film transistors, field-effect transistors, or other switching elements with the same characteristics. Here, we will explain using thin-film transistors as examples. For example, the active layer (channel region) of this transistor may be made of a semiconductor material, such as polycrystalline silicon (e.g., low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, or indium gallium tin oxide (IGZO), while the gate electrode, source electrode, drain electrode, etc., may be made of a metallic material, such as metallic aluminum or an aluminum alloy. The source and drain of the transistor used here may be structurally symmetrical, and therefore, the source and drain may not be structurally distinguishable. In the embodiments of this disclosure, in order to distinguish between the two electrodes other than the gate electrode of the transistor, it is directly stated that one electrode is the first electrode and the other is the second electrode. Also, in the embodiments of this disclosure, the electrodes of the capacitor may be made of metal, or one of the electrodes may be made of a semiconductor material (e.g., doped polycrystalline silicon).

[0097] Figure 1D is a signal timing diagram of the operation of the light emission control shift register unit 105 shown in Figure 1C. Below, we will describe the operation process of this light emission control shift register unit in detail by linking Figures 1C and 1D. For example, we will explain the operating principle of the first stage of the light emission control shift register unit 105, and the operating principles of the remaining stages of the light emission control shift register unit 105 are similar and will be omitted from the explanation. As shown in Figure 1D, the operation process of this light emission control shift register unit 105 includes six stages, which are the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5, and the sixth stage P6, and Figure 1D shows the timing waveforms of each signal in each stage.

[0098] In the first stage P1, as shown in Figure 1D, the first clock signal line ECK provides a low level, so the first clock signal terminal CK connected to the first clock signal line ECK receives the low-level first clock signal, causing the first transistor T1 and the third transistor T3 to turn on. The first transistor T1, which turns on, transmits a high-level trigger signal ESTV to the first node N1, changing the level of the first node N1 to a high level, which causes the second transistor T2, the eighth transistor T8, and the tenth transistor T10 to turn off. The third transistor T3, which turns on, transmits a low-level second voltage to the second node N2, changing the level of the second node N2 to a low level, which causes the fifth transistor T5 and the sixth transistor T6 to turn on. Since the second clock signal line ECB provides a high level, the second clock signal received by the second clock signal terminal CB connected to the second clock signal line ECB is high level, causing the fourth transistor T4 and the seventh transistor T7 to turn off. Furthermore, due to the memory function of the third capacitor C3, the level of the fourth node N4 can be kept high, thereby turning off the output transistor T9. In the first stage P1, both the output transistor T9 and the tenth transistor T10 are turned off, so the output signal output by the output terminal EOUT_1 of this light emission control shift register unit 105 retains the previous low level.

[0099] In the second stage P2, as shown in Figure 1D, the second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned on. The first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal, so the first transistor T1 and the third transistor T3 are turned off. Due to the memory function of the first capacitor C1, the second node N2 can continue to hold the low level from the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level third voltage VGH is transmitted to the first node N1 by the fifth transistor T5 and the fourth transistor T4, which are turned on, so the level of the first node N1 continues to hold the high level from the previous stage, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Furthermore, the low-level second clock signal is transmitted to the fourth node N4 by the sixth transistor T6 and the seventh transistor T7, which are turned on. As a result, the level of the fourth node N4 changes to a low level, causing the output transistor T9 to turn on. The turned-on output transistor T9 outputs a high-level third voltage VGH, and therefore the output signal output in the second stage P2 by the output terminal EOUT_1 of this light emission control shift register unit 105 is high level.

[0100] In the third stage P3, as shown in Figure 1D, the first clock signal line ECK provides a low-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal line ECB provides a high-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned off. Due to the memory function of the third capacitor C3, the level of the fourth node N4 can retain the low level from the previous stage, and thus the output transistor T9 remains on. Since the turned-on output transistor T9 outputs a high-level third voltage VGH, the output signal output in the third stage P3 by the output terminal EOUT_1 of this light emission control shift register unit 105 is still high level. Also in this stage, the output terminal EOUT_2 of the second stage light emission control shift register unit 105 outputs a high level (for a specific description, refer to the operation process of the first stage light emission control shift register unit 105 in the second stage P2 described above).

[0101] In the fourth stage P4, as shown in Figure 1D, the first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the memory function of the second capacitor C2, the level of the first node N1 retains the high level from the previous stage, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Due to the memory function of the first capacitor C1, the second node N2 continues to retain the low level from the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. Furthermore, the low-level second clock signal is transmitted to the fourth node N4 by the sixth transistor T6 and the seventh transistor T7, which are turned on. As a result, the level of the fourth node N4 changes to a low level, causing the output transistor T9 to turn on. The turned-on output transistor T9 outputs a high-level third voltage VGH, and therefore the output signal output in the fourth stage P4 by the output terminal EOUT_1 of this light emission control shift register unit 105 remains at a high level. Also, at this stage, the output terminal EOUT_2 of the second stage light emission control shift register unit 105 outputs a high level (for a specific description, refer to the operation process of the first stage light emission control shift register unit 105 in the third stage P3 described above).

[0102] In the fifth stage P5, as shown in Figure 1D, the first clock signal line ECK provides a low-level first clock signal to the first clock signal terminal CK, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal line ECB provides a high-level second clock signal to the second clock signal terminal CB, so the fourth transistor T4 and the seventh transistor T7 are turned off. The first transistor T1, which is turned on, transmits a low-level trigger signal ESTV to the first node N1, thereby changing the level of the first node N1 to a low level.

[0103] For example, in the fifth stage P5, the low-level voltage of the first clock signal is -6V, the low-level voltage of the trigger signal ESTV is -6V, and the threshold voltage Vth of the first transistor T1 is -1.5V. Since the first transistor T1 is a P-type transistor, in order to turn on the first transistor T1, the voltage Vgs between the gate and source of the first transistor T1 must be less than the threshold voltage Vth of the first transistor T1. Therefore, when the first node N1 is charged to -4.5V, the first transistor T1 is turned off, and charging to the first node N1 is stopped. That is, at this stage the low-level voltage of the first node N1 is -4.5V, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on. The second transistor T2, which is turned on, transmits a low-level first clock signal to the second node N2, further lowering the level of the second node N2. As a result, the second node N2 continues to maintain the low level from the previous step, turning on the fifth transistor T5 and the sixth transistor T6. The eighth transistor T8, which is turned on, transmits a high-level third voltage VGH to the fourth node N4, changing the level of the fourth node N4 to a high level, and thus turning off the output transistor T9. The 10th transistor T10, which is turned on, responds to the low level (e.g., -4.5V) of the first node N1 and outputs a low-level second voltage VGL (e.g., -6V). Similarly, the threshold voltage Vth of the 10th transistor T10 is -1.5V. In order to turn on the 10th transistor T10, the voltage Vgs between the gate and source of the 10th transistor T10 must be less than the threshold voltage Vth of the 10th transistor T10. Therefore, the 10th transistor T10 is turned off when the voltage output by the output terminal EOUT_1 is -3V. That is, at this stage the low-level voltage of the output terminal EOUT_1 is -3V, so the output signal output in the 5th stage P5 by the output terminal EOUT_1 of this first stage light emission control shift register unit 105 is changed to a first low level (e.g., -3V).Furthermore, at this stage, the output terminal EOUT_2 of the second stage light emission control shift register unit 105 outputs a high level (for a specific description, refer to the operation process of the first stage light emission control shift register unit 105 in the fourth stage P4 described above).

[0104] In the sixth stage P6, as shown in Figure 1D, the fourth transistor T4 and the seventh transistor T7 are turned on because the first clock signal line ECK provides a high-level first clock signal to the first clock signal terminal CK, and the second clock signal line ECB provides a low-level second clock signal to the second clock signal terminal CB. The second clock signal changes the fifth stage P5 from a high level to a low level, for example, by Δt (e.g., greater than 6V). Based on the bootstrap effect of the second capacitor C2, the level of the first node N1 is changed from the low level of the fifth stage P5 (e.g., -4.5V) to one lower low level (e.g., -4.5V-Δt). This causes the second transistor T2 and the tenth transistor T10 to be turned on by the control of the low level of the first node N1 (e.g., -4.5V-Δt). Based on the on-characteristics of the tenth transistor T10 described above, the low-level second voltage VGL (e.g., -6V) can be fully output to the output terminal EOUT_1. For example, in this sixth stage P6, the voltage output by this output terminal EOUT_1 is the second low level (e.g., -6V). Furthermore, at this stage, the output terminal EOUT_2 of the second stage light emission control shift register unit 105 outputs a low level (for example, -3V; for a specific description, refer to the operation process of the first stage light emission control shift register unit 105 in the fifth stage P5 described above).

[0105] Furthermore, in each of the above stages, since the second power line VGL always provides a low level, the 11th transistor T11 and the 12th transistor T12 are always on, which avoids the influence of the second clock signal provided by the second clock signal terminal CB connected to the 6th transistor T6 and the output signal of the output terminal EOUT connected to the 10th transistor on the levels of the second node N2 and the first node N1, respectively, thereby ensuring circuit stability.

[0106] Figure 1F is a schematic diagram of a gate scanning shift register unit according to at least one embodiment of the present disclosure. For example, as shown in Figure 1F, the gate scanning shift register unit 104 includes eight transistors (input transistor T21, first control transistor T22, second control transistor T23, output control transistor T24, gate output transistor T25, first noise reduction transistor T26, second noise reduction transistor T27, and voltage stabilization transistor T28) and two capacitors (first scanning capacitor C21 and second scanning capacitor C22). For example, when multiple gate scanning shift register units 104 are cascaded, the first electrode of the input transistor T1 in the first-stage gate scanning shift register unit 104 is connected to the input terminal IN, which is connected to the trigger signal line GSTV, thereby receiving the trigger signal as an input signal. The first electrode of the input transistor T1 in each of the other stages of the gate scanning shift register unit 104 is electrically connected to the output terminal of the preceding gate scanning shift register unit 104, so that it receives the output signal output by the output terminal GOUT of the preceding gate scanning shift register unit 104 and uses it as an input signal, thereby realizing a shift output, which is used to scan, for example, one row at a time, across an array of pixel units in an active display area.

[0107] As shown in Figure 1F, the gate electrode of input transistor T21 is connected to the first subclock signal line GCK, the second electrode of input transistor T1 is connected to the input terminal IN, and the first electrode of input transistor T1 is connected to the first scanning node N21.

[0108] The gate of the first control transistor T22 is connected to the first scanning node N21, the second electrode of the first control transistor T22 is connected to the first subclock signal line GCK, and the first electrode of the first control transistor T22 is connected to the second scanning node N22.

[0109] The gate of the second control transistor T23 is connected to the first subclock signal line GCK, the second electrode of the second control transistor is connected to the second power line VGL, and the first electrode of the second control transistor T23 is connected to the second scanning node N22.

[0110] The gate of the output control transistor T24 is connected to the second scanning node N22, the first electrode of the output control transistor T24 is connected to the third power line VGH, and the second electrode of the output control transistor T24 is connected to the output terminal GOUT.

[0111] The first electrode of the first scanning capacitor C21 is connected to the second scanning node N22, and the second electrode of the first scanning capacitor C21 is connected to the third power line VGH.

[0112] The gate of gate output transistor T25 is connected to the third scanning node N23, the first electrode of output transistor T5 is connected to the second clock sub-signal line GCB, and the second electrode of gate output transistor T25 is connected to the output terminal GOUT.

[0113] The first electrode of the second scanning capacitor C22 is connected to the third scanning node N23, and the second electrode of the second scanning capacitor C2 is connected to the output terminal GOUT.

[0114] The gate of the first noise reduction transistor T26 is connected to the second scanning node N2, the first electrode of the first noise reduction transistor T26 is connected to the third power line VGH, and the second electrode of the first noise reduction transistor T26 is connected to the second electrode of the second noise reduction transistor T7.

[0115] The gate of the second noise reduction transistor T27 is connected to the second sub-clock signal line GCB of the second clock signal, and the first electrode of the second noise reduction transistor T27 is connected to the first scanning node N21.

[0116] The gate of voltage stabilization transistor T28 is connected to the second power line VGL, the second electrode of voltage stabilization transistor T28 is connected to the first scanning node N21, and the first electrode of voltage stabilization transistor T28 is connected to the third scanning node N23.

[0117] The transistors in the gate scanning shift register unit 104 shown in Figure 1F are all described using P-type transistors as an example; that is, each transistor turns on when the gate receives a low level (on-level) and turns off when it receives a high level (off-level). In this case, the first electrode of the transistor may be the source electrode, and the second electrode of the transistor may be the drain electrode.

[0118] This gate scanning shift register unit includes, but is not limited to, the arrangement shown in Figure 1F. For example, capacitor C22 in the gate scanning shift register unit 104 may be connected between the second scanning node N2 and the second clock sub-signal line GCB, or a transistor with a similar function, such as a voltage stabilizing transistor T28, may be provided at node N22. Each transistor may be an N-type transistor, or a mixture of P-type and N-type transistors may be used, and the port polarity of the selected type of transistor should be connected according to the port polarity of the corresponding transistor in the embodiment of this disclosure.

[0119] The operating principle of this gate-scanning shift register unit can be found in the introduction to this field, and will not be explained here.

[0120] For example, the gate scan signal output by the gate scan drive circuit is held at an active level (effective level, e.g., low level) for a relatively short time in one frame, and is output to the gate (e.g., signal terminal GLm) of the data writing transistor M2 in the pixel circuit to control the writing of the data signal. In other words, this gate scan drive circuit outputs an active signal during the period in one frame during which the pixel should write the data signal, and the light emission control signal output by EM GOA is held at an active level (e.g., low level) for a relatively long time in one frame, and is output to the light emission control signal terminals EM1 / EM2 of the light emission control transistors M4 / M5 in the pixel circuit, thereby controlling the light emission of the pixel over a relatively long time period in one frame.

[0121] The inventors noticed that leakage current occurs when transistors in a circuit structure are affected by light or other factors, and that the adverse effects of leakage current are more severe in circuits that need to maintain the output of active signals such as EM GOA for extended periods. Therefore, how to design a new drive circuit structure to accommodate the different output signal needs of gate scanning drive circuits and EM GOA, i.e., the different requirements for preventing TFT leakage, is a problem that urgently needs to be solved.

[0122] At least one embodiment of the present disclosure provides a display substrate comprising a base substrate including a display area and a peripheral area located on at least one side of the display area; gate scanning drive circuits provided in the peripheral area of ​​the base substrate and sequentially arranged along one side away from the display area; a light emission control scanning drive circuit and a first power line, wherein the output terminal of the gate scanning drive circuit is electrically connected to at least one data writing transistor in the display area, the data writing transistor is configured to control the writing of a data signal in response to a gate scanning signal; and the output terminal of the light emission control scanning drive circuit is electrically connected to at least one light emission control transistor in the display area, the light emission control transistor is configured to control the emission of light-emitting elements in response to a light emission control signal. The display area is configured such that a first power line is electrically connected to the cathode of at least one light-emitting element in the display area, the gate scanning drive circuit includes a first stabilizing capacitor, the first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scanning drive circuit, and the second electrode plate of the first stabilizing capacitor is electrically connected to the first power line, the light emission control scanning drive circuit includes a second stabilizing capacitor, the first electrode plate of the second stabilizing capacitor is electrically connected to the output terminal of the light emission control scanning drive circuit, and the second electrode plate of the second stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the second stabilizing capacitor includes a first portion and a second portion, with an organic insulating layer between the first portion and the second portion along a direction perpendicular to the base substrate.

[0123] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate and a method for manufacturing the display substrate.

[0124] The display substrate according to the above embodiment of this disclosure can provide different degrees of interruption to transistors at different positions in the light emission control scanning drive circuit, thereby effectively preventing the generation of leakage current and improving the display quality of the display panel. Furthermore, although the EM GOA needs to maintain the output of an active signal for a long period of time, considering that the time for which the Gate GOA outputs an active signal to drive the data writing transistor of the pixel circuit to turn on is relatively short, the driving capability of the EM GOA can be effectively improved by adopting different structural designs for the first and second stabilizing capacitors in the above embodiment.

[0125] The embodiments and some examples thereof of this disclosure will be described in detail below, with reference to the attached drawings.

[0126] At least one embodiment of this disclosure provides a display substrate. Figure 1E is a schematic layout diagram of the light-emitting control shift register unit shown in Figure 1C on the display substrate. Figure 2A is a schematic layout diagram of the light-emitting control shift register unit 105 shown in Figure 1C on the display substrate. Figure 2B is a schematic diagram of a first shielding layer according to at least one embodiment of this disclosure. Figure 2C is a schematic diagram of a second shielding layer according to at least one embodiment of this disclosure, and Figure 3A is another schematic layout diagram of the light-emitting control shift register unit 105 shown in Figure 1C on the display substrate. Figure 3B is another schematic diagram of a first shielding layer according to at least one embodiment of this disclosure. Figure 3C is another schematic diagram of a second shielding layer according to at least one embodiment of this disclosure. Below, Figures 1E to 3C are linked together to describe in detail the display substrate according to at least one embodiment of this disclosure.

[0127] For example, as shown in Figures 1A and 2A, the display board 1 includes a base board 10 and a gate scanning drive circuit 4 and a light emission control scanning drive circuit 5 provided on the base board 10.

[0128] For example, as shown in Figure 1A, the base substrate 10 includes a display area 102 (for example, the display area 102 may be called the pixel array area) and a peripheral area 106 located on at least one side of the pixel array area. For example, the gate scanning drive circuit and the light emission control scanning drive circuit are located in the peripheral area 106 of the base substrate 10 and are sequentially arranged along one side away from the display area 102, for example, on one side of the base substrate 10 (as shown in Figure 1A, located between the display area 102 and the side edge of the base substrate 10). For example, as shown in Figure 1A, they are located to the left of the display area 102, and of course, they may be located to the right or on both sides of the display area 102, and the embodiments of this disclosure are not limited thereto. For example, as shown in Figure 1A, the gate scanning drive circuit 4 is located between the light emission control scanning drive circuit 5 and the display area 102.

[0129] For example, the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit 5 is greater than the duration of the active level of the gate scanning signal output by the gate scanning drive circuit 4. For example, the output terminal GOUT of the gate scanning drive circuit 4 is connected to at least one data writing transistor (e.g., M2 shown in Figure 1B) in the display area 102, and the data writing transistor M2 is configured to control the writing of the data signal Vdata in response to the gate scanning signal GLm. For example, the output terminals EOUT (e.g., output terminals E021 and E022) of the light emission control scanning drive circuit 5 are connected to at least one light emission control transistor (M4 or M5 shown in Figure 1B) in the display area 102, and the light emission control transistors M4 / M5 are configured to control the light emission of the light-emitting element LE in response to the light emission control signals EM1 / EM2. For a more detailed explanation, please refer to the description in Figure 1B above, and the explanation will be omitted here.

[0130] For example, as shown in Figure 2A, the output terminals E021 and E022 of the light emission control shift register unit 105 of the light emission control scanning drive circuit 5 are connected to the light emission control transistor of the display area 102 by wiring that penetrates laterally through the gate scanning shift register unit 104 in the gate scanning drive circuit 4. Specifically, the output terminals E021 and E022 include a second conductive layer pattern or a third conductive layer pattern connected to the second electrode of the output transistor T9 or the second electrode of the output transistor T10 in the light emission control shift register unit 105.

[0131] For example, the light emission control scanning drive circuit 5 includes a plurality of cascaded light emission control shift register units 105. Figures 1E and 2A show only one light emission control shift register unit 105, and the structure of the remaining light emission control shift register units 105 in this light emission control scanning drive circuit 5 is the same as in Figures 2A and 1E, and therefore their explanation is omitted.

[0132] For example, as shown in Figure 5D, the gate scanning drive circuit includes a first stabilizing capacitor C24, the first electrode plate C241 of the first stabilizing capacitor C24 being electrically connected to the output terminal GOUT of the gate scanning drive circuit 4, and the second electrode plate C242 of the first stabilizing capacitor C24 being electrically connected to the first power line VSS. Specifically, the output terminal GOUT of the gate scanning drive circuit 4 includes a second or third conductive layer pattern connected to the second electrode of the gate output transistor T25 or the second electrode of the output control transistor T24 in the gate scanning drive circuit. For example, the first electrode plate is an independent and complete pattern located in the peripheral region, which can be electrically connected to the signal lines of the display region by layer exchange or via holes, or it can be limited to the fact that the two electrode plates do not overlap with the anode of the light-emitting element (different from the small-dimensional peripheral cathode pattern).

[0133] As shown in Figures 5C and 5B, the light emission control scanning drive circuit 5 includes a second stabilizing capacitor C6, the first electrode plate C61 of the second stabilizing capacitor C6 is electrically connected to the output terminal EOUT of the light emission control scanning drive circuit 5, the second electrode plate C62 of the second stabilizing capacitor C6 is electrically connected to the first power line VSS, and the second electrode plate C62 of the second stabilizing capacitor C6 includes a first portion C621 and a second portion C622, with an organic insulating layer between the first portion C621 and the second portion C622 along a direction perpendicular to the base substrate 10 (for example, the second planarization layer PLN2 shown in Figure 5B).

[0134] For example, as shown in Figure 5C, the light emission control scanning drive circuit 5 further includes a third stabilizing capacitor C4, a fourth stabilizing capacitor C5, a first connection section E1 (as shown in Figures 1E and 5B), and a second connection section E2 (as shown in Figures 1E and 5B). For example, the first connection section E1 includes a first node N1, and the second connection section E2 includes a second node N2.

[0135] For example, as shown in Figures 5B and 5C, the first electrode plate C41 of the third stabilizing capacitor C4 is connected to the first connection E1 (i.e., the first node N1), the second electrode plate C42 of the third stabilizing capacitor C4 is electrically connected to the first power line VSS, and the second electrode plate C42 of the third stabilizing capacitor C4 includes a first portion C421 and a second portion C422, and has an organic insulating layer between the first portion C421 and the second portion C422 along a direction perpendicular to the base substrate 10 (for example, the second planarization layer PLN2 shown in Figure 5B).

[0136] For example, the first electrode plate C51 of the fourth stabilizing capacitor C5 is connected to the second connection E2 (i.e., the second node N2), the second electrode plate C52 of the fourth stabilizing capacitor C5 is electrically connected to the first power line VSS, and the second electrode plate C52 of the fourth stabilizing capacitor C5 includes a first portion C521 and a second portion C522, and has an organic insulating layer between the first portion C521 and the second portion C522 along a direction perpendicular to the base substrate 10 (for example, the second planarization layer PLN2 shown in Figure 5B).

[0137] For example, a detailed explanation of the shift register unit 105 of the light emission control scanning drive circuit 5 can be found in the introduction in Figure 5C, and will be omitted here.

[0138] For example, as shown in Figure 2A, the display board 1 further includes a first blocking layer 21 and a second blocking layer 22, which are sequentially provided on one side away from the base board 10, where the light emission control scanning drive circuit 5 (i.e., light emission control shift register unit 105) is located. For example, the first blocking layer 21 is represented by a solid line frame in Figure 2A, and the second blocking layer 22 is represented by a dotted line frame shown in Figure 2A. The following embodiments are the same and will not be described further. For example, the first blocking layer 21 and the second blocking layer 22 receive a first voltage by being connected to a first power line VSS.

[0139] Figure 2D is a perspective view of the light emission control shift register unit 105 shown in Figure 2A. Figure 2E is a schematic diagram of the second blocking layer of the light emission control shift register unit 105 shown in Figure 2D. Figure 2F is a schematic diagram of the first blocking layer of the light emission control shift register unit 105 shown in Figure 2D. For example, as shown in Figure 2D, the first blocking layer 21 is located between the light emission control shift register unit 105 and the second blocking layer 22.

[0140] For example, as shown in Figures 5B and 1E, the second stabilizing capacitor C6 (whose second electrode plates include C621 and C622) is located (i.e., formed) between the first blocking layer 21, the second blocking layer 22, and the third connection E3, specifically the third connection E3 including a third conductive layer pattern connected to the output terminals E021 and E022 of the light emission control shift register unit 105. The third stabilizing capacitor C4 (whose second electrode plates include C421 and C422) is located between the first blocking layer 21, the second blocking layer 22, and the first connection part E1, specifically the first connection part E1 including a third conductive layer pattern connected to the first node N1 of the light emission control shift register unit 105, and the fourth stabilizing capacitor C5 (whose second electrode plates include C651 and C652) is located between the first blocking layer 21, the second blocking layer 52, and the second connection part E2, specifically the second connection part E2 including a third conductive layer pattern connected to the second node N2 of the light emission control shift register unit 105. For example, as shown in Figure 5B, the first part C621 of the second stabilizing capacitor C6 is part of the first blocking layer 21, and the second part C622 of the second stabilizing capacitor C6 is part of the second blocking layer 22. The first portion C421 of the third stabilizing capacitor C4 is part of the first blocking layer 21, and the second portion C422 of the third stabilizing capacitor C4 is part of the second blocking layer 22. The first portion C521 of the fourth stabilizing capacitor C5 is part of the first blocking layer 21, and the second portion C522 of the fourth stabilizing capacitor C5 is part of the second blocking layer 22. That is, the second stabilizing capacitor C6 includes capacitors formed by the third connection portion E3 with the first blocking layer 21 and the second blocking layer 22, respectively; the third stabilizing capacitor C4 includes capacitors formed by the first connection portion E1 with the first blocking layer 21 and the second blocking layer 22, respectively; and the fourth stabilizing capacitor C5 includes capacitors formed by the second connection portion E2 with the first blocking layer 21 and the second blocking layer 22, respectively. The embodiments of this disclosure are not limited thereto.

[0141] For example, the first blocking layer 21 covers at least one transistor in the light emission control scanning drive circuit 5, and the second blocking layer 22 covers at least one transistor among a plurality of transistors other than the aforementioned at least one transistor in the light emission control scanning drive circuit 5.

[0142] For example, "covering" means that the orthographic projections of both onto the base substrate overlap at least partially, that is, the orthographic projections of the first shielding layer 21 and at least one transistor in the light emission control scanning drive circuit 5 onto the base substrate overlap at least partially, and the orthographic projections of the second shielding layer 22 and at least one transistor among the plurality of transistors other than the aforementioned at least one transistor onto the base substrate overlap at least partially.

[0143] For example, as shown in Figure 2A, the second blocking layer 22 is located on one side away from the base substrate 10 where the gate scanning drive circuit 4 is located, and the second blocking layer 22 covers at least one transistor in the gate scanning drive circuit 4, i.e., the orthographic projections of the second blocking layer 22 and at least one transistor in the gate scanning drive circuit 4 onto the base substrate overlap at least partially. For example, as shown in Figure 2A, the second blocking layer 22 covers each of the remaining transistors in the gate scanning shift register unit 104 except for the first control transistor T21. Embodiments of the present disclosure are not limited thereto.

[0144] For example, the arrangement method in the gate scanning shift register unit 104 in the gate scanning drive circuit 4 may, of course, be other layout methods as shown in Figure 1G, and the embodiments of this disclosure are not limited thereto.

[0145] For example, as shown in Figure 2A, taking one light emission control shift register unit 105 as an example, the first blocking layer 21 covers at least one transistor in the light emission control shift register unit 105 (for example, covering transistors T1, T3, T4, and T11), and the second blocking layer 22 covers at least one of several transistors other than the at least one transistor in the light emission control shift register unit 105 (for example, covering transistors T2, T3, T6, T11, and T12).

[0146] Therefore, the display substrate according to the above embodiment of the present disclosure can perform different degrees of interruption on transistors at different positions in the light emission control scanning drive circuit 5, thereby effectively preventing the generation of leakage current and improving the display quality of the display panel.

[0147] For example, as shown in Figure 1E, the display board 1 further includes a first power line VSS, which is connected, for example, to the cathode of a light-emitting element LE in the pixel circuit of the display area 102 shown in Figure 1B. For example, the light emission control shift register unit 10 further includes a second power line VGL, a third power line VGH, and a plurality of clock signal lines (for example, the first clock signal line ECK, the second clock signal line ECB, and the trigger signal line ESTV shown in the figure). For simplicity and conciseness, the light emission control shift register unit 105 will be referred to as the shift register unit below.

[0148] For example, the second power line VGL, the first power line VSS, the third power line VGH, and multiple clock signal lines (e.g., the first clock signal line ECK, the second clock signal line ECB, and the trigger signal line ESTV) extend along the first direction Y on the base board 10 and are configured to supply the shift register unit 105 with a second voltage, a first voltage, a third voltage, and multiple clock signals (e.g., the first clock signal, second clock signal, or trigger signal described above). For example, the second power line VGL is configured to supply the second voltage to the shift register unit 105, the third power line VGH is configured to supply the third voltage to the shift register unit 105, and the first clock signal line ECK and the second clock signal line ECB are configured to supply the first clock signal or the second clock signal to the shift register unit 105, respectively. For example, the second voltage is smaller than the third voltage, for example, the second voltage is a DC low level and the third voltage is a DC high level. The specific connection relationships between the second power line VGL, the third power line VGH, and the multiple clock signal lines and the shift register unit 105 may be described below. For example, the absolute value of the second voltage provided by the second power line VGL is greater than the absolute value of the first voltage provided by the first power line VSS, for example, the second voltage is approximately -7 volts (V) and the first voltage is approximately -3V. The values ​​of the second voltage and the first voltage depend on the specific circumstances, and the embodiments of this disclosure do not limit this.

[0149] Furthermore, the second power line VGL, the first power line VSS, the third power line VGH, and the multiple clock signal lines may be arranged parallel to each other along the first direction Y, or they may intersect at a certain angle (for example, 20° or less), and the embodiments of this disclosure are not limited thereto.

[0150] For example, the base substrate 10 may be made of, for instance, glass, plastic, quartz, or other suitable material, and the embodiments of this disclosure are not limited thereto.

[0151] For example, the orthographic projection of the second power line VGL onto the base substrate 10 is located on one side where the orthographic projection of the transistor (e.g., shift register unit 105) included in the light emission control scanning drive circuit 5 is close to the display area 102. For example, on the second direction X, it is located to the right of the shift register unit 105 shown in Figure 2A, that is, between the orthographic projection of the shift register unit 105 onto the base substrate 10 and the orthographic projection of the shift register unit 104 included in the gate scanning drive circuit onto the base substrate 10. The orthographic projection of the first power line VSS onto the base substrate 10 is located on one side where the orthographic projection of the light emission control scanning drive circuit 5 onto the base substrate 10 is away from the display area 102.

[0152] For example, the orthographic projection of the third power line VGH and the multiple clock signal lines onto the base board 10 is located on one side away from the display area 102, where the orthographic projection of the transistors included in the shift register unit 105 onto the base board 10 is located, for example, on the second direction X, to the left of the shift register unit 105 shown in Figure 2A. That is, the orthographic projection of the shift register unit 105 onto the base board 10 is located between the orthographic projection of the second power line VGL onto the base board 10 and the orthographic projection of the first power line VSS onto the base board 10.

[0153] For example, as shown in Figure 2A, the second power line VGL and the first power line VSS are positioned such that the first blocking layer 21 is located on one side away from the second blocking layer 22 in a direction perpendicular to the base substrate 10. As a result, the first blocking layer 21 covers the upper surface of the light emission control scanning drive circuit 5 and the second power line VSS, away from the second blocking layer 22, thereby achieving blocking.

[0154] For example, as shown in Figure 2A, the orthographic projection of the third power line VGH onto the base board 10 lies between the orthographic projections of the first clock signal line ECK and the second clock signal line ECB onto the base board 10 and the orthographic projection of the shift register unit 105 onto the base board 10. For example, the trigger signal line (not shown), the second clock signal line ECB, and the first clock signal line ECK are arranged sequentially on the base board 10 along the second direction X from left to right.

[0155] The above wiring locations are merely illustrative examples, and the embodiments of this disclosure are not limited to any arrangement that satisfies the requirements for wiring installation and facilitates connection to the shift register unit.

[0156] For example, the positions of the second power line VGL and the third power line VGH are not limited to the above wiring positions. The orthographic projection of the second power line VGL onto the base substrate 10 can be located on one side away from the display area 102, for example, on the second direction X, to the left of the shift register unit 105 shown in Figure 2A. The orthographic projection of the third power line VGH onto the base substrate 10 can be located on one side close to the display area 102, for example, on the second direction X, to the right of the shift register unit 105 shown in Figure 2A.

[0157] For example, the angle between the first direction Y and the second direction X is between 70° and 90°, and includes 70° and 90°. For example, the angle between the first direction Y and the second direction X may be 70°, 75°, 85°, 90°, or 80°, and may be set based on the actual situation, and the embodiments of this disclosure are not limited thereto. In the following, the first direction Y is given as an example where it is perpendicular to the second direction X, and the embodiments of this disclosure do not describe this.

[0158] For example, the display area 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel circuit and may further include, for example, a light-emitting element (not shown).

[0159] For example, multiple cascaded shift register units 105 constitute an emissive light-emitting controlled scanning drive circuit (EM GOA). For example, the output terminals EOUT of these multiple shift register units 105 are connected to the emissive light-emitting control signal terminals EM1 and EM2 of the emissive light-emitting control transistors M4 and M5 of each row pixel circuit (as shown in Figure 1B) located in the pixel array region. By providing output signals (e.g., emissive light-emitting control signals) to each row pixel circuit, the emissive light emission of the light-emitting element is driven. For example, this pixel circuit is not limited to the 7T1C circuit structure shown in Figure 1B, but may also include other pixel circuits within this field, such as 2T1C, 4T2C, 8T2C, etc., which will not be explained here.

[0160] Figure 1E shows only the Xth stage shift register unit 105 in the light emission control scanning drive circuit. For example, the first clock signal is received because the first clock signal terminal CK of the first stage shift register unit (not shown) (as shown in Figure 1C) is connected to the first clock signal line ECK, the second clock signal is received because the second clock signal terminal CB of the first stage shift register unit 105 is connected to the second clock signal line ECB, the first clock signal is received because the first clock signal terminal CK of the second stage shift register unit (not shown) is connected to the second clock signal line ECB, and the second clock signal is received because the second clock signal terminal CB of the second stage shift register unit is connected to the first clock signal line ECK, and by analogy... As shown in Figure 1E, the first clock signal is received by connecting the first clock signal terminal CK of the X-th (X is an odd number greater than 1) stage shift register unit 105 to the first clock signal ECK, the second clock signal is received by connecting the second clock signal terminal CB of the X-th stage shift register unit 105 to the second clock signal line ECB, the first clock signal is received by connecting the first clock signal terminal CK of the (X+1)-th stage shift register unit to the second clock signal line ECB, and the second clock signal is received by connecting the second clock signal terminal CB of the (X+1)-th stage shift register unit to the first clock signal line ECK. The connection method between each stage shift register unit and the clock signal line may be any other connection method within the art, and the specific method will depend on the actual situation, for example, on the number of signal lines, and the embodiments of this disclosure are not limited thereto. For example, the input terminal EI of the first-stage shift register unit is connected to the trigger signal line ESTV, thereby receiving a trigger signal as an input signal. The input terminal of the second-stage shift register unit 105 is connected to the output terminal EOUT of the preceding shift register unit (i.e., the first-stage shift register unit), and the connection method of the remaining shift register units is similar. In the following, the structure of the Xth-stage shift register unit 105 will be described as an example, but the embodiments of this disclosure are not limited thereto.

[0161] For example, as shown in Figure 1E, the first transistor T1, the third transistor T3, and the twelfth transistor T12 are arranged side by side in the second direction X, the orthographic projection of the second transistor T2 onto the base substrate lies between the orthographic projection of the first transistor T1 onto the base substrate and the orthographic projection of the third transistor T3 onto the base substrate, the fourth transistor T4 and the fifth transistor T5 are integrally formed and located on the imaginary line of the first transistor T1 in the first direction Y, the sixth transistor T6 and the seventh transistor T7 are integrally formed and located on the imaginary line of the fifth transistor T5 in the first direction Y, and the eleventh transistor T11 is located between the third transistor T3 The first capacitor C1 is located on a virtual line in the first direction Y and is arranged in parallel with the fifth transistor T5 in the second direction X. The first capacitor C1 is located on the extension of the eleventh transistor T11 in the first direction Y. The third capacitor C3 is located on the side where the second capacitor C2 moves away from the eleventh transistor T11. The second capacitor C2 is located on the extension of the twelfth transistor T12 in the first direction Y. The eighth transistor T8 is located between the second capacitor C2 and the third capacitor C3. The ninth transistor T9 and the tenth transistor T10 are integrally provided and extend along the first direction Y, and are located between the second capacitor C2 and the second power line VGL.

[0162] For example, as shown in Figure 2B, the orthographic projection of the first shielding layer 21 onto the base substrate 10 of the boundary on one side adjacent to the display area 102 is located on the side away from the display area 102 by the orthographic projection of the second power line VGL onto the base substrate 10. For example, the orthographic projection of the first shielding layer 21 onto the base substrate 10 of the boundary on one side away from the display area 102 overlaps with the orthographic projection of the first power line VSS onto the base substrate, thereby ensuring complete coverage of the transistors of the shift register unit 105 and preventing the transistors from generating leakage current.

[0163] For example, as shown in Figure 2B, the light emission control scanning drive circuit 105 includes multiple output transistors T9 and is configured to output light emission control signals to the light emission control transistors M4 and M5 of the display area 102, one line at a time. For a detailed explanation, please refer to the descriptions in Figures 1C and 1E, and the explanation will be omitted here.

[0164] For example, as shown in Figure 2B, the orthographic projection of the first shielding layer 21 onto the base substrate 10 of one boundary adjacent to the display area 102 is located between the orthographic projection of the multiple output transistors T9 onto the base substrate 10 and the orthographic projection of the second power line VGL onto the base substrate 10, thereby enabling covering of the transistors included in the light emission control scanning drive circuit 105, and thereby preventing the generation of leakage current.

[0165] For example, as shown in Figure 2C, the orthographic projection of the boundary on one side of the second blocking layer 22 that is close to the display area 102 onto the base substrate 10 coincides with the orthographic projection of the gate scanning drive circuit 4 onto the base substrate 10. For example, the orthographic projection of the boundary on one side of the second blocking layer 22 that is away from the display area 102 onto the base substrate 10 coincides with the orthographic projection of the first power line VSS onto the base substrate 10, thereby enabling covering of the transistors included in the light emission control scanning drive circuit 105, and thereby preventing the generation of leakage current.

[0166] For example, the orthographic projection of the second shielding layer 22 onto the base substrate 10 of one boundary adjacent to the display area 102 coincides with the orthographic projection of the output transistor T25 that outputs the gate scanning signal of the gate scanning drive circuit 4 onto the base substrate 10, or, as shown in Figure 2A, the orthographic projection of the second shielding layer 22 onto the base substrate 10 of one boundary adjacent to the display area 102 coincides with the orthographic projection of the gate scanning drive circuit 4 onto the base substrate 10 of one side adjacent to the display area 4, that is, the second shielding layer 22 covers the entire gate scanning drive circuit 5, and the embodiments of this disclosure are not limited thereto. For example, the circuit structure and layout of the gate scanning drive circuit 4 may adopt the configurations of the art, which are not described here.

[0167] For clarity and conciseness, the gate scanning shift register unit 104 is omitted in Figures 2B to 3C, and its specific covering method can be described in Figure 2A.

[0168] The arrangement of transistors in the gate scanning shift register unit 104 is not limited to the positional arrangement relationship shown in Figure 2A, and other types of stacked structures may also be adopted, which will not be explained here. The embodiments of this disclosure are not limited thereto.

[0169] Each light emission control shift register unit 105 corresponds to, for example, the light emission control shift register unit 105 shown in Figures 2B and 2C, which will be described as an example. The structure of the remaining light emission control shift register units is the same and will not be described.

[0170] For example, as shown in Figures 2B and 2C, the first blocking layer 21 includes a plurality of periodically arranged first apertures 210 (as shown in the solid rectangle in Figure 2B), the size of the first apertures C210 being q × r, where q is the dimension along the first direction and r is the dimension along the second direction, and the second blocking layer 22 includes a plurality of periodically arranged second apertures 220 (as shown in the dotted rectangle in Figure 2C), so that the first blocking layer 21 and the second blocking layer 22 each cover at least some of the transistors of the light emission control shift register unit 105. For example, as shown in Figure 2B, the first blocking layer 21 covers transistors T1, T3, T4, and T11 in the light emission control shift register unit 105. For example, as shown in Figure 2C, the second blocking layer 22 covers transistors T2, T3, T6, T11, and T12 in the light emission control shift register unit 105. Since the area below the first barrier layer 21 and the second barrier layer 22 is a flattening layer, gas may be released into the flattening layer through the first and second openings.

[0171] The number and location of transistors covered by the first blocking layer 21 and the second blocking layer 22, respectively, depend on the specific circumstances, and the embodiments of this disclosure do not limit this.

[0172] Furthermore, the periodically arranged multiple first apertures 210 represent that the size and spacing of the multiple first apertures 210 are the same within each light emission control shift register unit 105, and the periodically arranged multiple second apertures 220 represent that the size and spacing of the multiple second apertures 220 are the same within each light emission control shift register unit 105.

[0173] For example, in some cases, the density range of the multiple first apertures 210 is 10% to 50%, and the density range of the multiple second apertures 220 is 10% to 50%. For example, the density of the multiple first apertures 210 and the density of the multiple second apertures 220 may be the same, both may be 30%, for example, 10% or 50%, or 15%, 35%, 45%, etc., and of course the density of the multiple first apertures 210 and the density of the multiple second apertures 220 may be different, and the embodiments of this disclosure do not limit this, as it depends specifically on the actual situation.

[0174] For example, this density refers to the ratio of the area of ​​each opening to the projected area of ​​one shift register unit 105.

[0175] For example, in some examples, the shapes of the multiple first openings 210 and the multiple second openings 220 may be rectangular, for example, square, and of course, they may be circular, rhombic, or other regular or irregular shapes, and the embodiments of the present disclosure are not limited thereto.

[0176] For example, in some examples, the dimensional range of the multiple first openings 210 and the multiple second openings 220 is 10 μm × 10 μm to 20 μm × 20 μm. For example, the dimensions of the multiple first openings 210 and the multiple second openings 220 are the same, for example, all 15 μm × 15 μm, and of course they may be 10 μm × 10 μm, 16 μm × 16 μm, or 20 μm × 20 μm, etc., and the embodiments of this disclosure are not limited thereto. The dimensions of the multiple first openings 210 and the multiple second openings 220 may be different, and specifically depend on the actual situation, and the embodiments of this disclosure are not limited thereto.

[0177] For example, in some other examples, corresponding to each light emission control shift register unit, the first blocking layer 21 includes a plurality of non-periodically arranged first apertures 210 (as shown in the solid rectangle in Figure 3B), and the second blocking layer 22 includes a plurality of non-periodically arranged second apertures 220 (as shown in the dotted rectangle in Figure 3C), as shown in Figures 3B and 3C, so that the first blocking layer 21 and the second blocking layer 22 each cover at least some of the transistors of the light emission control shift register unit 105.

[0178] For example, as shown in Figure 3B, the first blocking layer 21 covers transistors T1, T2, T3, T4, T6, T8, and T12 in the light emission control shift register unit 105. For example, as shown in Figure 3C, the second blocking layer 22 covers transistors T5, T7, T9, T10, and T11 in the light emission control shift register unit 105.

[0179] The number and location of transistors covered by the first blocking layer 21 and the second blocking layer 22, respectively, depend on the specific circumstances, and the embodiments of this disclosure do not limit this.

[0180] Furthermore, the aperiodic arrangement of multiple first apertures 210 represents that the size and spacing of the multiple first apertures 210 change within one light emission control shift register unit 105, and the aperiodic arrangement of multiple second apertures 220 represents that the size and spacing of the multiple second apertures 220 change within one light emission control shift register unit 105.

[0181] For example, in some cases, the density range of the multiple first apertures 210 is 10% to 25%, and the density range of the multiple second apertures 220 is 10% to 25%. For example, the density of the multiple first apertures 210 and the density of the multiple second apertures 220 may be the same, both may be 20%, for example, 10% or 25%, or 15%, etc. Of course, the density of the multiple first apertures 210 and the density of the multiple second apertures 220 may be different, for example, the density of the multiple first apertures 210 may be 10%, and the density of the multiple second apertures 220 may be 20%, and the embodiments of this disclosure are not limited thereto, as it depends on the actual circumstances.

[0182] For example, this density refers to the ratio of the area of ​​each opening to the projected area of ​​one shift register unit 105.

[0183] For example, in some examples, the shapes of the multiple first openings 210 and the multiple second openings 220 may be rectangular, for example, square, and of course, they may be circular, rhombic, or other regular or irregular shapes, and the embodiments of the present disclosure are not limited thereto.

[0184] For example, in this example, the dimensions of the multiple first apertures 210 and the multiple second apertures 220 have a positive correlation with the area of ​​the corresponding transistors. For instance, if one first aperture 210 corresponds to the fifth transistor T5 and the eleventh transistor T11, and another first aperture 210 corresponds to the seventh transistor T7, then the area of ​​the fifth transistor T5 and the eleventh transistor T11 is larger than the area of ​​the seventh transistor T7. Therefore, the dimensions of the first apertures 210 corresponding to the fifth transistor T5 and the eleventh transistor T11 are larger than the dimensions of the first apertures 210 corresponding to the seventh transistor T7. The determination of the dimensions of the second apertures 220 is similar and therefore omitted from explanation.

[0185] For example, as shown in Figures 2A to 3C, the orthographic projections of the periphery of the multiple first apertures 210 and the periphery of the multiple second apertures 220 onto the base substrate 10 do not overlap, and they are arranged alternately. This prevents leakage current from the transistors by achieving shielding for different transistors with different shielding layers.

[0186] Figure 4 is a cross-sectional view of a display substrate according to at least one embodiment of the present disclosure.

[0187] For example, as shown in Figure 4, the display substrate 1 further includes a first planarization layer PLN1 and a second planarization layer PLN2. For example, the first planarization layer PLN1 is located on one side away from the second blocking layer 22 in a direction perpendicular to the base substrate 10, that is, between the first blocking layer 21 and the light emission control scanning drive circuit EMGOA, and the second planarization layer PLN2 is located between the first blocking layer 21 and the second blocking layer 22 in a direction perpendicular to the base substrate 10.

[0188] For example, as shown in Figure 4, the portion 211 of the first blocking layer 21 that separates from the display area 102 includes the first portion 2111 and the second portion 2112 located on one side away from the base substrate 10 where the first planarization layer PLN1 is located, and the portion 221 of the second blocking layer 22 that separates from the display area 102 includes the first portion 2211 and the second portion 2212 located on one side away from the base substrate 10 where the second planarization layer PLN2 is located.

[0189] For example, as shown in Figure 4, the first portion 2111 and the second portion 2112 of the first blocking layer 21 are formed integrally, and the first portion 2211 and the second portion 2212 of the second blocking layer 22 are formed integrally.

[0190] For example, the first power line VSS is located in the third conductive layer, and the first power line VSS is integrally formed with the first portion 2111 of the first blocking layer 21 and the second portion 2211 of the second blocking layer 22, that is, the first power line VSS includes the portion 3401 of the third conductive layer that is separated from the display area 102, the first portion 2111 of the first blocking layer 21, and the first portion 2211 of the second blocking layer 22, and the portion 3401 of the third conductive layer that is separated from the display area 102 and the first portion 2111 of the first blocking layer 21 are in direct contact with the first portion 2211 of the second blocking layer 22, so that the first blocking layer 21, the second blocking layer 22, and the portion 3401 of the third conductive layer 102 are all used to transmit the first voltage as the first power line VSS, thereby increasing the wiring thickness of the first power line VSS and reducing the wiring resistance of the first power line VSS.

[0191] For example, the range of the angle b between the second portion 2112 of the first barrier layer 22 and the third conductive layer is 20° to 30°, and may be, for example, 20°, 30°, or 25°, and the range of the angle a between the second portion 2212 of the second barrier layer 22 and the third conductive layer is 25° to 40°, and may be, for example, 25°, 30°, or 40°, and the embodiments of the present disclosure are not limited thereto.

[0192] For example, the second blocking layer 22 is connected to the first blocking layer 21 by a via hole HL that penetrates the second planarization layer PLN2, and the first blocking layer 21 is connected to the first power line VSS (for example, as shown in Figure 4, the first power line VSS includes a portion 3401 from which the third conductive layer is separated from the display area 102, a first portion 2111 of the first blocking layer 21, and a first portion 2211 of the second blocking layer 22, and the portion 3401 from which the third conductive layer is separated from the display area 102 and the first portion 2111 of the first blocking layer 21 are connected to the second blocking layer 22 The first voltage provided by the first power line VSS (in direct contact with the first portion 2211) can be uniformly applied to the first and second blocking layers 21 and 22, thereby allowing the portion 3401 of the third conductive layer, the first blocking layer 21 and the second blocking layer 22 to all transmit the first voltage, and increasing the thickness of the first power line VSS and reducing the wiring resistance on the first power line VSS is advantageous for accurately transmitting the first voltage on the first power line VSS to the cathode of the light-emitting element LE in the pixel circuit of the display area 102.

[0193] For example, as shown in Figures 4 and 5B, the display substrate further includes a support layer PS. For example, the support layer is located on one side where the second blocking layer 22 is separated from the first blocking layer 21, and the orthographic projection of the support layer PS onto the base substrate 10 coincides with the orthographic projection onto the base substrate 10 of a row of via holes separated from the display area 102 in the multiple via holes. That is, the support layer PS performs its support function by covering only the leftmost row of via holes along the second direction X in the via hole HL shown in Figure 5A. For example, this support layer PS may be provided in the same layer as the pixel definition layer PDL described below, and the material of the support layer PS may be the same as the material of the pixel definition layer PDL, which will be described in detail below and will be omitted here.

[0194] For example, as shown in Figure 5B, the orthographic projection of the pixel definition layer PDL onto the base substrate 10 coincides with the orthographic projection onto the base substrate of the periphery of the remaining via holes, excluding the leftmost row of via holes.

[0195] Figure 5A is a schematic diagram of another display substrate according to at least one embodiment of the present disclosure. Figure 5B is a cross-sectional view of the display substrate in Figure 5A along the A-A' and B-B' directions. Figure 5C is a schematic diagram of a light emission control shift register unit according to at least one embodiment of the present disclosure. Figure 5E is a diagram showing the connection relationship between the light emission control shift register unit and a pixel circuit according to at least one embodiment of the present disclosure.

[0196] For example, as shown in Figure 5A, along a second direction X perpendicular to the first direction Y, the via hole HL is located between a plurality of first openings 210 and a plurality of second openings 220.

[0197] For example, the via hole HL shape may be regular or irregular, such as circular, square, or rhombic, and the embodiments of this disclosure are not limited thereto. For example, the pore diameter range of the via hole HL may be 3 μm to 5 μm, and the specifics depend on the actual situation, and the embodiments of this disclosure are not limited thereto.

[0198] For example, as shown in Figure 1E, the light emission control shift register unit 105 further includes a plurality of connection parts, which include a first connection part E1, a second connection part E2, and a third connection part E3. For example, the first connection part E1 includes (or is assigned to) the first node N1 shown in Figure 1C, the second connection part E2 includes (or is assigned to) the second node N2 shown in Figure 1C, and the third connection part E3 includes (or is assigned to) the output terminal EOUT shown in Figure 1C.

[0199] For example, as shown in Figure 5C, since fixed levels (e.g., the second level on the first power line VSS described above) are applied to the first blocking layer 21 and the second blocking layer 22 respectively, the light emission control shift register unit 105 can further include a third stabilizing capacitor C4, a fourth stabilizing capacitor C5, and a second stabilizing capacitor C6 to improve the ability of the light emission control scanning drive circuit to maintain an active level output.

[0200] For example, as shown in Figure 5C, the first electrode plate of the third stabilizing capacitor C4 is connected to the first node N1, the second electrode plate of the third stabilizing capacitor C4 is connected to the first power line VSS, the first electrode of the fourth stabilizing capacitor C5 is connected to the second node N2, the second electrode of the fourth stabilizing capacitor C5 is connected to the first power line VSS, the first electrode plate of the second stabilizing capacitor C6 is connected to the second node N2, and the second electrode plate of the second stabilizing capacitor C6 is connected to the first power line VSS.

[0201] As shown in Figure 5E, the first power line VSS in the light emission control shift register unit 105 is connected to the cathode of the light-emitting element LE of the pixel circuit in the display area 102. Furthermore, the first power line VSS in the light emission control shift register unit 105 is connected to the cathode of the light-emitting element LE of the pixel circuit in the display area 102 and to the second substrate C242 of the first stabilizer capacitor C24 in the gate scanning shift register unit 104 shown in Figure 5D.

[0202] For example, as shown in Figures 5B and 5C, the third stabilizing capacitor C4 is located between the second blocking layer 22 and the first connection part E1, the fourth stabilizing capacitor C5 is located between the first blocking layer 21 and the second connection part E2, and the second stabilizing capacitor C6 is located between the first blocking layer 21 and the third connection part E3.

[0203] For example, as shown in Figure 5B, in a direction perpendicular to the base substrate 10, the semiconductor layer, the first insulating layer 350, the first conductive layer, the second insulating layer 360, the second conductive layer, the third insulating layer 370, the third conductive layer, and the fourth insulating layer 380 are arranged sequentially between the base substrate 10 and the first barrier layer 21.

[0204] For example, the first blocking layer 21 and the second blocking layer 22 each form stabilizing capacitors between the first conductive layer, the second conductive layer, and the third conductive layer, respectively. In Figure 5B, only the capacitors formed between the first blocking layer 21 and the second blocking layer 22 between the first connection part E1, the second connection part E2, and the third connection part E3 in the third conductive layer (e.g., the second stabilizing capacitor C6, the third stabilizing capacitor, and the fourth stabilizing capacitor) are shown, and the remaining capacitors are not shown, but it should be understood that they exist. The first blocking layer 21 and the multiple second blocking layers 22 jointly form the second electrode plate of the multiple stabilizing capacitors, and the first electrode plate of the multiple stabilizing capacitors is the first conductive layer, the second conductive layer, or the third conductive layer, of which the first electrode plate is an independent and complete pattern located in the peripheral region of the first conductive layer, the second conductive layer, or the third conductive layer, and it can be electrically connected to the signal line located in the display region by via holes.

[0205] For example, a semiconductor layer includes the active layers of multiple transistors. For instance, Figure 5B shows only the active layer A1 of the first transistor T1, the active layer A2 of the second transistor T2, the active layer A3 of the third transistor T3, the active layer A5 of the fifth transistor T5, and the active layer A9 of the ninth transistor T9.

[0206] For example, the first conductive layer includes gate electrodes of multiple transistors (for example, Figure 5B shows only the gate electrode of the first transistor T1, the gate electrode G2 of the second transistor T2, and the gate electrode G5 of the fifth transistor T5) and the first electrodes of multiple capacitors; the second conductive layer includes the second electrodes of multiple capacitors; and the third conductive layer includes multiple connections (for example, Figure 5B shows only the first connection E1, the second connection E2, and the third connection E3), a first clock signal line GCK, a second clock signal line GCB, a second power supply line VGL, and a third power supply line VGH.

[0207] For example, in some cases, the display substrate 1 further includes a fifth insulating layer and a sixth insulating layer.

[0208] For example, the fifth insulating layer is located between the first barrier layer 21 and the third conductive layer in a direction perpendicular to the base substrate 10, and the sixth insulating layer is located between the second barrier layer 22 and the third conductive layer in a direction perpendicular to the base substrate 10. For example, the fifth insulating layer includes a first planarization layer PLN1, and the sixth insulating layer includes the first planarization layer PLN1 and the second planarization layer PLN2. The distance between the first barrier layer 21 and the third conductive layer (e.g., the connection point of the third conductive layer) is different from the distance between the second barrier layer 22 and the third conductive layer (e.g., the connection point of the third conductive layer), so the capacitors formed are also different.

[0209] For example, the thickness range of the first planarization layer PLN1 and the second planarization layer PLN2 is 1.0 μm to 2.0 μm, respectively. For example, the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 is the same, for example, both are 1.5 μm, but they may also be 1.0 μm or 2.0 μm, etc., and therefore the thickness of the fifth insulating layer is approximately half the thickness of the sixth insulating layer.

[0210] Of course, the thicknesses of the first planarization layer PLN1 and the second planarization layer PLN2 do not have to be the same, and the embodiments of this disclosure do not limit this.

[0211] For example, the capacitor formed between the first barrier layer 21 and the third conductive layer (e.g., the fourth stabilizing capacitor C5 and the second stabilizing capacitor C6) is one-tenth the size of the first capacitor C1, the second capacitor C2, or the third capacitor C3. For example, the capacitor formed between the second barrier layer 22 and the third conductive layer (e.g., the third stabilizing capacitor C4) is several-tenths the size of the first capacitor C1, the second capacitor C2, or the third capacitor C3.

[0212] Furthermore, the first blocking layer 21 and the second blocking layer 22 form capacitors with the first conductive layer and the second conductive layer, respectively. In other words, by forming capacitors (not shown) with the first power line VSS at each electrode of each transistor and capacitor, the ability of EM GOA to maintain an active level output can be improved.

[0213] Furthermore, capacitors are also formed between each conductive layer of the gate scanning drive circuit and the second blocking layer 22. The principle is the same as that of EMGOA, and therefore will not be explained here.

[0214] For example, in some embodiments, the gate scanning drive circuit further includes a first scanning capacitor, and the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship. GH1 / EH1 <C24 / C21<GH1 / EH2

[0215] However, GH1 is the duration of the active level of the gate scanning signal output by the gate scanning drive circuit within one frame, EH1 is the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit within one frame, and EH2 is the duration of the inactive level of the light emission control scanning drive circuit within one frame time. By adjusting the ratio of the active or inactive levels of the gate scanning signal and the light emission control signal, the size of the first stabilizing capacitor C24 can be rationally controlled to satisfy the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit, without significantly affecting the capacitance of the gate scanning drive circuit.

[0216] For example, the active level of the gate scanning signal output by the gate scanning drive circuit in one frame is the level that controls the ON state of M2 shown in Figure 1B, the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame is the level that controls the ON state of M4 or M5 shown in Figure 1B, and the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame is the level that controls the OFF state of M4 or M5 shown in Figure 1B.

[0217] for example,

number

[0218] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emission control scanning drive circuit satisfies the following relationship. GH1 / EH1 <C6 / C2<GH1 / EH2

[0219] However, GH1 is the duration of the active level of the gate scanning signal output by the gate scanning drive circuit in one frame, EH1 is the duration of the active level of the light emission control signal output by the light emission control scanning drive circuit in one frame, and EH2 is the duration of the inactive level of the light emission control scanning drive circuit in one frame time. By adjusting the ratio of the active or inactive levels of the gate scanning signal and the light emission control signal, the size of the second stabilizing capacitor C6 can be reasonably controlled to satisfy the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit, without significantly affecting the capacitance of the light emission control scanning drive circuit.

[0220] for example,

number

[0221] For example, in some embodiments, the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship. GOL / GOW <C24 / C21<GH1 / EH2

[0222] However, GOL / GOW is the aspect ratio of the output transistor of the gate scanning drive circuit.

[0223] For example, GOL / GOW may be the aspect ratio of the output control transistor of the gate scanning drive circuit. By further limiting the relationship between the first stabilizing capacitor C24 and the first scanning capacitor, the size of the first stabilizing capacitor C24 can be designed more precisely based on the dimensions of the output transistor or output control transistor, thereby ensuring that the size of the first stabilizing capacitor C24 satisfies the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit without significantly affecting the capacitance of the gate scanning drive circuit.

[0224] For example, C24 / C21 is approximately equal to 1 / 10, GOL / GOW = 1 / 50, and GH1 / EH2 = 1 / 2 or 1 / 3.

[0225] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emission control scanning drive circuit satisfies the following relationship. End of Life / End of Life <C6 / C2<GH1 / EH2

[0226] However, EOL / EOW is the aspect ratio of the output transistor of the light emission control scanning drive circuit. By further limiting the relationship between the second stabilizing capacitor C6 and the second capacitor, the size of the second stabilizing capacitor C6 can be designed more precisely based on the dimensions of the output transistor, thereby ensuring that the size of the second stabilizing capacitor C6 satisfies the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit without significantly affecting the capacitance of the light emission control scanning drive circuit.

[0227] For example, C6 / C2 is approximately equal to 1 / 5, EOW / EOL = 3.5 / 75 = 1 / 21, and GH1 / EH2 = 1 / 2 or 1 / 3.

[0228] For example, in some embodiments, the ratio of the first stabilizing capacitor C24 to the first scanning capacitor C21 satisfies the following relationship. (GSW / GSL) / (GOW / GOL) <C24 / C21<GH1 / EH2

[0229] However, GOW / GOL is the width-to-length ratio of the output transistor of the gate scanning drive circuit, for example, output transistor T25 in Figure 1F, and GSW / GSL is the width-to-length ratio of any one of the switch transistors of the gate scanning drive circuit, for example, switch transistors T21, T22, T23, T26, T27, T28 in Figure 1F. By further limiting the relationship between the first stabilizing capacitor C24 and the first scanning capacitor, the size of the first stabilizing capacitor C24 can be designed more precisely based on the dimensions of the output transistor or output control transistor and the other switch transistors, thereby ensuring that the size of the first stabilizing capacitor C24 satisfies the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit without significantly affecting the capacitance of the gate scanning drive circuit.

[0230] With respect to GateGOA, the width-to-length ratio of the output transistor is in the range of 170-235 / 3.5-4, and the width-to-length ratio of the switch transistor is in the range of 3-40 / 3.5-8. For example, the width-to-length ratio of transistor T21 is, for example, 7.6 / 7 or 7.5 / 8, and transistor T22 is a double-gate transistor, with a width-to-length ratio of, for example, 3 / 3.5 or 3.5 / 3.5. The width-to-length ratio of output transistor T25 is, for example, 175 / 3.5, and the embodiments of this disclosure are not limited thereto. Other transistors may employ appropriate width-to-length ratios in the art, which are not described here.

[0231] For example, (GSW / GSL) / (GOW / GOL)=(7.5 / 3.5) / (175 / 3.5)=1 / 23, and taking the switch transistor with the maximum width-to-length ratio as an example, C24 / C21 is approximately equal to 1 / 10, and GH1 / EH2=1 / 2 or 1 / 3.

[0232] For example, in some embodiments, the ratio of the second stabilizing capacitor C6 to the second capacitor C2 of the light emission control scanning drive circuit satisfies the following relationship. (ESW / ESL) / (EOW / EOL) <C6 / C2<GH1 / EH2

[0233] However, EOW / EOL is the width-to-length ratio of the output transistor of the light emission control scanning drive circuit, and may be, for example, the output transistor T9 or T10 in Figure 1C.

[0234] ESW / ESL is the width-to-length ratio of any one of the switch transistors in the light emission control scanning drive circuit, and may be, for example, switch transistors T1, T2, T3, T4, T5, T6, T7, T8, T11, T12 in Figure 1C. By further limiting the relationship between the second stabilizing capacitor C6 and the second capacitor, the size of the second stabilizing capacitor C6 can be designed more precisely based on the dimensions of the output transistor and the other switch transistors, thereby ensuring that the size of the second stabilizing capacitor C6 satisfies the different driving capabilities of the gate scanning drive circuit and the light emission control scanning drive circuit without significantly affecting the capacitance of the light emission control scanning drive circuit.

[0235] For example, (ESW / ESL) / (EOW / EOL) = (7.5 / 3.2) / (75 / 3.5) = 1 / 9. Taking a switch transistor with the maximum width-to-length ratio as an example, C6 / C2 is approximately equal to 1 / 5, and GH1 / EH2 = 1 / 2 or 1 / 3. For EMGOA, the width-to-length ratio range of the output transistor is 75-80 / 3.5-4, and the width-to-length ratio range of the switch transistor is 3.2-8 / 3.2-11. For example, the width-to-length ratio of transistor T1 is 7.5-7.8 / 4.6-5.5, for example 7.5 / 4.6 or 7.5 / 5.5. Transistor T2 is a double-gate transistor, and its width-to-length ratio is 3.6-4 / 8.2-11, for example 3.7 / 8.2 or 3.7 / 10. Transistor T5 has a width-to-length ratio of 7-8 / 4.7-5, for example 7.5 / 4.7. Output transistor T9 has a width-to-length ratio of, for example 75 / 3.5. The specifics depend on the actual situation, and the embodiments of this disclosure are not limited thereto. Other transistors may employ appropriate width-to-length ratios in the art, which are not described here.

[0236] For example, GOW / GOL may be the width-to-length ratio of the output control transistor T24 of the gate scanning drive circuit.

[0237] In the above formula, the second capacitor C2 may be replaced with the first capacitor C1 or the third capacitor C3, and the first scanning capacitor C21 may be replaced with the second scanning capacitor C22; the embodiments of this disclosure are not limited thereto.

[0238] In the embodiments of this disclosure, by controlling the sizes of the first stabilizing capacitor C24 and the second stabilizing capacitor C6, the first stabilizing capacitor C24 and the second stabilizing capacitor C6 have the driving capability to secure the gate scanning drive circuit and the light emission control scanning drive circuit, and these coupling capacitors do not significantly affect the original storage capacitor.

[0239] Furthermore, since the first blocking layer 21 does not cover the shift register unit in the gate scanning drive circuit, there is virtually no capacitor formed between the first blocking layer 21 and the gate scanning drive circuit. Of course, this depends specifically on the actual situation, and the embodiments of this disclosure are not limited thereto.

[0240] For example, one side of the second blocking layer 22 that separates from the first blocking layer 21 further includes a pixel definition layer PDL for defining pixels in the display area 102.

[0241] For example, in some cases, as shown in Figure 4, the first planarization layer PLN1 and the second planarization layer PLN2 further include a groove 30 provided between the light emission control scanning drive circuit 5 and the gate scanning drive circuit 4.

[0242] For example, the first planarization layer PLN1 includes a first portion located on one side of the groove 30 away from the display area 102 and covering the light emission control scanning drive circuit 5, and a second portion covering the gate scanning drive circuit 4. For example, the second planarization layer PLN2 includes a first portion located on one side of the groove 30 away from the display area 102 and covering the light emission control scanning drive circuit 5, and a second portion covering the gate scanning drive circuit 4.

[0243] For example, the orthographic projection of the boundary on one side of the first shielding layer 21 adjacent to the display area 102 onto the base substrate 10 falls within the orthographic projection of the first portion of the second planarization layer PLN2 onto the base substrate 10, and the orthographic projection of the first portion of the second planarization layer PLN2 onto the base substrate 10 falls within the orthographic projection of the first portion of the first planarization layer PLN1 onto the base substrate. As a result, the second planarization layer PLN2 can cover the first shielding layer 21, and it is ensured that the boundary of the second planarization layer PLN2 and the boundary of the first planarization layer PLN1 maintain a certain distance from each other. This ensures that the gradient angle between the second planarization layer PLN2 and the groove 30 of the first planarization layer PLN1 is not too large, thus ensuring that the second shielding layer 22 is less likely to be damaged at the groove 30.

[0244] For example, the second blocking layer 22 extends from the region corresponding to the light emission control scanning drive circuit 5 to the region corresponding to the gate scanning drive circuit 4 and covers the groove 30.

[0245] For example, the width B along the second direction X of the orthographic projection of the second blocking layer 22 covering the groove 30 on the base substrate 10 is expressed by the following formula. B = A + k1×P1 + k2×Q1 + k3×P2 + k4×Q2 P1 = d1×tan(c1) P2 = d2×tan(c2)

[0246] However, A represents the width of the orthographic projection of the groove 30 on the base substrate 10 along the second direction X, P1 represents the width of the orthographic projection of the first gradient portion 231 of the second blocking layer 22 on the base substrate 10, Q1 represents the width of the orthographic projection of the first platform 230 of the second blocking layer 22 on the base substrate 10, P2 represents the width of the orthographic projection of the second gradient portion of the second blocking layer 22 on the base substrate 10, Q2 represents the width of the orthographic projection of the second platform 228 of the second blocking layer 22 on the base substrate 10, d1 represents the thickness of the first planarization layer PLN1, d2 represents the thickness of the second planarization layer PLN2, c1 represents the gradient angle of the first planarization layer PLN1, c2 represents the gradient angle of the second planarization layer PLN2, k1, k2, k3, k4 are coefficients, provided that 1 < k1 ≤ 2, 1 < k2 ≤ 2, 1 < k3 ≤ 2, 1 < k4 ≤ 2. That is, by adjusting the thickness or gradient angle of the first planarization layer PLN1 or by adjusting the thickness or gradient angle of the second planarization layer PLN2, the width along the second direction X of the orthographic projection of the second blocking layer 22 covering the groove 30 on the base substrate 10 can be adjusted, thereby ensuring that the second blocking layer 22 covering the groove 30 has relatively high continuity and is less likely to cause disconnection defects. Of course, k1, k2, k3, and k4 do not have to be equal, and their specific numerical values depend on the actual situation, and the embodiments of the present disclosure do not limit this.

[0247] For example, A is 11-12 μm, for example A = 11.3 μm, 11.5 μm, etc., d1 is 1.5-1.8 μm, d2 is 1.5-1.8 μm, for example d1 and d2 are both 1.5 μm, the angular range of c1 is 20°-30°, the angular range of c2 is 20°-30°, for example c1 is 25°, c2 is 28°, the range of Q1 is 3-5 μm, for example Q1 = 4 μm, and the range of Q2 is 1-4 μm, for example Q2 = 2 μm.

[0248] For example, based on the parameter range described above, the range of B is found to be 30 to 50 μm, and for instance, B = 35.8 μm.

[0249] For example, at a position where the first barrier layer 21 is close to the groove 30, the angle between the first barrier layer 21 and the second barrier layer 22 is 25° to 40°. For example, the angle between the first barrier layer 21 and the second barrier layer 22 may be 25°, 40°, 30°, etc., and the embodiments of this disclosure are not limited thereto.

[0250] Figure 6 is a cross-sectional view of another display substrate according to at least one embodiment of the present disclosure. As shown in Figure 6, the display substrate 1 further includes a pixel rendering layer PDL, a cathode layer 23, a first packaging layer TFE-1, a second packaging layer TFE-2, and a third packaging layer TFE-3.

[0251] For example, the pixel definition layer PDL is located in the display area 102 and defines multiple pixel units by including multiple apertures, and the second shielding layer 22 is located on one side away from the base substrate 10, and the orthographic projection of the boundary where the pixel definition layer PDL is close to the peripheral area onto the base substrate coincides with the boundary where the gate scanning drive circuit 4 is close to the display area 102. For example, the pixel definition layer PDL can be turned off by extending from the display area 102 to the output transistor location of the gate scanning drive circuit. For example, the output transistor of the gate scanning drive circuit is configured to output a gate scanning signal.

[0252] The cathode layer 23 is located on one side away from the pixel definition layer PDL (Photon Rendering Layer) 10. For example, the portion of the cathode layer 23 away from the display area 102 contacts the first portion 2211 of the second shielding layer 22, and the portion of the cathode layer 23 other than the portion in contact with the first portion 2211 of the second shielding layer 22 contacts the portion of the second shielding layer 22 other than the second opening. This allows the first voltage on the first power line VSS to be transmitted to the cathode layer 23, thereby driving the emission of light from the light-emitting element LE in the display area 102.

[0253] For example, the anode layer of the light-emitting element LE is provided in the same layer as the second blocking layer 22, and the anode layer of the light-emitting element LE does not overlap with the first blocking layer 21 and the second blocking layer 22.

[0254] For example, the first packaging layer TFE-1 is located on one side away from the base substrate 10 where the cathode layer 23 is located, the second packaging layer TFE-2 is located on the same side as the first packaging layer TFE-1 where it is located, and the third packaging layer TFE-3 is located on the same side as the second packaging layer TFE-2 where it is located.

[0255] For example, the dimensions of the gate scanning drive circuit 4 in the second direction X are approximately 250 μm, the dimensions of the light emission control scanning drive circuit 5 in the second direction X are approximately 100 μm, the third packaging layer TFE-3 completely covers the first shielding layer 21, and the distance range between the boundary where the first shielding layer 21 leaves the display area 102 and the boundary where the third packaging layer TFE-3 leaves the display area 102 is 95 μm to 105 μm, for example, approximately 95 μm, 100 μm, or 105 μm, and the embodiments of this disclosure are not limited thereto.

[0256] For example, the display substrate 1 further includes a touch structure 200, which is, for example, a Flexible Multi-Layer On-Cell (FMLOC) structure, and the touch function of the display panel is realized by positioning the third packaging layer TFE-3 on one side away from the base substrate 10.

[0257] For example, FMLOC includes a touch driving electrode Tx and a touch sensing electrode Rx, and multiple touch wirings TL connected to them, respectively. For example, the touch driving electrode Tx and the touch sensing electrode Rx are located in the 102 display area to realize the touch function of the display panel, and their specific structure and specific operating principle may be found in the design of this field and will not be explained here.

[0258] For example, as shown in Figure 6, the orthographic projection of the first blocking layer 21 and the second blocking layer 22 onto the base substrate 10 is such that the touch wiring TL overlaps, at least partially, with the orthographic projection onto the base substrate 10.

[0259] For example, as shown in Figure 6, the orthographic projection of at least a portion of the touch wiring TL onto the base substrate 10 falls into the grooves 30 of the first planarization layer PLN1 and the second planarization layer PLN2.

[0260] For example, in some cases, as shown in Figures 4 and 6, the first shielding layer 21 further includes a third portion 2213, and the orthographic projection of this third portion 2113 onto the base substrate 10 overlaps with and contacts the orthographic projection of the signal lines of the gate scanning drive circuit 4 (e.g., third signal line GCK and fourth signal line GCB) onto the base substrate 10, thereby increasing the signal wiring thickness and reducing the wiring resistance on the signal lines. For example, the signal lines of the gate scanning drive circuit 4 are configured to provide a clock signal to the gate scanning drive circuit 4. For example, the third signal line GCK and the fourth signal line GCB are configured to control the shift output of the gate scanning drive circuit 4 by providing the gate scanning drive circuit 4 with a third clock signal and a fourth clock signal, respectively, and the specific operating process may be found in the introduction to this art and will not be described here.

[0261] It should be explained that, for example, the semiconductor layer material may include oxide semiconductors, organic semiconductors, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)), and polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of this disclosure are not limited thereto. It should be explained that the source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited thereto.

[0262] For example, the material of the third conductive layer may include titanium, titanium alloys, aluminum, aluminum alloys, copper, copper alloys, or any other suitable composite material, and the embodiments of this disclosure are not limited thereto. For example, the materials of the first conductive layer and the second conductive layer may be the same as the material of the third conductive layer, and this will not be explained further here.

[0263] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include, for example, inorganic insulating materials such as SiNx, SiOx, and SiNxOy, or organic insulating materials such as organic resins, or other suitable materials, and the embodiments of this disclosure are not limited thereto.

[0264] For example, the anode layer of this light-emitting element LE may be made from a material containing a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has a relatively high light transmittance. The material of the anode layer of this light-emitting element LE is a metal, and for example, the metal may be made from a material such as magnesium, magnesium alloy, aluminum, or aluminum alloy.

[0265] For example, the material of the first blocking layer 21 and the second blocking layer 22 is a metal, and the metal may be made of materials such as magnesium, magnesium alloy, aluminum, or aluminum alloy, thereby achieving blocking to the transistor, and the embodiments of this disclosure are not limited thereto.

[0266] For example, the first planarization layer PLN1 and the second planarization layer PLN2 include an organic material, such as a polymer resin material, such as polyimide (PI), polymethyl methacrylate or polystyrene (PS), and aromatic, propylene-based polymers, phthalimide-based polymers, aryl ether-based polymers, amino-based polymers, fluorine-based polymers, p-xylylene-based polymers, vinyl alcohol-based polymers, and the like.

[0267] For example, the first packaging layer TFE-1 to the third packaging layer TFE-3 may include an inorganic material or an organic material. For example, the inorganic material may include inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. For example, the organic material may be an organic material such as a polymer material containing a desiccant or a polymer material capable of blocking water vapor. These organic materials can perform a planarization treatment on the surface of the display substrate and can also relieve the stress between the first inorganic packaging layer and the second inorganic packaging layer. They may further contain a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that intrude into the interior.

[0268] At least one embodiment of the present disclosure further provides a light emission control scanning drive circuit. FIG. 7 is a schematic diagram of a light emission control scanning drive circuit according to at least one embodiment of the present disclosure. As shown in FIG. 7, it includes a plurality of light emission control shift register units 105 connected in cascade. For example, the circuit structure of this light emission control shift register unit 105 can be realized as the circuit structure shown in FIG. 5C.

[0269] For example, for each light emission control shift register unit 105, the light emission control shift register unit 105 includes a plurality of transistors, a plurality of capacitors, a plurality of connection parts, a first blocking layer 21, and a second blocking layer 22.

[0270] For example, the first blocking layer 21 is located between the plurality of connection parts and the second blocking layer 22.

[0271] For example, the plurality of transistors includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 (also referred to as an output transistor), a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The plurality of capacitors includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a third stabilizing capacitor C4, a fourth stabilizing capacitor C5, and a second stabilizing capacitor C6.

[0272] For example, as shown in FIG. 5C, the gate electrode of the first transistor T1 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line ECK), so that the first transistor T1 receives the first clock signal. The second electrode of the first transistor T1 is connected to the input terminal EI, and the first electrode of the first transistor T1 is connected to the first node N1.

[0273] The gate electrode of the second transistor T2 is connected to the first node N1. The first electrode of the second transistor T2 is connected to the second node N2. The second electrode of the second transistor T2 is connected to the first clock signal terminal CK, so that the second transistor T2 receives the first clock signal.

[0274] The gate of the third transistor T3 is connected to the first clock signal terminal CK, so that the third transistor T3 receives the first clock signal. The first electrode of the third transistor T3 is connected to the second node N2. The second electrode of the third transistor T3 is connected to the second power supply line VGL, so that the third transistor T3 receives the second voltage.

[0275] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (for example, the second clock signal terminal CB is connected to the second clock signal line ECB), thereby receiving the second clock signal. The first electrode of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.

[0276] The gate of the fifth transistor T5 is connected to the second node N2, and the first electrode of the fifth transistor T5 is connected to the third power line VGH, thereby receiving the third voltage.

[0277] The gate of the sixth transistor T6 is connected to the second electrode of the eleventh transistor T11, and the first electrode of the sixth transistor T6 is connected to the second clock signal terminal CB, thereby receiving the second clock signal, and the second electrode of the sixth transistor T6 is connected to the third node N3.

[0278] The first electrode of the first capacitor C1 is connected to the second electrode of the eleventh transistor T11, and the second electrode of the first capacitor C2 is connected to the third node N3.

[0279] The gate of the seventh transistor T7 is connected to the second clock signal terminal CB, thereby receiving the second clock signal. The first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0280] The gate of the 8th transistor T8 is connected to the 1st node N1, the 1st electrode of the 8th transistor T8 is connected to the 4th node N4, and the 2nd electrode of the 8th transistor T8 is connected to the 3rd power line VGH, thereby receiving the 3rd voltage.

[0281] The gate of the ninth transistor T9 is connected to the fourth node N4, the first electrode of the ninth transistor T9 is connected to the third power line VGH and receives the third voltage, and the second electrode of the ninth transistor T9 is connected to the output terminal EOUT.

[0282] The first electrode of the third capacitor C3 is connected to the fourth node N4, and the second electrode of the third capacitor C3 is connected to the third power line VGH, thereby receiving the third voltage.

[0283] The gate of the 10th transistor T10 is connected to the second electrode of the 12th transistor T12, and the first electrode of the 10th transistor T10 is connected to the second power line VGL, thereby receiving the second voltage, and the second electrode of the 10th transistor T10 is connected to the output terminal EOUT.

[0284] The first electrode of the second capacitor C2 is connected to the second electrode of the 12th transistor T12, and the second electrode of the second capacitor C2 is connected to the second clock signal terminal CB, thereby receiving the second clock signal.

[0285] The gate of the 11th transistor T11 is connected to the second power line VGL, thereby receiving the second voltage, and the first electrode of the 11th transistor T11 is connected to the second node N2.

[0286] The gate of the 12th transistor T12 is connected to the second power line VGL, thereby receiving the second voltage, and the first electrode of the 12th transistor T12 is connected to the first node N1.

[0287] For example, as shown in Figure 5C, the first electrode plate of the third stabilizing capacitor C4 is connected to the first node N1, the second electrode plate of the third stabilizing capacitor C4 is connected to the first power line VSS, the first electrode of the fourth stabilizing capacitor C5 is connected to the second node N2, the second electrode of the fourth stabilizing capacitor C5 is connected to the first power line VSS, the first electrode plate of the second stabilizing capacitor C6 is connected to the second node N2, and the second electrode plate of the second stabilizing capacitor C6 is connected to the first power line VSS.

[0288] For example, these multiple connections include a first connection E1, a second connection E2, and a third connection E3. For example, the first connection E1 includes (or is assigned to) the first node N1 shown in Figure 1C, the second connection E2 includes (or is assigned to) the second node N2 shown in Figure 1C, and the third connection E3 includes (or is assigned to) the output terminal EOUT shown in Figure 1C.

[0289] For example, in the embodiments of this disclosure, the first blocking layer 21 covers at least one transistor in the light emission control shift register unit 105, and the second blocking layer 22 covers at least one transistor among a plurality of transistors in the light emission control shift register unit 105 other than the aforementioned at least one transistor.

[0290] For a detailed explanation of the above-mentioned light emission control scanning drive circuit, please refer to the descriptions in Figures 1A to 6, and the explanation will be omitted here.

[0291] The technical effects of the light emission control scanning drive circuit according to the above embodiment may be explained by referring to the technical effects of the display substrate 1 according to the embodiment of this disclosure, and will not be explained here.

[0292] At least one embodiment of the present disclosure further provides a display device. Figure 8 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 8, the display device 2 includes a display substrate 1 according to any one embodiment of the present disclosure, for example, the display substrate 1 shown in Figure 2A.

[0293] It should be noted that the display device 2 may be any product or component having an arbitrary display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc. The display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., and the embodiments of the present disclosure do not limit this.

[0294] It should be noted that, for the sake of clear and concise illustration, the embodiments of the present disclosure do not provide all the constituent units of this display device. In order to realize the basic functions of this display device, those skilled in the art can provide and provide other structures not shown specifically according to specific requirements, and the embodiments of the present disclosure do not limit this.

[0295] Regarding the technical effects of the display device 2 according to the above embodiment, reference may be made to the technical effects of the display substrate 1 according to the embodiments of the present disclosure, and the description is omitted here.

[0296] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. FIG. 9 is a flowchart of a method for manufacturing a display substrate according to at least one embodiment of the present disclosure. For example, this manufacturing method can be used to manufacture a display substrate according to any one of the embodiments of the present disclosure. For example, it can be used to manufacture the display substrate 1 shown in FIG. 2A.

[0297] As shown in FIG. 9, the method for manufacturing the display substrate includes steps S110 to S120. Step S110: Provide a base substrate.​​​​​For example, the first blocking layer 21 covers at least one transistor in the light emission control scanning drive circuit 105, and the second blocking layer 22 covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control scanning drive circuit 105.

[0299] It should be noted that in some embodiments of this disclosure, the flow of the method for manufacturing the display board may include more or fewer operations, which may be performed sequentially or in parallel. The flow of the manufacturing method described above includes several operations that appear in a specific order, but it should be clearly understood that the order of the operations is not restricted. The manufacturing method described above may be performed once or multiple times according to predetermined conditions.

[0300] The technical effects of the method for manufacturing the display board according to the above embodiment may be discussed by referring to the technical effects of the display board according to the embodiment of this disclosure, and will not be explained here.

[0301] The following points need to be explained. (1) The accompanying drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures may refer to conventional designs. (2) If there is no conflict, the embodiments and features of the embodiments of this disclosure can be combined with each other to obtain new embodiments.

[0302] The foregoing describes only exemplary embodiments of the Disclosure and is not intended to limit the scope of protection of the Disclosure, which is determined by the appended claims. [Explanation of Symbols]

[0303] 1 Display board 2 Display device 4 gate scanning drive circuit 5. Light emission control scanning drive circuit 10 base boards 21. First barrier layer 22 Second Barrier Layer 23 Cathode layer 101 Display Panel 102 Display area 103 pixel unit 104 Scanning Drive Shift Register Unit 105 Light Emission Control Shift Register Unit 106 Peripheral area

Claims

1. A display board, A base substrate including a display area and a peripheral area located on at least one side of the display area, The base substrate includes a gate scanning drive circuit, a light emission control scanning drive circuit, and a first power line, which are provided in the peripheral region of the base substrate and are arranged sequentially along one side away from the display area. The gate scanning drive circuit is configured to output a gate scanning signal, the output terminal of the light emission control scanning drive circuit is electrically connected to at least one light emission control transistor in the display area, the light emission control scanning drive circuit is configured to output a light emission control signal, the light emission control transistor is configured to control the light emission of the light-emitting element in response to the light emission control signal, and the first power line is electrically connected to the cathode of at least one light-emitting element in the display area. The gate scanning drive circuit includes a first stabilizing capacitor, the first electrode plate of the first stabilizing capacitor is electrically connected to the output terminal of the gate scanning drive circuit, and the second electrode plate of the first stabilizing capacitor is electrically connected to the first power line. The light emission control scanning drive circuit includes a second stabilizer capacitor, the first electrode plate of the second stabilizer capacitor is electrically connected to the output terminal of the light emission control scanning drive circuit, the second electrode plate of the second stabilizer capacitor is electrically connected to the first power line, and the second electrode plate of the second stabilizer capacitor includes a first portion and a second portion, and has a first organic insulating layer between the first portion of the second electrode plate of the second stabilizer capacitor and the second portion of the second electrode plate of the second stabilizer capacitor, in a direction perpendicular to the base substrate, the display substrate.

2. The light emission control scanning drive circuit further includes a third stabilizing capacitor, The first electrode plate of the third stabilizing capacitor is connected to a first node, the second electrode plate of the third stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the third stabilizing capacitor includes a first portion and a second portion, and has a second organic insulating layer between the first portion of the second electrode plate of the third stabilizing capacitor and the second portion of the second electrode plate of the third stabilizing capacitor, in a direction perpendicular to the base substrate. The display board according to claim 1, wherein the light emission control scanning drive circuit includes a plurality of cascaded light emission control shift register units, each of which includes a plurality of transistors, the plurality of transistors including a first transistor, a second transistor, and a twelfth transistor, and the first electrode of the first transistor, the gate of the second transistor, and the first electrode of the twelfth transistor are connected to form the first node.

3. The light emission control shift register unit includes a plurality of capacitors, The first transistor receives a first clock signal by having its gate connected to a first clock signal line, has a first electrode connected to the first node, and a second electrode connected to the input terminal. The second transistor receives the first clock signal by having its gate connected to the first node, its first electrode connected to the second node, and its second electrode connected to the first clock signal line. The aforementioned multiple transistors are, A third transistor whose gate is connected to the first clock signal line, which receives the first clock signal, and whose first electrode is connected to the second node, and whose second electrode is connected to the second power line, which receives the second voltage, The sixth transistor, whose first electrode is connected to the second clock signal line, receives the second clock signal, and whose second electrode is connected to the third node, A seventh transistor, whose gate is connected to the second clock signal line, receives the second clock signal, whose first electrode is connected to the third node, and whose second electrode is connected to the fourth node, A ninth transistor whose gate is connected to the fourth node, whose first electrode is connected to the third power line and receives a third voltage, and whose second electrode is connected to the output terminal, A 10th transistor, whose first electrode is connected to the second power line, receives the second voltage, and whose second electrode is connected to the output terminal, The 11th transistor further includes an 11th transistor, wherein the gate of the 6th transistor is connected to the second electrode of the 11th transistor, the first electrode of the first capacitor is connected to the second electrode of the 11th transistor, the gate of the 11th transistor is connected to the second power line so as to receive the second voltage, and the first electrode of the 11th transistor is connected to the second node, The gate of the 10th transistor is connected to the second electrode of the 12th transistor, the first electrode of the second capacitor is connected to the second electrode of the 12th transistor, the gate of the 12th transistor receives the second voltage by being connected to the second power line, and the first electrode of the 12th transistor is connected to the first node. The aforementioned plurality of capacitors The first capacitor, to which the second electrode is connected at the third node, A third capacitor is included, which receives the third voltage by having a first electrode connected to the fourth node and a second electrode connected to the third power line, The display board according to claim 2.

4. The light emission control scanning drive circuit further includes a fourth stabilizing capacitor, The display substrate according to claim 3, wherein the first electrode plate of the fourth stabilizing capacitor is connected to the second node, the second electrode plate of the fourth stabilizing capacitor is electrically connected to the first power line, and the second electrode plate of the fourth stabilizing capacitor includes a first portion and a second portion, and has a third organic insulating layer between the first portion of the second electrode plate of the fourth stabilizing capacitor and the second portion of the second electrode plate of the fourth stabilizing capacitor, in a direction perpendicular to the base substrate.

5. The light emission control scanning drive circuit includes a plurality of transistors, the first portion of the second electrode plate of the second stabilizer capacitor is located in the first blocking layer, the second portion of the second electrode plate of the second stabilizer capacitor is located in the second blocking layer, and the first blocking layer and the second blocking layer are sequentially provided on one side of the light emission control scanning drive circuit away from the base substrate. The first blocking layer covers at least one transistor in the light emission control scanning drive circuit, and the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control scanning drive circuit. The display substrate according to any one of claims 1 to 3, wherein the second blocking layer is further provided on one side of the gate scanning drive circuit away from the base substrate, and the second blocking layer covers at least one transistor in the gate scanning drive circuit.

6. The light emission control scanning drive circuit includes a plurality of transistors, wherein the first portion of the second electrode plate of the third stabilizer capacitor is located in the first blocking layer, and the second portion of the second electrode plate of the third stabilizer capacitor is located in the second blocking layer. The first portion of the second electrode plate of the fourth stabilization capacitor is located in the first blocking layer, and the second portion of the second electrode plate of the fourth stabilization capacitor is located in the second blocking layer, The first blocking layer and the second blocking layer are sequentially provided on one side of the light emission control scanning drive circuit that is away from the base substrate, The first blocking layer covers at least one transistor in the light emission control scanning drive circuit, and the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control scanning drive circuit. The display substrate according to claim 4, wherein the second blocking layer is further provided on one side of the gate scanning drive circuit away from the base substrate, and the second blocking layer covers at least one transistor in the gate scanning drive circuit.

7. The first blocking layer and the second blocking layer are connected to the first power line, thereby receiving the first voltage. The light emission control scanning drive circuit includes a plurality of cascaded light emission control shift register units, and each light emission control shift register unit includes a plurality of transistors. The display substrate according to claim 5, wherein, for each of the light-emitting control shift register units, the first blocking layer covers at least one transistor in the light-emitting control shift register unit, and the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light-emitting control shift register unit.

8. The light emission control scanning drive circuit further includes a second power line or a third power line extending along the first direction, The display board further includes a first power line extending along the first direction, The orthographic projection of the second power line or the third power line onto the base substrate is such that the transistor included in the light emission control scanning drive circuit is located between the orthographic projection of the base substrate and the orthographic projection of the gate scanning drive circuit onto the base substrate. The orthographic projection of the first power line onto the base substrate is located on one side away from the display area, where the orthographic projection of the light emission control scanning drive circuit onto the base substrate is located. The second power line, the third power line, and the first power line are located on one side of the first shielding layer away from the second shielding layer, along a direction perpendicular to the base substrate. The boundary on one side of the orthographic projection of the first shielding layer onto the light emission control scanning drive circuit that is close to the display area is located on the side where the orthographic projection of the second power line or the third power line onto the base substrate is away from the display area. The orthographic projection onto the base substrate of the boundary on one side where the first shielding layer separates from the display area is such that the first power line overlaps with the orthographic projection onto the base substrate. The light emission control scanning drive circuit includes a plurality of output transistors and is configured to output the light emission control signal to the light emission control transistors of the display area one row at a time. The display board according to claim 5, wherein the orthographic projection of the first barrier layer onto the base substrate of one boundary adjacent to the display area is such that the plurality of output transistors are located between the orthographic projection onto the base substrate and the second power line or the third power line is located between the orthographic projection onto the base substrate.

9. The orthographic projection of the boundary on one side of the second barrier layer adjacent to the display area onto the base substrate coincides with the orthographic projection of the gate scanning drive circuit onto the base substrate. The orthographic projection onto the base substrate of the boundary on one side where the second shielding layer separates from the display area is such that the first power line overlaps with the orthographic projection onto the base substrate. The display substrate according to claim 8, wherein the orthographic projection onto the base substrate of the boundary on one side of the second barrier layer adjacent to the display area coincides with the orthographic projection onto the base substrate of the output transistor that outputs the gate scanning signal in the gate scanning drive circuit, or the orthographic projection onto the base substrate of the boundary on one side of the second barrier layer adjacent to the display area coincides with the orthographic projection onto the base substrate of the gate scanning drive circuit adjacent to the display area.

10. Corresponding to each of the light emission control shift register units, the first blocking layer includes a plurality of periodically arranged first apertures, and the second blocking layer includes a plurality of periodically arranged second apertures, so that the first blocking layer and the second blocking layer each cover at least some of the transistors of the light emission control shift register unit. The density range of the first opening is 10% to 50%, and the density range of the second opening is 10% to 50%. The shapes of the first and second openings are rectangular, and the dimensional range of the first and second openings is 10 μm × 10 μm to 20 μm × 20 μm. The orthographic projections of the periphery of the first opening and the periphery of the second opening onto the base substrate do not overlap. The display substrate according to claim 7, wherein orthographic projections of the periphery of the first opening onto the base substrate and orthographic projections of the periphery of the second opening onto the base substrate are alternately provided.

11. Corresponding to each of the light emission control shift register units, the first blocking layer includes a plurality of first apertures arranged aperiodically, and the second blocking layer includes a plurality of second apertures arranged aperiodicly, so that the first blocking layer and the second blocking layer each cover at least some of the transistors of the light emission control shift register unit. The density range of the first opening is 10% to 25%, and the density range of the second opening is 10% to 25%. The dimensions of the first aperture and the dimensions of the second aperture are positively correlated with the area of ​​the corresponding transistor. The orthographic projections of the periphery of the first opening and the periphery of the second opening onto the base substrate do not overlap. The display substrate according to claim 7, wherein orthographic projections of the periphery of the first opening onto the base substrate and orthographic projections of the periphery of the second opening onto the base substrate are alternately provided.

12. It further includes a first flattening layer and a second flattening layer, The first planarization layer is located on one side of the first barrier layer away from the second barrier layer, along a direction perpendicular to the base substrate, and the second planarization layer is located between the first barrier layer and the second barrier layer, along a direction perpendicular to the base substrate. The material of the aforementioned second planarization layer is an organic insulating material. The second barrier layer is connected to the first barrier layer by a plurality of via holes that penetrate the second flattening layer. The light emission control scanning drive circuit includes a plurality of cascaded light emission control shift register units, and each light emission control shift register unit includes a plurality of transistors. For each of the light emission control shift register units, the first blocking layer covers at least one transistor in the light emission control shift register unit, and the second blocking layer covers at least one transistor among a plurality of transistors other than the at least one transistor in the light emission control shift register unit. Corresponding to each of the light emission control shift register units, the first blocking layer includes a plurality of periodically arranged first apertures, and the second blocking layer includes a plurality of periodically arranged second apertures, so that the first blocking layer and the second blocking layer each cover at least some of the transistors of the light emission control shift register unit. Along a second direction perpendicular to the first direction, the plurality of via holes are located between the first opening and the second opening. The display substrate according to claim 8 or 9, wherein the shape of the via hole is circular or rectangular, and the hole diameter range of the via hole is 3 μm to 5 μm.

13. The display substrate according to claim 12, further comprising a support layer, wherein the support layer is located on one side of the second barrier layer away from the first barrier layer, and the orthographic projection of the support layer onto the base substrate coincides with the orthographic projection onto the base substrate of the periphery of a row of via holes away from the display area in the plurality of via holes.

14. The semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, and a fourth insulating layer are arranged sequentially between the base substrate and the first insulating layer along a direction perpendicular to the base substrate. The semiconductor layer includes the active layers of the plurality of transistors, the first conductive layer includes the gates of the plurality of transistors and the first electrodes of the plurality of capacitors, the second conductive layer includes the second electrodes of the plurality of capacitors, and the third conductive layer includes a first clock signal line, a second clock signal line, a second power supply line, and a third power supply line. The first blocking layer and the second blocking layer each form a plurality of stabilizing capacitors between themselves and the third conductive layer. The first blocking layer and the second blocking layer are each the second electrode plates of the plurality of stabilizing capacitors, and the first electrode plates of the plurality of stabilizing capacitors are the third conductive layer. The portion of the first shielding layer that is separated from the display area includes a first portion and a second portion located on one side of the first planarization layer that is separated from the base substrate, and the portion of the second shielding layer that is separated from the display area includes a first portion and a second portion located on one side of the second planarization layer that is separated from the base substrate, The first power line includes a portion of the third conductive layer that is separated from the display area, a first portion of the first shielding layer, and a first portion of the second shielding layer, and the portion of the third conductive layer that is separated from the display area and the first portion of the first shielding layer are in direct contact with the first portion of the second shielding layer. The display substrate according to claim 12 or 13, wherein the angle range between the second portion of the first barrier layer and the third conductive layer is 20° to 30°, and the angle range between the second portion of the second barrier layer and the third conductive layer is 25° to 40°.

15. The first planarization layer and the second planarization layer further include a groove provided between the light emission control scanning drive circuit and the gate scanning drive circuit, The first planarization layer includes a first portion located on one side of the groove away from the display area and covering the light emission control scanning drive circuit, and a second portion covering the gate scanning drive circuit. The second planarization layer includes a first portion located on one side of the groove away from the display area and covering the light emission control scanning drive circuit, and a second portion covering the gate scanning drive circuit. The orthographic projection of the boundary on one side of the first barrier layer adjacent to the display area onto the base substrate falls within the orthographic projection of the first portion of the second planarization layer onto the base substrate. The orthographic projection of the first portion of the second planarization layer onto the base substrate falls within the orthographic projection of the first portion of the first planarization layer onto the base substrate. The second blocking layer extends from the region corresponding to the light emission control scanning drive circuit to the region corresponding to the gate scanning drive circuit and covers the groove. The width B of the second barrier layer covering the groove along the second direction perpendicular to the first direction when orthographically projected onto the base substrate is expressed by the following formula: B=A+k1×P1+k2×Q1+k3×P2+k4×Q2 P1=d1×tan(c1) P2=d2×tan(c2) However, A represents the width of the orthographic projection of the groove onto the base substrate along the second direction, P1 represents the width of the orthographic projection of the first gradient portion of the second barrier layer onto the base substrate, Q1 represents the width of the orthographic projection of the first platform of the second barrier layer onto the base substrate, P2 represents the width of the orthographic projection of the second gradient portion of the second barrier layer onto the base substrate, Q2 represents the width of the orthographic projection of the second platform of the second barrier layer onto the base substrate, d1 represents the thickness of the first planarization layer, d2 represents the thickness of the second planarization layer, c1 represents the gradient angle of the first planarization layer, c2 represents the gradient angle of the second planarization layer, and k1, k2, k3, and k4 are coefficients, where 1 < k1 ≤ 2, 1 < k2 ≤ 2, 1 < k3 ≤ 2, and 1 < k4 ≤ 2. The display substrate according to any one of claims 12 to 14, wherein, at a position adjacent to the groove of the first blocking layer, the angle range between the first blocking layer and the second blocking layer is 25° to 40°.

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