Ceramic electronic components, dielectric materials, and methods for manufacturing ceramic electronic components
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-03-17
- Publication Date
- 2026-08-13
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Figure 0007904702000003 
Figure 0007904702000004 
Figure 0007904702000005
Abstract
Description
[Technical Field]
[0001] This invention relates to ceramic electronic components, dielectric materials, and methods for manufacturing ceramic electronic components. [Background technology]
[0002] Ceramic electronic components such as multilayer ceramic capacitors, in which internal electrode layers and dielectric layers are alternately stacked, are known. These ceramic electronic components are manufactured by stacking a metal conductive paste for forming the internal electrode layer and a dielectric green sheet for the dielectric layer, and then firing these stacks. During firing, the internal electrode layer, which is mainly composed of metal, shrinks faster than the dielectric layer, which may cause cracks to occur in these layers. Lowering the firing temperature is effective in preventing this. For example, Patent Document 1 discloses a dielectric material that can be fired at 1300°C or below. Furthermore, Patent Document 2 achieves lower firing temperatures by using a glass component with a low softening point temperature as the dielectric material. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-335169 [Patent Document 2] Japanese Patent Publication No. 2005-179105 [Overview of the Initiative] [Problems that the invention aims to solve]
[0004] However, to effectively suppress cracking in the dielectric layer, it is preferable to lower the firing temperature even further than the 1300°C disclosed in Patent Document 1. Furthermore, if a glass component is used as in Patent Document 2, the ceramic particles may aggregate during firing, potentially reducing the smoothness of the dielectric layer and decreasing its mechanical strength. Moreover, attempting to achieve both a lower firing temperature and improved mechanical strength may lead to a deterioration in the quality of the dielectric layer.
[0005] The present invention aims to provide a ceramic electronic component, a dielectric material, and a method for manufacturing a ceramic electronic component that can maintain the quality of the dielectric layer even at a low firing temperature for the dielectric layer. [Means for solving the problem]
[0006] The ceramic electronic component according to the present invention is a ceria-zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The device comprises a dielectric layer containing a main component that can be expressed as O3(0.6≦x1≦0.9, 0≦x2≦0.1, 0≦y≦0.1), wherein the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less when the main component is set to 100 mol%, and internal electrode layers provided via the dielectric layer and facing each other.
[0007] In the above-described ceramic electronic component, the dielectric layer may further contain a manganese compound, a silicon compound, and a boron compound, and when the main component is considered to be 100 mol%, the concentration of the manganese compound may be 0.2 mol% or more and 5.0 mol% or less when converted to MnO, the concentration of the silicon compound may be 0.5 mol% or more and 5.0 mol% or less when converted to SiO2, and the concentration of the boron compound may be 0.2 mol% or more and 1.0 mol% or less when converted to (B2O3) / 2.
[0008] In the above-described ceramic electronic component, the area ratio occupied by the ceria-zirconia solid solution particles in the cross-section of the dielectric layer may be 1% or more and 15% or less.
[0009] In the above-described ceramic electronic component, the dielectric layer has a plurality of voids, and the total area occupied by the voids in the cross-section may be smaller than the total area occupied by the ceria-zirconia solid solution particles in the cross-section.
[0010] In the above ceramic electronic component, the major axis of the void may be 0.1 μm or more and 0.6 μm or less.
[0011] In the above ceramic electronic component, the void and the particle may be in contact with each other.
[0012] In the above ceramic electronic component, the thickness of the dielectric layer may be 2 μm or less.
[0013] The dielectric material according to the present invention contains a ceria-zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y )O3 (0.6 ≤ x1 ≤ 0.9, 0 ≤ x2 ≤ 0.1, 0 ≤ y ≤ 0.1) as a main component, and when the main component is 100 mol%, the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less.
[0014] The above dielectric material further contains a manganese compound, a silicon compound, and a boron compound. When the main component is 100 mol%, the concentration of the manganese compound is 0.2 mol% or more and 5.0 mol% or less in terms of MnO, the concentration of the silicon compound is 0.5 mol% or more and 5.0 mol% or less in terms of SiO2, and the concentration of the boron compound may be 0.2 mol% or more and 1.0 mol% or less in terms of (B2O3) / 2.
[0015] The method for manufacturing a ceramic electronic component according to the present invention includes a ceria-zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-yThe method includes the steps of: preparing a dielectric green sheet containing a ceramic material that includes a main component that can be expressed as O3(0.6≦x1≦0.9, 0≦x2≦0.1, 0≦y≦0.1), and in which the concentration of the ceria zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less when the main component is set to 100 mol%; forming an internal electrode pattern on the dielectric green sheet; stacking the dielectric green sheets on which the internal electrode pattern is formed to obtain a laminate; and firing the laminate.
[0016] In the above method for manufacturing ceramic electronic components, the ceramic material has a concentration of 0.2 mol% or more and 1.0 mol% or less when the main component is set to 100 mol%, converted to (B2O3) / 2, and a specific surface area of 100 m². 2 / g or more 300m 2 It may contain boron nitride in amounts less than or equal to / g. [Effects of the Invention]
[0017] According to the present invention, the quality of the dielectric layer can be maintained even at a low firing temperature for the dielectric layer. [Brief explanation of the drawing]
[0018] [Figure 1] This is a partial cross-sectional perspective view of a multilayer ceramic capacitor according to the present invention. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a cross-sectional view along line BB in Figure 1. [Figure 4] This diagram illustrates a flow chart of the manufacturing process for multilayer ceramic capacitors. [Figure 5] (a) and (b) are diagrams illustrating the lamination process. [Figure 6] This is a diagram illustrating the lamination process. [Figure 7] This is a diagram illustrating the lamination process. [Figure 8]This is a schematic diagram of an image obtained by observing the polished surface of a cross-section perpendicular to the stacking direction between the dielectric layer and the internal electrode layer of the multilayer ceramic capacitor according to Example 1 using SEM-EDS. [Modes for carrying out the invention]
[0019] The embodiments will be described below with reference to the drawings. (Embodiment) First, an overview of the multilayer ceramic capacitor will be described. Figure 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. Figure 2 is a cross-sectional view taken along line AA in Figure 1. Figure 3 is a cross-sectional view taken along line BB in Figure 1. As illustrated in Figures 1 to 3, the multilayer ceramic capacitor 100 comprises a multilayer chip 10 having a rectangular parallelepiped shape and external electrodes 20a and 20b provided on two opposing end faces of either of the multilayer chip 10. Of the four faces of the multilayer chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a and 20b extend to the top, bottom, and two side faces of the multilayer chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.
[0020] The multilayer chip 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed to the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. Consequently, the multilayer ceramic capacitor 100 has a structure in which multiple dielectric layers 11 are stacked via internal electrode layers 12. Furthermore, in the laminate of dielectric layers 11 and internal electrode layers 12, the outermost layer in the stacking direction is an internal electrode layer 12, and the top and bottom surfaces of the laminate are covered by a cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the main components of the cover layer 13 are the same as those of the dielectric layer 11 and the ceramic material.
[0021] The thickness of the dielectric layer 11 is preferably 2 μm or less from the viewpoint of increasing the capacitance of the multilayer ceramic capacitor 100. The thickness of the internal electrode layer 12 is preferably 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.0 μm or less. This range allows for cost, capacitance acquisition due to the continuity of the internal electrodes, and stability in the firing process. The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.
[0022] As illustrated in Figure 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region in the multilayer ceramic capacitor 100 that generates capacitance. Therefore, this region is referred to as the capacitance region 14. In other words, the capacitance region 14 is the region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.
[0023] The region where internal electrode layers 12 connected to external electrode 20a face each other without being connected to an internal electrode layer 12 connected to external electrode 20b is called the end margin 15. Similarly, the region where internal electrode layers 12 connected to external electrode 20b face each other without being connected to an internal electrode layer 12 connected to external electrode 20a is also called the end margin 15. In other words, the end margin 15 is the region where internal electrode layers 12 connected to the same external electrode face each other without being connected to an internal electrode layer 12 connected to a different external electrode. The end margin 15 is a region where no capacitance is generated.
[0024] As illustrated in Figure 3, in the stacked chip 10, the region extending from the two sides of the stacked chip 10 to the internal electrode layer 12 is referred to as the side margin 16. That is, the side margin 16 is a region provided in the stacked structure that covers the ends of the multiple internal electrode layers 12 that extend to the two sides.
[0025] The cover layer 13 and side margin 16 protect the outer periphery of the capacitance region 14. Therefore, in the following description, the cover layer 13 and side margin 16 will be collectively referred to as the ceramic protective portion 50.
[0026] The internal electrode layer 12 mainly consists of base metals such as nickel (Ni), copper (Cu), and tin (Sn). Precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these, may also be used as the internal electrode layer 12.
[0027] The dielectric layer 11 mainly consists of a perovskite compound and contains a ceria-zirconia solid solution. The ceria-zirconia solid solution is a solid solution of ceria (CeO2) in zirconia (ZrO2). In this embodiment, (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-yO3 is used. The ceria-zirconia solid solution has higher strength and toughness than perovskite compounds used as dielectrics. Therefore, even if the dielectric layer 11 and the internal electrode layer 12 are fired at low temperatures, the mechanical strength of the dielectric layer 11 can be increased. In addition, yttria (Y2O3) can be cited as a rare earth oxide that solidifies in zirconia, but when yttria solidifies in zirconia, oxygen vacancies are generated during solid solution due to the difference in valence between zirconium ions and yttrium ions, which is a factor that reduces insulation, especially at high temperatures. However, when ceria solidifies in zirconia, it mainly takes the same valence, so such a phenomenon is less likely to occur. Therefore, the decrease in insulation at high temperatures can be suppressed. Note that this perovskite structure is an ABO that deviates from the stoichiometric composition. 3-α Includes.
[0028] Also, (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y If the concentration of the ceria-zirconia solid solution exceeds 5.0 mol% when O3 is set to 100 mol%, the densification of the dielectric layer 11 during firing may be hindered by the ceria-zirconia solid solution. Therefore, (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y When O3 is considered to be 100 mol%, the concentration of the ceria-zirconia solid solution is preferably 5.0 mol% or less. On the other hand, if the concentration of the ceria-zirconia solid solution is less than 0.5 mol%, there is a risk that the mechanical strength of the dielectric layer 11 cannot be sufficiently increased. For this reason, it is preferable that the concentration of the ceria-zirconia solid solution be 0.5 mol% or more.
[0029] In this embodiment, the main component is (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y Let the compositional ratios of O3 be 0.6≦x1≦0.9, 0≦x2≦0.1, and 0≦y≦0.1, and this (Ca x1 Ba x2Sr 1-x1-x2 )(Ti y Zr 1-y The concentration of the ceria-zirconia solid solution is set to 0.5 mol% or more and 5.0 mol% or less, with O3 being 100 mol%. This makes it possible to maintain the quality of the dielectric layer 11, such as its mechanical strength, even when the dielectric layer 11 is fired at a low temperature.
[0030] The dielectric layer of a multilayer ceramic capacitor is called Class I according to the EIA standard if its material is a paraelectric, and Class II if it is a ferroelectric. The dielectric layer 11 according to this embodiment is a dielectric layer belonging to Class I.
[0031] The Class 1 dielectric layer 11 may exhibit changes in temperature characteristics as its film thickness decreases. This is thought to be due to the difference in thermal expansion coefficients between the internal electrode layer 12 and the dielectric layer 11. Ceria-zirconia solid solution also helps to suppress such changes in temperature characteristics. When ceria-zirconia solid solution is not added to the dielectric layer 11, the main component is (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y ) In O3, it is necessary to adjust the composition ratios x1, x2, and y to suppress changes in temperature characteristics, but in this embodiment, changes in the temperature characteristics of the dielectric layer 11 can be suppressed simply by adjusting the amount of ceria-zirconia solid solution added.
[0032] Furthermore, the dielectric layer 11 may further contain manganese compounds, silicon compounds, and boron compounds. These compounds work together to lower the sintering temperature of the dielectric layer 11. Examples of manganese compounds include MnO and MnCO3, and examples of silicon compounds include SiO2. Examples of boron compounds include B2O3, boron nitride, and boric acid.
[0033] In particular, it is preferable that the dielectric layer 11 contains manganese compounds at concentrations of 0.2 mol% to 5.0 mol% when converted to MnO, silicon compounds at concentrations of 0.5 mol% to 5.0 mol% when converted to SiO2, and boron compounds at concentrations of 0.2 mol% to 1.0 mol% when converted to (B2O3) / 2. x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This is the concentration when O3 is set to 100 mol%. By adopting this concentration range, it becomes easier to fire the dielectric layer 11 at low temperatures of 1220°C or below.
[0034] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 4 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.
[0035] (Process for producing raw material powder) First, the starting materials for forming the dielectric layer 11 are prepared. Here, powders of SrCO3, CaCO3, TiO2, BaCO3, and ZrO2 are prepared as starting materials. Next, these powders are weighed and dispersed in ion-exchanged water and a dispersant using a ball mill to obtain the dielectric material.
[0036] Next, the dielectric material is dried and then dry-ground, and further calcined at 1100°C to obtain (Ca) perovskite powder, which is the main component of the dielectric layer 11. x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y )O3 powder is obtained. In this embodiment, 0.6≦x1≦0.9, 0≦x2≦0.1, and 0≦y≦0.1 are assumed.
[0037] Next, an inverse pattern material is prepared to form the end margin 15 and side margin 16. The inverse pattern material contains the main component ceramic of the end margin 15 and side margin 16. As the main component ceramic, (Ca x1 Ba x2 Sr1-x1-x2 )(Ti y Zr 1-y Prepare O3 powder.
[0038] Next, a cover material is prepared to form the cover layer 13. The cover material contains the main component ceramic of the cover layer 13. As the main component ceramic, (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y Prepare O3 powder.
[0039] Next, prepare the starting materials for the ceria-zirconia solid solution. For example, a specific surface area of 30 m² 2 ZrO2 / g and specific surface area of 50m 2 Prepare CeO2 in units of 1g. Then, weigh a predetermined amount of these and disperse them in a ball mill with deionized water and a dispersant to obtain a mixture of ceria and zirconia.
[0040] Next, this mixture is dried, then dry-ground, and further calcined at 1200°C to obtain ceria-zirconia solid solution powder.
[0041] (Lamination process) Next, a ceramic powder is prepared by adding a manganese compound, a silicon compound, a boron compound, and a ceria-zirconia solid solution to the perovskite powder obtained in the raw material powder preparation process, and a slurry is obtained by ball milling this powder together with an organic solvent, a binder, and a dispersant. In this case, (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y When O3 is considered to be 100 mol%, the concentration of the ceria-zirconia solid solution should be between 0.5 mol% and 5.0 mol%.
[0042] The concentration of ceria (CeO2) in the ceria-zirconia solid solution shall be between 6 mol% and 18 mol%. A ceria-zirconia solid solution with a ceria concentration of 6 mol% and a zirconia concentration of 94 mol% will be referred to as 6CEZ below. A ceria-zirconia solid solution with a ceria concentration of 10 mol% and a zirconia concentration of 90 mol% will be referred to as 10CEZ below. A ceria-zirconia solid solution with a ceria concentration of 18 mol% and a zirconia concentration of 82 mol% will be referred to as 18CEZ below.
[0043] Furthermore, the manganese compound is, for example, MnCO3, and is added to the ceramic powder at a concentration of 0.2 mol% to 5.0 mol% when converted to MnO. On the other hand, the silicon compound is, for example, SiO2, and is added to the ceramic powder at a concentration of 0.5 mol% to 5.0 mol%. In addition, the boron compound is, for example, boron nitride, and is added to the ceramic powder at a concentration of 0.2 mol% to 1.0 mol% when converted to (B2O3) / 2. The molar concentrations of these are (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This is the molar concentration when O3 is considered to be 100 mol%.
[0044] Furthermore, since boron nitride does not easily dissolve in organic solvents, it can suppress gelation of the slurry. In particular, when the specific surface area is 100 m² 2 / g or more 300m 2 Boron nitride at concentrations of less than / g can effectively suppress gelation of the slurry. Alternatively, B2O3 or boric acid may be used instead of boron nitride.
[0045] Subsequently, a dielectric green sheet with a thickness of approximately 3 μm is obtained by tape casting the slurry onto a substrate such as PET (polyethylene terephthalate) film.
[0046] Next, a metal conductive paste for the internal electrode layer containing an organic binder is printed onto the surface of the dielectric green sheet by screen printing, gravure printing, or the like. In addition to nickel, ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferable that it is the same as the main component ceramic of the dielectric layer 11.
[0047] Next, as illustrated in Figure 5(a), a first pattern 52 for the internal electrode layer is arranged on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like, by printing a metal conductive paste containing an organic binder for forming internal electrodes. In addition to nickel, ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferable that it is the same as the main component ceramic of the dielectric layer 11.
[0048] Next, an ethylcellulose-based binder and an organic solvent such as terpineol-based solvent are added to the inverse pattern material obtained in the raw material powder preparation process, and the mixture is kneaded in a roll mill to obtain an inverse pattern paste for the inverse pattern layer. As illustrated in Figure 5(a), the second pattern 53 is placed on the dielectric green sheet 51 by printing the inverse pattern paste in the peripheral area where the first pattern 52 is not printed, thereby filling the step between it and the first pattern 52.
[0049] Subsequently, as illustrated in Figure 5(b), dielectric green sheets 51, the first pattern 52, and the second pattern 53 are stacked so that the internal electrode layer 12 and the dielectric layer 11 are staggered, and the edges of the internal electrode layer 12 are alternately exposed on both ends of the dielectric layer 11 in the longitudinal direction, alternately leading to a pair of external electrodes 20a and 20b with different polarities. For example, the number of stacked dielectric green sheets 51 is 100 to 500.
[0050] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the cover material obtained in the raw material powder preparation process and wet-mixed. Using the resulting slurry, a strip-shaped cover sheet 54, for example, with a thickness of 10 μm or less, is coated onto the substrate using a die coater or doctor blade method and dried. As illustrated in Figure 6, a predetermined number of cover sheets 54 (for example, 2 to 10 layers) are laminated above and below the laminated dielectric green sheet 51 and heat-pressed, then cut to a predetermined chip size (for example, 1.0 mm × 0.5 mm), and then a metal conductive paste, which will become the external electrodes 20a and 20b, is applied to both sides of the cut laminate using a dip method or the like and dried. This yields a ceramic laminate. Alternatively, the predetermined number of cover sheets 54 may be laminated and pressed together before being attached to the above and below the laminated dielectric green sheet 51.
[0051] In the methods shown in Figures 5(a) to 6, the region where the dielectric green sheet 51 corresponds to the first pattern 52 and the first pattern 52 are stacked is (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This corresponds to a laminated portion in which sheets with O3 particles as the main component ceramic and patterns of metal conductive paste are alternately stacked. The region in which the portion of the dielectric green sheet 51 that extends beyond the first pattern 52 and the second pattern 53 are stacked corresponds to a side margin region located on the side of the laminated portion.
[0052] The side margin region may be attached to or applied to the side surface of the laminated portion. Specifically, as illustrated in Figure 7, a laminated portion is obtained by alternately laminating a dielectric green sheet 51 and a first pattern 52 having the same width as the dielectric green sheet 51. Next, the side margin region may be formed on the side surface of the laminated portion with a second pattern 53 obtained by attaching a sheet formed with reverse pattern paste or by applying reverse pattern paste.
[0053] (Firing process) The thus obtained ceramic laminate was subjected to a debinding treatment in a N2 atmosphere, and then a Ni paste serving as a base for the external electrodes 20a and 20b was applied by dipping, and the oxygen partial pressure was 10 -5 ~10 -8 atm, and fired at a temperature of 1220 °C or lower for 10 minutes to 2 hours in a reducing atmosphere. Thus, the multilayer ceramic capacitor 100 is obtained. In the firing process, a method of baking the external electrodes after firing the ceramic laminate may be used.
[0054] (Re-oxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600 °C to 1000 °C in a N2 gas atmosphere.
[0055] (Plating process) Thereafter, a metal coating such as Cu, Ni, or Sn may be applied to the external electrodes 20a and 20b by plating.
[0056] According to the above-described embodiment, the dielectric layer 11 contains a ceria-zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr[[ID=3 ]] 1-y )O₃ (0.6 ≤ x1 ≤ 0.9, 0 ≤ x2 ≤ 0.1, 0 ≤ y ≤ 0.1), and when (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti[[ID=]8] y [[ID=]9] 1-y Zr )O₃ is 100 mol%, the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less.
[0057] Thereby, even when the temperature in the firing process is as low as 1220 °C or lower, the mechanical strength of the dielectric layer 11 can be enhanced by the mechanically strong ceria-zirconia solid solution.
[0058] In the embodiments described above, multilayer ceramic capacitors were explained as an example of ceramic electronic components, but the invention is not limited to them. For example, other electronic components such as varistors and thermistors may be used. [Examples]
[0059] Next, we will describe the examples and comparative examples. Table 1 shows the conditions for each of the examples and comparative examples.
[0060] [Table 1] (Example 1) SrCO3, CaCO3, TiO2, and ZrO2 powders were weighed and dispersed in deionized water and a dispersant using a ball mill to obtain a dielectric material. Next, the dielectric material was dried and then dry-ground, and further calcined at 1100°C to obtain (Ca) perovskite powder, which is the main component of the dielectric layer 11. 0.7 Sr 0.3 )(Ti 0.03 Zr 0.97 )O3 powder was obtained.
[0061] To the perovskite powder, 1 mol% of MnCO3 (calculated as MnO), 1 mol% of SiO2 (calculated as silicon), and 0.3 mol% of boron nitride (calculated as (B2O3) / 2) were added. Furthermore, 2 mol% of 6CEZ was added to the perovskite powder. Note that all of these concentrations are (Ca 0.7 Sr 0.3 )(Ti 0.03 Zr 0.97 This is the concentration when O3 is considered to be 100 mol%. This is the same for each example and comparative example described later.
[0062] Furthermore, the dielectric layer 11 had a thickness of 2 μm, and the number of layers between the internal electrode layer 12 and the dielectric layer 11 was 100. The chip shape was 3.2 × 1.6 × 1.0 mm in size.
[0063] (Example 2) Perovskite powder was treated with 0.2 mol% of MnCO3 (calculated as MnO) as a manganese compound, 2 mol% of SiO2 (calculated as a silicon compound), and 0.2 mol% of boron nitride (calculated as (B2O3) / 2) as a boron compound. All other treatments were the same as in Example 1.
[0064] (Example 3) Perovskite powder was treated with 1.5 mol% of MnCO3 (calculated as MnO) as a manganese compound, 1 mol% of SiO2 (calculated as a silicon compound), and 0.3 mol% of boron nitride (calculated as (B2O3) / 2) as a boron compound. All other treatments were the same as in Example 1.
[0065] (Example 4) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.6.
[0066] Furthermore, to this perovskite powder, MnCO3 was added at a concentration of 1 mol% (converted to MnO) as a manganese compound, SiO2 at a concentration of 3 mol% (converted to MnO) as a silicon compound, and boron nitride at a concentration of 0.2 mol% (converted to (B2O3) / 2) as a boron compound. Other than these additions, the procedure was the same as in Example 1.
[0067] (Example 5) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.9.
[0068] To this perovskite powder, 2 mol% of MnCO3 (calculated as MnO), 0.5 mol% of SiO2 (calculated as a silicon compound), and 0.5 mol% of boron nitride (calculated as (B2O3) / 2) were added. Furthermore, 2.5 mol% of 6CEZ was added to the perovskite powder. The rest of the procedure was the same as in Example 1.
[0069] (Example 6) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of y at O3 was set to 0.
[0070] To this perovskite powder, 3 mol% of MnCO3 (calculated as MnO), 5 mol% of SiO2 (calculated as a silicon compound), and 1 mol% of boron nitride (calculated as (B2O3) / 2) were added. Furthermore, 1.5 mol% of 6CEZ was added to the perovskite powder. The rest of the procedure was the same as in Example 1.
[0071] (Example 7) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of y at O3 was set to 0.05.
[0072] To this perovskite powder, 5 mol% of MnCO3 (calculated as MnO), 1 mol% of SiO2 (calculated as a silicon compound), and 0.2 mol% of boron nitride (calculated as (B2O3) / 2) were added. All other details were the same as in Example 1.
[0073] (Example 8) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-yThe value of x1 in O3 was set to 0.8, and the value of y was set to 0.07.
[0074] To this perovskite powder, 0.2 mol% of MnCO3 (calculated as MnO), 1 mol% of SiO2 (calculated as a silicon compound), and 0.7 mol% of boron nitride (calculated as (B2O3) / 2) were added. Furthermore, 1.5 mol% of 6CEZ was added to the perovskite powder. The rest of the procedure was the same as in Example 1.
[0075] (Example 9) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.8, and the value of y was set to 0.1.
[0076] To this perovskite powder, 2 mol% of MnCO3 (calculated as MnO), 1 mol% of SiO2 (calculated as a silicon compound), and 0.4 mol% of boron nitride (calculated as (B2O3) / 2) were added. Furthermore, 0.5 mol% of 6CEZ was added to the perovskite powder. The rest of the procedure was the same as in Example 1.
[0077] (Example 10) Perovskite powder was mixed with 0.1 mol% of MnCO3 (calculated as MnO) as a manganese compound, 0.5 mol% of SiO2 (calculated as a silicon compound), and 0.4 mol% of boron nitride (calculated as (B2O3) / 2) as a boron compound. Additionally, 1 mol% of 6CEZ was added to the perovskite powder. The procedure was otherwise the same as in Example 1.
[0078] (Example 11) Perovskite powder was treated with 7 mol% of MnCO3 (calculated as MnO) as a manganese compound and 2 mol% of SiO2 as a silicon compound. Additionally, 3 mol% of 6CEZ was added to the perovskite powder. The procedure was otherwise the same as in Example 1.
[0079] (Example 12) Perovskite powder was treated with SiO2 as a silicon compound at a concentration of 0.4 mol%. Otherwise, the procedure was the same as in Example 1.
[0080] (Example 13) Perovskite powder was to which 5.2 mol% of SiO2 was added as a silicon compound and 0.2 mol% of boron nitride was added as a boron compound (calculated as (B2O3) / 2). In addition, 3.5 mol% of 6CEZ was added to the perovskite powder. The rest of the procedure was the same as in Example 1.
[0081] (Example 14) Boron nitride was added to the perovskite powder at a concentration of 0.1 mol% (calculated as (B2O3) / 2) as a boron compound. Additionally, 6CEZ was added to the perovskite powder at a concentration of 1.5 mol%. The procedure was otherwise the same as in Example 1.
[0082] (Example 15) Perovskite powder was mixed with 1.5 mol% of MnCO3 (calculated as MnO) as a manganese compound, 1.5 mol% of SiO2 (calculated as a silicon compound), and 1.2 mol% of boron nitride (calculated as (B2O3) / 2) as a boron compound. Additionally, 1.5 mol% of 6CEZ was added to the perovskite powder. The procedure was otherwise the same as in Example 1.
[0083] (Example 16) 6CEZ was added to the perovskite powder at a concentration of 5 mol%. Otherwise, the procedure was the same as in Example 1.
[0084] (Example 17) Boron nitride was added to the perovskite powder at a concentration of 0.4 mol% (calculated as (B2O3) / 2) as a boron compound. Additionally, 10CEZ was added to the perovskite powder at a concentration of 1 mol%. The procedure was otherwise the same as in Example 1.
[0085] (Example 18) (Cax1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of y at O3 was set to 0.04.
[0086] To this perovskite powder, MnCO3 was added as a manganese compound at a concentration of 1.5 mol% (calculated as MnO). Furthermore, 10CEZ was added to the perovskite powder at a concentration of 3 mol%. The rest of the procedure was the same as in Example 1.
[0087] (Example 19) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of y at O3 was set to 0.04.
[0088] To this perovskite powder, MnCO3 was added as a manganese compound at a concentration of 2 mol% (equivalent to MnO). Furthermore, 18CEZ was added to the perovskite powder at a concentration of 1 mol%. The rest of the procedure was the same as in Example 1.
[0089] (Example 20) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of y at O3 was set to 0.04.
[0090] Perovskite powder was mixed with SiO2 as a silicon compound at a concentration of 2 mol%. Additionally, 18CEZ was mixed with the same perovskite powder at a concentration of 3 mol%. The procedure was otherwise the same as in Example 1.
[0091] (Example 21) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-yThe value of x2 in O3 was set to 0.01. Otherwise, it is the same as in Example 1.
[0092] (Example 22) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.65, and the value of x2 was set to 0.1. All other aspects were the same as in Example 1.
[0093] (Comparative Example 1) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.5. In addition, boron nitride was added to this perovskite powder as a boron compound at a concentration of 0.2 mol% when converted to (B2O3) / 2. The rest of the procedure was the same as in Example 1.
[0094] (Comparative Example 2) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y The value of x1 in O3 was set to 0.95. Furthermore, 6CEZ was added to the perovskite powder at a concentration of 3 mol%. The rest of the procedure was the same as in Example 1.
[0095] (Comparative Example 3) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-yThe value of x1 in O3 was set to 0.8 and the value of y to 0.12. Furthermore, MnCO3 was added to this perovskite powder at a concentration of 1.5 mol% (converted to MnO) as a manganese compound, and boron nitride was added at a concentration of 0.4 mol% (converted to (B2O3) / 2) as a boron compound. In addition, 6CEZ was added to the perovskite powder at a concentration of 1.5 mol%. The rest of the procedure was the same as in Example 1.
[0096] (Comparative Example 4) 6CEZ was added to the perovskite powder at a concentration of 0.3 mol%. Otherwise, the procedure was the same as in Example 1.
[0097] (Comparative Example 5) Perovskite powder was mixed with 1.5 mol% of MnCO3 (calculated as MnO) as a manganese compound, 2 mol% of SiO2 (calculated as a silicon compound), and 0.5 mol% of boron nitride (calculated as (B2O3) / 2) as a boron compound. Additionally, 7 mol% of 6CEZ was added to the perovskite powder. The procedure was otherwise the same as in Example 1.
[0098] (Comparative Example 6) (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y In O3, the value of x1 was set to 0.45, the value of x2 to 0.15, and the value of y to 0.05. All other aspects were the same as in Example 1.
[0099] Table 2 shows the results of the quality investigation of the dielectric layer 11 for each of Examples 1 to 22 and Comparative Examples 1 to 6. In this example, the relative permittivity (ε) is used as the quality of the dielectric layer 11. r The following parameters were used: Q value, temperature coefficient (τC), high-temperature insulation, accelerated lifetime, and three-point bending strength. Furthermore, Table 2 also shows the firing temperature of the dielectric layer 11 and the proportion of the ceria-zirconia solid solution phase contained in the dielectric layer 11. [Table 2]
[0100] Here, capacitance and Q value were measured using an LCR meter under the setting conditions of 1kHz-1Vrms. Relative permittivity ε r This was calculated from the capacitance C based on the following formula. ε r = (C × thickness of dielectric layer 11) / (number of dielectric layers 11 × ε0 × effective crossing area) However, ε0 is the permittivity of vacuum. The temperature coefficient (τC) is the change in capacitance (ppm) when the temperature changes by 1°C. Here, the temperature coefficient was determined from the difference in capacitance at 25°C and 125°C. The capacitance was measured in a constant temperature bath.
[0101] Accelerated life is the average time it takes for the resistance of a multilayer ceramic capacitor 100 to decrease by two orders of magnitude from its initial value after being heated to 200°C in a 50V / μm electric field.
[0102] The three-point bending strength is the average value obtained when three-point bending tests were performed on multiple multilayer ceramic capacitors 100.
[0103] For high-temperature insulation, the insulation resistance value was measured at 150°C - 100V - 60 seconds.
[0104] In this study, materials were deemed acceptable if they had a dielectric constant of 29 or higher, a Q value of 2000 or higher, a temperature coefficient within ±300 ppm / °C, an accelerated life of 500 hours or higher, a three-point bending test of 250 MPa or higher, and a high-temperature insulation of 10 GΩ or higher. Furthermore, materials that could be densified and fired at a firing temperature of 1220°C or lower were deemed acceptable.
[0105] As shown in Table 2, in Examples 1 to 22, the quality of the dielectric layer 11 is within the acceptable range in all cases.
[0106] On the other hand, Comparative Example 1 has a temperature coefficient of -310 ppm / °C, which is outside the acceptable range (±300 ppm / °C). This is because in Comparative Example 1, the material of the perovskite powder is (Ca x1 Ba x2 Sr 1-x1-x2 )(Tiy Zr 1-y This is thought to be because the value of the composition ratio x1 in O3 is less than 0.6.
[0107] Furthermore, Comparative Example 2 has a relative permittivity of 28, which is outside the acceptable range (29 or higher). Also, its three-point bending strength is 240 MPa, which is outside the acceptable range. This is because in Comparative Example 2, the perovskite powder material (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This is thought to be because the value of the composition ratio x1 in O3 exceeds 0.9.
[0108] Comparative Example 3 has a temperature coefficient of -345 ppm / °C, which is outside the acceptable range (±300 ppm / °C). Furthermore, its accelerated life is 480 h, which is also outside the acceptable range (500 h or more). This is because, in Comparative Example 3, the perovskite powder material (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This is thought to be because the composition ratio y in O3 exceeds 0.1. Furthermore, the high-temperature insulation performance also did not meet the acceptable range.
[0109] Comparative Example 4 had a three-point bending strength of 160 MPa, which falls outside the acceptable range (250 MPa or higher). This is likely because, in Comparative Example 4, the amount of 6CEZ added to the perovskite powder was less than 0.5 mol%, and therefore the strength improvement due to the ceria-zirconia solid solution was not achieved. Furthermore, the high-temperature insulation performance also did not meet the acceptable range.
[0110] Comparative Example 5 did not densify at firing temperatures below 1220°C. This is thought to be because, in Comparative Example 10, the amount of 6CEZ added to the perovskite powder exceeded 5.0 mol%.
[0111] Comparative Example 6 has a three-point bending strength of 135 MPa, which is outside the acceptable range (250 MPa or higher). Furthermore, its temperature coefficient is -330 ppm / °C, which is also outside the acceptable range. This is because, in Comparative Example 11, the perovskite powder material (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y This is thought to be because, in O3, the value of composition ratio x1 is less than 0.6, and furthermore, the value of composition ratio x2 exceeds 0.1.
[0112] From the above results, in order to maintain the quality of the dielectric layer 11 even when firing the dielectric layer 11 at a temperature of 1220°C or lower, the concentration of the ceria-zirconia solid solution should be in the range of 0.5 mol% to 5.0 mol%, and (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y It was confirmed that the compositional ratios of x1, x2, and y in O3 are preferably 0.6 ≤ x1 ≤ 0.9, 0 ≤ x2 ≤ 0.1, and 0 ≤ y ≤ 0.1.
[0113] In Examples 1 to 22, the dielectric layer 11 can be fired at a temperature of 1220°C or lower. Moreover, no structural defects such as delamination or cracks occur in the dielectric layer 11, and a high-quality, high-strength multilayer ceramic capacitor 100 can be provided that satisfies the EIA (Electronic Industries Alliance) standards of C0K, C0J, C0H, and C0G with a temperature characteristic of ±250 ppm / °C, and the EIA standards of R2H and S2K with a temperature characteristic of ±300 ppm / °C.
[0114] Figure 8 is a schematic diagram of an image obtained by observing the polished surface of a cross-section perpendicular to the stacking direction between the dielectric layer 11 and the internal electrode layer 12 of the multilayer ceramic capacitor 100 according to Example 1 using SEM-BSE (Scanning Electron Microscope-Backscattered Electron). The SEM magnification was 5000x.
[0115] The composition of the dielectric layer 11 can be identified and quantified not only by chemical analysis using ICP (Inductively Coupled Plasma) emission spectroscopy, but also by analyzing a cross-section of the dielectric layer 11 as shown in Figure 8 using SEM-EDS (Scanning Electron Microscope-Energy Dispersive Spectroscopy). When performing the analysis, it is preferable to ensure a sufficiently large area is available to avoid the influence of segregated compositions, and to improve the reliability of the quantitative analysis values by simultaneously analyzing and comparing standard samples that serve as calibration curves, if necessary.
[0116] Also, as mentioned above (Ca x1 Ba x2 Sr 1-x1-x2 )(Ti y Zr 1-y When the concentration of the ceria-zirconia solid solution is set to 0.5 mol% or more and 5.0 mol% or less, with O3 being 100 mol%, it was found that the area ratio occupied by the ceria-zirconia solid solution particles 11p in the cross-section of the dielectric layer 11 is 1% or more and 15% or less. The area ratio is calculated from an area of 10 μm from any position in the SEM cross-section of the dielectric layer 11. 2 A region is cut out, and the ratio of the total area of all particles 11p contained in that region to the area of that region is defined.
[0117] Furthermore, multiple voids 11s are formed in the dielectric layer 11, and these voids 11s improve the toughness of the dielectric layer 11. However, if the total area of the voids 11s is too large, the mechanical strength of the dielectric layer 11, such as the three-point bending strength, will decrease. Therefore, it is preferable to prevent a decrease in the mechanical strength of the dielectric layer 11 caused by the voids 11s by making the total area occupied by the voids 11s in the cross-section of the dielectric layer 11 smaller than the total area occupied by the particles 11p in the cross-section of the dielectric layer 11.
[0118] The total area of the void 11s is calculated from an area of 10 μm² at any point in the SEM cross-section of the dielectric layer 11. 2The region is cut out and defined as the sum of the areas of all voids 11s contained within that region. Similarly, the total area of particles 11p is defined as the sum of the areas of all particles 11p contained within the same region used to calculate the total area of voids 11s.
[0119] Furthermore, if a single void 11s is too large, the mechanical strength of the dielectric layer 11 will decrease. Therefore, it is preferable to set the major axis of the void 11s in cross-section to 0.1 μm or more and 0.6 μm or less. The reason for setting the lower limit of the major axis to 0.1 μm is that it is difficult to improve the toughness of the dielectric layer 11 with voids 11s smaller than this. The reason for setting the upper limit of the major axis to 0.6 μm is that if it is larger than this, the mechanical strength of the dielectric layer 11 will decrease due to the voids 11s.
[0120] More preferably, the major axis of the void 11s in the cross-sectional view should be 0.15 μm or more and 0.3 μm or less. This is because it allows for the maintenance of a higher level of mechanical quality.
[0121] Furthermore, it is preferable that the ceria-zirconia solid solution particles 11p are in contact with the voids 11s in the cross-section of the dielectric layer 11. This allows the mechanically strong particles 11p to suppress the occurrence of cracks in the dielectric layer 11 that originate from the voids 11s.
[0122] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of Symbols]
[0123] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13. Cover layer 14 capacity area 15 End margin 16 Side margins 20a,20b external electrode 50 Ceramic protective section 100 Multilayer Ceramic Capacitors
Claims
1. Ceria zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 ) (Ti y Zr 1-y ) O 3 (0.6 ≤ x) 1 ≤ 0.9, 0 ≤ x 2 A dielectric layer containing a main component that can be expressed as (≤0.1, 0 ≤ y ≤ 0.1), wherein the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less when the main component is 100 mol%, A ceramic electronic component having internal electrode layers that are provided via the dielectric layer and face each other.
2. The dielectric layer further comprises a manganese compound, a silicon compound, and a boron compound. When the main component is 100 mol%, the concentration of the manganese compound is 0.2 mol% or more and 5.0 mol% or less in terms of MnO, and the concentration of the silicon compound is SiO 2 in terms of 0.5 mol% or more and 5.0 mol% or less, and the concentration of the boron compound is (B 2 O 3 ) / 2 in terms of a concentration of 0.2 mol% or more and 1.0 mol% or less. The ceramic electronic component according to claim 1.
3. The ceramic electronic component according to claim 1 or claim 2, wherein the area ratio occupied by the ceria-zirconia solid solution particles in the cross-section of the dielectric layer is 1% or more and 15% or less.
4. The ceramic electronic component according to claim 3, wherein the dielectric layer has a plurality of voids, and the total area occupied by the voids in the cross-section is smaller than the total area occupied by the particles of the ceria-zirconia solid solution in the cross-section.
5. The ceramic electronic component according to claim 4, wherein the major axis of the void is 0.1 μm or more and 0.6 μm or less.
6. The ceramic electronic component according to claim 4 or 5, characterized in that the void and the particles are in contact.
7. The ceramic electronic component according to any one of claims 1 to 6, wherein the thickness of the dielectric layer is 2 μm or less.
8. Ceria zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 ) (Ti y Zr 1-y ) O 3 (0.6 ≤ x) 1 ≤ 0.9, 0 ≤ x 2 A dielectric material containing a main component that can be expressed as (≤0.1, 0 ≤ y ≤ 0.1), wherein the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less when the main component is 100 mol%.
9. Furthermore, it contains manganese compounds, silicon compounds, and boron compounds. When the aforementioned main component is set to 100 mol%, the concentration of the manganese compound is 0.2 mol% or more and 5.0 mol% or less when converted to MnO, and the concentration of the silicon compound is SiO 2 Converted to 0.5 mol% or more and 5.0 mol% or less, the concentration of the boron compound is (B 2 O 3 The dielectric material according to claim 8, wherein the concentration is 0.2 mol% or more and 1.0 mol% or less when converted to ) / 2.
10. Ceria zirconia solid solution and (Ca x1 Ba x2 Sr 1-x1-x2 ) (Ti y Zr 1-y ) O 3 (0.6 ≤ x) 1 ≤ 0.9, 0 ≤ x 2 A step of preparing a dielectric green sheet containing a ceramic material that includes a main component that can be expressed as (≤0.1, 0 ≤ y ≤ 0.1), and in which the concentration of the ceria-zirconia solid solution is 0.5 mol% or more and 5.0 mol% or less when the main component is 100 mol%, The process of forming an internal electrode pattern on the dielectric green sheet, A step of obtaining a laminate by stacking the dielectric green sheets on which the internal electrode pattern is formed, A method for manufacturing a ceramic electronic component, comprising the step of firing the laminated body.
11. The ceramic material has a concentration of (B) when the main component is set to 100 mol%. 2 O 3 Converted to ) / 2, it is 0.2 mol% or more and 1.0 mol% or less, and the specific surface area is 100 m². 2 / g or more 300m 2 A method for manufacturing a ceramic electronic component according to claim 10, comprising boron nitride in a quantity of less than or equal to / g.
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