Semiconductor equipment

Abstract

To provide a semiconductor device, capable of suppressing occurrence of cracks in an interlayer dielectric film in the vicinity of a first wiring portion.SOLUTION: A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface disposed on an opposite side of the first main surface; a plurality of interlayer dielectric films; and a plurality of pieces of wiring. The plurality of interlayer dielectric films includes a first interlayer dielectric film farthest from the first main surface in a first direction perpendicular to the first main surface, and a second interlayer dielectric film in contact with the first interlayer dielectric film in the first direction. The plurality of pieces of wiring includes first wiring disposed on the first interlayer dielectric film, and second wiring disposed on the second interlayer dielectric film so as to be covered with the first interlayer dielectric film. A trench recessed toward the second main surface is formed on the first main surface. The trench includes a straight portion extending in a second direction orthogonal to the first direction. A distance between the straight portion and a first end of a first wiring portion included in the first wiring is smaller than a distance between the straight portion and a second end in the first wiring portion.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] For example, Japanese Patent Application Laid-Open No. 2021-9865 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a semiconductor substrate, a plurality of wirings, and a plurality of interlayer insulating films. The semiconductor substrate has a main surface. The plurality of wirings are laminated above the main surface. A groove is formed in the main surface. An insulating film is embedded in the groove.

[0003] The wiring that is farthest from the main surface in the normal direction of the main surface is defined as the uppermost layer wiring. An interlayer insulating film is interposed between two adjacent wirings. The interlayer insulating film is also interposed between the wiring closest to the main surface in the normal direction of the main surface and the main surface.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor device described in Patent Document 1, cracks may occur in the interlayer insulating film near the end of the wiring portion of the uppermost layer wiring, and the cracks may extend through the interlayer insulating film toward the groove. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure comprises a semiconductor substrate having a first main surface and a second main surface located opposite the first main surface, a plurality of interlayer insulating films laminated on the first main surface along a first direction which is the normal direction to the first main surface, and a plurality of wirings. A groove is formed in the first main surface that is recessed toward the second main surface. The groove has a straight portion extending along a second direction which is perpendicular to the first direction. The plurality of interlayer insulating films have a first interlayer insulating film furthest from the first main surface in the first direction and a second interlayer insulating film in contact with the first interlayer insulating film in the first direction. The plurality of wirings have a first wiring that is located on the first interlayer insulating film and a second wiring that is located on the second interlayer insulating film so as to be covered by the first interlayer insulating film. The first wiring has a first wiring portion. The first wiring portion has a first end and a second end opposite to the first end in a third direction which is perpendicular to the first and second directions. The second wiring has a second wiring portion. The second wiring section has a third end and a fourth end opposite to the third end in the third direction. The distance between the straight section and the first end in the third direction is smaller than the distance between the straight section and the second end in the third direction, and is 0.5 times or less the first thickness of the first wiring. The distance between the first end and the third end in the third direction is smaller than the distance between the first end and the fourth end in the third direction, and is greater than 0.5 times the first thickness. [Effects of the Invention]

[0007] The semiconductor device of this disclosure makes it possible to suppress the extension of cracks in the interlayer insulating film near the first wiring portion. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of semiconductor device DEV1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 along line II-II in Figure 1. [Figure 3] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 4] This is a cross-sectional view illustrating the first ion implantation step S2. [Figure 5] This is a cross-sectional view illustrating the first groove formation process S3. [Figure 6] It is a cross-sectional view for explaining the first insulating film formation step S4. [Figure 7] It is a cross-sectional view for explaining the second groove formation step S5. [Figure 8] It is a cross-sectional view for explaining the second insulating film formation step S6. [Figure 9] It is a cross-sectional view for explaining the gate insulating film formation step S7. [Figure 10] It is a cross-sectional view for explaining the gate electrode formation step S8. [Figure 11] It is a cross-sectional view for explaining the second ion implantation step S9. [Figure 12] It is a cross-sectional view for explaining the first interlayer insulating film formation step S10. [Figure 13] It is a cross-sectional view for explaining the contact plug formation step S11. [Figure 14] It is a cross-sectional view for explaining the first wiring formation step S12. [Figure 15] It is a cross-sectional view for explaining the second interlayer insulating film formation step S13. [Figure 16] It is a cross-sectional view for explaining the via plug formation step S14. [Figure 17] It is a cross-sectional view for explaining the second wiring formation step S15. [Figure 18] It is a cross-sectional view of the semiconductor device DEV1 according to Modification 1. [Figure 19] It is a cross-sectional view of the semiconductor device DEV1 according to Modification 2. [Figure 20] It is a plan view of the semiconductor device DEV1 according to Modification 3. [Figure 21] It is a cross-sectional view of the semiconductor device DEV1 according to Modification 4. [Figure 22] It is a plan view of the semiconductor device DEV1 according to Modification 5. [Figure 23] It is a cross-sectional view of the semiconductor device DEV1 according to Modification 5 along XXIII-XXIII in FIG. 22. [Figure 24] It is a cross-sectional view of the semiconductor device DEV1 near the end WL1aa. [Figure 25A]It is a first graph showing the relationship between the distance from the end WL1aa in the third direction D3 and the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1aa. [Figure 25B] It is a second graph showing the relationship between the distance from the end WL1aa in the third direction D3 and the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1aa. [Figure 25C] It is a graph showing the relationship between the maximum value of the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1aa and the thickness T3. [Figure 25D] It is a graph showing the relationship between the position of the end WL2aa where the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1aa becomes the maximum value and the thickness T3. [Figure 26] It is a plan view of the semiconductor device DEV2. [Figure 27] It is a plan view of the semiconductor device DEV3. [Figure 28] It is a plan view of the semiconductor device DEV4. [Figure 29] It is a plan view of the semiconductor device DEV5.

Embodiments for Carrying Out the Invention

[0009] Embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and duplicate explanations will not be repeated.

[0010] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0011] <Configuration of the Semiconductor Device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0012] Figure 1 is a plan view of semiconductor device DEV1. Figure 2 is a cross-sectional view of semiconductor device DEV1 along line II-II in Figure 1. As shown in Figures 1 and 2, semiconductor device DEV1 comprises a semiconductor substrate SUB, insulating film IF1, insulating film IF2, insulating film IF3, gate insulating film GI, gate electrode GE, multiple wiring WL, and multiple interlayer insulating films ILD.

[0013] The semiconductor substrate SUB has a main surface MS1 and a main surface MS2 located on the opposite side of the main surface MS1. The normal direction of the main surface MS1 is defined as the first direction D1. The main surface MS2 is located on the opposite side of the main surface MS1 in the first direction D1. The semiconductor substrate SUB is formed from, for example, a single crystal of silicon (Si). The semiconductor substrate SUB may also have a laminated structure having a semiconductor substrate and an epitaxial growth layer formed on the semiconductor substrate. In this case, the source region SR, drain region DR, body region BR, and drift region DRI, which will be described later, are formed within the epitaxial growth layer.

[0014] A semiconductor substrate SUB has a source region SR, a drain region DR, a body region BR, and a drift region DRI. The conductivity type of the source region SR, the drain region DR, and the drift region DRI is the first conductivity type. The conductivity type of the body region BR is the second conductivity type. The second conductivity type is the opposite conductivity type of the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type. The dopant concentration in the source region SR and the dopant concentration in the drain region DR are higher than the dopant concentration in the drift region DRI.

[0015] The source region SR is located on the main surface MS1. The drain region DR is located on the main surface MS1. The source region SR and the drain region DR are spaced apart from each other. The body region BR is located on the main surface MS1 so as to surround the source region SR. The drift region DRI is located so as to surround the drain region DR.

[0016] A groove TR1 is formed on the main surface MS1. The groove TR1 is recessed toward the main surface MS2. The groove TR1 is located next to the drain region DR, between the source region SR and the drain region DR. The groove TR1 is surrounded by the drift region DRI. An insulating film IF1 is embedded in the groove TR1. The insulating film IF1 is formed of, for example, silicon oxide. That is, the insulating film IF1 is formed by the STI (Shallow Trench Isolation) method. The insulating film IF1 may be formed by the LOCOS (Local Oxidation of Silicon) method instead of the STI method. If sufficient breakdown voltage is ensured between the drain region DR and the gate electrode GE, the insulating film IF1 may not be formed.

[0017] The gate insulating film GI is located on the portion of the main surface MS1 between the source region SR and the groove TR1. The gate insulating film GI is formed of, for example, silicon oxide. The gate electrode GE is located on the gate insulating film GI. The gate electrode GE is formed of, for example, polycrystalline silicon containing a dopant. The source region SR, drain region DR, body region BR, drift region DRI, gate insulating film GI, and gate electrode GE constitute a transistor. This transistor is an LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor).

[0018] Grooves TR2 and TR3 are further formed on the main surface MS1. Groove TR2 is recessed toward the main surface MS2. Groove TR2 is formed to surround the transistor in a plan view. The insulating film IF2 is embedded in groove TR2. The insulating film IF2 is made of, for example, silicon oxide. The bottom of groove TR2 is positioned, for example, closer to the main surface MS1 than the bottom of the drift region DRI.

[0019] Groove TR3 is formed in the portion of the main surface MS1 located at the bottom of groove TR2. Groove TR3 is recessed toward the main surface MS2. The bottom of groove TR3 is located closer to the main surface MS2 than the bottom of the drift region DRI. In Figure 1, the position of groove TR3 is indicated by a dotted line. The insulating film IF3 is embedded in groove TR3. The insulating film IF3 is formed of, for example, silicon oxide.

[0020] The groove TR3 has straight sections TR3a, TR3b, TR3c, and TR3d. Straight sections TR3a and TR3b extend along the second direction D2. Straight sections TR3c and TR3d extend along the third direction D3. The second direction D2 is perpendicular to the first direction D1. The third direction D3 is perpendicular to both the first direction D1 and the second direction D2. Straight section TR3a has one end and the other end on the opposite side of the first end in the second direction D2. The one end and the other end of straight section TR3a are connected to straight sections TR3c and TR3d, respectively. Straight section TR3b has one end and the other end on the opposite side of the first end in the second direction D2. The one end and the other end of straight section TR3b are connected to straight sections TR3c and TR3d, respectively. From another perspective, groove TR3 is rectangular in plan view.

[0021] Multiple interlayer insulating films (ILDs) are stacked on the main surface MS1 along a first direction D1. The multiple interlayer insulating films (ILDs) are formed of, for example, silicon oxide. In the example shown in Figure 2, the number of multiple interlayer insulating films is 4. However, the number of multiple interlayer insulating films (ILDs) can be 2 or more. Of the multiple interlayer insulating films (ILDs), the interlayer insulating film ILD furthest from the main surface MS1 in the first direction D1 is designated as interlayer insulating film ILD1. Interlayer insulating film ILD1 is the uppermost interlayer insulating film ILD. The interlayer insulating film in contact with interlayer insulating film ILD1 in the first direction D1 is designated as interlayer insulating film ILD2. The interlayer insulating film ILD in contact with interlayer insulating film ILD2 on the side opposite to the side in contact with interlayer insulating film ILD1 in the first direction D1 is designated as interlayer insulating film ILD3. In the first direction D1, the interlayer insulating film ILD3 that is in contact with the interlayer insulating film ILD3 on the side opposite to the interlayer insulating film ILD2 is defined as interlayer insulating film ILD4.

[0022] Multiple wiring WLs are stacked on top of the main surface MS1. As shown in Figure 2, each wiring WL has wiring WL1, wiring WL2, wiring WL3, and wiring WL4. In the example shown in Figure 2, there are 4 wiring WLs. However, the number of wiring WLs can be 2 or more. The wiring WLs are formed of, for example, aluminum (Al) or an aluminum alloy.

[0023] Wiring WL1 is located on the interlayer insulating film ILD1, i.e., it is the uppermost wiring WL. Wiring WL2 is located on the interlayer insulating film ILD2 and is covered by the interlayer insulating film ILD1. Wiring WL3 is located on the interlayer insulating film ILD3 and is covered by the interlayer insulating film ILD2. Wiring WL4 is located on the interlayer insulating film ILD4 and is covered by the interlayer insulating film ILD3. In the example shown in Figure 2, wiring WL4 is the wiring WL located closest to the main surface MS1 in the first direction D1.

[0024] The thickness T1 of wiring WL1 is, for example, greater than the thickness T2 of wiring WL2. It is preferable that the thickness T1 is 5 times, 7 times, or 10 times greater than the thickness T2. The thickness T3 of the interlayer insulating film ILD2 formed on wiring WL2 is preferably 0.5 μm or more, 1.0 μm or more, or 1.5 μm or more.

[0025] Wiring WL1 has wiring section WL1a and wiring section WL1b. Wiring section WL1a and wiring section WL1b are spaced apart in the third direction D3.

[0026] The wiring section WL1a has an end WL1aa and an end WL1ab opposite to end WL1aa in the third direction D3. End WL1aa faces wiring section WL1b with a gap between them. The distance DIS1 between end WL1aa and straight section TR3a in the third direction D3 is smaller than the distance between end WL1ab and straight section TR3a in the third direction D3. The straight section TR3a is, for example, located between wiring section WL1a and wiring section WL1b. The distance DIS1 is 0.5 times the thickness T1 or less.

[0027] The distance between the end WL1ab and the straight section TR3b in the third direction D3 is, for example, smaller than the distance between the end WL1aa and the straight section TR3b in the third direction D3. The straight section TR3b overlaps with the wiring section WL1a in a plan view, for example. The distance between the end WL1ab and the straight section TR3b in the third direction D3 may be 0.5 times or less the thickness T1 of the wiring WL1, or it may be greater than 0.5 times the thickness T1.

[0028] The wiring section WL1a has an end WL1ac and an end WL1ad opposite to end WL1ac in the second direction D2. The distance between end WL1ac and the straight section TR3c in the second direction D2 is, for example, smaller than the distance between end WL1ad and the straight section TR3c in the second direction D2. The distance between end WL1ad and the straight section TR3d in the second direction D2 is, for example, smaller than the distance between end WL1ac and the straight section TR3d in the second direction D2. The straight sections TR3c and TR3d overlap the wiring section WL1a in a plan view, for example. The distance between end WL1ac and the straight section TR3c and the distance between end WL1ad and the straight section TR3d in the second direction D2 may be 0.5 times the thickness T1 or less, or greater than 0.5 times the thickness T1.

[0029] Wiring WL2 has a wiring section WL2a. In Figure 1, the wiring section WL2a is shown by a dashed line. Wiring section WL2a has an end WL2aa and an end WL2ab opposite to end WL2aa in the third direction D3. Wiring section WL2a has an end WL2ac and an end WL2ad opposite to end WL2ac in the second direction D2.

[0030] End WL2aa is located, for example, between end WL1aa and end WL1ab in the third direction D3. That is, end WL2aa overlaps with wiring section WL1a in a plan view, for example. End WL2aa does not necessarily overlap with wiring section WL1a in a plan view. The distance DIS2 between end WL1aa and end WL2aa in the third direction D3 is smaller than the distance between end WL1aa and end WL2ab in the third direction D3. The distance DIS2 is greater than 0.5 times the thickness T1.

[0031] End WL2ab is located, for example, between end WL1aa and end WL1ab in the third direction D3. That is, end WL2ab may overlap with wiring section WL1a in a plan view, for example. End WL2ab does not have to be located between end WL1aa and end WL1ab in the third direction D3. In this case, the distance between end WL2ab and end WL1aa in the third direction D3 is greater than the distance between end WL2ab and end WL1ab in the third direction D3.

[0032] Distance DIS3, the distance between ends WL1ac and WL2ac in the second direction D2, is smaller than the distance between ends WL1ac and WL2ad. Similarly, distance DIS4, the distance between ends WL1ad and WL2ad in the second direction D2, is smaller than the distance between ends WL1ad and WL2ac in the second direction D2. Distances DIS3 and DIS4 may also be smaller than distance DIS2 between ends WL1aa and WL2aa in the third direction D3. Preferably, distances DIS3 and DIS4 are greater than 0.5 times the thickness T1.

[0033] Two adjacent wirings WL are electrically connected by via plugs VP. The via plugs VP are embedded in via holes formed in the interlayer insulating film ILD interposed between the two adjacent wirings WL. Wiring WL4 is electrically connected to the source region SR, drain region DR, and gate electrode GE by contact plugs CP. The contact plugs CP are embedded in contact holes formed in the interlayer insulating film ILD (interlayer insulating film ILD4) interposed between wiring WL4 and the main surface MS1. The via plugs VP and CP are made of, for example, tungsten (W).

[0034] <Manufacturing method for semiconductor device DEV1> The manufacturing method for the semiconductor device DEV1 is described below.

[0035] Figure 3 is a manufacturing process diagram for semiconductor device DEV1. As shown in Figure 3, the manufacturing method for semiconductor device DEV1 includes a preparation step S1, a first ion implantation step S2, a first groove formation step S3, a first insulating film formation step S4, a second groove formation step S5, a second insulating film formation step S6, a gate insulating film formation step S7, a gate electrode formation step S8, and a second ion implantation step S9.

[0036] The manufacturing method for semiconductor device DEV1 further includes a first interlayer insulating film formation step S10, a contact plug formation step S11, a first wiring formation step S12, a second interlayer insulating film formation step S13, a via plug formation step S14, and a second wiring formation step S15.

[0037] In preparation step S1, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB prepared in preparation step S1 may have a laminated structure having a semiconductor substrate and an epitaxial growth layer formed on the semiconductor substrate. Figure 4 is a cross-sectional view illustrating the first ion implantation step S2. As shown in Figure 4, in the first ion implantation step S2, a body region BR and a drift region DRI are formed by ion implantation.

[0038] Figure 5 is a cross-sectional view illustrating the first groove formation step S3. As shown in Figure 5, in the first groove formation step S3, grooves TR1 and TR2 are formed on the main surface MS1. Grooves TR1 and TR2 are formed, for example, by anisotropic dry etching. Figure 6 is a cross-sectional view illustrating the first insulating film formation step S4. As shown in Figure 6, in the first insulating film formation step S4, insulating films IF1 and IF2 are formed. Insulating films IF1 and IF2 are formed, for example, by embedding the constituent material of insulating film IF1 (insulating film IF2) into grooves TR1 and TR2, for example by CVD, and then removing the constituent material of insulating film IF1 (insulating film IF2) that has protruded from grooves TR1 and TR2 by CMP (Chemical Mechanical Polishing).

[0039] Figure 7 is a cross-sectional view illustrating the second groove formation step S5. As shown in Figure 7, groove TR3 is formed in the second groove formation step S5. Groove TR3 is formed, for example, by anisotropic dry etching. Figure 8 is a cross-sectional view illustrating the second insulating film formation step S6. As shown in Figure 8, insulating film IF3 is formed in the second insulating film formation step S6. Insulating film IF3 is formed, for example, by embedding the constituent material of insulating film IF3 in groove TR3, for example by CVD, and then removing the constituent material of insulating film IF3 that protrudes from groove TR3 by CMP.

[0040] Figure 9 is a cross-sectional view illustrating the gate insulating film formation process S7. As shown in Figure 9, in the gate insulating film formation process S7, the gate insulating film GI is formed by, for example, thermal oxidation. Figure 10 is a cross-sectional view illustrating the gate electrode formation process S8. As shown in Figure 10, in the gate electrode formation process S8, the gate electrode GE is formed. The gate electrode GE is formed by first depositing the constituent material of the gate electrode GE using, for example, a CVD method, and then patterning the deposited constituent material of the gate electrode GE by dry etching.

[0041] Figure 11 is a cross-sectional view illustrating the second ion implantation step S9. As shown in Figure 11, in the second ion implantation step S9, a source region SR and a drain region DR are formed by ion implantation. Figure 12 is a cross-sectional view illustrating the first interlayer insulating film formation step S10. As shown in Figure 12, in the first interlayer insulating film formation step S10, an interlayer insulating film ILD4 is formed. The interlayer insulating film ILD4 is formed by depositing the constituent material of the interlayer insulating film ILD4 by, for example, a CVD method, and then planarizing the deposited interlayer insulating film ILD4 constituent material by a CMP method.

[0042] Figure 13 is a cross-sectional view illustrating the contact plug formation process S11. As shown in Figure 13, in the contact plug formation process S11, a contact plug CP is formed. In the formation of the contact plug CP, firstly, contact holes are formed in the interlayer insulating film ILD4, for example by dry etching. Secondly, the constituent material of the contact plug CP is embedded in the contact holes, for example by CVD. Thirdly, the constituent material of the contact plug CP that has protruded from the contact holes is removed, for example by CMP. This forms the contact plug CP. Figure 14 is a cross-sectional view illustrating the first wiring formation process S12. As shown in Figure 14, in the first wiring formation process S12, wiring WL4 is formed. The wiring WL4 is formed by first depositing the constituent material of the wiring WL4 onto the interlayer insulating film ILD4 by sputtering, for example, and then patterning the deposited wiring WL4 constituent material by dry etching.

[0043] Figure 15 is a cross-sectional view illustrating the second interlayer insulating film formation process S13. As shown in Figure 13, in the second interlayer insulating film formation process S13, the interlayer insulating film ILD3 is formed on the interlayer insulating film ILD4 in the same manner as the interlayer insulating film ILD4, so as to cover the wiring WL4. Figure 16 is a cross-sectional view illustrating the via plug formation process S14. As shown in Figure 16, in the via plug formation process S14, a via plug VP is formed on the interlayer insulating film ILD3 in the same manner as the contact plug CP. Figure 17 is a cross-sectional view illustrating the second wiring formation process S15. As shown in Figure 17, in the second wiring formation process S15, the wiring WL3 is formed on the interlayer insulating film ILD3 in the same manner as the wiring WL4. The second interlayer insulating film formation step S13, the via plug formation step S14, and the second wiring formation step S15 are repeated to form the interlayer insulating film ILD2, the interlayer insulating film ILD1, the wiring WL2, the wiring WL1, the via plug VP connecting the wiring WL3 and wiring WL2, and the via plug VP connecting the wiring WL2 and wiring WL1. As a result, the semiconductor device DEV1 with the structure shown in Figures 1 and 2 is formed.

[0044] <Example 1> Figure 18 is a cross-sectional view of semiconductor device DEV1 according to Modification 1. As shown in Figure 18, air gaps AG may be present in the insulating film IF3. The presence of air gaps AG in the insulating film IF3 further enhances the insulating properties of the element isolation structure formed by the groove TR3 and the insulating film IF3.

[0045] <Modification 2> Figure 19 is a cross-sectional view of a semiconductor device DEV1 according to Modification 2. As shown in Figure 19, the semiconductor device DEV1 may further have a conductive layer CL. The conductive layer CL is formed of, for example, tungsten. The conductive layer CL is embedded in a groove TR3 and is electrically connected to the semiconductor substrate SUB at the bottom of the groove TR3. In this case, the insulating film IF3 is interposed between the inner wall surface of the groove TR3 and the conductive layer CL.

[0046] <Modification 3 and Modification 4> Figure 20 is a plan view of the semiconductor device DEV1 according to Modification 3. As shown in Figure 20, the straight section TR3a may overlap the wiring section WL1a in the second direction D2. That is, the entire groove TR3 may overlap the wiring section WL1a in a plan view. Figure 21 is a cross-sectional view of the semiconductor device DEV1 according to Modification 4. As shown in Figure 21, the semiconductor device DEV1 may not have an insulating film IF3. In this case, the distance DIS1 between the end WL1aa and the straight section TR3a in the third direction D3 becomes the distance between the groove TR2 and the end WL1aa in the third direction D3.

[0047] <Modification 5> Figure 22 is a plan view of semiconductor device DEV1 according to Modification 5. Figure 23 is a cross-sectional view of semiconductor device DEV1 according to Modification 5 along line XXIII-XXIII in Figure 22. As shown in Figures 22 and 23, the end WL2ab may not be between the ends WL1aa and WL1ab in the third direction D3, and the distance between the end WL2ab and WL1aa in the third direction D3 may be smaller than the distance between the ends WL2ab and WL1ab in the third direction D3.

[0048] <Effects of Semiconductor Device DEV1> The effects of semiconductor device DEV1 are explained below.

[0049] Figure 24 is a cross-sectional view of the semiconductor device DEV1 near the edge WL1aa. As shown in Figure 24, over-etching occurs when forming the wiring WL1, creating a step on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa. During the cooling process after dry etching for forming the wiring WL1, thermal stress concentrates at the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa due to the difference in thermal expansion coefficients between the wiring WL1 and the interlayer insulating film ILD1. This concentration of thermal stress becomes more pronounced as the thickness T1 increases (for example, when the thickness T1 is 5 times, 7 times, or 10 times or more the thickness T2). As a result, cracks may occur at the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa, and these cracks may extend through multiple interlayer insulating films ILD toward the straight section TR3a.

[0050] Figure 25A is the first graph showing the relationship between the distance from the edge WL1aa in the third direction D3 and the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa. Figure 25B is the second graph showing the relationship between the distance from the edge WL1aa in the third direction D3 and the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa. The graph in Figure 25A is the graph for the case where the edge WL2ab is not located between the edges WL1aa and WL1ab in the third direction D3, and the distance between the edge WL2ab and the edge WL1aa in the third direction D3 is greater than the distance between the edges WL2ab and WL1ab in the third direction D3 (Pattern 1). The graph in Figure 25B shows the case where end WL2ab is not located between ends WL1aa and WL1ab in the third direction D3, and the distance between end WL2ab and end WL1aa in the third direction D3 is smaller than the distance between end WL2ab and end WL1ab in the third direction D3 (Pattern 2).

[0051] In the graphs in Figures 25A and 25B, the distance from end WL1aa in the third direction D3 is considered negative when end WL2aa overlaps with wiring section WL1a in the third direction D3, and is considered positive when end WL2aa does not overlap with wiring section WL1a in the third direction D3. The graphs in Figures 25A and 25B were obtained by performing T-CAD (Technology Computer Aided Design) simulations with a thickness T1 of 3.0 μm and varying the thickness T3.

[0052] As shown in Figures 25A and 25B, the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa peaks within the range where the distance from the edge WL1aa in the third direction D3 is 1.5 μm or less (i.e., the distance from the edge WL1aa in the third direction D3 is 0.5 times the thickness T1 or less). In semiconductor device DEV1, the distance DIS2 between the edge WL1aa and the edge WL2aa in the third direction D3 is greater than 0.5 times the thickness T1, so the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa is smaller than the above peak. Therefore, the extension of the crack is suppressed in semiconductor device DEV1.

[0053] Figure 25C is a graph showing the relationship between the maximum value of thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa and the thickness T3. The graph in Figure 25C was obtained from the graphs in Figures 25A and 25B. As shown in Figure 25C, the maximum value of thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa decreases as the thickness T3 decreases. Therefore, in semiconductor device DEV1, by setting the thickness T3 to 0.5 μm or more (1.0 μm or more, 1.5 μm or more), it is possible to further suppress the extension of cracks caused by the concentration of thermal stress at the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa.

[0054] Figure 25D is a graph showing the relationship between the position of edge WL2aa where the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near edge WL1aa is at its maximum, and the thickness T3. The graph in Figure 25D was obtained from the graphs in Figures 25A and 25B. As shown in Figure 25D, the smaller the thickness T3, the smaller the distance between the position of edge WL2aa where the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near edge WL1aa is at its maximum and edge WL1aa. Therefore, by reducing the thickness T3, edge WL2aa can be placed closer to edge WL1aa, increasing the degree of freedom in wiring arrangement compared to when the thickness T3 is not small.

[0055] Based on Figure 25D, if we let X (in μm) be the distance between the point where the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa is at its maximum and the edge WL1aa, and let T3 (in μm) be the thickness T3, then X is 0.6T3 + 0.1 in the first pattern and -0.4 - 0.02T3 in the second pattern. If X is a negative value in this equation, it means that the point where the thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near the edge WL1aa is at its maximum coincides with the wiring section WL1a in the third direction D3.

[0056] Similarly, a step is formed on the upper surface of the interlayer insulating film ILD1 near the end WL1ac. While end WL1aa receives overlapping stress from the wiring section WL1b, end WL1ac does not receive overlapping stress from the adjacent wiring section. Therefore, thermal stress is less likely to concentrate on the step near end WL1ac than on the step near end WL1aa. As a result, even if the distance DIS3 between end WL1ac and end WL2ac in the second direction D2 is made smaller than the distance DIS1 between end WL1aa and the straight section TR3a in the third direction D3, it is possible to suppress the extension of cracks caused by thermal stress acting on the step formed on the upper surface of the interlayer insulating film ILD1 near end WL1ac.

[0057] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, the differences from the semiconductor device DEV1 will be mainly explained, and redundant explanations will not be repeated.

[0058] <Configuration of Semiconductor Device DEV2> The configuration of the semiconductor device DEV2 is described below.

[0059] The semiconductor device DEV2 comprises a semiconductor substrate SUB, insulating films IF1, IF2, and IF3, a gate insulating film GI, a gate electrode GE, multiple wirings WL, multiple interlayer insulating films ILD, a contact plug CP, and a via plug VP. In this respect, the configuration of semiconductor device DEV2 is the same as that of semiconductor device DEV1.

[0060] Figure 26 is a plan view of the semiconductor device DEV2. As shown in Figure 26, in the semiconductor device DEV2, the wiring WL3 has a wiring portion WL3a. The wiring portion WL3a extends along the third direction D3 so as to intersect with region R. Region R is a region located within a certain distance from the end WL1aa in the third direction D3, and this certain distance is 0.5 times or less of the thickness T1. Note that both ends of region R in the second direction D2 may be in positions that protrude from, for example, the ends WL1ac and WL1ad, respectively. This protrusion distance is, for example, 10 μm.

[0061] The wiring section WL3a has an end WL3aa and an end WL3ab opposite to end WL3aa in the third direction D3. End WL3aa overlaps with the wiring section WL1b in the third direction D3, for example. End WL3ab overlaps with the wiring section WL1a in the third direction D3, for example.

[0062] The wiring section WL3a has an end WL3ac and an end WL3ad opposite to end WL3ac in the second direction D2. The distance DIS5 between end WL3ac and the straight section TR3c in the second direction D2 is smaller than the distance between end WL3ac and the straight section TR3d in the second direction D2. The distance DIS6 between end WL3ad and TR3d in the second direction D2 is smaller than the distance between end WL3ad and the straight section TR3c in the second direction D2. The straight sections TR3c and TR3d are located between end WL3ac and end WL3ad in the second direction D2. Distances DIS5 and DIS6 are preferably 0.5 times the thickness T1 or more, and more preferably 1.0 times the thickness T1 or more. In these respects, the configuration of semiconductor device DEV2 differs from the configuration of semiconductor device DEV1.

[0063] <Effects of Semiconductor Device DEV2> The effects of the semiconductor device DEV2 are explained below.

[0064] In semiconductor device DEV2, the wiring portion WL3a extends along the third direction D3 so as to intersect with region R. Therefore, even if a crack occurs due to thermal stress acting on a step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1ac, and even if the crack extends through the interlayer insulating film ILD toward the straight portion TR3a, the extension of the crack is more likely to stop upon contact with the wiring portion WL3a. As a result, in semiconductor device DEV2, the crack is less likely to extend to a layer below the wiring WL3.

[0065] (Third embodiment) The semiconductor device DEV3 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0066] <Configuration of Semiconductor Device DEV3> The configuration of semiconductor device DEV3 is described below.

[0067] The semiconductor device DEV3 comprises a semiconductor substrate SUB, insulating films IF1, IF2, and IF3, a gate insulating film GI, a gate electrode GE, multiple wirings WL, multiple interlayer insulating films ILD, a contact plug CP, and a via plug VP. In this respect, the configuration of semiconductor device DEV3 is the same as that of semiconductor device DEV2.

[0068] Figure 27 is a plan view of semiconductor device DEV3. As shown in Figure 27, in semiconductor device DEV3, the distance DIS7 between edge WL3aa and edge WL1aa in the third direction D3 is smaller than the distance between edge WL3ab and edge WL1aa in the third direction D3. The distance DIS7 is greater than 0.5 times the thickness T1. Preferably, the distance DIS7 is 1.0 times or more the thickness T1. In these respects, the configuration of semiconductor device DEV3 differs from the configuration of semiconductor device DEV2.

[0069] <Effects of Semiconductor Device DEV3> The effects of the semiconductor device DEV3 are explained below.

[0070] When a crack is generated due to thermal stress acting on a step formed on the upper surface of the interlayer insulating film ILD1 near WL1ac, and the crack extends to the vicinity of the end WL3aa, if the distance between the end WL1aa and the end WL3aa in the third direction D3 is small, stress concentrates at the tip of the crack, causing it to extend further.

[0071] In semiconductor device DEV3, the distance DIS7 is large, exceeding 0.5 times the thickness T1. Therefore, even if the crack extends to the vicinity of the edge WL3aa, stress concentration at the tip of the crack is suppressed. Thus, according to semiconductor device DEV3, even if the crack extends to the vicinity of the edge WL3aa, further extension of the crack can be suppressed.

[0072] (Fourth Embodiment) The semiconductor device DEV4 according to the fourth embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0073] <Configuration of semiconductor device DEV4> The configuration of semiconductor device DEV4 is described below.

[0074] The semiconductor device DEV4 comprises a semiconductor substrate SUB, insulating films IF1, IF2, and IF3, a gate insulating film GI, a gate electrode GE, multiple wirings WL, multiple interlayer insulating films ILD, a contact plug CP, and a via plug VP. In this respect, the configuration of semiconductor device DEV4 is the same as that of semiconductor device DEV2.

[0075] Figure 28 is a plan view of semiconductor device DEV4. As shown in Figure 28, in semiconductor device DEV3, the wiring WL3 further includes dummy wiring sections WL3b and WL3c. The dummy wiring sections WL3b and WL3c extend along a third direction D3 so as to intersect with region R. Wiring section WL3a is positioned between dummy wiring sections WL3b and WL3c in a second direction D2. The width of dummy wiring section WL3b in the second direction D2 and the width of dummy wiring section WL3c in the second direction D2 are preferably 10 μm or more. The width of dummy wiring section WL3b in the second direction D2 and the width of dummy wiring section WL3c in the second direction D2 are preferably 20 μm or more. The width of the wiring section WL3a in the second direction D2 is preferably less than or equal to the distance between the wiring section WL3a and the dummy wiring section WL3b (dummy wiring section WL3c) in the second direction D2.

[0076] In the example shown in Figure 28, there is one wiring section WL3a positioned between dummy wiring section WL3b and dummy wiring section WL3c, but there may be multiple wiring sections WL3a positioned between dummy wiring section WL3b and dummy wiring section WL3c. In semiconductor device DEV4, although not shown, wiring WL3 may have other dummy wiring sections. Dummy wiring sections WL3b and WL3c are positioned between other dummy wiring sections in the second direction D2. In these respects, the configuration of semiconductor device DEV4 differs from the configuration of semiconductor device DEV2.

[0077] <Effects of Semiconductor Device DEV4> The effects of the semiconductor device DEV4 are explained below.

[0078] As described above, in semiconductor device DEV2, the wiring portion WL3a extends along the third direction D3 so as to intersect with region R. Therefore, even if a crack occurs due to thermal stress acting on a step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1ac, and even if the crack extends through the interlayer insulating film ILD toward the straight portion TR3a, the extension of the crack is likely to be stopped by contact with the wiring portion WL3a.

[0079] However, if the crack described above extends in a direction deviating from the wiring section WL3a, the wiring section WL3a cannot stop the crack. In semiconductor device DEV4, dummy wiring sections WL3b and WL3c are positioned next to the wiring section WL3a, extending along the third direction D3 so as to intersect with region R. Therefore, even if the direction of extension of the crack described above deviates from the wiring section WL3a, the extension of the crack can be easily stopped by the dummy wiring sections WL3b and WL3c.

[0080] (Fifth embodiment) The semiconductor device DEV5 according to the fifth embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0081] <Configuration of Semiconductor Device DEV5> The configuration of the semiconductor device DEV5 is described below.

[0082] The semiconductor device DEV5 comprises a semiconductor substrate SUB, insulating films IF1, IF2, and IF3, a gate insulating film GI, a gate electrode GE, multiple wirings WL, multiple interlayer insulating films ILD, a contact plug CP, and a via plug VP. In this respect, the configuration of semiconductor device DEV5 is the same as that of semiconductor device DEV2.

[0083] Figure 29 is a plan view of semiconductor device DEV5. As shown in Figure 29, in semiconductor device DEV5, the wiring WL3 does not have a wiring portion WL3a, but rather has a dummy wiring portion WL3d. The dummy wiring portion WL3d extends along a third direction D3 so as to intersect with region R. The width of the dummy wiring portion WL3d in the third direction D3 is preferably 20 μm or more. Although not shown, in semiconductor device DEV5, the wiring WL3 may further have other dummy wiring portions.

[0084] In semiconductor device DEV5, the wiring WL4 has a wiring portion WL4a. The wiring portion WL4a extends along a third direction D3 so as to intersect with region R. The wiring portion WL4a has an end WL4aa and an end WL4ab opposite to the end WL4aa in the third direction D3. The end WL4aa overlaps, for example, the wiring portion WL1b in the third direction D3. The end WL4ab overlaps, for example, the wiring portion WL1a in the third direction D3. The wiring portion WL4a overlaps with a dummy wiring portion WL3d in the second direction D2. The distance between the end of the dummy wiring portion WL3d in the second direction D2 and the end of the wiring portion WL4a in the second direction D2 is preferably 10 μm or more. In these respects, the configuration of semiconductor device DEV5 differs from the configuration of semiconductor device DEV2.

[0085] <Effects of the DEV5 semiconductor device> The effects of the semiconductor device DEV5 are explained below.

[0086] In semiconductor device DEV5, the dummy wiring section WL3d extends along the third direction D3 so as to intersect with region R. Therefore, even if a crack occurs due to thermal stress acting on a step formed on the upper surface of the interlayer insulating film ILD1 near the end WL1ac, and this crack extends through the interlayer insulating film ILD toward the straight section TR3a, the extension of the crack is more likely to stop upon contact with the dummy wiring section WL3d. As a result, semiconductor device DEV5 makes it less likely for the crack to extend to a layer below the wiring WL3, thus protecting the wiring section WL4a from the crack.

[0087] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0088] BR Body region, CL Conductor layer, CP Contact plug, D1 First direction, D2 Second direction, D3 Third direction, DEV1, DEV2, DEV3, DEV4, DEV5 Semiconductor device, DIS1, DIS2, DIS3, DIS4, DIS5, DIS6, DIS7 Distance, DR Drain region, DRI Drift region, GE Gate gate, GI Gate insulating film, IF1, IF2, IF3 Insulating film, ILD, ILD1, ILD2 Interlayer insulating film, MS1 Main surface, MS2 Main surface, R Region, S1 Preparation process, S2 First ion implantation process, S3 First groove formation process, S4 First insulating film formation process, S5 Second groove formation process, S6 Second insulating film formation process, S7 Gate insulating film formation process, S8 Gate gate formation process, S9 Second ion implantation process, S10 First interlayer insulating film formation process, S11 Contact plug formation process, S12 S13 First wiring formation process, S14 Second interlayer insulating film formation process, S14 Via plug formation process, S15 Second wiring formation process, SR Source region, SUB Semiconductor substrate, T1, T2, T3 Thickness, TR1 Groove, TR2 Groove, TR3 Groove, TR3a, TR3b, TR3c, TR3d Straight section, VP Via plug, WL Wiring, WL1, WL2, WL3, WL4 Wiring, WL1aa, WL1ab, WL1ac, WL1ad, WL2aa, WL2ab, WL2ac, WL2ad, WL3aa, WL3ab, WL3ac, WL3ad, WL4aa, WL4ab End, WL1a, WL1b, WL2a, WL3a, WL4a Wiring section, WL3b, WL3c, WL3d Dummy wiring section.

Claims

1. A semiconductor substrate having a first main surface and a second main surface located on the opposite side of the first main surface, A plurality of interlayer insulating films are stacked on the first main surface along a first direction which is the normal direction of the first main surface, Equipped with multiple wirings, The first main surface has grooves formed therein that are recessed toward the second main surface. The groove has a straight portion extending along a second direction perpendicular to the first direction, The plurality of interlayer insulating films each have a first interlayer insulating film that is furthest from the first main surface in the first direction, and a second interlayer insulating film that is in contact with the first interlayer insulating film in the first direction. The plurality of wirings include a first wiring arranged on the first interlayer insulating film and a second wiring arranged on the second interlayer insulating film so as to be covered by the first interlayer insulating film. The first wiring has a first wiring section, The first wiring section has a first end and a second end opposite to the first end in a third direction perpendicular to the first and second directions. The aforementioned second wiring has a second wiring section, The second wiring portion has a third end and a fourth end opposite to the third end in the third direction. The distance between the straight portion and the first end in the third direction is smaller than the distance between the straight portion and the second end in the third direction, and is 0.5 times or less the first thickness of the first wiring. The distance between the first end and the third end in the third direction is smaller than the distance between the first end and the fourth end in the third direction, and is greater than 0.5 times the first thickness. The first wiring further comprises a third wiring section, The third wiring section is arranged in the third direction with a gap between it and the first end. The upper surface of the first interlayer insulating film has a first portion located below the first wiring portion and a second portion located between the first end and the third wiring portion in the third direction, and a step is formed at the boundary between the first portion and the second portion such that the second portion is recessed relative to the first portion, wherein the semiconductor device has a step.

2. The semiconductor device according to claim 1, wherein, in a plan view, the straight portion is arranged between the first wiring portion and the third wiring portion in the third direction.

3. The first wiring section has a fifth end and a sixth end opposite to the fifth end in the second direction. The second wiring portion has a seventh end and an eighth end opposite to the seventh end in the second direction. The semiconductor device according to claim 1, wherein the distance between the fifth end and the seventh end in the second direction is smaller than the distance between the fifth end and the eighth end in the second direction, and smaller than the distance between the first end and the third end in the third direction.

4. The semiconductor device according to claim 1, wherein the linear portion overlaps the first wiring portion in the second direction.

5. The semiconductor device according to claim 1, wherein the first thickness is 10 times or more the second thickness of the second wiring.

6. The plurality of interlayer insulating films further have a third interlayer insulating film that is in contact with the second interlayer insulating film on the side opposite to the side of the second interlayer insulating film that is in contact with the first interlayer insulating film in the first direction. The plurality of wirings further comprises a third wiring arranged on the third interlayer insulating film so as to be covered by the second interlayer insulating film, The third wiring has a fourth wiring section, The fourth wiring portion extends along the third direction so as to intersect with a region located within a certain distance from the first end in the third direction, The semiconductor device according to claim 1, wherein the aforementioned certain distance is 0.5 times or less the first thickness.

7. The third wiring further comprises a first dummy wiring section and a second dummy wiring section extending along the third direction so as to intersect with the region. The semiconductor device according to claim 6, wherein the fourth wiring portion is arranged between the first dummy wiring portion and the second dummy wiring portion in the second direction.

8. The plurality of interlayer insulating films further have a third interlayer insulating film that is in contact with the second interlayer insulating film on the side opposite to the side of the second interlayer insulating film that is in contact with the first interlayer insulating film in the first direction. The plurality of wirings further comprises a third wiring arranged on the third interlayer insulating film so as to be covered by the second interlayer insulating film, The third wiring has a fourth wiring section, The fourth wiring section has a ninth end and a tenth end opposite to the ninth end in the third direction. The semiconductor device according to claim 1, wherein the distance between the first end and the ninth end in the third direction is smaller than the distance between the first end and the tenth end in the third direction, and is 0.5 times or more the first thickness.

9. The plurality of interlayer insulating films further comprises a third interlayer insulating film in contact with the second interlayer insulating film on the side opposite to the side of the second interlayer insulating film that is in contact with the first interlayer insulating film in the first direction, and a fourth interlayer insulating film in contact with the third interlayer insulating film on the side opposite to the side of the third interlayer insulating film that is in contact with the second interlayer insulating film in the first direction. The plurality of wirings further comprises a third wiring arranged on the third interlayer insulating film so as to be covered by the second interlayer insulating film, and a fourth wiring arranged on the fourth interlayer insulating film so as to be covered by the third interlayer insulating film. The third wiring has a third dummy wiring section, The third dummy wiring section extends along the third direction so as to intersect with a region located within a certain distance from the first end in the third direction. The aforementioned certain distance is 0.5 times or less the first thickness. The fourth wiring section has a fifth wiring section, The fifth wiring section extends along the third direction so as to intersect with the region, The semiconductor device according to claim 1, wherein the fifth wiring portion overlaps with the third dummy wiring portion in the second direction.

10. The semiconductor device according to claim 1, further comprising an insulating film embedded in the groove.

11. The semiconductor device according to claim 10, wherein a cavity is provided inside the insulating film.

12. The semiconductor substrate has a source region disposed on the first main surface, a drain region disposed on the first main surface at a distance from the source region, a body region disposed on the first main surface so as to surround the source region, and a drift region disposed so as to surround the drain region. The semiconductor device according to claim 10, wherein the bottom of the groove is positioned closer to the second main surface than the drift region with respect to the second main surface.

13. The conductive layer embedded in the groove, The system further comprises an insulating film interposed between the conductive layer and the inner wall surface of the groove, The semiconductor device according to claim 1, wherein the conductive layer is electrically connected to the semiconductor substrate at the bottom of the groove.

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