FMCW Chirp Bandwidth Control

Abstract

In the described example, a frequency modulated continuous wave (FMCW) synthesizer (208) includes a control engine (304) and a phase locked loop (302) (PLL), which includes a frequency divider (310), a control voltage generator (CVG), and a voltage controlled oscillator VCO (330). The frequency divider varies the VCO output frequency based on a control input (340). The CVG generates a control voltage (328) based on the frequency reference (308) and the divider output. The VCO outputs an FMCW output (336) having a VCO output frequency in response to the control voltage (328). The control engine (304) generates the control input (340) such that the VCO output frequency is at a first frequency from a first time to a second time, changes at a first rate from the second time to a third time, changes at a second rate different from the first rate from the third time to a fourth time, and is at the second frequency from the fourth time to a fifth time.

Description

[Technical Field]

[0001] This application relates in general to frequency-modulated continuous-wave (FMCW) radar, and more specifically to the accurate generation of FMCW chirp waveforms. [Background technology]

[0002] Conventional high-speed FMCW radar systems include an FMCW synthesizer, which generates chirp signals, which are processed (e.g., phase shifted, amplified) and transmitted. When an FMCW radar system receives a reflection of a transmitted chirp signal from an object, it can process these signals to determine the distance, speed, and range to that object. Each chirp signal undergoes frequency slewing up and down over a period of time.

[0003] Figure 1 shows an illustrative diagram of a conventional FMCW signal 100 generated by a conventional FMCW synthesizer, with frequency on the vertical axis and time on the horizontal axis. Figure 1 also shows a corresponding control timing diagram 102, with control signals on the vertical axis and time on the horizontal axis. The control timing diagram 102 shows a number of control signals 104 (sometimes referred to as control words), where a start pulse initiates action on the corresponding control signals 104, represented as vertical lines occurring at various times (t0, t1, etc.). Each control signal 104 has a corresponding number of pairs, including a start frequency (F0 in each of the illustrative control signals 104 in Figure 1) and a gradient for generating a subsequent chirp frequency (0 or s1 in the illustrative control signals 104 in Figure 1). The gradient corresponds to the change in frequency per unit time, e.g., ΔHz / s.

[0004] The interval t0~t1 is an idle time 106, during which no FMCW chirp is transmitted. This idle time begins at time t0, when the control signal 104(F0,0) causes the FMCW synthesizer to generate a frequency F0 with a gradient of 0, producing a constant tone with frequency F0110. Time t1~t2 corresponds to the generation and transmission of the FMCW chirp 108. At time t1, the control signal 104(F0, s1) instructs the FMCW synthesizer 108 to start at frequency F0, pass the output frequency 112 higher with a gradient s1, and generate the FMCW chirp 108. At time t2, the FMCW chirp 108 has reached frequency F1 (the maximum frequency 114 of the FMCW chirp 108). The maximum frequency 114 of the FMCW chirp 108F1 corresponds to the starting frequency F0 plus the gradient of the FMCW chirp 108 multiplied by the duration of the FMCW chirp 108, which can be expressed as F1 = F0 + s1 × (t2 - t1).

[0005] The interval t2~t3 corresponds to the idle time 106. The control signal 104(F0,0) at time t2 causes the FMCW synthesizer to attempt to directly change its output to frequency F0 using an intended waveform 116 that may have a conventional sawtooth pattern. However, the result of this change in frequency separability may be an actual waveform 118 that includes an unintended overshoot 120 above the target new starting frequency F0. Such overshoots may result in an additional resettling time before the FMCW signal 100 stabilizes and before the generation of the next FMCW chirp 108 is possible. A reduced FMCW chirp 108 rate reduces the number of data samples that can be collected, thus degrading the accuracy of the FMCW radar system. Some FMCW radars do not collect radar data samples during the settling time, or do not use collected data samples during the settling time, in order to determine the presence, range, and speed of a target.

[0006] In some cases, the FMCW radar system operates within the allocated bandwidth, and a frequency overshoot 120 may cause the FMCW signal to exceed the allocated bandwidth. In some cases, F0 and F1 are selected so that any overshoot 120 remains within the allocated bandwidth. However, this may reduce the accuracy of the FMCW radar system, because the accuracy of the FMCW radar system is proportional to the bandwidth of the transmitted FMCW chirp 108. In some cases, the radar system power amplifier is turned off to prevent transmission during idle time 106. However, this may result in additional resettling time in the FMCW radar system receiver, because it transitions between not receiving a signal and receiving a signal, and receiver accuracy may be reduced during resettling. Also, turning the FMCW radar system power amplifier 118 off and on may result in additional resettling time in the FMCW synthesizer, because the power amplifier state transitions pull the frequencies generated by the FMCW synthesizer. [Overview of the Initiative]

[0007] In the examples described, a frequency-modulated continuous wave (FMCW) synthesizer includes a control engine and a phase-locked loop (PLL), the PLL including a frequency divider, a control voltage generator (CVG), and a voltage-controlled oscillator (VCO). The frequency divider modulates the VCO output frequency based on the control input. The CVG generates a control voltage based on a frequency reference and the divider output. The VCO outputs an FMCW output having a VCO output frequency in response to the control voltage. The control engine generates the control input such that the VCO output frequency is a first frequency from the first to the second time, changes at a first rate from the second to the third time, changes at a second rate different from the first rate from the third to the fourth time, and is a second frequency from the fourth to the fifth time. [Brief explanation of the drawing]

[0008] [Figure 1] FIG. showing an example of an FMCW signal generated by a prior art FMCW synthesizer, and a corresponding control timing diagram.

[0009] [Figure 2] FIG. showing an exemplary functional block layout of an FMCW radar system.

[0010] [Figure 3] FIG. showing an exemplary functional block layout of the FMCW synthesizer of FIG. 2.

[0011] [Figure 4] FIG. showing an example of an FMCW signal generated by the FMCW synthesizer of FIG. 3, and a corresponding control timing diagram.

[0012] [Figure 5] FIG. showing an example of an FMCW signal generated by the FMCW synthesizer of FIG. 3, and a corresponding control timing diagram. <0OO0092>

[0013] [Figure 6] FIG. showing an example of a process for generating an FMCW signal.

[0014] [Figure 7] FIG. showing an exemplary process 700 for operating the FMCW radar system 200 of FIG. 2 including the FMCW synthesizer 208 of FIG. 3.

BEST MODE FOR CARRYING OUT THE INVENTION

[0015] Figure 2 shows an illustrative functional block layout of a prior art FMCW radar system 200, which has certain characteristics known in the art, but the system is further improved by the teachings herein. The system 200 includes a receiver (RX) 202, which receives signals and outputs them to a low-noise amplifier (LNA) 204. The receiver 202 may include multiple receiver sensors to enable determination of information such as distance, speed, and range. The LNA 204 outputs to a mixer 206. An FMCW synthesizer 208 generates an FMCW chirp to be transmitted (for example, for object detection and range determination). The FMCW synthesizer 208 outputs the FMCW chirp to the mixer 206 and a phase-shift block 210. Mixer 206 mixes the amplified received signal from LNA 204 with the chirp from FMCW synthesizer 208 and outputs it to bandpass filter / variable gain amplifier (BPF / VGA) 212. BPF / VGA 212 outputs to analog-to-digital converter (ADC) 214, which outputs to digital signal processor (DSP) 216 or other analysis components. Phase shift block 210 outputs the phase-shifted FMCW chirp to power amplifier (PA) 118, which outputs to transmitter (TX) 220.

[0016] In the system 200 of Figure 2, the transmitter 220 transmits an amplified and phase-shifted FMCW chirp 222, which can be reflected from objects within the range 224 of the transmitted FMCW chirp 222. (The range of an FMCW radar, such as the FMCW radar system 200, depends, for example, on the modulation frequency of the transmitted signal, the frequency change per unit time of the chirp in the transmitted signal, i.e., the "slope" or "through" of the chirp in the transmitted signal, the bandwidth of the BPF, and the ADC sampling rate.) The reflected FMCW signal 224 is received by the receiver 202. The DSP 216 may be used to determine information about objects within the range 224, such as distance, direction, and speed.

[0017] Figure 3 shows an illustrative functional block layout of the FMCW synthesizer 208 of Figure 2. The FMCW synthesizer 208 includes a phase-locked loop (PLL) 302 and a timing and control engine 304. In the PLL 302, a phase frequency detector (PFD) 306 sets the frequency reference 308 to a reference frequency F ref The PFD 306 receives the signal as input, and also receives the output of the frequency divider 310 as input. The PFD 306 outputs UP and DN (down) control signals to the charge pump (CP) 312. The CP 312 outputs a control signal to the filter 314, which generates the filtered control signal VCTRL 328.

[0018] Filter 314 has a first resistor R F A first resistor 316 having and a second resistor R z A second resistor 318 having and a third resistor R F A third resistor 320 having a first capacitance C z A first capacitor 322 having a second capacitance C F A second capacitor 324 having a third capacitance C F The circuit includes a third capacitor 326 having a first terminal of the first resistor 316 and a first terminal of the second resistor 318. The second terminal of the second resistor 318 is connected to the first plate of the first capacitor 322. The second terminal of the first resistor 316 is connected to the first terminal of the third resistor 320 and the first plate of the second capacitor 324. The second terminal of the third resistor is connected to the first plate of the third capacitor 326, and is used to output the filtered control signal VCTRL 328 from the filter 314 to the voltage-controlled oscillator (VCO) 330. A reference node 332 of a reference voltage GRND, such as the ground voltage, is connected to the second plate of the first capacitor 322, the second plate of the second capacitor 324, and the second plate of the third capacitor 326.

[0019] VCO 330 outputs to buffer (BUF) 334, and buffer (BUF) 334 outputs an FMCW output signal 336 at frequency F0 from FMCW synthesizer 208. Also, buffer 334 outputs the FMCW output signal 336 to frequency divider 310. Frequency divider 310 outputs to PFD 306 and digital ramp generator 338 (as described above). Digital ramp generator 338 is connected to receive timing and control signal 340 from timing and control device 304. Timing and control signal 340 can include, for example, a start frequency, a slope, and a start pulse (for starting execution based on the start frequency and slope). Timing and control engine 304 can be a low-speed timing and control engine. Timing and control engine 304 can also be clocked by a clock (not shown) that has a fixed frequency relationship to reference frequency F ref and can be clocked by, for example, a 40 MHz clock, and F ref is equal to 900 MHz.

[0020] Digital ramp generator 338 is connected to frequency divider 310, CP 312, and filter 314. The connection from digital ramp generator 338 to CP 312 and filter 314 is shown as a single line for clarity, but can correspond to separate signals transmitted via separate lines.

[0021] Frequency divider 310 divides the FMCW output signal 336 by number N and outputs a signal at frequency F0 / N. PFD 306 compares the reference frequency F ref with the frequency divider output frequency F0 / N and outputs UP and DN control signals to make these two frequencies equal. Thus, F ref 0 = N × F

[0022] Figure 4 shows an example of the FMCW signal generated by the FMCW synthesizer 208 in Figure 3, as well as the corresponding control timing diagram 402. The control timing diagram 402 shows multiple control signals 404 (sometimes referred to as control words), and includes an initiation pulse to start action for the corresponding control signals 404, which are represented as vertical lines occurring at various times (t0, t1, etc.). The control signals 404 are generated by the timing and control engine 304, and the digital ramp generator 338 uses the control signals 404 to control the frequency divider 310. The frequency divider 310 adjusts N in response to the control by the digital ramp generator 338 and changes the FMCW signal 400 (corresponding to the FMCW output signal 336) accordingly. As described above, the FMCW output frequency is N × F ref Each control signal 404 has a corresponding pair of signals, each including a starting frequency (F0 or F1 of the example control signal 404 in Figure 4) and a gradient for generating a subsequent chirp frequency (0, s1, or s2 of the example control signal 404 in Figure 4). The gradient corresponds to the change in frequency per unit time, e.g., ΔHz / s.

[0023] The interval t0 to t1 is an idle time 406 during which no FMCW chirp is transmitted. At time t0, the control signal 404(F0,0) instructs the FMCW synthesizer 208 to generate a frequency F0 with a zero gradient, and a constant tone at frequency F0410. The interval t1 to t2 corresponds to the generation and transmission of the FMCW chirp 408. At time t1, the control signal 404(F0, s1) instructs the FMCW synthesizer 208 to start at frequency F0, and to slew the output frequency 412 higher with a gradient s1, thereby generating the FMCW chirp 408. At time t2, the FMCW chirp 408 has reached frequency F1 (the maximum frequency 414 of the FMCW chirp 408). The maximum frequency of FMCW chirp 408F1, 414, corresponds to adding the sum of the gradient of FMCW chirp 408 multiplied by its duration to the starting frequency F0, which can be expressed as F1 = F0 + s1 × (t2 - t1).

[0024] The timing and control engine 304 can calculate F1 as shown, and F1, F0, and ramp-down period T down Based on 420, we can calculate s2, where T down This is the time period during which the FMCW chirp 408 passes down from its maximum frequency 414 to F0. Therefore, T down 420 can be selected. For example, T down 420 may be selected, F0, F1, and T down Based on this, s2 can be calculated, and the cycle slip is: s2 = (F0 - F1) / T down This can be avoided. Cycle slip is a slip of a cycle relative to the frequency reference 308 and corresponds to the phase lock loss in PLL302. Cycle slip can be caused by a gradient s2 higher than what PLL302 can tolerate.

[0025] The interval t2~t4 corresponds to the idle time 406. An ideal sawtooth pattern includes a zero-time return 416 to the chirp start frequency F0. However, to avoid overshoot when returning to the chirp start frequency F0, the control signal 404(F1, s2) at time t2 causes the FMCW synthesizer 208 to start at frequency F1 and pass the output frequency 418 lower with a linear gradient s2. This creates a controlled time period T, which is the time interval from t2 to t3. down Over 420, the output frequency returns to the chirp start frequency F0. For example, s1 can be 100 MHz / microsecond and s2 can be 1000 MHz / microsecond, allowing for higher FMCW chirp 408 repetition frequencies and thus shorter periods for repetition of the FMCW chirp waveform. The FMCW chirp waveform corresponds to the idle time 406 plus the FMCW chirp 408. Thus, the repetition period of the FMCW chirp waveform corresponds to the period from t0 to t2 and the period from t2 to t5 (each corresponding to the periods of two separate FMCW chirp 408s). The repetition frequency is the reciprocal of the repetition period.

[0026] The FMCW signal 400 in Figure 4 shows a sawtooth-shaped signal. A reverse sawtooth-shaped FMCW signal can also be used, and such a reverse sawtooth-shaped signal can also correspond to the FMCW signal 400, but the time order of the control signal 404 is intended to be reversed. Therefore, the FMCW signal 400 can be generated as shown in Figure 4, and the time intervals corresponding to the signal generated in response to the control signal are t0~t1, t1~t2, t2~t3, t3~t4, t4~t5, and t5~t6, or in reverse, corresponding to the time periods t6~t5, t5~t4, t4~t3, t3~t2, t2~t1, and t1~t0.

[0027] The digital lamp generator 338 in Figure 3 generates gradient s2 To shorten the time interval t2~t3, which corresponds to increasing the absolute value of the steepness, CP312 can be controlled to allow the increased current to flow to filter 314. For example, the current supplied to filter 314 can be increased by increasing the current supplied to charge pump 312 to a higher value than that used during the time interval t1~t2. This allows VCO330 and PLL302 to change the output frequency more quickly and accurately without losing lock and therefore without causing cycle slip.

[0028] To shorten the time interval t2~t3, the digital lamp generator 338 can also control one or more of the resistors 316, 318, 320 or capacitors 322, 324, 326 of the filter 314 to increase the bandwidth of the filter 314, thereby increasing the response rate of the filter 314 and increasing the rate of change of the VCTRL 328. The bandwidth of the filter 314 can be increased, for example, to 10 times the bandwidth used during the generation of the FMCW chirp 408. Thus, the digital lamp generator 338 can change the bandwidth of the filter 314 by controlling R F , R Z , C FOne, some, or all of the following (some or all of which may be programmable) can be controlled: , and Cz. Increasing the bandwidth of filter 314 increases the phase noise at the FMCW synthesizer output 336, but allows for faster re-ordering of the FMCW synthesizer output 336 to the chirp start frequency F0. Conversely, decreasing the bandwidth of filter 314 reduces the phase noise at the FMCW synthesizer output 336. Thus, the bandwidth of filter 314 corresponds to the frequency ramp-down period (the intervals t2-t3 and t5-t6 in each ramp-down period shown in Figure 4). down The bandwidth of filter 314 can be reduced after 420). The bandwidth of filter 314 can be reduced during the remainder of idle time 406 and during FMCW chirp 408 to reduce phase noise in FMCW synthesizer output 336.

[0029] In some cases, when ADC214 in Figure 2 is not sampling data for analysis, the idle time 406 can be considered "wasted" time. ADC214 in Figure 2 samples data during the FMCW chirp 408 (and thus the data is received by receiver 202). The increased filter noise from the increased bandwidth of filter 314 is T down During a period of 420, idle time can be reduced by 406.

[0030] The increased current of s2, CP312, and the increased bandwidth of filter 314 result in T down During the idle time 406, including 420, the PLL 302 is selected to remain locked, increasing the accuracy of frequency control of the VCO 330 and avoiding frequency overshoot. Additionally, the increased current of CP 312 and the increased bandwidth of filter 314 may be selected to shorten the time interval t2~t3, and thus the time to transition from frequency F1 to frequency F0.

[0031] Figure 5 shows an illustrative diagram of the FMCW signal 500 generated by the FMCW synthesizer 208 in Figure 3, and the corresponding control timing in Figure 502. The FMCW signal 500 is generated similarly to the FMCW signal 400 in Figure 4. However, the FMCW signal 500 in Figure 5 shows that the FMCW synthesizer 208 in Figure 3 can generate an FMCW output signal 336 without overshoot, including FMCW chirps 508a, 508b that start at multiple different frequencies (e.g., F0, F2) and end at multiple different frequencies (e.g., F1, F3), as well as multiple different corresponding slopes (e.g., s1 and s3 between FMCW chirps 508a, 508b, and ramp-down period T). down1 516 and T down2 This includes s2 and s4 between 528.

[0032] The interval t0 to t1 is the first idle time 506a. At time t0, the timing and control engine 304 sends a control signal 504 to the PLL 302 to instruct it to generate an FMCW synthesizer output 336 having a constant frequency 510F0 (start frequency F0, gradient zero).

[0033] The interval t1 to t2 is the first FMCW chirp 508a. At time t1, the PLL 302 in Figure 3 is instructed to pass through an output frequency 512, starting at frequency F0 and increasing with a gradient s1. At time t2, the FMCW chirp 508a reaches a maximum frequency 514, F1. With respect to Figure 4, as described above, the timing and control engine 304 is instructed to pass through F0, t 1、 Using t2, F1 can be calculated.

[0034] The interval t2~t4 is the second idle time 506b. The interval t2~t3 is the ramp-down period T down1This is the first ramp-down 518 over 516. Between intervals t2 and t3, the FMCW synthesizer output frequency ramps down 518 from frequency F1 to frequency F2 with a gradient s2. As described above with respect to Figure 4, the timing and control engine 304 controls CP312 to increase its output current and controls filter 314 to increase its bandwidth, thereby making the gradient s2 of the ramp-down 518 steeper than the gradient s1, T down1 Shorten 516. Also, the gradient s2 is F1, F2, T down1 516: s2=(F2-F1) / T down1 This can be calculated based on the following: At time t3, the FMCW synthesizer output 336 is set to a constant frequency 520F2, and therefore the frequency F2 has a zero gradient.

[0035] The interval t4 to t5 is the second FMCW chirp 508b. At time t4, the PLL 302 is instructed to pass through an output frequency 522, starting at frequency F2 and increasing with a gradient s3. At time t5, the FMCW chirp 508b reaches a maximum frequency 524, F3. As described above with respect to Figure 4, the timing and control engine 304 can calculate F3 using F2, t4, and t5.

[0036] Time t5 marks the start of the third idle time 506c (the end of the third idle time 506c, corresponding to the start of the third FMCW chirp, is not shown). The interval t5~t6 is of duration T down2 This is a second ramp-down 526 over 528. Between intervals t5 and t6, the FMCW synthesizer output frequency ramps down 526 from frequency F3 to frequency F4 with a gradient s4. As described above with respect to Figure 4, the timing and control engine 304 controls CP312 to increase its output current and controls filter 314 to increase its bandwidth, thereby making the gradient s4 of the ramp-down 526 steeper than the gradient s3, T down2 Shorten 528. Also, gradient s4 is F3, F4, T down2 516: s4=(F4-F3) / T down2This can be calculated based on the following: At time t6, the FMCW synthesizer output 336 is set to a constant frequency 530F4, and therefore the frequency F4 has a zero gradient.

[0037] Figure 6 shows an exemplary process 600 for operating the FMCW radar system 200 of Figure 2. In step 602, the transmitter 220 transmits an FMCW synthesizer signal. In step 604, the receiver 202 receives an FMCW chirp reflection signal 226. In step 606, the FMCW synthesizer 208 generates an FMCW synthesizer signal at the FMCW synthesizer output frequency, where the FMCW synthesizer output frequency is: between the first time and the second time, it is the first FMCW idle frequency; between the second time and the third time, it varies at a specified first rate; between the third time and the fourth time, it varies at a specified second rate, the first rate being different from the second rate; and between the fourth time and the fifth time, it is the second FMCW idle frequency. In step 608, the mixer 206 mixes the FMCW chirp reflection signal and the FMCW synthesizer signal to generate a mixer output. In step 610, the ADC 214 samples the mixer output.

[0038] Figure 7 shows an illustrative process 700 for operating the FMCW radar system 200 of Figure 2, including the FMCW synthesizer 208 of Figure 3. To generate the FMCW chirp 408, a digital state machine (not shown) controls the ADC 214, TX 202, RX 220, and FMCW synthesizer 208 to operate synchronously as follows: In step 702, the bandwidth of filter 314 is changed to a relatively low value by changing the impedance of filter 314. In step 704, the current supplied to CP 312 is changed to a relatively low value. In step 706, the output frequency of VCO 330 is ramped up to generate the FMCW chirp 408, and the FMCW chirp is transmitted using transmitter 220. In step 708, the FMCW chirp reflected signal 226 is received using receiver 202. In step 710, data is sampled using ADC 214.

[0039] During the time between FMCW chirps 408, the digital state machine controls the ADC 214 and FMCW synthesizer 208 as follows: In step 712, the ADC 214 stops sampling data. In step 714, the bandwidth of the filter 314 is increased to a relatively high value by changing the impedance of the filter 314. In step 716, the current supplied to the CP 312 is increased to a relatively high value. In step 718, the output frequency of the VCO 330 is ramped down using a gradient with a higher absolute value than the gradient of the FMCW chirp 408, by setting the gradient so as to avoid cycle slip, with the ramp-down starting at the last frequency of the FMCW chirp 408 and ending at the starting frequency of the next FMCW chirp 408. The process 700 can then be repeated from step 702.

[0040] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

[0041] In some embodiments, the filter is T downDuring this time, the bandwidth is set to high. In some embodiments, the filter is set to high bandwidth during idle time.

[0042] In some embodiments, the ADC samples the signal transmitted from the receiver over a period corresponding to an FMCW synthesizer that generates an FMCW chirp.

[0043] In some embodiments, the input of a frequency divider connected to the output of a buffer may be referred to as a tone input, and the input of a frequency divider connected to a digital ramp generator may be referred to as a control input.

[0044] In some embodiments, a control voltage generator can be used in a phase-locked loop to generate a control voltage (VCTRL) for the VCO in response to a reference frequency and to feed it back in response to the VCO output signal. In some embodiments, the control voltage generator includes a PFD, a charge pump, and a filter, as described with reference to Figure 3.

[0045] In some embodiments, the FMCW chirp corresponds to a decreasing frequency, and the ramp-down corresponds to an increasing frequency.

[0046] In some embodiments, during the initial portion of an FMCW chirp, such as the first 10% of the FMCW chirp, the FMCW synthesizer remains stable toward the precise frequency ramp. This time can be considered "wasted" time when the ADC is not sampling data for analysis.

[0047] In some embodiments, the time between FMCW chirps (idle time) can be called the inter-chirp time.

[0048] In some embodiments, a ramp-down occurs before the FMCW chirp, generating a signal similar to a reverse sawtooth pattern. Thus, starting at the idle frequency, the frequency changes at a specified gradient for a specified duration to reach the FMCW chirp initiation frequency, while the charge pump output current and filter bandwidth relatively increase. Then, starting at the FMCW chirp initiation frequency, the frequency changes at a specified gradient for a specified duration to generate the FMCW chirp, while the charge pump output current and filter bandwidth relatively decrease.

[0049] In some embodiments of 76-81 GHz commercial automotive radar, the durations of the idle time, FMCW chirp, and ramp-down period are 5 μs, 30 μs, and 2 μs, respectively. In some embodiments, the FMCW chirp duration is 15 μs to facilitate accurate detection of the presence, range, and speed of objects at very high speeds.

[0050] In some embodiments, a processor (e.g., a DSP) processes the sampled data (e.g., by an ADC) during the FMCW chirp to determine one or more of the presence, distance, or velocity of a target object. In some embodiments, the processor does not process the sampled data during the ramp-down or idle time (or both) to determine the presence, distance, or velocity of a target object.

[0051] In certain embodiments, with respect to Figures 2 to 6, the frequency of the output signal is controlled to have a specific value between the first and second time periods and a specific slope starting from a specific value between the second and third time periods, and it is intended to suggest that the frequency of the output signal avoids other unintended values ​​or slopes during the described time periods. However, in certain embodiments, the actual signal frequency does not have to exhibit perfectly linear behavior, and normal frequency fluctuations common to smooth transitions in the controlled characteristics of a signal (as opposed to disjoint frequency controls that result in overshoot, such as those described herein) are intended to be taken into account within the described signal performance with respect to the specified behavior during the specified intervals.

Claims

1. A frequency-modulated continuous wave (FMCW) synthesizer, It is a phase-locked loop (PLL), A frequency divider including a control input, a frequency divider input, and a frequency divider output, A control voltage generator (CVG) including a control voltage generator (CVG) input coupled to the frequency divider output, wherein the CVG is configured to generate a control voltage in response to the CVG input, A voltage-controlled oscillator (VCO) including a VCO input coupled to the CVG and a VCO output coupled to the frequency divider input, wherein the VCO is configured to output an FMCW output signal having an FMCW output frequency in response to the VCO input, The PLL includes, A control engine including a first control output coupled to the control input of the frequency divider, wherein the FMCW output frequency is From the first time period to the second time period, the first idle frequency is... It changes at a first rate specified from the second time to the third time, From the third time to the fourth time, it changes at a specified second rate that is different from the specified first rate, From the fourth time to the fifth time, the second idle frequency is different from the first idle frequency. The control engine is configured to control the PLL, An FMCW synthesizer comprising, wherein the control engine is configured to output to the first control output a signal containing information about the second rate for controlling at least the period from the third time to the fourth time, such that the second rate, calculated from the maximum frequency when changed at the first rate, the second idle frequency, and the time period from the third time to the fourth time, does not exceed the allowable slope of the PLL.

2. The FMCW synthesizer according to claim 1, A receiver adapted to receive reflected FMCW chirp, the receiver including a receiver output, An analog-to-digital converter (ADC) including an ADC input and an ADC output coupled to the receiver output, wherein the ADC is configured to sample the signal received by the ADC input and output the sampled signal, A processor including a processor input coupled to the ADC output, configured to determine at least one of the presence, distance, and velocity of a target object in response to the sampled signal being sampled between the second time and the third time, and configured not to perform a determination operation between the third time and the fourth time, A transmitter including a transmitter input coupled to the VCO output, configured to transmit a signal received by the transmitter input, The FMCW synthesizer further includes this.

3. The FMCW synthesizer according to claim 2, An FMCW synthesizer in which the absolute value of the specified second rate is greater than the absolute value of the specified first rate.

4. The FMCW synthesizer according to claim 1, The control engine further includes a second control output and a third control output, The aforementioned CVG, A charge pump (CP) including a charge pump (CP) control input and a CP output coupled to the second control output, wherein the current of the CP output is configured to change in response to the CP control input, A filter comprising a filter signal input coupled to the CP output, a filter control input coupled to the third control output, and a filter output, wherein the bandwidth of the filter is configured to change in response to the filter control input, It further includes, An FMCW synthesizer in which the control engine controls the second rate with the first control output, increases the current of the CP output via the second control output, and increases the bandwidth of the filter via the third control output.

5. The FMCW synthesizer according to claim 4, The aforementioned control engine The bandwidth of the filter is controlled to be relatively lower between the second time and the third time. The bandwidth of the filter is controlled to be relatively higher between the third time and the fourth time. The FMCW synthesizer is further configured in this way.

6. The FMCW synthesizer according to claim 5, An FMCW synthesizer in which the filter is configured to change the bandwidth of the filter by changing the impedance of the filter.

7. The FMCW synthesizer according to claim 4, The aforementioned control engine The current of the CP output is controlled to become relatively lower between the second time and the third time. The current of the CP output is controlled to become relatively higher between the third time and the fourth time. The FMCW synthesizer is further configured in this way.

8. The FMCW synthesizer according to claim 1, An FMCW synthesizer in which the first specified rate is constant and the second specified rate is constant.

9. The FMCW synthesizer according to claim 1, The control engine further includes a second control output, The CVG further includes a CVG control input coupled to the second control output, and the CVG is further configured to change the current of the control voltage output in response to the CVG control input. The aforementioned control engine The current of the control voltage output is controlled to become relatively lower between the second time and the third time. The current of the control voltage output is controlled to become relatively higher between the third time and the fourth time. The FMCW synthesizer is further configured in this way.

10. The FMCW synthesizer according to claim 1, The aforementioned control engine The FMCW output frequency is, It changes at a third rate specified from the fifth time to the sixth time, From the sixth time to the seventh time, it changes at a specified fourth rate that is different from the specified third rate, From the seventh time to the eighth time, the third idle frequency is An FMCW synthesizer further configured to control the PLL as described above.

11. The FMCW synthesizer according to claim 1, An FMCW synthesizer, wherein the control engine is further configured to control the PLL to maintain phase lock both when generating the FMCW chirp and during the idle time between FMCW chirp generation.

12. The FMCW synthesizer according to claim 1, An FMCW synthesizer whose time sequence begins with the first time, then the second time, then the third time, then the fourth time, then the fifth time, or begins with the fifth time, then the fourth time, then the third time, then the second time, then the first time.

13. The FMCW synthesizer according to claim 1, An FMCW synthesizer in which the PLL includes a ramp generator coupled to the first control output, the ramp generator includes a feedback input coupled to the periodic divider output, and the ramp generator is configured to control the frequency divider in response to a signal received at the feedback input.

14. A frequency-modulated continuous wave (FMCW) data system, A receiver adapted to receive reflected FMCW chirp, the receiver including a receiver output, It is an FMCW synthesizer, FMCW synthesizer output and A phase-locked loop (PLL) including a control input and a phase-locked loop (PLL) output coupled to the FMCW synthesizer output, wherein the phase-locked loop (PLL) is configured to output an FMCW signal having a certain FMCW output frequency in response to the control input, A control engine including a control output coupled to the control input, wherein the FMCW output frequency is From the first time period to the second time period, the first FMCW idle frequency is... It changes at a first rate specified from the second time to the third time, From the third time to the fourth time, it changes at a specified second rate that is different from the specified first rate, From the fourth time to the fifth time, the second FMCW idle frequency is different from the first FMCW idle frequency. The control engine is configured to control the PLL and to output a signal to the control output that includes information about the second rate for controlling at least the period from the third time to the fourth time, such that the second rate, calculated from the maximum frequency when changed at the first rate, the second idle frequency, and the period from the third time to the fourth time, does not exceed the allowable slope of the PLL. The FMCW synthesizer, including, A mixer comprising a first mixer input coupled to the receiver output and a second mixer input and mixer output coupled to the FMCW synthesizer output, configured to generate a mixer output signal in response to the first mixer input and the second mixer input; and an analog-to-digital converter (ADC) comprising an ADC input and an ADC output coupled to the mixer output, configured to sample a signal received by the ADC input and output the sampled signal; A processor including a processor input coupled to the ADC output, configured to determine at least one of the presence, distance, and velocity of a target object in response to a sampled signal sampled between the second time and the third time, and configured not to perform any determination operations between the third time and the fourth time; and a transmitter including a transmitter input coupled to the FMCW synthesizer output, configured to transmit a signal received by the transmitter input. FMCW Data Systems, including...

15. The FMCW radar system according to claim 14, An FMCW radar system in which the absolute value of the specified second rate is greater than the absolute value of the specified first rate.

16. The FMCW radar system according to claim 14, An FMCW radar system, wherein the control engine is further configured to control the PLL such that it maintains phase lock both when generating FMCW chirps and during the idle time between FMCW chirp generation.

17. The FMCW radar system according to claim 14, The aforementioned control engine Increase the filter bandwidth of the PLL filter during the idle time between FMCW chirp generation, During the generation of the FMCW chirp, the filter bandwidth of the PLL filter is reduced. During the idle time between FMCW chirp generation, the current of the control voltage of the PLL's voltage-controlled oscillator (VCO) is increased. During the generation of the FMCW chirp, the current of the control voltage of the VCO of the PLL is reduced. An FMCW radar system further configured to control the PLL.

18. A method for operating a frequency-modulated continuous wave (FMCW) radar, The receiver receives the FMCW chirp reflection signal, The method involves generating an FMCW synthesizer signal at the FMCW synthesizer output frequency using an FMCW synthesizer, by providing the PLL with information regarding a second rate for controlling a period from at least a third time to a fourth time, thereby controlling the FMCW synthesizer output frequency. From the first time period to the second time period, the first FMCW idle frequency is... It changes at a first rate specified from the second time to the third time, From the third time to the fourth time, it changes at a specified second rate that is different from the specified first rate, From the fourth time to the fifth time, the second FMCW idle frequency is different from the first FMCW idle frequency. The second rate is calculated from the maximum frequency when the first rate is applied, the second FMCW idle frequency, and the time period from the third time to the fourth time, such that the rate does not exceed the gradient that the PLL can tolerate. To generate the FMCW synthesizer signal, The FMCW chirp reflection signal and the FMCW synthesizer signal are mixed using a mixer to generate a mixer output, The mixer output is sampled using an analog-to-digital converter (ADC), Transmitting the FMCW synthesizer signal using the transmitter, Methods that include...

19. The method according to claim 18, The bandwidth of the filter of the phase-locked loop (PLL) of the FMCW synthesizer is made relatively lower between the second time and the third time, The bandwidth of the PLL filter of the FMCW synthesizer is made relatively higher between the third time and the fourth time, Methods that further include the above.

20. The method according to claim 18, The current output of the charge pump of the phase-locked loop (PLL) of the FMCW synthesizer is made relatively lower between the second time and the third time, The current output of the charge pump of the PLL of the FMCW synthesizer is made relatively higher between the third time and the fourth time, Methods that further include the above.

21. The method according to claim 18, The FMCW synthesizer signal is generated using the FMCW synthesizer, The FMCW synthesizer output frequency is, It changes at a third rate specified between the fifth time and the sixth time, Between the sixth time and the seventh time, it changes at a specified fourth rate that is different from the specified third rate, A method further comprising generating the FMCW synthesizer signal, which is a third FMCW idle frequency, between the seventh time and the eighth time.

22. A method according to claim 18, further comprising using a phase-locked loop (PLL) of the FMCW synthesizer to maintain phase synchronization both when generating the FMCW chirp and during the idle time between the generation of the FMCW chirp.

23. The method according to claim 18, A method in which the time sequence begins with the first time, followed by the second time, then the third time, then the fourth time, then the fifth time, or begins with the fifth time, followed by the fourth time, then the third time, then the second time, then the first time.

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